CN106463522A - 形成集成电路的方法及相关的集成电路 - Google Patents

形成集成电路的方法及相关的集成电路 Download PDF

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CN106463522A
CN106463522A CN201580011709.4A CN201580011709A CN106463522A CN 106463522 A CN106463522 A CN 106463522A CN 201580011709 A CN201580011709 A CN 201580011709A CN 106463522 A CN106463522 A CN 106463522A
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layer
led
cmos
ingan
integrated circuit
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CN106463522B (zh
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张文甲
王冰
张利
朱兆旻
尤尔根·米歇尔
蔡树仁
白俐翾
谢小明
永坚·K·李
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National University of Singapore
Nanyang Technological University
Massachusetts Institute of Technology
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National University of Singapore
Nanyang Technological University
Massachusetts Institute of Technology
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    • GPHYSICS
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    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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Abstract

公开了一种形成集成电路的方法(100)。该方法包括:i)由设置在一半导体基底上的至少一第一晶圆材料形成至少一对光电器件,所述第一晶圆材料不同于硅;ii)刻蚀所述第一晶圆材料以形成一第一凹槽,供一第二材料填充;iii)处理(104)所述第二材料以形成用于耦接所述至少一对光电器件的一波导,从而定义一光学互连件;以及iv)将具有至少一个晶体管的至少一个经部分处理的CMOS器件层与所述第二半导体基底相键合(106),以形成集成电路,该经部分处理的CMOS器件层与该光学互连件邻近设置。还公开了一种集成电路。

Description

形成集成电路的方法及相关的集成电路
技术领域
本发明涉及一种形成集成电路的方法,及相关的集成电路。
背景技术
在近几年来,半导体产业已通过增加处理器的内核数目(即多核处理器)而提升处理器的性能,根据摩尔定律(Moore's law),集成电路中的晶体管数目大约每两年会倍增。由此,对设计低功耗的片上通信骨干网,例如一片上网络(NoC),以在内核和相关的存储器之间传输数据位带来挑战。可以理解的是,电气(基于金属的)互连件在现代的处理器中已是传统上主流的片上通信元件,且迄今可满足传统的多核处理器的通信需求。但是,若内核的数目增加,则可分配给对应的多核处理器的功率预算则会明显地受到限制,此外,该处理器的性能还将会由于使用电气互连件而严重地受限,导致不理想地受困于一固有的带宽/距离/功率的折衷妥协。
因此需要新型的互连件以使未来的多核处理器能有更高的可扩充性。根据文献,光学互连件被认为具有能克服电气互连件的上述带宽/距离/功率的折衷妥协的潜力。一光学/光子式互连件通常包含一发光源用以产生一信息载体,一调制器用于电/光(E/O)的数据转换,一光电二极管用于光探测,多种被动元件用以导光,及外围电子器件用以驱动和偏压光子器件。就一光学互连件而言,该发光源通常为最重要的器件,因其会耗掉所用的总连结功率的一绝大部分。针对于此,现有的方案倾向于利用芯片外的激光作为该发光源,但由于它们的高阈值电流,会消耗大量的功率。即使当所述光学互连件被间断地使用时,所述激光的功率消耗仍会保持大致固定不变,因为通信数据是在所述激光的连续波长上由外部地调制,因此,不论通过所述光学互连件的实际数据传输量如何,都会因所述激光而造成高功率消耗。
因此本发明的一目的为解决该现有技术的至少一个所述问题,和/或提供一种该技术中可用的选择。
发明内容
根据本发明的第一方面,提供一种形成集成电路的方法,包括:i)由设置在一半导体基底上的至少一第一晶圆材料形成至少一对光电器件,该第一晶圆材料不同于硅;ii)刻蚀该第一晶圆材料以形成一第一凹槽,供一第二材料填充;iii)处理该第二材料以形成用以耦接所述至少一对光电器件的一波导,来定义一光学互连件;及iv)将具有至少一个晶体管的至少一个经部分处理的CMOS器件层与第二半导体基底相键合,来形成集成电路,该经部分处理的CMOS器件层与该光学互连件邻近设置。
所提供的方法有利地采用一单片式集成工艺来键合一III-V基底和一硅基底,其与传统的CMOS工艺直接地兼容,故不需要对现有的CMOS制造技术进行高成本且复杂的重建来实现该方法以获得该集成电路。
优选地,该不同于硅的第一晶圆材料包括III-V族半导体材料或有机材料。
优选地,所述III-V族半导体材料包括GaN、InGaP、GaAs、AlGaAs或InGaAs。
优选地,该第二材料包括氮化硅。
优选地,其中将该经部分处理的CMOS器件层与该半导体基底相键合包括处理该经部分处理的CMOS器件层,以提供能触及该光学互连件的第二凹槽,并以一电绝缘材料填充该第二凹槽;及处理该电绝缘材料来电连接该至少一个晶体管和所述至少一对光电器件以形成该集成电路。
优选地,该电绝缘材料包括二氧化硅。
优选地,所述光电器件选自光探测器和发光器件。
优选地,所述发光器件可包括发光二极管或有机发光二极管。
优选地,该方法还包含对另一半导体基底执行CMOS工艺,以获得具有所述至少一个晶体管的所述至少一个经部分处理的CMOS器件层;并从该另一半导体基底移除该经部分处理的CMOS器件层。
优选地,该另一半导体基底包括一绝缘体上硅基底。
优选地,该方法可还包含在形成所述至少一对光电器件之后,沉积一电绝缘材料来覆盖该第一晶圆材料;以及使用化学机械抛光法来平坦化所沉积的电绝缘材料。
优选地,该方法可还包含在该第一凹槽填充该第二材料之后,使用化学机械抛光法来平坦化该填充有第二材料的第一凹槽。
优选地,其中处理该第二材料以形成该波导可包括使用光刻和/或刻蚀。
优选地,该方法还可包含在形成该波导之后,沉积一电绝缘材料来覆盖该第一晶圆材料和第二材料;以及使用化学机械抛光法来平坦化所沉积的电绝缘材料。
优选地,其中处理该经部分处理的CMOS器件层来提供该第二凹槽包括使用刻蚀和/或机械研磨。
优选地,该方法可还包括使用化学机械抛光法来平坦化该经部分处理的CMOS器件层和该填充有电绝缘材料的第二凹槽。
优选地,其中处理该电绝缘材料来电连接该至少一个晶体管和该对光电器件包括在该电绝缘材料中形成多个通孔,并以一导电材料填充所述通孔。
优选地,其中将该部分处理的CMOS器件层与该半导体基底相键合包括将该光学互连件设置于该经部分处理的CMOS器件层下方。
优选地,其中所述至少一第一晶圆材料包括多层晶圆材料,每一层由一不同的材料形成。
根据本发明的第二方面,提供一种集成电路,包括:至少一个晶体管,设置在一经部分处理的CMOS器件层中;以及至少一对光电器件,由一波导耦接来在一半导体基底上定义一光学互连件,所述半导体基底与该经部分处理的CMOS器件层邻近设置,其中所述光电器件用于电连接至所述晶体管,且所述光电器件由不同于硅的至少一第一晶圆材料形成,以及其中该波导由第二材料形成,该第二材料沉积在形成于所述第一晶圆材料中的第一凹槽内。
优选地,该不同于硅的第一晶圆材料包括III-V族半导体材料或有机材料。
优选地,所述III-V族半导体材料包括GaN、InGaP、GaAs、AlGaAs或InGaAs。
优选地,该集成电路形成为单个处理器,或一处理器的一部分。
优选地,该光学互连件设置于该经部分处理的CMOS器件层的下方。
优选地,该第二材料包括氮化硅。
显然地,有关本发明的一方面的特征还可适用于本发明的其它方面。
本发明的这些及其它的方面将可由参照以下所述实施例的说明而明显易知。
附图说明
下面参照所附图式对本发明的实施例进行描述,其中:
图1为根据本发明的一实施例的一种形成集成电路的方法的流程图;
图2包括图2a至2c,为图1所示方法的步骤102的流程图;
图3包括图3a至3d,为图1所示方法的步骤104的流程图;
图4包括图4a和4b,为图1所示方法的步骤106的流程图;
图5包括图5a至5d,为图1所示方法的步骤108的流程图;
图6a为使用图1所示方法形成的集成电路的一例,图6b为图6a的一简化图,示出该集成电路中各光电器件的示意图;
图7为一InGaN LED的示意图,其可被设置在用图1所示方法形成的集成电路中;
图8为列出图7的LED的一外延生长层结构的各层的表;
图9包括图9a和9b,分别示出用于制造图7的InGaN LED的掩模布局图,及图7的InGaN LED的一PDK设计和相应的硅驱动器;
图10为列出用于图7的InGaN LED的各种设计参数的表;
图11a为使用图1所示方法形成的集成电路的另一例,图11b示出图11a的集成电路的光场传输和耦接损耗性能;
图12a示出根据现有技术的SMART微结构,图12b示出采用了图1的方法形成的集成电路的一变型的SMART微结构;
图13a为传统方案与通过图1所示方法形成的集成电路间的能量效率性能图表;
图13b为图12a的SMART微结构与图12b的变型的SMART微结构间的归一化动态网络能量性能图表;以及
图14为列出根据另一实施例的用于图7的InGaN LED的各种设计参数的表。
具体实施方式
图1为根据一实施例的一种形成集成电路的方法的流程图100。该集成电路可形成为单个处理器或一处理器的一部分,但对于本实施例(作为一例),该集成电路形成为一处理器。该方法概述如下:在步骤102中,对一Si-CMOS基底202(例如一绝缘体上硅(SOI)基底)执行CMOS工艺以形成至少一个晶体管(其为硅基的);在步骤104中,对一III-V基底302进行处理以在该基底上形成光电器件(例如LED、OLED、光探测器和/或其他)。应当理解,该III-V基底302可以由任何适当的III-V材料(如InGaN或GaN,但并非作为限制)所形成。需要说明的是,步骤102是使用传统的互补金属氧化物半导体(CMOS)工艺技术来执行的,为了简单明了,在此省略更深入的说明。此外,该具有至少一个晶体管的Si-CMOS基底202可被视为经部分处理的Si-CMOS基底。该经部分处理的Si-CMOS基底还可被称为经部分处理的Si-CMOS器件层。应当理解,至少一个Si-CMOS器件层是必须的。但在本例中,所述至少一个晶体管包括多个晶体管,其可被配置成具有相应的高速缓存器、路由器、连结驱动器等的处理器。然后在步骤106中,将经处理的Si-CMOS和III-V基底202、302键合在一起;最后,在步骤108中,将分别形成于该经处理的Si-CMOS和III-V基底202、302中的晶体管和光电器件进行电连接。因此,应可理解该集成电路如上所述单片地形成。各步骤102-108的详细说明现将进一步提供于下。
如上所述,该集成电路由Si-CMOS和III-V材料共同形成。就使用该GaN材料制成的光电器件而言,应当理解,因为GaN必须在具有匹配的晶格方向的Si(111)基底上生长,而Si-CMOS电路通常在Si(100)基底上制造,故键合技术必须能将所述晶体管和光电器件集成在单个晶圆上。考虑到通常用以生长GaN的温度对所述晶体管可完好存续而言太高(即大约1000℃),故所述晶体管必须作为该Si-CMOS基底的一前端基底被分开制造,同样的,所述光电器件的外延也要被分开地进行,之后再在步骤106中,将该经处理的Si-CMOS和III-V基底键合在一起。
图2a至2c共同地示出形成图1所示方法的步骤102的各按次序的步骤1022、1024、1026的流程图。在图2a的步骤1022中,使用该Si-CMOS基底202来制作晶体管200,所述基底202在本例中是一SOI基底(但并非作为限制),且于下文中会如此进行描述。该SOI基底200(以由上向下顺序)包括顶Si(100)层202a、第一SiO2层202b以及底Si(001)层202c。为易于参照,此被称为该SOI基底200的正面向上排列。所述晶体管200形成在该顶Si(100)层202a上,其形成后会被第二SiO2层204覆盖。需要时,可使用化学机械抛光法(CMP)或其它适当的工艺对该第二SiO2层204进行平坦化。应当理解,该SOI基底200仍以正面向上的方向放置。在图2b的步骤1024中,该SOI基底200会被键合于一Si载片206,其邻接且平坦于该第二SiO2层204。然后,在图2c的步骤1026中,该SOI基底200的底Si(001)层202c被基本移除,直到该第一SiO2层202b暴露。完成图2c中所示的步骤1026后,得到该经处理的SOI基底200。该经处理的SOI基底200可被称为一处理器晶圆。
其后,图3a至3d共同地示出形成图1所示方法的步骤104的各按次序步骤1042、1044、1046、1048的流程图。在图3a的步骤1042中,首先使用该III-V基底302来制作光电器件300,所述III-V基底302在本例中包括(以由上向下的顺序)一GaN层302a以及一Si(111)层302b。应当理解在本实施例中为了易于说明,该GaN层302a于此被描述为一单层,但并非以此作为限制,因为在其它的变化实施例中,该GaN层302a可包含多个GaN层,或包含由取代GaN的其它材料(如AlGaN或InGaN)等所形成的多层。即是,为了易于说明,图3仅概念性地示出该GaN材料和光电器件300位于该III-V基底302中何处-其并非真正地代表实际的LED层。为供易于参照,此称为该III-V基底302的正面向上排列。于此例中,所制成的光电器件300(位于GaN层302a)包括至少一个GaN LED及与之相对排列的一对应的光探测器。故本例中的光电器件300包括至少一对光电器件。如所理解,该GaN层302a(为一III-V材料)不同于硅。当然,在某些实施例中,多对的所述GaN LED和对应的光探测器还可根据所需的用途来形成。位于该GaN LED和对应的光探测器中间的一部分该GaN层302a然后可经由刻蚀移除而来形成至少一凹槽用以后续容纳一波导310,以将该GaN LED和对应的光探测器耦接在一起。该刻蚀的定义包括化学刻蚀。应当理解该GaN LED、对应的光探测器及该波导310构成该集成电路的一基于LED的光学互连件(即一光学互连件)。在图3b的步骤1044中,沉积第一SiO2层304以覆盖该GaN层302a和该至少一凹槽。若有需要,还可通过CMP工艺来对该第一SiO2层304进行平坦化。
然后如图3c中的步骤1046所示,沉积在该至少一凹槽(在图3a的步骤1042中所形成)中的该第一SiO2层304的相应部分,会再度被刻蚀而在相同位置,部分地暴露另一新的凹槽。然后,用以形成该波导310的SiN层306(例如Si3N4)则会沉积于该新凹槽中,其同样会覆盖该第一SiO2层304。基本上,该SiN层306会填入在图3c的步骤1046中形成的凹槽中。若有需要,通过CMP来平坦化该SiN层306。在图3d的步骤1048中,该SiN层306然后会使用光刻和/或刻蚀来处理以形成该波导310。该波导310可适于耦接所述光电器件300来形成该基于LED的光学互连件。然后,沉积第二SiO2层308以覆盖并包封该SiN层306(其包含该波导310),且若有需要会后续进行CMP平坦化。随着步骤1048完成,则会获得该经处理的III-V基底302(仍呈该正面向上排列)。该经处理的III-V基底302可被称为一光子式晶圆。
如上所述,应当理解所述光电器件300可包含多个不同材料/合金的层,如在现有技术中所理解的。例如,在该基于GaN的LED的例子中,所述不同层可为二元素的材料,例如GaN、AlN和InN,及InAlGaN的三元素或四元素合金等。通常地,所有的层在单个外延工艺中形成(例如同样在图3a的步骤1042中),但其还可先形成一GaN缓冲层/模板(与所需的AlN和AlGaN缓冲层一起完成),然后进行选择区域的再生长来形成后续各层,而能直接地形成所述器件凸台。
图4a和4b示出形成图1的方法的步骤106的按次序的步骤1062、1064的流程图。在图4a的步骤1062中,该经处理的SOI基底200(在图2c的步骤1026中所获得),及经处理III-V基底302(在图3d的步骤1048中所获得)会被相应对准并键合在一起。应当理解经处理的SOI基底200键合在经处理的III-V基底302顶上且相邻于经处理的III-V基底302。即是,经处理的SOI基底200的第一SiO2层202b设成平坦的且沿垂直方向直接地邻接于该经处理的III-V基底302的第二SiO2层308。此外,该经处理的SOI基底200和该经处理的III-V基底302(当键合后)位于不连接的平面中(即所述晶体管200和光电器件300位于各自不同的平面中)。在图4b的步骤1064中,该经处理的SOI基底200的Si载片206会被移除。具体地,该经处理的SOI基底200和经处理的III-V基底302仍呈它们的各正面向上排列。此外,应当理解此单片集成能使该经处理的SOI基底200的Si(100)层202a与该经处理的III-V基底302的Si(111)层302b之间的方向错配被避免。
图5a至5d示出共同形成图1的方法的步骤108的各按次序步骤1082、1084、1086、1088的流程图。在图5a的步骤1082中,对该已键合的经处理的SOI基底200和III-V基底302(由图4b的步骤1064所获得)执行刻蚀/机械研磨,而使该经处理的SOI基底200的一部分被移除来形成一凹槽。该经处理的SOI基底200被移除部分的量依需要而定,但应当理解执行步骤1082是为了移除部分顶Si(100)层202a,该部分顶Si(100)层202a对应于后续将形成多个通孔502的区域以使得所述晶体管200与光电器件300电连接。即是说,刻蚀/机械研磨只须在那些欲形成通孔502的区域中进行,且该刻蚀/机械研磨然后会在该第一SiO2层202b内的一适当的预定位置停止,而使该SiN层306和GaN层302a皆会因此仍被一些量的SiO2保护。即是,通过该凹槽可触及到该基于LED的光学互连件。在步骤1082中形成该凹槽的目的,是为了能方便(该经处理的SOI基底200的)所述晶体管200的后续电连接于(该经处理的III-V基底302的)光电器件300。在图5b的步骤1084中,该凹槽然后被基本填满一电绝缘材料500(例如SiO2),且然后若有需要则以CMP平坦化。在图5c的步骤1086中,该多个通孔502会被适当地形成于该电绝缘材料500中,且所述各通孔502会在图5d的步骤1088中填充一导电材料504(例如一适合的金属),以将所述晶体管200电连接于光电器件300,从而获得完成的集成电路。若有需要,该完成的集成电路的平坦化会通过CMP来进行。
就此实施例而言,图1的方法描述为由单个实体来实施。但并非要作为限制,同样地,请理解针对图1的方法,若有需要则相关的步骤102-108可分开地由不同的实体,例如不同的CMOS制造厂来选择地进行。例如,第一CMOS制造厂可执行步骤102,而不同的非CMOS制造厂实体则可执行步骤104。然后,第二CMOS制造厂可执行步骤106,再可由该第一CMOS制造厂执行步骤108。当然,若有需要时,所述步骤102、106和108的不同的子步骤还可被指配于另外的不同CMOS制造厂,例如假使技术上可能且经济上可行。又于此情况下,则图1的步骤102可简单地被省略,或被重定义为接收一已经部分处理的Si-CMOS基底,而非处理该CMOS基底。上述变化操作的一优点为,由所述不同的CMOS制造厂在CMOS技术上所作的先前投资可有利地被杠杆化操用来使许多所提供的集成电路能被以一量产规模便宜地制造。当然,此优点同样会被本实施例分享。在其它例中,步骤106不必在CMOS制造厂中进行,因为CMOS制造厂可较佳地选择接收步骤106完成后所获得的组合晶圆,因此该CMOS制造厂可仅需要执行步骤108中的标准CMOS工艺。
图6a为使用图1的方法形成的集成电路的第一例600,图6b为图6a的一简化图,示出构制于图6a的集成电路中的光电器件的示意概况。就该第一例600而言,图6a中的集成电路包含两个(第一和第二)处理器602a、602b(由该经处理的SOI基底200的晶体管形成),并具有一InGaN LED 604及一对应的InGaN光探测器606(由该经处理的III-V基底302的光电器件300形成)。一波导608(由SiNx制成)将该InGaN LED 604耦接于该InGaN光探测器606,而该第一处理器602a电连接于该InGaN LED 604用以控制该InGaN LED 604。该第二处理器602b则电连接于该InGaN光探测器606用以控制该InGaN光探测器606。应当理解SiNx已被广泛研究作为一用于构制光波导的材料,因为SiNx可被易于与硅基底集成。应当理解在本文中,SiN与SiNx可互换地用来指称相同的介电材料。
被构制能在一大约450nm的波长操作,(该第一例600的)该InGaN LED 604和InGaN光探测器606各皆同样地以如下各层(以由上向下的顺序描述)来形成:一p-GaN层650、一p-AlGaN层652、一InGaN MQW(多量子阱)层654、第一n-GaN层656、一n-AlGaN层658、第二n-GaN层660以及一AlGaN缓冲层662。具体地,显然有关于光发射和光探测的双功能操作仅使用该InGaN MQW层654是可能的,因此可解释为何该InGaN LED 604和InGaN光探测器606被相似地形成。以信息而言,应当理解虽具有所述InGaN/GaN MQW层的LED通常被用作为固态光源,但这些LED通常只使用于屋内灯具,而几乎没有文献有关于最佳化所述LED以供片上通信使用。应当理解用于片上通信的关键考量为高速度、小波形系数及高效率,它们大致以重要性的顺序被列示。
图7为另一InGaN LED 700的示意图,其还可被形成于所提供的集成电路中。该InGaN LED 700的各不同层被以如之前在图3a中所述的相似方式来形成,且为简明的原因,其说明不再重复。简要地概述,如现有技术中所理解的,不同的各层被形成以执行特定的功能,例如带隙平缓化、电流扩散、光学模式整形等等。特别地,所形成的该InGaN LED 700可以包括以下各层(以由上向下的顺序):一p++-GaN层702、一p-GaN层704、一p-AlGaN层706、五个InGaN/GaN MQW层708、第一n-GaN层710、第二n-GaN层712、一AlN/分级的AlGaN缓冲层714以及作为基底层的一Si(111)层716。该p++-GaN层702、p-GaN层704、p-AlGaN层706以及五个InGaN/GaN MQW层708会共同形成一主动发光区域。形成一p-电极层718邻接于该p++-GaN层702,而形成两个n-电极层720a、720b以邻接于该第二n-GaN层712,以方便该InGaN LED 700的控制。该两个n-电极层720a、720b之间的(最外侧的)边缘至边缘的距离被定义为该n-凸台724。应当理解在图7中所示的全部各层702-720经由外延来沉积,然后再开始该InGaNLED 700器件的制作。图8为一表800,其列出图11a的一InGaN/GaN光探测器1104的一外延生长层结构的各层的相关的参数,后续会对该光探测器1104进行详细说明。应当理解,该InGaN LED 700构制成具有微尺寸,因而基于该InGaN LED 700的微尺寸效果,以及能更有效率地使用注入的电流的原因,而可在高速通信中找到用途。
对图6b而言,显然还可设置单个连续的n-电极来包围该p-凸台(即该p-GaN层650、p-AlGaN层652、InGaN MQW层654以及第一n-GaN层656的组合结构)的全部四个侧面,但就本实施例而言,所形成的n-电极仅限于三个侧面,从而空出空间以供形成该波导608。但对其它可设想的实施例而言,该波导608也可设为沿两个方向延伸,即延伸至该InGaN LED 604的左侧,在这种情况下,该n-电极将会被限制于最多在该p-凸台的两侧。故图6b和图7如所呈现可被视为是一具有该n-电极设置成包围该p-凸台的三侧面的器件的两个不同的正交切面。
此外,应当理解在本例中的该“微尺寸效果”的定义是指非常小的器件与大的器件之间的特性差异,特别是有关于速度,和L-I-V(即光输出功率-电流-电压)特性。另一方面,该“注入的电流”的定义是指用来驱动该器件的电流——基本上,就一特定的注入电流而言,按比例计算的话,较小的器件会比较大的器件产生更多的光,进而产生L-I-V特性的差异。
根据图1的方法100,图9a和9b分别示出一可适合用于制造图7的InGaN LED 700的掩模布局900,及一用于图7的InGaN LED 700的PDK设计950,和一用以驱动该InGaN LED700的相应的晶体管(其在本例中构制成一Si驱动器)。应当理解,为符合0.25μm技术节点,采用类似于用于传统的电VLSI设计的布局设计规则(用于该掩模布局900)以便允许DRC和LVS检查。应当理解假使一光学互连件由一LED、一波导及一光探测器所构成,则其中没有晶体管,且因此没有“栅极”存在。但是,该“0.25μm技术节点”定义仍可适用且被理解为根据所提供的方法的最小的特征尺寸(例如该LED、波导和/或光探测器的宽度)为0.25μm。因为相同的制造工具和设计规则可被用于制造任何有关的RF电路,故在该所述的RF电路中的最小特征尺寸(例如所述栅极长度)同样被限制于0.25μm。
相应地,图10为一表,其列示出用于该InGaN LED 700的部件的各种举例设计参数,特别是示出该InGaN LED 700的各部件的一最小尺寸,及所述部件之间的一最小间隔。请参阅图10,该InGaN LED 700的部件包括一键合焊盘(其为一连接焊垫以方便该InGaNLED 700的外部电接入),该p-电极718,该n-电极720a、720b,至少一个多量子阱(即所述InGaN/GaN MQW 708),及一凸台(即器件至器件间隔)。同样地,应当理解,用于该布局设计规则的数据应考量图1所示方法所须的器件需求、材料系统和工艺限制等而获得。此处所述“材料系统”的定义可包括要用以形成一LED/光探测器的材料,及要用以形成一相应的波导的材料等的选择。这会影响到将被应用于所述LED/光探测器(或是相反地会被其驱动)的一所需的光波长。为能更明确,“材料系统”的选择还可意指例如,在要被用来形成该LED/光探测器的InGaN/GaN(若使用波长为450nm的光),或InGaAs/GaAs(若使用波长为1μm的光)之间作选择。
图11a为使用图1的方法形成的集成电路的第二例1100,而图11b示出图11a的第二例1100的光场传输和耦接损耗性能的图表1150。就该第二例1100而言,所形成的该集成电路可以包含一InGaN/GaN LED1102和该InGaN/GaN光探测器1104,它们被一波导1106耦接在一起。如现在已理解的,该InGaN/GaN LED 1102和InGaN/GaN光探测器1104形成在一Si基底1108的顶部。具体地,该InGaN/GaN LED 1102包括(以一由上向下顺序)一p-GaN层1102a、一InGaN MQW层1102b、一n-GaN层1102c以及一AlGaN层1102d。该InGaN/GaN光探测器1104包括(以一由上向下顺序)第一n-GaN层1104a、一InGaN层1104b、第一p-GaN层1104c、一GaN分隔层1104d、第二p-GaN层1104e、一InGaN MQW层1104f、第二n-GaN层1104g及一AlGaN层1104h。该InGaN/GaN LED 1102和InGaN/GaN光探测器1104的各不同层以如前在图3a中所述的相似方式形成,故不再重复说明。
相较于图6b,其中所述InGaN LED 604和InGaN光探测器606皆以相同方式形成,该第二例1100的InGaN/GaN LED 1102和InGaN/GaN光探测器1104,尽管在器件叠层的底部共用共同的多个层,但整体结构稍有不同。具体地,所述共同的多个层为所述p-GaN层1102a、InGaN MQW层1102b、n-GaN层1102c以及AlGaN层1102d(均属于所述InGaN/GaN LED 1102)分别地对应于所述第二p-GaN层1104e、InGaN MQW层1104f、第二n-GaN层1104g以及AlGaN层1104h(均属于所述InGaN/GaN光探测器1104)。应当理解形成所述具有不同结构的InGaN/GaN LED 1102和InGaN/GaN光探测器1104具有某些优点和缺点。例如,就该InGaN/GaN光探测器1104而言,将该InGaN层1104b设置在该InGaN MQW层1104f的顶上(并由层1104c-1104e分开)的益处为会对该LED MQW发光波长具有较佳的吸收性,但缺点为该生长工艺和制造工艺会变得较复杂。在其它实施例中,利用如前所述的选择区域再生长,还可选择性生长(该LED和/或光探测器的)一侧或两侧,而使各光电器件可具有不同的结构。
此外,采用SiNx作为用来形成该波导1106的材料,以促进由该InGaN/GaN LED1102发射的可见波长的光的传输。该波导1106通过金属镶嵌(Damascene)工艺来与该InGaN/GaNLED 1102和InGaN/GaN光探测器1104进行集成。当使用波长约400nm至500nm的光波来操作该InGaN/GaN LED 1102时,该波导1106的通常的传送损耗低于1dB/cm。SiON用作一光隔离层1110设置在该波导1106和该Si基底1108中间。该SiON的可调谐折射率还可提供一灵活的设计尺寸。模拟显示若该波导1106构制成具有一500nm的长度及一200nm的核芯尺寸(而SiON的n=1.8且SiO2用作上覆层),则其仅会支持具有高限制因子(即大于80%)的基本TE和TM模式。该InGaN/GaN LED 1102、波导1106和InGaN/GaN光探测器1104之间的耦接损耗性能被评估为小于1dB。请参阅图11b,在所发射的光进入该InGaN/GaN光探测器1104之后,该光首先会在下方的发光层(即所述InGaN MQW层1104f)中传送一小段距离,然后耦接于上光探测器层(即所述InGaN层1104b)中。应当理解该上光探测器层(即所述InGaN层1104b)和发光层(即所述InGaN MQW层1104f)中的铟成分转变还会加强该光探测效率。就此,初步评估显示在大约450nm的光波长时,可达到约0.03A/W至0.3A/W之间的响应度。
其余的构造将会在下文中进行描述。为了简明的原因,在所述不同构造之间共同的相似元件、功能和操作不再重复说明;参照说明将会取代地对相关构造的类似部件做调整。
应当理解光子式片上网络(NoC)的传统设计通常使用激光作为发光源,且微环共振器作为调制器、探测器和路由器等。特别地,传统的光子式NoC构制成能以相应的滤波器来杠杆化操作多个波长,且同样设置有NoC结构,例如总线和令牌环等,其能形成一对多的连接。但不同于所述传统设计,因(使用于所提供的集成电路中的)LED为非相干光源,且基于LED的电路不能使用谐振器件,故容许以超低功率在一对一的连接上作多流路的多工运作的NoC结构会被替代地采用,从而能够适配所提供的集成电路的应用。例如,可采用常用于现代多核处理器的具有网络拓扑的NoC,而以图1所示方法的步骤104中提供的各基于LED的光学互连件来替代一对一的基于金属的电互连件(其会连结相邻的内核)。此外,应当理解传统的位于处理器的各内核的电气路由器能够轻易地处理所述一对一连接上的多个流路的仲裁。但此会导致高电能消耗,因为在每个路由运作中的电气路由器上都有光-电-光转换和电缓冲/切换,其会导致所提供的集成电路的基于LED的光学互连件在用于长距离晶片间通信时,其有益效果降低。
在另一实施例中,如图12a所示,采用了根据称为单周期多跳异步中继传输(SMART)1200的NoC结构的一变化例,该结构1200原本在文献中提出时是用于电气的无时钟重复链路,以实现跨整个芯片(即完整地由源至目标)的一单周期数据路径。作为背景,该SMART微结构1200使得消息能被动态地仲裁,并通过共享的网络组织产生跨所需芯片的多跳旁通链路。只有出现拥堵时,消息才会在中间的路由器上缓冲。通过绕过中间的电气路由器,消息能够直接由源路由器穿行至目的路由器,从而避免在大部分情况下中间路由器的高能量消耗。尽管原本是作为打破NoC延迟壁垒的解决方案而提出,该SMART微结构1200仍会消耗28-32fJ/bit/mm,使得最坏的情况下要以600fJ的传输能量来在一典型的20mm×20mm尺寸的芯片上将一个比特从一芯片边缘传输至另一芯片边缘。
相应地,在本实施例中可设想,在所述SMART微结构1200中采用基于LED的光学互连件(如通过图1所示方法的步骤104所提供),可进一步打破片上通信的功率壁垒。针对于此,图12b示出一变型的SMART微结构1250(基于SMART微结构1200),其中将SMART微结构1200的旁通链路替换为所述的基于LED的光学互连件(如可通过图1所示方法形成)。此SMART微结构1250会有利地使得光子的与距离无关的低功率传输能进行杠杆化操作。而且,图1的方法也可有利地使所述基于LED的光学互连件能与所述Si-CMOS路由器和处理器近距离地集成。
为供比较,采用DSENT(一种定时驱动的NoC功率模拟软件)对所提出的基于LED的光学互连件与45nm节点的基线电子无时钟重复互连件和激光使能光学互连件的能量效率进行了评估(即全部被模拟在一1GHz的操作频率),对应的性能结果示于图13a的一图表1300中。具体地,该激光使能光学互连件被模拟为具有芯片外激光器、微环调制器、接收器和外围电子器件的构成。在DSENT中,采用电LED模型来估计该Si-驱动器的尺寸。具体地,根据该LED的有效电容(即大约6.3fF)和所述通孔的寄生电容(即大约1.7fF)来确定该Si-驱动器的尺寸及其相应的功率消耗。此外,波导损耗设定为1dB/cm,且该光探测器的响应度对于一Ge探测器设定为1A/W,或对于一InGaN探测器设定为0.3A/W。在与相应的互连件的长度有关的一短距离内(即小于8mm),大部分的操作功率被光学互连件中的电驱动和漏电所消耗。因此,在图13a中示出该电子互连件的能量消耗会直线地增加,而该基于LED的光学互连件/激光使能光学互连件会保持几乎固定不变的能量消耗,且与传送距离无关。如图13a中清楚地可见,所提供的基于LED的光学互连件以38fJ/b的功率效率轻松地超越了该电子互连件/激光使能光学互连件的性能。
图13b为一图表1350,显示了在一64核处理器上使用SPLASH-2应用程序对该SMART微结构1200和变型的SMART微结构1250的归一化动态网络能量性能进行比较的结果。具体地,全部64线的SPLASH-2应用程序的并行段在一8×8多核处理器上共用L2高速缓存来执行,然后对该多个应用程序的结果取平均值。采用两个电气NoC基线:具有单周期流水线路由器的现有NoC,及基于SMART微结构1200的NoC。全部的结果相对于该单周期路由器进行归一化。应当理解所述两个电气NoC基线都已高度最佳化,且在延迟和能量上更胜过目前的工业用芯片模型,例如具有3周期路由器的Intel 48核SCC。性能方面,该SMART微结构1200可达到比该单周期路由器电气基线低五至八倍的延迟,而该变型的SMART微结构1250能够保持如图13b中所示的性能优势。该SMART微结构1200具有一稍优于该基线单周期路由器的能量优势,这是因为省去了在中间路由器的缓冲,而该变型的SMART微结构1250可基本将链路和交叉开关矩阵的动态能量消耗分别减少68%和37%,因此在全部的应用程序上比该SMART微结构1200大约节省28%的总体能量。
总的来说,随着多核处理器的发展,对于低功耗的片上通信的市场需求也逐步增加,图1所示的方法能实现符合该目的的具有基于LED的光学互连件的集成电路。特别是所提供的方法使用一单片集成工艺来键合一III-V基底及一硅基底,其有利地能与传统的CMOS工艺直接地兼容。故其不需要对现有的CMOS制造技术进行昂贵且复杂的重构,并且易于与所述CMOS制造技术集成从而方便量产。对于所提供的方法,特别地提出一中晶圆上集成技术,其中,所述晶体管200由CMOS工艺制成,所述光电器件300形成为III-V半导体。故使用图1所示的方法,可形成基于LED的光学互连件,其中各基于LED的光学互连件包括至少一直接调制的高速LED(其可通过III-氮化物来形成),及一对应的光探测器,它们共同由一中间波导耦接。作为信息,应当理解使用基于氮化物的材料(III-V族材料)形成的LED比使用其它III-V材料所形成的LED更为可靠且实用。应当理解,与传统的基于电气互连件的设计相比,所提出的用于片上网络的基于LED的光学互连件可使多核处理器(具有连结不同的内核的片上网络)具有更低的能量消耗、更高的带宽密度、更小的覆盖面积以及改善的性能。此外,由于在所述小尺寸的LEDs中有效率的散热是更具挑战性的,对所述基于LED的光学互连件来说,热效应可能更突显,但是此发热问题可通过所述光电器件300改良的封装而轻易地解决。
广义而言,该集成电路包括至少一个设置在一经部分处理的CMOS基底中的晶体管200;及至少一对可适于以一波导进行耦接的光电器件300,所述波导及光电器件300共同设置在一半导体基底上。该半导体基底设置成邻接于该经部分处理的CMOS基底。所述光电器件也电连接于该晶体管,且所述光电器件由一不同于硅的晶圆材料形成。
附加地,图1所示的方法可有利地解决以下传统方案所面临的问题。
问题1
在一个集中化的工艺平台上来实现包括高速LED和探测器,及可见光透明的波导等的多种光子器件是具挑战性的。硅通常被视为可供构建光电器件的未来平台的一种选择,能够适配Si-CMOS晶体管以及集成的光子元件。但是,因硅具有一间接的带隙,其只能提供活动电荷载体与光子之间很微弱的交互作用,故用硅来制造主动光子器件(如LED)会有障碍。
对问题1的解决方案
因III-V材料特别适合用于制造光电器件,故图1所述方法提出制成片上基于LED的光学互连件,如图1的步骤104中所述,其中晶体管通过CMOS工艺来形成,而所述光电器件由III-V材料所形成(即参见图1-5)。
问题2
用以制成片上光学互连件的传统方案倾向于依赖利用芯片外激光作为发光源,但以此方法会有一些不利之处。首先,由于激光的高阈值电流会导致激光消耗超大量的功率;即使当所述互连件被间断地使用时,不论通过所述光学互连件的实际数据传输如何,所述激光的功率消耗仍会如同通信数据在所述连续的波长上被由外部调制般地保持固定不变,而造成高激光功率消耗。其次,外部调制器需要具有若干放大级的驱动器,其会消耗大量的驱动功率,特别是用于具有严苛驱动需求的高数据速率调制。而且,调制器的插入损耗(其通常大于5dB)会劣化该光学功率预算,故甚至需要来自所述激光的更大的输出功率。
对问题2的解决方案
以所提供的方法,用于片上光学互连件的替代发光源被设想为:直接调制的LED。首先,LED可作为不用阈值电流来开启的可靠发光源。特别地,当LED的操作电压高于称为启动电压(ToV)的最小阈值时,则该电流和光输出会随着电压呈指数地增加。在低于该ToV值时,该LED会被关闭,且通过该LED的仅为可忽略的电流,故仅消耗和发散最少的功率。其次,通过在所述片上光学互连件中使用LED也可本质上减少功率消耗,因为不再需要外部调制器。
问题3
InGaN/GaN MQW LED结构一般用作固态光源。但是,具有上述结构的LED通常设计为供屋内灯具使用。就片上通信而言,通常期望采用尽量高的调制带宽。但应当理解,LED即便构制成具有较低的调制带宽,即使低于1Gb/s,仍可有效地用于片上通信。作为比较,现代的电信激光通常具有大于40Gb/s的带宽。
对问题3的解决方案
带宽限制基本上由所注入的电子或空穴的自然放射性重组寿命时间来决定,可推测在纳秒(ns)范围内。但是,近来已经成功实现(记载在文献中)通过增加电子和空穴的有源层浓度,或通过改善双分子重组的方式来将LED驱动至高频率。因此根据图1所提供的方法,用于片上通信集成的InGaN MQW微尺寸LED是可实现且易行的。例如,一10μm×10μm LED的频率响应,经由模拟评估,被判定能达到5GHz以上。并且,具有较小尺寸的LED可获得3dB更高的带宽还可以较小的LED中具有更强的放射重组率来解释,其与对一具有5μm直径的单个微碟蓝光LED所作的实验测量十分吻合(根据文献)。
问题4
如何以既知的方案来方便且低成本地将(硅基)晶体管与光电器件集成在一起是一个问题。
对问题4的解决方案
使用图1所提供的方法,该InGaN/GaN光探测器和InGaN/GaN LED可通过单个外延生长工艺来制造,而能实现该基于LED的光学互连件的光探测和发射。所述光发射和吸收层(例如分别参见图11a中的InGaN层1104b和InGaN MQW层1104f)间有效率的光耦接,会确保下方的光发射层(例如图11a的InGaN MQW层1104f)中具有低损耗的高效率探测。该吸收层为该光探测层的另一名称。经由性能模拟,已确定与波导(例如由SiNx制成)集成的InGaN/GaN光探测器具有比正常入射探测器更高的响应度,因为在该吸收层(例如图11a的InGaN层1104b)中的光传送距离更长。该高响应度表示须要较少的光功率来促成信号接收,因此能够减少该系统的功率预算。该低损耗的波导(即工作在400nm至500nm的光波长下具有一小于1dB/cm的损耗),及有源和无源器件之间的低耦接损耗(即小于1dB)对保证该光学互连件(如通过所提供的方法形成)的低功率操作是很重要的。
问题5
业界公认电互连件所消耗的功率与所述电互连件的电容、供给电压和时钟频率有关。由于电容会随着该互连件的长度和所设定的时钟频率(其会影响该互连件的带宽)而增加,故一电互连件的功率消耗会随着距离和带宽而增长。此外,为能改良该互连件延迟,长导线通常会被分段成较小段,并以重发器并入其间,故会增加总体导线耦接电容及该互连件的功率消耗。即使以积极性的设计,一电气互连件通常仍会消耗大约28-32fJ/bit/mm,使得最坏的情况下要以600fJ的传输能量来在一典型的20mm×20mm尺寸的芯片上将一个数据比特从一芯片边缘传输至另一芯片边缘。
对问题5的解决方案
使用图1所提供的方法,可通过将LED使能的光学互连件与CMOS晶体管(它们是基于电的)相集成来改善片上通信的功率效率。具体地,所提供的方法能使所述LED使能的光学互连件与所述CMOS晶体管近距离地集成。如图2和图3中所示,所述CMOS晶体管形成在该Si-CMOS基底202上,而所述光电器件和波导则形成在该III-V基底302上。此外,如前面讨论的,图12b示出该变型的SMART微结构1250,其可适合于利用所述基于LED的光学互连件(如通过所提供的方法形成)。具体地,旁通链路被包含LED、波导和耦接器的光学互连件所取代,从而能有效地杠杆化光子数据通信所提供的与距离无关的低功率传输特性。
虽本发明已在所述图式和以上说明中详细示出并描述,但所述图式和描述视为说明或举例的,而非限制的;本发明并不限制于所公开的实施例。对所公开实施例的其它变型能被本领域技术人员在实行所请求的发明时所理解并作成。
例如,对于该集成电路,并非全部的互连件皆被形成为该基于LED的光学互连件。即,可以灵活地将一些互连件形成为传统的电气互连件,而其它的互连件则形成为根据图1所示方法的步骤106的基于LED的光学互连件。此外,可视需要而使用适合于图1的方法的其它III-V材料,例如InGaP(以适配红色区域中的波长),或GaAs/AlGaAs/InGaAs(以适配近红外线区域中的波长,即850nm,1310nm,1550nm)。同样地,应当理解基于LED的光学互连件本质上是双向的:该LED和对应的光探测器为相同的器件,只是在不同的偏压状态下操作。此外,应当理解上述情况对于图6中所示的示意结构是适用的,但对图11a来说可能不适用,因为图11a中的InGaN/GaN LED 1102和InGaN/GaN光探测器1104具有不同的结构。尽管如此,该InGaN/GaN LED 1102和InGaN/GaN光探测器1104理论上仍可被双向地操作,尽管在各方向可能具有不同的连结性能。并且,各基于LED的光学互连件并不限于形成为一对一(即点对点)的连接;该基于LED的光学互连件事实上可形成为一对多的连接、多对一的连接或多对多的连接(虽然后两种连接可能须要利用时间多工技术)。此外,若采用OLED取代LED作为所述光电器件300,则适合的有机材料会被用于该III-V基底302上。再者,其也可使用选择区域再生长,而在进行图3a的步骤1042之前,于该III-V基底302顶部来形成所需的器件凸台。根据一变化例,图14为列示出用于该InGaN LED 700部件的各种举例设计参数的表1400。如所理解,图14中的设计参数基本是在前述用于图10的表1000的所述参数上改良。

Claims (25)

1.一种形成集成电路的方法,其特征在于,包括:
i)由设置在一半导体基底上的至少一第一晶圆材料形成至少一对光电器件,所述第一晶圆材料不同于硅;
ii)刻蚀所述第一晶圆材料以形成第一凹槽,供一第二材料填充;
iii)处理所述第二材料以形成用于耦接所述至少一对光电器件的一波导,从而定义一光学互连件;以及
iv)将具有至少一个晶体管的至少一个经部分处理的CMOS器件层与所述半导体基底相键合,以形成集成电路,该经部分处理的CMOS器件层与该光学互连件邻近设置。
2.如权利要求1所述的方法,其特征在于,不同于硅的所述第一晶圆材料包括III-V族半导体材料或有机材料。
3.如权利要求2所述的方法,其特征在于,所述III-V族半导体材料包括GaN、InGaP、GaAs、AlGaAs或InGaAs。
4.如前述任一项权利要求所述的方法,其特征在于,所述第二材料包括氮化硅。
5.如前述任一项权利要求所述的方法,其特征在于,将该经部分处理的CMOS器件层与该半导体基底相键合包括处理该经部分处理的CMOS器件层以提供能触及该光学互连件的第二凹槽,并以一电绝缘材料填充该第二凹槽;及处理该电绝缘材料来电连接所述至少一个晶体管与所述至少一对光电器件以形成该集成电路。
6.如权利要求5所述的方法,其特征在于,该电绝缘材料包括二氧化硅。
7.如前述任一项权利要求所述的方法,其特征在于,所述光电器件选自光探测器和发光器件。
8.如权利要求7所述的方法,其特征在于,所述发光器件包括发光二极管或有机发光二极管。
9.如前述任一项权利要求所述的方法,其特征在于,还包括:对另一半导体基底执行CMOS工艺,以获得具有所述至少一个晶体管的所述至少一个经部分处理的CMOS器件层;及从该另一半导体基底移除该经部分处理的CMOS器件层。
10.如权利要求9所述的方法,其特征在于,该另一半导体基底包括一绝缘体上硅基底。
11.如前述任一项权利要求所述的方法,其特征在于,还包括:
在形成所述至少一对光电器件之后,沉积一电绝缘材料来覆盖该第一晶圆材料;以及
使用化学机械抛光法来平坦化所沉积的电绝缘材料。
12.如前述任一项权利要求所述的方法,其特征在于,还包括:
在该第一凹槽填充该第二材料之后,使用化学机械抛光法平坦化该填充有所述第二材料的所述第一凹槽。
13.如前述任一项权利要求所述的方法,其特征在于,处理所述第二材料以形成该波导包括使用光刻和/或刻蚀。
14.如前述任一项权利要求所述的方法,其特征在于,还包括:
在形成该波导之后,沉积一电绝缘材料来覆盖所述第一晶圆材料和第二材料;以及
使用化学机械抛光法来平坦化所沉积的电绝缘材料。
15.如权利要求5所述的方法,其特征在于,处理该经部分处理的CMOS器件层来提供该第二凹槽包括使用刻蚀和/或机械研磨。
16.如权利要求5所述的方法,其特征在于,还包括:
使用化学机械抛光法来平坦化该经部分处理的CMOS器件层和填充有所述电绝缘材料的第二凹槽。
17.如权利要求5所述的方法,其特征在于,处理所述电绝缘材料来电连接该至少一个晶体管和所述至少一对光电器件包括在该电绝缘材料中形成多个通孔,并以一导电材料填充所述通孔。
18.如前述任一项权利要求所述的方法,其特征在于,将该经部分处理的CMOS器件层与该半导体基底相键合包括将该光学互连件设置于该经部分处理的CMOS器件层下方。
19.如前述任一项权利要求所述的方法,其特征在于,所述至少一第一晶圆材料包括多层晶圆材料,每一层由一不同的材料形成。
20.一种集成电路,其特征在于,包括:
至少一个晶体管,设置在一经部分处理的CMOS器件层中;以及
至少一对光电器件,由一波导耦接而在一半导体基底上定义一光学互连件,所述半导体基底与该经部分处理的CMOS器件层邻近设置;
其中所述光电器件用于电连接至该晶体管,且所述光电器件由不同于硅的至少一第一晶圆材料所形成;以及
其中该波导由第二材料形成,该第二材料沉积在形成于所述第一晶圆材料中的第一凹槽内。
21.如权利要求20所述的集成电路,其特征在于,该不同于硅的第一晶圆材料包括III-V族半导体材料或有机材料。
22.如权利要求21所述的集成电路,其特征在于,所述III-V族半导体材料包括GaN、InGaP、GaAs、AlGaAs或InGaAs。
23.如权利要求20至22中任一项所述的集成电路,其特征在于,该集成电路形成为单个处理器或一处理器的一部分。
24.如权利要求20至23中任一项所述的集成电路,其特征在于,该光学互连件设置于该经部分处理的CMOS器件层下方。
25.如权利要求20至24中任一项所述的集成电路,其特征在于,所述第二材料包括氮化硅。
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