CN113809070A - 一种基带rf一体化集成结构及集成方法 - Google Patents
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
本发明涉及一种基带RF一体化集成结构及集成方法。其包括基带芯片逻辑器件和射频器件;基带芯片逻辑器件采用FinFET结构;射频器件采用平面场效应晶体管;射频器件集成于基带芯片的上方,并且通过层间介质隔离;层间介质中设有通孔,使射频器件与基带芯片逻辑器件互连。集成方法包括:提供具有FinFET结构的基带芯片逻辑器件;在基带芯片逻辑器件上方形成层间介质层;形成半导体层;制作平面场效应晶体管,形成射频器件;刻蚀通孔,填充、金属化,使器件互连。本发明采用单片三维工艺集成,二者的物理距离大大缩短,提高了信号传输速度和降低了功耗,并且兼具FinFET基带芯片与FD SOI射频器件的优良特性。
Description
技术领域
本发明涉及射频电路领域,特别涉及一种基带RF一体化集成结构及集成方法。
背景技术
随着通信制式升级,射频前端价值量提升。5G频谱提升带来射频器件材料和工艺发生变化。比如,基于传统GaAs-HEMT工艺的射频开关面临淘汰,RF SOI成为射频开关的主流工艺;RF SOI工艺也成为射频低噪声放大器的主流工艺。总之,RF SOI在5G中重要性日益凸显。另一方面,5G时代终端小型化,尤其是消费电子智能手机端,射频前端模组化程度越来越高,射频与基带一体化集成成为趋势,然而现有技术中射频与基带仍是以分立为主。
发明内容
本发明的主要目的在于提供一种基带RF一体化集成结构及其集成方法,实现了基带与RF的三维一体化集成。
为了实现以上目的,本发明提供了以下技术方案。
一种基带RF一体化集成结构,包括基带芯片逻辑器件和射频器件;
所述基带芯片逻辑器件采用FinFET结构;
所述射频器件采用平面场效应晶体管;
所述射频器件集成于所述基带芯片的上方,并且通过层间介质隔离;
所述层间介质中设有通孔,所述通孔填充有导电材料,使所述射频器件的平面场效应晶体管与所述基带芯片逻辑器件实现互连。
基带RF一体化集成结构的集成方法,包括:
提供具有FinFET结构的基带芯片逻辑器件;
在所述基带芯片逻辑器件上方形成层间介质层;
在所述层间介质层上形成半导体层;
在所述半导体层上制作平面场效应晶体管,形成射频器件;
在所述层间介质层中刻蚀通孔,向所述通孔内填充导电材料,使所述射频器件与所述基带芯片逻辑器件形成互连。
与现有技术相比,本发明第一层采用成熟FinFET CMOS工艺制备基带数字芯片,第二层采用SOI CMOS工艺制备低功耗RF芯片及RF前端,二者采用三维顺序加工方式,这种集成结构及方法具有以下优势:
(1)基带芯片逻辑器件采用现有成熟FinFET,具备高速的信息处理能力;
(2)RF器件采用SOI源漏平面器件,具有低的寄生电阻,截止频率高;
(3)信号处理单元和RF模块采用单片三维工艺集成,二者的物理距离大大缩短,提高了信号传输速度和降低了功耗;
(4)单片三维集成上层是天然的类SOI,分别结合FinFET的高开关电流特性和SOI器件的优良RF特性,形成基带RF一体化集成。
附图说明
通过阅读下文优选实施方式的详细描述,各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的,而并不认为是对本发明的限制。
图1为本发明提供的基带RF一体化集成结构示意图;
图2至图7为本发明提供的基带RF一体化集成结构的制备方法各步骤形成的结构示意图。
具体实施方式
以下,将参照附图来描述本公开的实施例。但是应该理解,这些描述只是示例性的,而并非要限制本公开的范围。此外,在以下说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的,其中为了清楚表达的目的,放大了某些细节,并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的,实际中可能由于制造公差或技术限制而有所偏差,并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中,当将一层/元件称作位于另一层/元件“上”时,该层/元件可以直接位于该另一层/元件上,或者它们之间可以存在居中层/元件。另外,如果在一种朝向中一层/元件位于另一层/元件“上”,那么当调转朝向时,该层/元件可以位于该另一层/元件“下”。
射频与基带芯片分立不利于设备微型化,并且二者间的电阻会增大,增加了器件缺陷的风险,为此,本发明提供了以下的基带RF集成结构。
一种基带RF一体化集成结构,如图1所示,其包括基带芯片逻辑器件1和射频器件2。
其中,所述基带芯片逻辑器件1采用FinFET结构,位于第一层。FinFET类似鱼鳍的3D结构,其沟道由绝缘衬底上凸起的高而薄的鳍构成,这种鳍形结构增大了栅围绕沟道的面,加强了栅对沟道的控制,从而可以有效缓解短沟道效应,大幅改善电路控制并减少漏电流,也可以大幅缩短晶体管的栅长,也正由于该特性,FinFET无须高掺杂沟道,因此能够有效降低杂质离子散射效应,提高沟道载流子迁移率,更具备高速的信息处理能力,将其用于基带芯片具有显著优势。
所述射频器件2采用平面场效应晶体管;由于平面场效应晶体管的P-n结没有暴露在外,因此稳定性和可靠性更高,具有低的寄生电阻和高的截止频率,尤其是FD-SOI用一个非常薄的硅膜制作晶体管沟道,因为沟道非常薄,无需对通道进行掺杂工序,耗尽层充满整个沟道区,具有背面偏置能力,极好的晶体管匹配特性,可使用接近阈值的低电源电压,对辐射具有超低的敏感性,以及具有非常高的晶体管本征工作速度等,这些优点使得它能工作在毫米波频段的应用中。
所述射频器件2集成于所述基带芯片的上方,即位于第二层,射频器件与基带芯片之间通过层间介质隔离;该层间介质就可以作为FD-SOI的天然埋氧层,缩短了射频器件与基带芯片的垂直距离,提高了信号传输速度和降低了功耗。该层间介质可以是典型的氧化硅、金属氧化物、氮氧化物等。
所述射频器件2中的源漏优选采用金属化源漏,以降低上层器件制备工艺热预算(≤500℃),避免下层基带芯片逻辑器件性能发生退化。
同时,所述层间介质中设有通孔,所述通孔填充有导电材料,使所述射频器件的平面场效应晶体管与所述基带芯片逻辑器件实现互连。导电材料可以是多晶硅、金属硅化物、金属、金属复合物等。
本发明提供的以上基带RF一体化集成结构可采用如下的方法集成。
首先,提供具有FinFET结构的基带芯片逻辑器件1。FinFET可采用常规的工艺制程,例如其前段工艺包括HKMG技术和应变硅技术等,后段包括大马士革结构的制程等,本发明对此不作限制,无论采用哪种具体工艺,形成如图2所示的基带芯片逻辑器件,包括衬底101、衬底上的浅沟槽隔离102、高k绝缘的栅103(HKMG)、通孔刻蚀停止层104(CESL)、接触孔106等基本结构。
然后在所述基带芯片逻辑器件1上方形成层间介质层105,如图2所示,层间介质的材料包括但不限于典型的氧化硅SiO2或金属氧化物(例如Ta2O5、TiO2、氮化钛、Al2O3、Pr2O3、La2O3、LaAlO3、HfO2、ZrO2等高k介质材料)等。层间介质层的形成方法包括但不限于氧化法、LPCVD、RTCVD、PECVD、原子层沉积等工艺。
接下来在层间介质层105上形成半导体层201,如图3所示,该半导体层201通常为低温半导体,形成方法包括但不限于LPCVD、RTCVD、PECVD、原子层沉积等沉积法或键合法,工艺温度优选控制在500℃以下。半导体的材料包括但不限于典型的硅、GaAs、锗、锗硅等。
之后在半导体层201上制作出有源区,如图4所示,可以借助光刻、刻蚀等手段。
接下来在有源区上依次制作假栅202、源漏扩展区(SDE)、侧墙203等,如图5所示。假栅202可以是多晶硅等半导体材料。侧墙203可选用典型的氧化硅SiO2或金属氧化物(例如Ta2O5、TiO2、氮化钛、Al2O3、Pr2O3、La2O3、LaAlO3、HfO2、ZrO2等高k介质材料)或者氮化物等,层数不受限,一层或多层。
然后在假栅202两侧的半导体层上利用低温全硅化工艺形成金属化源漏204,如图5所示,并在硅化物中分别掺杂N+、P+,FD SOI金属源漏器件减小了寄生电阻,具有高的截止频率。
之后去除假栅202,生长栅介质207和金属栅206,如图6所示,在这一步工艺中会形成层间介质205,以保护金属源漏结构等有源区。栅介质207可以是氧化硅SiO2或金属氧化物(例如Ta2O5、TiO2、氮化钛、Al2O3、Pr2O3、La2O3、LaAlO3、HfO2、ZrO2等高k介质材料)
此时已完成平面场效应晶体管的制作,即射频器件。在晶体管表面形成绝缘层,以隔绝保护。
然后如图7所示,形成通孔208,填充,完成源漏、栅的金属化。如图1所示,之后还有继续形成通孔209,填充,实现射频器件与基带芯片的互连。
最后还可以在整体集成结构上形成一层绝缘保护层210,如图1所示。
上述制作栅极的流程仅仅为列举,本发明对此并不作限制。
本发明上述方法制备的集成结构可用于多个领域,尤其是智能手机端。
以上对本公开的实施例进行了描述。但是,这些实施例仅仅是为了说明的目的,而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围,本领域技术人员可以做出多种替代和修改,这些替代和修改都应落在本公开的范围之内。
Claims (10)
1.一种基带RF一体化集成结构,其特征在于,包括基带芯片逻辑器件和射频器件;
所述基带芯片逻辑器件采用FinFET结构;
所述射频器件采用平面场效应晶体管;
所述射频器件集成于所述基带芯片的上方,并且通过层间介质隔离;
所述层间介质中设有通孔,所述通孔填充有导电材料,使所述射频器件的平面场效应晶体管与所述基带芯片逻辑器件实现互连。
2.根据权利要求1所述的基带RF一体化集成结构,其特征在于,所述射频器件中的平面场效应晶体管的源漏为金属源漏。
3.基带RF一体化集成结构的集成方法,其特征在于,包括:
提供具有FinFET结构的基带芯片逻辑器件;
在所述基带芯片逻辑器件上方形成层间介质层;
在所述层间介质层上形成半导体层;
在所述半导体层上制作平面场效应晶体管,形成射频器件;
在所述层间介质层中刻蚀通孔,向所述通孔内填充导电材料,使所述射频器件与所述基带芯片逻辑器件形成互连。
4.根据权利要求3所述的集成方法,其特征在于,制作所述平面场效应晶体管中栅极的方法包括:
制作假栅和栅极侧墙;
去除假栅,依次生长栅介质和金属栅。
5.根据权利要求4所述的集成方法,其特征在于,制作所述平面场效应晶体管中源漏的方法包括:
对所述假栅两侧的所述半导体层进行金属硅化处理,并进行掺杂,形成金属源漏。
6.根据权利要求5所述的集成方法,其特征在于,所述源漏的制作在所述去除假栅之前进行。
7.根据权利要求3所述的集成方法,其特征在于,形成半导体层的方法为:
沉积法或键合。
8.根据权利要求7所述的集成方法,其特征在于,所述沉积或键合的温度≤500℃;
和/或,所述平面场效应晶体管的制备工艺温度≤500℃。
9.根据权利要求3所述的集成方法,其特征在于,制作平面场效应晶体管之后,还在其表面形成绝缘层,并且之后刻蚀的所述通孔贯穿绝缘层和所述层间介质层。
10.根据权利要求3所述的集成方法,其特征在于,在实现互连后还在所述集成结构的表面形成绝缘层。
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CN114530447B (zh) * | 2022-04-24 | 2022-10-25 | 合肥晶合集成电路股份有限公司 | 半导体结构及其制作方法 |
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