CN106158824B - 集成电路封装件及其形成方法 - Google Patents

集成电路封装件及其形成方法 Download PDF

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Publication number
CN106158824B
CN106158824B CN201510171945.4A CN201510171945A CN106158824B CN 106158824 B CN106158824 B CN 106158824B CN 201510171945 A CN201510171945 A CN 201510171945A CN 106158824 B CN106158824 B CN 106158824B
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connector
redistributing layers
redistributing
layers
tube core
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CN106158824A (zh
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黄麟智
邓宏安
陈新瑜
吴仓聚
谢政杰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了集成电路封装件及其形成方法。在载体上形成一个或多个再分布层。在RDL的第一侧上形成第一连接件。使用第一连接件将管芯接合至RDL的第一侧。在RDL的第一侧上和管芯周围形成密封剂。从上面的结构剥离载体，以及在RDL的第二侧上形成第二连接件。切割产生的结构以形成单独的封装件。

Description

集成电路封装件及其形成方法
技术领域
本发明涉及集成电路器件，更具体地，涉及集成电路封装件及其形成方法。
背景技术
由于各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成度的不断改进，半导体工业已经经历了快速增长。在大多数情况下，集成度的这种改进来自最小部件尺寸的反复减小(例如，朝着亚20nm节点缩小半导体工艺节点)，这允许更多的部件集成到给定区域内。由于近来对微型化、更高的速度和更大的带宽以及更低的功耗和延迟的需求增长，所以对半导体管芯的更小和更具创造性的封装技术的需求也增长。
随着半导体技术进一步发展，堆叠半导体器件(例如，3D集成电路(3DIC))已经作为有效替代出现以进一步减小半导体器件的物理尺寸。在堆叠半导体器件中，晶圆/管芯堆叠在彼此的顶部并且使用诸如通孔(TV)的连接件互连。例如，3DIC的一些益处包括展示出较小的覆盖区域、通过减小信号互连件的长度减小功耗、以及改进良率和制造成本(如果在组装之前单独地测试各个管芯)。
发明内容
为了解决现有技术中存在的问题，提供了一种方法，包括：在载体上方形成一个或多个再分布层(RDL)；在所述一个或多个RDL的第一侧上形成第一连接件；使用所述第一连接件将管芯接合至所述一个或多个RDL的所述第一侧；在所述一个或多个RDL的所述第一侧上和所述管芯周围形成密封剂；在形成所述密封剂之后，从所述一个或多个RDL分离所述载体；以及在所述一个或多个RDL的第二侧上形成第二连接件，所述第二侧与所述第一侧相对，其中，所述第二连接件大于所述第一连接件。
在上述方法中，其中，所述方法还包括：在所述载体上形成释放层；在所述释放层上形成晶种层；以及在所述晶种层上形成凸块下金属(UBM)，其中，所述UBM介于所述晶种层和所述一个或多个RDL之间。
在上述方法中，其中，所述密封剂的部分介于所述管芯和所述一个或多个RDL之间并且围绕所述第一连接件。
在上述方法中，其中，所述一个或多个RDL包括位于所述一个或多个RDL的所述第一侧上的第一互连件和位于所述一个或多个RDL的所述第二侧上的第二互连件，所述第二互连件的间距大于所述第一互连件的间距。
在上述方法中，其中，所述一个或多个RDL包括位于所述一个或多个RDL的所述第一侧上的第一互连件和位于所述一个或多个RDL的所述第二侧上的第二互连件，所述第二互连件的间距大于所述第一互连件的间距，其中，使用双镶嵌技术形成所述第一互连件和所述第二互连件。
在上述方法中，其中，所述一个或多个RDL包括位于所述一个或多个RDL的所述第一侧上的第一互连件和位于所述一个或多个RDL的所述第二侧上的第二互连件，所述第二互连件的间距大于所述第一互连件的间距，其中，所述第一互连件和所述第二互连件包括阻挡/晶种层。
在上述方法中，其中，所述第一连接件是微凸块。
在上述方法中，其中，所述第二连接件是球栅阵列(BGA)连接件。
根据本发明的另一方面，提供了一种方法，包括：在载体上形成凸块下金属(UBM)；在所述UBM上形成一个或多个再分布层(RDL)，所述UBM电连接至所述一个或多个RDL；在所述一个或多个RDL上形成第一连接件，其中，所述UBM和所述第一连接件位于所述一个或多个RDL的相对两侧上；使用所述第一连接件将管芯接合至所述一个或多个RDL；在所述一个或多个RDL上形成密封剂，其中，所述密封剂的部分介于所述管芯和所述一个或多个RDL之间；在形成所述密封剂之后，从所述UBM分离所述载体；以及在所述UBM上形成第二连接件。
在上述方法中，其中，形成所述UBM包括在所述载体上形成晶种层。
在上述方法中，其中，所述方法还包括实施分割以形成封装件，每个封装件均包括至少一个所述管芯。
在上述方法中，其中，所述第一连接件的间距小于所述第二连接件的间距。
在上述方法中，其中，所述第一连接件是微凸块。
在上述方法中，其中，所述第二连接件是球栅阵列(BGA)连接件。
根据本发明的又一方面，提供了一种器件，包括：一个或多个再分布层(RDL)，所述一个或多个RDL具有第一侧和与所述第一侧相对的第二侧；第一连接件，位于所述一个或多个RDL的所述第一侧上，其中，所述第一连接件由第一低温回流材料形成；第二连接件，位于所述一个或多个RDL的所述第二侧上，其中，所述第二连接件大于所述第一连接件，并且其中，所述第二连接件由第二低温回流材料形成；管芯，附接至所述第一连接件；以及密封剂，位于所述一个或多个RDL的所述第一侧上，其中，所述密封剂沿着所述管芯的侧壁延伸，并且所述密封剂的至少部分延伸在所述管芯和所述一个或多个RDL之间。
在上述器件中，其中，所述密封剂的最顶面与所述管芯的后侧基本共面。
在上述器件中，其中，所述器件还包括凸块下金属(UBM)，所述UBM介于所述第二连接件和所述一个或多个RDL之间。
在上述器件中，其中，所述第一连接件的间距小于所述第二连接件的间距。
在上述器件中，其中，所述第一连接件是微凸块。
在上述器件中，其中，所述第二连接件是球栅阵列(BGA)连接件。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图9是根据一些实施例的在制造集成电路封装件期间的各个处理步骤的截面图。
图10是根据一些实施例的安装在衬底上的集成电路封装件的截面图。
图11是根据一些实施例的示出形成集成电路封装件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的许多不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，本文中可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。
根据各个实施例，提供了集成电路封装件及其形成方法。具体地，示出了形成集成电路封装件的中间阶段。贯穿各个视图和说明性实施例，相同的参考标号用于指代相同的元件。
图1至图9示出了根据一些实施例的在制造封装件中的中间阶段的截面图。首先参照图1，示出了具有形成在载体101上的释放层103的载体101的部分。载体101可以由石英、玻璃、陶瓷材料等形成并且为随后的操作提供机械支撑。载体101可以具有圆形的平面图形状并且可以是硅晶圆的尺寸。例如，载体101可以具有8英寸的直径、12英寸的直径等。释放层103可以由聚合物基材料形成，释放层103可以与载体101一起从将在随后步骤中形成的上面的结构中去除。在一些实施例中，释放层103可以包括光热转换(LTHC)材料、紫外(UV)粘合剂(当暴露于UV辐射时，其失去粘附特性)、环氧树脂基热释放材料(当暴露于热源时，其失去粘附特性)等。可以使用沉积工艺、旋涂、印刷工艺、层压工艺等形成释放层103。随后可以固化释放层103。在一些实施例中，释放层103的顶面是水平的并且具有高度的共面性，这对形成随后的层可以是有利的。
还参照图1，在释放层103上毯状形成晶种层105。在一些实施例中，晶种层105可以包括铜、钛、镍、金、锰等或它们的组合的一个或多个层，并且可以通过原子层沉积(ALD)、物理汽相沉积(PVD)、溅射等或它们的组合形成。
参照图2，在晶种层105上形成第一介电层201。第一介电层201的底面可以与晶种层105的顶面接触。在一些实施例中，第一介电层201由聚合物形成，该聚合物可以是使用光刻掩模可以被容易地图案化的诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。在可选实施例中，第一介电层201可以包括诸如氮化硅、碳化硅、氧化硅、氮氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等或它们的组合的非可光图案化介电材料。可以通过化学汽相沉积(CVD)、PVD、ALD、旋涂工艺等或它们的组合沉积第一介电层201。
还参照图2，图案化第一介电层201以在第一介电层201中形成诸如第一开口203的开口。因此，通过第一介电层201中的第一开口203暴露晶种层105。在第一介电层201由可光图案化材料形成的实施例中，可以使用合适的光刻技术以将第一介电层201暴露于光来形成第一开口203。在这样的实施例中，在曝光之后显影和/或固化第一介电层201。
图3和图4示出了第一介电层201的第一开口中的凸块下金属(UBM)的形成，诸如第一开口203(见图2)中的UBM 401(见图4)。在一些实施例中，在第一开口203中形成第一导电材料301和第二导电材料303，其中，第二导电材料303过填充第一开口203。第一导电材料301和第二导电材料303可以包括铜、钨、铝、镍、银、金等或它们的组合，并且可以使用电化学镀工艺、化学镀工艺、ALD、PVD等或它们的组合形成。在一些实施例中，晶种层105用作用于镀工艺的晶种层。在一些实施例中，第一导电材料301是镍，并且第二导电材料303是铜。
参照图4，去除过填充第一开口203(见图2)的第二导电材料303的部分，从而使得第二导电材料303的顶面与第一介电层201的顶面基本共面。可以使用蚀刻工艺、平坦化工艺(例如，化学机械抛光(CMP)工艺)等去除过填充第一开口203的第二导电材料303的部分。
参照图5至图7，在第一介电层201和UBM 401上形成一个或多个再分布层(RDL)701。在一些实施例中，RDL 701包括一个或多个介电层以及设置在一个或多个介电层内的一个或多个导电部件。在一些实施例中，使用双镶嵌工艺在一个或多个介电层中形成一个或多个导电部件。在可选实施例中，可以使用其他合适的方法形成该一个或多个导电部件。如下面更详细地描述的，RDL 701提供随后接合的集成电路管芯之间的电界面以及集成电路管芯和外部器件之间的电界面。
首先参照图5，在第一介电层201和UBM 401上形成RDL 701的最底部介电层501。最底部介电层501的材料可以选自与第一介电层201相同的候选材料。图案化最底部介电层501以在最底部介电层501中形成诸如第二开口503的第二开口。在最底部介电层501由可光图案化材料形成的实施例中，可以使用合适的光刻技术以将最底部介电层501暴露于光来形成第二开口503。在这样的实施例中，在曝光之后显影和/或固化最底部介电层501。如图5所示，第二开口503暴露UBM 401。在示出的实施例中，第二开口503包括也可以称为导通孔503L的第一部分503L和也可以称为沟槽503U的第二部分503U。
参照图6，在最底部介电层501中的第二开口中形成导电部件，诸如第二开口503(见图5)中的导电部件601。在一些实施例中，阻挡/晶种层603毯状形成在最底部介电层501上方并且内衬于第二开口503。阻挡/晶种层603可以包括铜、镍、金、锰、钛、氮化钛、钽、氮化钽等或它们的组合的一个或多个层，并且可以通过ALD、PVD、溅射等或它们的组合形成。随后，使用电化学镀工艺、化学镀工艺、ALD、PVD等或它们的组合以诸如铜、钨、铝、镍、银、金等或它们的组合的导电材料填充第二开口503以形成导电部件601。在一些实施例中，导电部件601和阻挡/晶种层603的导电材料可以过填充第二开口503。可以使用蚀刻工艺、平坦化工艺(例如，CMP工艺)等去除过填充第二开口503的导电材料的部分。
还参照图6，导电部件601包括也可以称为导电通孔601L的第一部分601L和也可以称为导电线/迹线601U的第二部分601U。在一些实施例中，导电通孔601L具有介于约10μm和约20μm之间的第一宽度W1，而导电线/迹线601U具有介于约20μm和约100μm之间的第二宽度W2。
参照图7，在最底部介电层501上方形成上介电层703、导电通孔705和导电线/迹线707，这完成RDL 701的形成。在一些实施例中，上介电层703的材料可以选自与第一介电层201和最底部介电层501相同的候选材料。可以使用与上面参照导电部件601(见图5和图6)描述的方法类似的方法在相应的上介电层703中形成导电线/迹线707和导电通孔705，并且本文中不重复该描述。此外，导电线/迹线707和导电通孔705还包括类似于阻挡/晶种层603的阻挡/晶种层(未示出)。在一些实施例中，导电通孔705具有介于约0.2μm和约2μm之间的第三宽度W3，而导电线/迹线707具有介于约10μm和约30μm之间的第四宽度W4。
还参照图7，在RDL 701的顶侧上形成第一连接件709。在一些实施例中，图案化上介电层703的最顶部介电层(未单独示出)以形成开口并且暴露诸如位于上介电层703的最顶部介电层下方的导电线/迹线707的导电部件。随后，由金属材料、焊料材料等填充最顶部介电层中的开口以形成第一连接件709。在一些实施例中，第一连接件709由低温回流材料形成。低温回流材料是在低于用于形成连接衬底的其他材料的回流温度的温度下可回流以形成两个衬底之间的电连接并且在连接衬底的热预算内的温度下可回流的材料。作为低温回流材料的实例，一些实施例可以利用具有约150摄氏度的回流温度的SnPb焊料。作为低温回流材料的另一实例，一些实施例可以利用具有约200摄氏度的回流温度的无铅焊料。这些实例通常具有例如铜线或铝线的较低回流温度并且将可能在连接衬底的热预算内。可以使用其他低温回流材料。在一些实施例中，第一连接件709可以是微凸块等。如图7所示，第一连接件709延伸至RDL 701的最顶面之上。在一些实施例中，第一连接件709具有介于约10μm和约30μm之间的第五宽度W5，并且延伸至RDL 701的最顶面之上的第一连接件709的部分具有介于约5μm和约60μm之间的第一高度H1。
如图7所示，第一连接件709形成在RDL 701的顶侧上。然而，本领域技术人员将认识到，第一连接件709的具体数量仅提供用于说明的目的而不限制本发明的范围。在其他实施例中，可以根据设计需求改变第一连接件709的数量。
接下来，参照图8，使用第一连接件709将管芯801接合至RDL 701。在一些实施例中，管芯801可以是逻辑管芯、存储管芯、传感器管芯、模拟管芯等。可以使用互补金属氧化物半导体(CMOS)工艺、微电子机械系统(MEMS)工艺、纳米电子机械系统(NEMS)工艺等或它们的组合形成管芯801。在一些实施例中，管芯801可以形成为晶圆的部分。然后通过锯切、激光烧蚀等分割该晶圆以形成单独的管芯801。随后，可以对管芯801实施功能测试。因此，图8中的管芯801可以仅包括已经经过一个或多个功能质量测试的已知良好管芯(KGD)。
管芯801可以包括衬底、位于衬底上的各种有源和无源器件以及位于衬底上方的各种金属化层，由于包括它们对于理解本文中描述的各个实施例不是必须的，所以它们未在图8中明确示出。衬底可以由硅形成，但是衬底也可以由其他III族、IV族和/或V族的元素形成，诸如硅、锗、镓、砷和它们的组合。衬底也可以是绝缘体上硅(SOI)的形式。SOI衬底可以包括形成在绝缘层(例如，掩埋氧化物等)上方的半导体材料(例如，硅、锗等)层，绝缘层形成在硅衬底上。此外，可以使用的其他衬底包括多层衬底、梯度衬底、混合取向衬底、它们的任何组合等。
在一些实施例中，各种有源和无源器件可以包括诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等的各种n型金属氧化物半导体(NMOS)器件和/或p型金属氧化物半导体(PMOS)器件。
金属化层可以包括形成在衬底上方的层间电介质(ILD)/金属间介电层(IMD)。例如，ILD/IMD可以通过诸如旋压、CVD和等离子体增强化学汽相沉积(PECVD)的本领域已知的任何合适的方法由低k介电材料形成，低k介电材料诸如磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等。
在一些实施例中，例如，可以使用镶嵌工艺、双镶嵌工艺等在ILD/IMD中形成互连结构。可以使用光刻技术图案化ILD/IMD以形成沟槽和通孔。通过使用各种沉积和镀方法等在ILD/IMD的沟槽和通孔中沉积合适的导电材料来形成互连结构。此外，互连结构可以包括一个或多个阻挡/粘合层(未示出)以保护ILD/IMD免受扩散和金属毒害的影响。一个或多个阻挡/粘合层可以包括钛、氮化钛、钽、氮化钽或其他替代物。可以使用PVD、ALD、溅射等形成阻挡层。互连结构的导电材料可以包括铜、铜合金、银、金、钨、钽、铝等。在实施例中，用于形成互连结构的步骤可以包括：毯状形成一个或多个阻挡/粘合层，沉积导电材料的薄晶种层，以及例如通过镀用导电材料填充ILD/IMD中的沟槽和通孔。然后实施CMP以去除互连结构的过量部分。在一些实施例中，互连结构可以提供在衬底上形成的各种无源和有源器件之间的电连接。
还参照图8，在位于管芯801的前侧801F上的金属化层上方形成包括一个或多个接触焊盘的接触层(未示出)，并且接触层可以通过金属化层的各个互连结构电连接至有源器件。在一些实施例中，接触焊盘可以包括铝，但是也可以使用诸如铜、钨、银、金等或它们的组合的其他导电材料。
如图8所示，管芯801接合至RDL，从而管芯801的前侧801F接触第一连接件709。在一些实施例中，位于管芯801的前侧801F上的接触焊盘暴露，并且第一连接件709接合至相应的接触焊盘，从而使得第一连接件709提供管芯801和RDL 701之间的电连接。
还参照图8，在RDL 701上方以及相邻的管芯801之间形成密封剂803。密封剂803也可以填充管芯801和RDL 701之间的空隙。在一些实施例中，密封剂803可以包括诸如环氧化物、树脂、可模制聚合物等的模塑料。模塑料可以在基本呈液状时施加，并且然后通过诸如环氧化物或树脂中的化学反应固化模塑料。在其他实施例中，模塑料可以是作为能够设置在管芯801周围和之间的凝胶或可塑固体施加的紫外(UV)或热固化的聚合物。
在一些实施例中，可以去除延伸在管芯801的顶面上方的密封剂803的部分以暴露管芯801的后侧801B。可以使用CMP、研磨工艺、蚀刻工艺或其他合适的减薄工艺去除密封剂803的部分。如图8所示，在一些实施例中，实施减薄工艺，直到密封剂803的顶面与管芯801的后侧801B基本共面。
参照图9，实施载体剥离工艺以从上面的结构分离(剥离)载体101。在一些实施例中，该剥离包括使光(诸如激光或UV光)投射到释放层103上，使得释放层103在光的热量下分解，并且可以安全地去除载体101。例如，也可以使用研磨工艺、CMP工艺、蚀刻工艺等去除晶种层105。在晶种层105由铜形成的实施例中，通过用FeCl3、HCl和H2O的混合物蚀刻来去除晶种层105。
还参照图9，形成诸如第二连接件901的第二连接件以连接至诸如UBM 401的UBM。第二连接件901可以是球栅阵列(BGA)球并且可以包括焊料材料，诸如铅基焊料(诸如PbSn组分)、无铅焊料(包括InSb、锡、银和铜(“SAC”)组分)和具有共熔点并且形成电子应用中的导电焊料连接件的其他共晶材料。对于无铅焊料，可以使用不同组分的SAC焊料，作为实例，诸如SAC 105(Sn 98.5％、Ag 1.0％、Cu 0.5％)、SAC 305和SAC 405。无铅焊料也包括不使用银(Ag)的SnCu化合物和不使用铜(Cu)的SnAg化合物。在一些实施例中，形成诸如BGA球的第二连接件901包括将焊料球放置在UBM 401上以及然后实施回流工艺。在可选实施例中，形成诸如BGA球的第二连接件901包括在UBM 401上镀焊料以及然后回流所镀的焊料。
如图9所示，第一连接件709的尺寸小于第二连接件901的尺寸。为了说明的目的，图9还示出了位于每个管芯801上的一个第一连接件709。在其他实施例中，每个管芯801可以包括具有第一间距(未示出)的许多第一连接件709。在一些实施例中，第一连接件709的第一间距小于第二连接件901的第二间距。因此，RDL的导电部件具有多个尺寸和间距以提供第一连接件709和第二连接件901之间的电连接。在示出的实施例中，RDL 701的导电通孔601L和导电线/迹线601U通过UBM 401与第二连接件901电接触并且具有比与第一连接件709电接触的导电通孔705和导电线/迹线707更大的尺寸和间距。
在形成诸如第二连接件901的第二连接件之后，例如，通过切割、激光烧蚀等分割图9中示出的结构。该分割导致多个封装件的形成，在一些实施例中，多个封装件可以是相同的。随后，测试每个封装件以识别已知良好封装件(KGP)，从而用于进一步处理。
图10示出了使用上面参照图1至图9描述的方法并且接合至诸如印刷电路板(PCB)、另一封装件、管芯、晶圆等的衬底1001的示例性KGP 1000。在示出的实施例中，KGP1000包括两个管芯(诸如管芯801)和两个连接件(诸如第二连接件901)。本领域技术人员将认识到，管芯的数量和连接件的数量仅提供用于说明的目的并不限制本发明的范围。在其他实施例中，根据KGP 1000的设计需求，KGP 1000可以包括合适数量的管芯和连接件。
还参照图10，使用第二连接件901将KGP 1000接合至衬底1001。在第二连接件901是BGA球的实施例中，实施焊料回流工艺以将KGP 1000附接至衬底1001。在示出的实施例中，第二连接件901、RDL 701和第一连接件709提供管芯801和衬底1001之间的电连接。反过来，衬底1001提供KGP 1000和放置在衬底1001上的其他功能系统之间的电连接。在示出的实施例中，KGP 1000不包括封装衬底，并且RDL 701提供管芯801和衬底1001之间的直接电界面。因此，KGP 1000也可以称为无衬底封装件。
图11是根据一些实施例的示出形成集成电路封装件的方法的流程图。该方法开始于步骤1101，其中，如上面参照图1至图4描述的，在载体(诸如载体101)上形成凸块下金属(诸如UBM 401)。接下来，在步骤1103中，如上面参照图5至图7描述的，在UBM上形成一个或多个再分布层(诸如RDL 701)。在步骤1105中，如上面参照图7描述的，在RDL的第一侧上形成第一连接件(诸如第一连接件709)。随后，在步骤1107中，使用第一连接件将管芯(诸如管芯801)接合至RDL的第一侧。在步骤1109中，如上面参照图8描述的，在RDL的第一侧上和管芯周围形成密封剂(诸如密封剂803)。在步骤1111中，如上面参照图9描述的，从上面的结构剥离载体，并且在UBM上形成第二连接件(诸如第二连接件901)。最后，在步骤1113中，如上面参照图9和图10描述的，切割产生的结构以形成单独的封装件(诸如KGP 1000)。
本发明的实施例的有利特征可以包括但不限于更有效的制造工艺和成本降低。具体地，通过消除封装件中的封装衬底，消除了与封装衬底相关的工艺步骤(例如，通过衬底通孔(TSV)形成)，这转而可以加速封装工艺并且提供成本节约。此外，通过消除封装衬底，可以制造超薄封装件。
根据实施例，一种方法包括：在载体上方形成一个或多个再分布层(RDL)，在一个或多个RDL的第一侧上形成第一连接件，以及使用第一连接件将管芯接合至一个或多个RDL的第一侧。该方法还包括：在一个或多个RDL的第一侧上和管芯周围形成密封剂，在形成密封剂之后，从一个或多个RDL分离载体，以及在一个或多个RDL的第二侧上形成第二连接件，第二侧与第一侧相对，其中，第二连接件大于第一连接件。
根据另一实施例，一种方法包括：在载体上形成凸块下金属(UBM)，在UBM上形成一个或多个再分布层(RDL)，UBM电连接至一个或多个RDL，以及在一个或多个RDL上形成第一连接件，其中，UBM和第一连接件位于一个或多个RDL的相对两侧上。该方法还包括：使用第一连接件将管芯接合至一个或多个RDL，在一个或多个RDL上形成密封剂，其中，密封剂的部分介于管芯和一个或多个RDL之间，在形成密封剂之后，从UBM分离载体，以及在UBM上形成第二连接件。
根据又另一实施例，一种器件包括：一个或多个再分布层(RDL)，一个或多个RDL具有第一侧和与第一侧相对的第二侧；第一连接件，位于一个或多个RDL的第一侧上，其中，第一连接件由第一低温回流材料形成；以及第二连接件，位于一个或多个RDL的第二侧上，其中，第二连接件大于第一连接件，并且其中，第二连接件由第二低温回流材料形成。该器件还包括：管芯，附接至第一连接件；以及密封剂，位于一个或多个RDL的第一侧上，其中，密封剂沿着管芯的侧壁延伸，并且密封剂的至少部分延伸在管芯和一个或多个RDL之间。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (19)

1.一种形成集成电路封装件的方法，包括：
在载体上方形成一个或多个再分布层(RDL)；
在所述一个或多个再分布层的第一侧上形成第一连接件；
使用所述第一连接件将管芯接合至所述一个或多个再分布层的所述第一侧；
在所述一个或多个再分布层的所述第一侧上和所述管芯周围形成密封剂；
在形成所述密封剂之后，从所述一个或多个再分布层分离所述载体；以及
在所述一个或多个再分布层的第二侧上形成第二连接件，所述第二侧与所述第一侧相对，其中，所述第二连接件大于所述第一连接件，所述一个或多个再分布层包括位于所述一个或多个再分布层的所述第一侧上的第一互连件和位于所述一个或多个再分布层的所述第二侧上的第二互连件，所述第二互连件的间距大于所述第一互连件的间距。
2.根据权利要求1所述的方法，还包括：
在所述载体上形成释放层；
在所述释放层上形成晶种层；以及
在所述晶种层上形成凸块下金属(UBM)，其中，所述凸块下金属介于所述晶种层和所述一个或多个再分布层之间。
3.根据权利要求1所述的方法，其中，所述密封剂的部分介于所述管芯和所述一个或多个再分布层之间并且围绕所述第一连接件。
4.根据权利要求1所述的方法，其中，使用双镶嵌技术形成所述第一互连件和所述第二互连件。
5.根据权利要求1所述的方法，其中，所述第一互连件和所述第二互连件包括阻挡层或晶种层。
6.根据权利要求1所述的方法，其中，所述第一连接件是微凸块。
7.根据权利要求1所述的方法，其中，所述第二连接件是球栅阵列(BGA)连接件。
8.一种形成集成电路封装件的方法，包括：
在载体上形成凸块下金属(UBM)；
在所述凸块下金属上形成一个或多个再分布层(RDL)，所述凸块下金属电连接至所述一个或多个再分布层；
在所述一个或多个再分布层的第一侧上形成第一连接件，其中，所述凸块下金属和所述第一连接件分别位于所述一个或多个再分布层的第二侧和第一侧上，所述第二侧与所述第一侧相对；
使用所述第一连接件将管芯接合至所述一个或多个再分布层；
在所述一个或多个再分布层上形成密封剂，其中，所述密封剂的部分介于所述管芯和所述一个或多个再分布层之间；
在形成所述密封剂之后，从所述凸块下金属分离所述载体；以及
在所述凸块下金属上形成第二连接件，
其中，所述一个或多个再分布层包括位于所述一个或多个再分布层的所述第一侧上的第一互连件和位于所述一个或多个再分布层的所述第二侧上的第二互连件，所述第二互连件的间距大于所述第一互连件的间距。
9.根据权利要求8所述的方法，其中，形成所述凸块下金属包括在所述载体上形成晶种层。
10.根据权利要求8所述的方法，还包括实施分割以形成封装件，每个封装件均包括至少一个所述管芯。
11.根据权利要求8所述的方法，其中，所述第一连接件的间距小于所述第二连接件的间距。
12.根据权利要求8所述的方法，其中，所述第一连接件是微凸块。
13.根据权利要求8所述的方法，其中，所述第二连接件是球栅阵列(BGA)连接件。
14.一种集成电路封装件，包括：
一个或多个再分布层(RDL)，所述一个或多个再分布层具有第一侧和与所述第一侧相对的第二侧；
第一连接件，位于所述一个或多个再分布层的所述第一侧上，其中，所述第一连接件由第一低温回流材料形成；
第二连接件，位于所述一个或多个再分布层的所述第二侧上，其中，所述第二连接件大于所述第一连接件，并且其中，所述第二连接件由第二低温回流材料形成；
管芯，附接至所述第一连接件；以及
密封剂，位于所述一个或多个再分布层的所述第一侧上，其中，所述密封剂沿着所述管芯的侧壁延伸，并且所述密封剂的至少部分延伸在所述管芯和所述一个或多个再分布层之间，
其中，所述一个或多个再分布层包括位于所述一个或多个再分布层的所述第一侧上的第一互连件和位于所述一个或多个再分布层的所述第二侧上的第二互连件，所述第二互连件的间距大于所述第一互连件的间距。
15.根据权利要求14所述的集成电路封装件，其中，所述密封剂的最顶面与所述管芯的后侧共面。
16.根据权利要求14所述的集成电路封装件，还包括凸块下金属(UBM)，所述凸块下金属介于所述第二连接件和所述一个或多个再分布层之间。
17.根据权利要求14所述的集成电路封装件，其中，所述第一连接件的间距小于所述第二连接件的间距。
18.根据权利要求14所述的集成电路封装件，其中，所述第一连接件是微凸块。
19.根据权利要求14所述的集成电路封装件，其中，所述第二连接件是球栅阵列(BGA)连接件。
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