TW201611220A - 方法與裝置 - Google Patents

方法與裝置 Download PDF

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Publication number
TW201611220A
TW201611220A TW104129306A TW104129306A TW201611220A TW 201611220 A TW201611220 A TW 201611220A TW 104129306 A TW104129306 A TW 104129306A TW 104129306 A TW104129306 A TW 104129306A TW 201611220 A TW201611220 A TW 201611220A
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TW
Taiwan
Prior art keywords
connectors
forming
layer
rewiring
die
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TW104129306A
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English (en)
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TWI587466B (zh
Inventor
黃麟智
鄧宏安
陳新瑜
吳倉聚
謝政傑
Original Assignee
台灣積體電路製造股份有限公司
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Publication of TW201611220A publication Critical patent/TW201611220A/zh
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Publication of TWI587466B publication Critical patent/TWI587466B/zh

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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
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Abstract

本揭露提供積體電路封裝及其形成方法。一個或多個再佈線層(RDL)形成於載體上。第一連接物形成於RDL的第一側上。藉由第一連接物，將晶粒接合至RDL的第一側。密封劑形成於RDL的第一側上以圍繞晶粒。自上面結構剝離載體，並形成第二連接物於RDL的第二側上。切割上述製程完成的結構，以形成個別封裝。

Description

方法與裝置
本發明關於積體電路裝置，更特別關於積體電路封裝及其形成方法。
由於各種電子構件如電晶體、二極體、電阻器、電容、或類似物的積體密度持續改善，半導體工業已快速成長一段時間。大部份積體密度的改善來自最小結構尺寸的持續縮小(比如將半導體製程節點朝次20nm節點的尺寸縮小)，即允許更多的構件整合至固定面積中。近來對更微型化、更高速度、更大帶寬、及更低功耗/延遲的需求增加，所以對更小及更創造性的半導體晶粒的封裝技術的需求也增加。
隨著半導體技術進一步發展，堆疊半導體裝置如3D積體電路(3DIC)為有效替代品，以進一步減小半導體裝置的物理尺寸。在堆疊半導體裝置中，晶圓/晶粒堆疊在彼此頂部並經通孔(TV)等連接物內連線。舉例來說，3DIC的某些優點包含較小的覆蓋區域、減少信號內連線的長度以降低功耗、以及若在組裝前個別測試各個晶粒即可改進良率與降低製造成本。
本揭露一實施例提供之方法方法，包括：形成一或多個再佈線層於載體上；形成第一連接物於再佈線層之第一側上；以第一連接物將晶粒接合至再佈線層之第一側；形成密 封劑於再佈線層之第一側上以圍繞晶粒；在形成密封劑後，自再佈線層分離載體；以及形成第二連接物於再佈線層的第二側上，且第一側與第二側相對，其中第二連接物大於第一連接物。
本揭露一實施例提供之方法，包括形成多個凸塊下金屬化物於載體上；形成一或多個再佈線層於凸塊下金屬化物上，且凸塊下金屬化物電性耦接至再佈線層；形成多個第一連接物於再佈線層上，其中凸塊下金屬化物與第一連接物位於再佈線層的相對兩側上；以第一連接物將多個晶粒接合至再佈線層；形成密封劑於再佈線層上，其中部份密封劑夾設於晶粒與再佈線層之間；在形成密封劑後，自凸塊下金屬化物分離載體；以及形成多個第二連接物於凸塊下金屬化物上。
本揭露一實施例提供之裝置，包括：一或多個再佈線層，其具有相對之第一側與第二側；多個第一連接物位於再佈線層的第一側上，其中第一連接物係由第一低溫再流動材料所形成；第二連接物位於再佈線層的第二側上，其中第二連接物大於第一連接物，且其中第二連接物係由第二低溫再流動材料所形成；晶粒貼附至第一連接物；以及密封劑位於再佈線層的第一側上，其中密封劑沿著晶粒之側壁延伸，且至少部份的密封劑延伸於晶粒與再佈線層之間。
H1‧‧‧第一高度
W1‧‧‧第一寬度
W2‧‧‧第二寬度
W3‧‧‧第三寬度
W4‧‧‧第四寬度
W5‧‧‧第五寬度
101‧‧‧載體
103‧‧‧離型層
105‧‧‧晶種層
201‧‧‧第一介電層
203‧‧‧第一開口
301‧‧‧第一導電材料
303‧‧‧第二導電材料
401‧‧‧UBM
501‧‧‧最底部介電層
503‧‧‧第二開口
503L、601L‧‧‧第一部份
503U、601U‧‧‧第二部份
601‧‧‧導電結構
603‧‧‧阻障/晶種層
701‧‧‧RDL
703‧‧‧較上介電層
705‧‧‧導電通孔
707‧‧‧導電線路
709‧‧‧第一連接物
801‧‧‧晶粒
801B‧‧‧背面
801F‧‧‧正面
803‧‧‧密封劑
901‧‧‧第二連接物
1000‧‧‧KGP
1001‧‧‧基板
1101、1103、1105、1107、1109、1111、1113‧‧‧步驟
第1至9圖係某些實施例中，積體電路封裝於製作時的多種製程步驟中的剖視圖。
第10圖係某些實施例中，安裝在基板上的積體電路封裝之 剖面圖。
第11圖係某些實施例中，積體電路封裝件的形成方法之流程圖。
下述內容提供的不同實施例可實施本揭露的不同結構。特定構件與排列的實施例係用以簡化本揭露而非侷限本揭露。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本揭露之多種實例將重複標號及/或符號。不同實施例中具有相同標號的元件並不必然具有相同的對應關係及/或排列。標號重複僅為了簡化並清楚說明，並不代表不同實施例及/或排列中具有相同標號的元件具有類似的相對關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
多種實施例提供積體電路封裝與其形成方法。在特定實施例中，將說明形成積體電路封裝的中間階段。在多種圖式與實施例中，將以相同標號標示類似單元。
第1至9圖係某些實施例中，積體電路封裝於製作時的多種製程步驟中的剖視圖。如第1圖所示之部份載體101，其具有離型層103形成其上。載體101之組成可為石英、玻璃、 陶瓷材料、或類似物，其可於後續步驟中提供機械支撐。載體101可具有圓形的平面形狀，且可為矽晶圓的尺寸。舉例來說，載體101可具有8英吋的直徑、12英吋的直徑、或類似尺寸。離型層103之組成可為高分子為主的材料，其可與載體101一起從後續步驟形成之上面的結構中去除。在某些實施例中，離型層103可包含光熱轉換(LTHC)材料、紫外光(UV)黏結劑(暴露至UV輻射時將失去黏性)、環氧樹脂為主的熱離型材料(暴露至熱源時將失去黏性)、或類似物。離型層103的形成方法可為沉積製程、旋轉塗佈製程、印刷製程、壓合製程、或類似製程。離型層103之後可硬化。在某些實施例中，離型層103的上表面齊平且具有高度平坦性，這將有利於形成後續層狀物。
如第1圖所示，晶種層105係毯覆式地形成於離型層103上。在某些實施例中，晶種層105可包含銅、鈦、鎳、金、錳、類似物、或上述之組合的一或多層，且其形成方法可為原子層沉積(ALD)、物理氣相沉積(PVD)、濺鍍、類似方法、或上述之組合。
如第2圖所示，形成第一介電層201於晶種層105上。第一介電層201的下表面可接觸晶種層105的上表面。在某些實施例中，第一介電層201之組成為聚合物，包含微影光罩可輕易圖案化的光敏材料，比如聚苯并噁唑(PBO)、聚醯亞胺、苯并環丁烯(BCB)、或類似物。在其他實施例中，第一介電層201為光不可圖案化的介電材料如氮化矽、碳化矽、氧化矽、氮氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜的磷矽酸鹽玻璃(BPSG)、類似物、或上述之組合。第一介電層 201之沉積方法可為化學氣相沉積(CVD)、PVD、ALD、旋轉塗佈製程、類似方法、或上述之組合。
如第2圖所示，圖案化第一介電層201以形成開口(如第一開口203)於第一介電層201中。因此，經由第一介電層201中的第一開口203可露出晶種層105。在第一介電層201為可光圖案化材料的實施例中，可採用合適的微影技術曝光第一介電層201，以形成第一開口203。在此實施例中，可在曝光後顯影及/或固化第一介電層201。
第3與4圖顯示形成凸塊下金屬化物(UBM)於第一介電層201的第一開口203中，比如第一開口203(見第2圖)中的UBM 401(見第4圖)。在某些實施例中，形成第一導電材料301與第二導電材料303於第一開口203中，其中第二導電材料303超出第一開口203。第一導電材料301和第二導電材料303可包含銅、鎢、鋁、鎳、銀、金、類似物、或上述之組合，其形成方法可為電化學電鍍製程、無電電鍍製程、ALD、PVD、類似製程、或上述之組合。在某些實施例中，晶種層105作為電鍍製程的晶種層。在某些實施例中，第一導電材料301是鎳，而第二導電材料303是銅。
如第4圖所示，移除超出第一開口203(見第2圖)的部份第二導電材料303，使第二導電材料303的上表面與第一介電層201的上表面實質上共平面。移除超出第一開口203的部份第二導電材料303之方法，可為蝕刻製程、平坦化製程如化學機械拋光(CMP)製程、或類似製程。
如第5至7圖所示，形成一或多個RDL(再佈線層) 701於第一介電層201和UBM 401上。在某些實施例中，RDL 701包含一或多個介電層與設置其中的一或多個導電結構。在某些實施例中，形成導電結構於介電層中的方法可為雙鑲嵌製程。在其他實施例中，可採用其他合適方法形成導電結構。RDL 701可提供後續接合的積體電路晶粒之間的電性界面，以及積體電路晶粒和外部裝置之間的電性界面，如下述詳細內容。
如第5圖所示，形成RDL 701之最底部介電層501於第一介電層201和UBM 401上。最底部介電層501的材料可與第一介電層201的材料相同。圖案化最底部介電層501可形成開口(如第二開口503)於最底部介電層501中。在最底部介電層501為可光圖案化材料的實施例中，可採用合適的微影技術曝光最底部介電層501以形成第二開口503。在此實施例中，曝光後顯影及/或固化最底部介電層501。如第5圖所示，第二開口503露出UBM 401。在此實施例中，第二開口503包括第一部份503L(又稱作通孔)，以及第二部份503U(又稱作溝槽)。
如第6圖所示，形成導電結構於最底部介電層501中的第二開口503，比如第二開口503(見第5圖)中的導電結構601。在某些實施例中，阻障/晶種層603毯覆性地形成於最底部介電層501上並襯墊第二開口503。阻擋/晶種層603可包含銅、鎳、金、錳、鈦、氮化鈦、鉭、氮化鉭、類似物、或上述之組合的一或多層，且其形成方法可為ALD、PVD、濺鍍、類似方法、或上述之組合。隨後，使用電化學電鍍製程、無電電鍍製程、ALD、PVD、類似製程、或上述之組合。接著將導電材料如銅、鎢、鋁、鎳、銀、金、類似物、或上述之組合填入 第二開口503以形成導電結構601。在某些實施例中，導電結構601與阻障/晶種層603的導電材料可超出第二開口503。將超出第二開口503的部份導電材料移除的方法，可為蝕刻製程、平坦化製程如CMP製程、或類似方法。
如第6圖所示，導電結構601包含第一部分601L(又稱作導電通孔)與第二部分601U(又稱作導電線路)。在某些實施例中，第一部份601L的第一寬度W1介於約10μm至約20μm之間，而第二部份601U的第二寬度W2介於約20μm至約100μm之間。
如第7圖所示，形成較上介電層703、導電通孔705、及導電線路707於最底部介電層501上，以完成RDL 701。在某些實施例中，較上介電層703的材料與第一介電層201及最底部介電層501的材料相同。在對應的上介電層703中形成導電線/跡線707和導電通孔705的方法，可採用前述形成導電結構601的方法(見第5與6圖)，在此不贅述。此外，導電線路707和導電通孔705還包含與阻障/晶種層603類似的阻障/晶種層(未圖示)。在某些實施例中，導電通孔705的第三寬度W3介於約0.2μm至約2μm之間，而導電線路707之第四寬度W4介於約10μm至約30μm之間。
如第7圖所示，形成第一連接物709於RDL 701的頂側上。在某些實施例中，圖案化較上介電層703的最頂部介電層(未個別圖示)以形成開口，並露出導電結構如位於最頂部介電層下方的導電線路707。接著將金屬材料、焊料材料、或類似物填入最頂部介電層中的開口，以形成第一連接物709。在 某些實施例中，第一連接物709由低溫再流動材料所形成。上述低溫再流動材料可在特定溫度下再流動，以形成兩基板間的電性連接。上述特定溫度低於形成連接基板的其他材料之再流動溫度(在連接基板的熱預算內)。舉例來說，低溫再流動材料可採用錫鉛焊料，其再流動溫度為約150℃。在另一實施例中，低溫再流動材料可採用無鉛焊料，其再流動溫度為約200℃。低溫再流動材料通常具有較低的再流動溫度(例如低於銅線或鋁線)，且可符合連接基板的熱預算。此外亦可以採用其他低溫再流動材料。在某些實施例中，第一連接物709可為微凸塊或類似物。如第7圖所示，第一連接物709延伸至RDL 701的最頂表面上。在某些實施例中，第一連接物709的第五寬度W5介於約10μm至約30μm之間，且延伸至RDL 701的最頂表面上的部份第一連接物709其第一高度H1介於約5μm至約60μm之間。
如第7圖所示，第一連接物709形成於RDL 701的頂側上。然而，本技術領域中具有通常知識者應知圖式中第一連接物709的數目僅用以說明而非侷限本揭露範疇。在其他實施例中，可依設計需求改變第一連接物709的數目。
接著如第8圖所示，以第一連接物709將晶粒801接合至RDL 701。在某些實施例中，晶粒801可為邏輯晶粒、存儲晶粒、感測器晶粒、類比晶粒、或類似物。晶粒801的形成方法可為互補式金氧半(CMOS)製程、微機電系統(MEMS)製程、奈米機電系統(NEMS)製程、類似製程、或上述之組合。在某些實施例中，晶片801可為部份的晶圓。接著以切割、雷射剝離、或類似方法分割晶圓，以形成個別的晶粒801。接著可對 晶粒801進行功能測試。如此一來，第8圖的晶粒801可只包含經過一或多個功能品質測試的已知良好晶粒(KGD)。
晶粒801可包含基板、位於基板上的各種主動和被動裝置、及位於基板上的多種金屬化層，上述單元並非理解多種實施例的必要特徵，因此均未圖示於第8圖中。基板可由矽形成，但亦可由其他III族、IV族、及/或V族的元素形成，比如矽、鍺、鎵、砷、或上述之組合。基板亦可為絕緣層上矽(SOI)。SOI基板可包括半導體材料層(如矽、鍺、或類似物)形成於絕緣層(如埋置氧化物及/或類似物)上，而絕緣層形成在矽基板上。此外，可採用其他基板如多層基板、組成漸變基板、混合取向基板、上述之組合、及/或類似物。
在某些實施例中，多種主動和被動裝置可包括n型金氧半(NMOS)及/或p型金氧半(PMOS)裝置，比如電晶體、電容、電阻、二極體、光二極體、熔絲、及/或類似物。
金屬化層可包括層間介電層(ILD)/金屬間介電層(IMD)形成於基板上。舉例來說，ILD/IMD可為低介電常數介電材料如磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、FSG、SiOxCy、旋塗玻璃、旋塗聚合物、矽碳材料、上述之化合物、上述之複合物、上述之組合、或類似物，且其形成方法可為本技術領域所知的任何合適方法如旋轉塗佈法、CVD、或電漿增強式化學氣相沉積(PECVD)。
在某些實施例中，內連線結構形成於ILD/IMD中的方法可為雙鑲嵌製程或類似製程。ILD/IMD可經由光微影技術圖案化，以形成溝槽與通孔。內連線結構的形成方法為沉積合 適的導電材料於溝槽與通孔中，比如沉積、電鍍、或類似方法。此外，內連線結構可包含一或多個阻障/黏著層(未圖示)，以保護ILD/IMD免於擴散及金屬毒化等問題。上述阻障/黏著層可包含鈦、氮化鈦、鉭、氮化鉭、或其他類似物。阻障層之形成方法可為PVD、ALD、濺鍍、或類似方法。內連線結構的導電材料可包含銅、銅合金、銀、金、鎢、鉭、鋁、或類似物。在一實施例中，形成內連線結構之步驟可包含毯覆性地形成一或多個阻障/黏著層、沉積導電材料之薄晶種層、以及將導電材料填入ILD/IMD的溝槽與通孔中(比如電鍍法)。接著進行CMP以移除內連線結構的多餘部份。在某些實施例中，內連線結構可提供形成於基板中的多種被動與主動裝置之間的電性連接。
如第8圖所示，形成接點層於晶粒801之正面801F上的金屬化層上。接點層含有一或多個接點墊(未圖示)，並經由金屬化層的多種內連線結構電性耦接至主動裝置。在某些實施例中，接點墊可包含鋁，但亦可為其他導電材料如銅、鎢、銀、金、類似物、或上述之組合。
晶粒801接合至RDL，因此晶粒801的正面801F接觸第一連接物709，如第8圖所示。在某些實施例中，露出晶粒801之正面801F上的接點墊，且第一連接物709接合至對應的接點墊，使第一連接物709提供晶粒801與RDL 701之間的電性連接。
如第8圖所示，形成密封劑803於RDL 701與相鄰的晶粒801之間。密封劑803亦可填入晶粒801與RDL 701之間的空洞。在某些實施例中，密封劑803可包含成型化合物如環氧化合物、樹脂、可成型高分子、或類似物。成型化合物可在實質 上液態時施加，接著經由環氧化合物或樹脂中的化學反應固化。在其他實施例中，位於晶粒801周圍和之間的成型化合物可為紫外光(UV)或熱固化的聚合物，其可在膠態或可塑固體態時施加。
在某些實施例中，可移除延伸至晶粒801之上表面上的部份密封劑803，以露出晶粒801的背面801B。移除部份密封劑803的方法可為CMP、研磨製程、蝕刻製程、或其他合適的薄化製程。在某些實施例中，進行薄化製程直到密封劑803的上表面與晶粒801的背面801B實質上共平面，如第8圖所示。
如第9圖所示，進行分離載板製程，自上面的結構分離載板101。在某些實施例中，分離步驟包含將光如雷射光或紫外線照射至離型層103上，使離型層103在光熱下分解，以安全地移除載板101。晶種層105亦可移除，其移除方法可為研磨製程、CMP製程、蝕刻製程、或類似製程。在晶種層105由銅形成的實施例中，移除晶種層的方法可為蝕刻法，且蝕刻混合物為FeCl3、HCl、與H2O。
如第9圖所示，形成第二連接物(如第二連接物901)連接至UBM(如UBM 401)。第二連接物901可為球柵陣列(BGA)球，且可包含焊料材料如鉛為主的焊料(如鉛錫組成)、無鉛焊料(如銦錫、錫銀銅組成(SAC))、或其他共熔材料(在電子應用中具有一般熔點並形成導電焊料連接)。以無鉛焊料為例，SAC焊料可具有多種組成如SAC105(98.5%的錫、1.0%的銀、與0.5%的銅)、SAC305、或SAC405。無鉛焊料亦可包含錫銅化合物(不含銀)或錫銀化合物(不含銅)。在某些實施例中，形成第二連接 物901如BGA球的方法包含將焊料球置於UBM 401上，接著進行再流動製程。在其他實施例中，形成第二連接物901如BGA球的方法包含電鍍焊料至UBM 401上，接著使電鍍的焊料再流動。
如第9圖所示，第一連接物709的尺寸小於第二連接物901的尺寸。為說明目的，第9圖中的每一晶粒801上具有一第一連接物709。在其他實施例中，每一晶粒801上可具有多個第一連接物709，且第一連接物709之間具有間距(未圖示)。在某些實施例中，第一聯接物709的第一間距小於第二連接物901的第二間距。綜上所述，RDL的導電結構具有多種尺寸與間距，可提供第一連接物709與第二連接物901之間的電性連接。在此實施例中，RDL 701中的導電結構601其第一部份601L與第二部份601U經由UBM 401電性接觸第二連接物901。第一部份601L與第二部份601U之尺寸與間距，大於與第一連接物709電性連接之導電通孔705與導電線路707的尺寸與間距。
在形成第二連接物如第二連接物901後，分割第9圖中的結構，且分割方法可為切割、雷射剝除、或類似方法。在某些實施例中，上述分割步驟形成多個相同的封裝。接著測試每一封裝，以識別可用於後續製程的已知良好封裝(KGP)。
在第10圖中，以第1至9圖所述的方法所形成之KGP1000接合至基板1001如印刷電路板(PCB)、另一封裝、晶粒、晶圓、或類似物。在此實施例中，KGP 1000包括兩個晶粒(如晶粒801)和兩個連接物(如第二連接物901)。本技術領域中具有通常知識者應理解，晶粒的數目和連接物的數目僅用於說明而 非侷限本揭露範疇。在其他實施例中，KGP 1000可包含合適數目的晶粒和連接物，其取決於KGP 1000的設計需求。
如第10圖所示，KGP 1000經由第二連接物901接合至基板1001。在第二連接物901是BGA球的實施例中，進行焊料再流動製程使將KGP 1000貼附至基板1001。在此實施例中，第二連接物901、RDL 701、與第一連接物709提供基粒801與基板1001之間的電性連接。如此一來，基板1001提供KGP 1000和位於基板1001上的其他功能系統之間的電性連接。在此實施例中，KGP 1000不含封裝基板，且RDL 701提供晶粒801和基板1001之間的直接電性界面。因此，KGP 1000亦可稱作無基板封裝。
第11圖係某些實施例中，積體電路封裝之形成方法的流程圖。上述方法起始於步驟1101，如前述之第1至4圖所示，凸塊下金屬化物(如UBM 401)係形成於載體(如載體101)上。接著在步驟1103中，如前述之第5至7圖所示，形成一或多個再分佈層(如RDL 701)於UBM上。在步驟1105中，如前述之第7圖所示，形成第一連接物(如第一連接物709)於RDL的第一側上。之後在步驟1107中，以第一連接物將晶粒(如晶粒801)接合至RDL的第一側。在步驟1109中，如前述之第8圖所示，形成密封劑(如密封劑803)於RDL的第一側上以圍繞晶粒。在步驟1111中，如前述之第9圖所示，自上面的結構剝離載體，並形成第二連接物(如第二連接物901)於UBM上。最後在步驟1113中，如前述之第9與10圖所述，切割上述步驟產生的結構以形成個別的封裝件(如KGP 1000)。
本揭露實施例的有利特徵可包括但不限於：更有效的製程與降低成本。在特定實施例中，自封裝消除封裝基板，可消除與封裝基板相關的製程步驟(比如形成穿透基板通孔(TSV))，這可加速封裝製程並節省成本。此外，藉由消除封裝基板可製造超薄封裝。
在一實施例中，方法包括形成一或多個再佈線層(RDL)於載體上；形成第一連接物於RDL之第一側上；以及以第一連接物將晶粒接合至RDL之第一側。此方法亦包含形成密封劑於RDL之第一側上以圍繞晶粒；在形成密封劑後，自RDL分離載體；以及形成第二連接物於RDL的第二側上，且第一側與第二側相對，其中第二連接物大於第一連接物。
在另一實施例中，方法包括形成多個凸塊下金屬化物(UBM)於載體上；形成一或多個再佈線層(RDL)於UBM上，且UBM電性耦接至RDL；以及形成多個第一連接物於RDL上，其中UBM與第一連接物位於RDL的相對兩側上。上述方法亦包含以第一連接物將多個晶粒接合至RDL；形成密封劑於RDL上，其中部份密封劑夾設於晶粒與RDL之間；在形成密封劑後，自UBM分離載體；以及形成多個第二連接物於UBM上。
在另一實施例中，裝置包括一或多個再佈線層(RDL)，其具有相對之第一側與第二側；多個第一連接物位於RDL的第一側上，其中第一連接物係由第一低溫再流動材料所形成；以及第二連接物位於RDL的第二側上，其中第二連接物大於第一連接物，且其中第二連接物係由第二低溫再流動材料所形成。裝置亦包含晶粒貼附至第一連接物；以及密封劑位於 RDL的第一側上，其中密封劑沿著晶粒之側壁延伸，且至少部份的密封劑延伸於晶粒與RDL之間。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本揭露。本技術領域中具有通常知識者應理解可採用本揭露作為基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本揭露之精神與範疇，並可在未脫離本揭露之精神與範疇的前提下進行改變、替換、或更動。
201‧‧‧第一介電層
401‧‧‧UBM
601L‧‧‧第一部份
601U‧‧‧第二部份
603‧‧‧阻障/晶種層
701‧‧‧RDL
703‧‧‧較上介電層
705‧‧‧導電通孔
707‧‧‧導電線路
709‧‧‧第一連接物
801‧‧‧晶粒
803‧‧‧密封劑
901‧‧‧第二連接物
1000‧‧‧KGP
1001‧‧‧基板

Claims (20)

  1. 一種方法，包括：形成一或多個再佈線層於一載體上；形成一第一連接物於該或該些再佈線層之第一側上；以該第一連接物將一晶粒接合至該或該些再佈線層之第一側；形成一密封劑於該或該些再佈線層之第一側上以圍繞該晶粒；在形成該密封劑後，自該或該些再佈線層分離該載體；以及形成一第二連接物於該或該些再佈線層的第二側上，且該第一側與該第二側相對，其中該第二連接物大於該第一連接物。
  2. 如申請專利範圍第1項所述之方法，更包括：形成一離型層於該載體上；形成一晶種層於該離型層上；以及形成一凸塊下金屬化物於該晶種層上，其中該凸塊下金屬化物係夾設於該晶種層與該或該些再佈線層之間。
  3. 如申請專利範圍第1項所述之方法，其中部份該密封劑係夾設於該晶粒與該或該些再佈線層之間，並圍繞該第一連接物。
  4. 如申請專利範圍第1項所述之方法，其中該或該些再佈線層包括：多個第一內連線位於該或該些再佈線層的第一側上；以及 多個第二內連線位於該或該些再佈線層的第二側上，且該些第二內連線之間距大於該些第一內連線之間距。
  5. 如申請專利範圍第4項所述之方法，其中該些第一內連線與該些第二內連線的形成方法為雙鑲嵌技術。
  6. 如申請專利範圍第4項所述之方法，其中該些第一內連線與該些第二內連線包括阻障/晶種層。
  7. 如申請專利範圍第1項所述之方法，其中該第一連接物係微凸塊。
  8. 如申請專利範圍第1項所述之方法，其中該第二連接物係球柵陣列連接物。
  9. 一種方法，包括：形成多個凸塊下金屬化物於一載體上；形成一或多個再佈線層於該些凸塊下金屬化物上，且該些凸塊下金屬化物電性耦接至該或該些再佈線層；形成多個第一連接物於該或該些再佈線層上，其中該些凸塊下金屬化物與該些第一連接物位於該或該些再佈線層的相對兩側上；以該些第一連接物將多個晶粒接合至該或該些再佈線層；形成一密封劑於該或該些再佈線層上，其中部份該密封劑夾設於該些晶粒與該或該些再佈線層之間；在形成該密封劑後，自該些凸塊下金屬化物分離該載體；以及形成多個第二連接物於該些凸塊下金屬化物上。
  10. 如申請專利範圍第9項所述之方法，其中形成該些凸塊下金 屬化物之步驟包括形成一晶種層於該載體上。
  11. 如申請專利範圍第9項所述之方法，更包括進行一切割步驟以形成多個封裝，且每一該些封裝包括至少一該些晶粒。
  12. 如申請專利範圍第9項所述之方法，其中該些第一連接物的間距小於該些第二連接物的間距。
  13. 如申請專利範圍第9項所述之方法，其中該些第一連接物係微凸塊。
  14. 如申請專利範圍第9項所述之方法，其中該些第二連接物係球柵陣列連接物。
  15. 一種裝置，包括：一或多個再佈線層，其具有相對之第一側與第二側；多個第一連接物位於該或該些再佈線層的第一側上，其中該些第一連接物係由第一低溫再流動材料所形成；多個第二連接物位於該或該些再佈線層的第二側上，其中該些第二連接物大於該些第一連接物，且其中該些第二連接物係由第二低溫再流動材料所形成；一晶粒貼附至該些第一連接物；以及一密封劑位於該或該些再佈線層的第一側上，其中該密封劑沿著該晶粒之側壁延伸，且至少部份的該密封劑延伸於該晶粒與該或該些再佈線層之間。
  16. 如申請專利範圍第15項所述之裝置，其中該密封劑的上表面與該晶粒的背面實質上共平面。
  17. 如申請專利範圍第15項所述之裝置，更包括多個凸塊下金屬化物夾設於該些第二連接物與該或該些再佈線層之間。
  18. 如申請專利範圍第15項所述之裝置，其中該些第一連接物的間距小於該些第二連接物的間距。
  19. 如申請專利範圍第15項所述之裝置，其中該些第一連接物係微凸塊。
  20. 如申請專利範圍第15項所述之裝置，其中該些第二連接物係球柵陣列連接物。
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