WO2020098212A1 - 一种半导体芯片封装方法及封装器件 - Google Patents

一种半导体芯片封装方法及封装器件 Download PDF

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Publication number
WO2020098212A1
WO2020098212A1 PCT/CN2019/082309 CN2019082309W WO2020098212A1 WO 2020098212 A1 WO2020098212 A1 WO 2020098212A1 CN 2019082309 W CN2019082309 W CN 2019082309W WO 2020098212 A1 WO2020098212 A1 WO 2020098212A1
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Prior art keywords
chip
layer
pad
hole
transparent protective
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PCT/CN2019/082309
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English (en)
French (fr)
Inventor
俞国庆
Original Assignee
通富微电子股份有限公司
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Priority claimed from CN201811341982.5A external-priority patent/CN109545809B/zh
Priority claimed from CN201811341256.3A external-priority patent/CN109524479B/zh
Application filed by 通富微电子股份有限公司 filed Critical 通富微电子股份有限公司
Publication of WO2020098212A1 publication Critical patent/WO2020098212A1/zh
Priority to US17/317,062 priority Critical patent/US11990398B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Definitions

  • the present application relates to the field of semiconductor technology, in particular to a semiconductor chip packaging method and a packaging device.
  • a chip with a photosensitive area is a very important part of a camera device.
  • common packaging methods include: adding a transparent glass cover plate above the photosensitive area of the chip to protect the photosensitive area of the chip.
  • the inventor of the present application discovered during the long-term research that, on the one hand, because the thickness of the transparent glass cover plate is generally thick, refraction, reflection, and energy loss will occur when light penetrates the transparent glass, which will deteriorate the photosensitive effect of the chip;
  • the transparent glass cover and the chip are connected by glue. After using for a long time, the glue is easy to fall off, and the external dust is easy to enter the photosensitive area of the chip, thereby affecting the photosensitive effect of the chip.
  • the technical problem mainly solved by the present application is to provide a semiconductor chip packaging method and a packaging device, which can improve the photosensitive effect of the chip.
  • the packaging method includes: providing a chip, the chip includes a front side and a back side, and a photosensitive region and A pad located around the photosensitive area, and a transparent protective layer is formed on the front surface of the chip, the transparent protective layer covering the photosensitive area and the pad of the chip; corresponding to the back surface of the chip A through hole is formed at the position of the pad, and the pad corresponds to the through hole one by one, so that the pad is exposed from the through hole; the pad of the chip is transmitted through the The through hole is electrically connected to the circuit board.
  • the providing chip includes: providing a wafer, the wafer is provided with a plurality of the chips arranged in a matrix, and a scribe groove is provided between the chips, the wafer includes a front side and a back side, the chip The front side of the chip is the front side of the wafer, and the back side of the chip is the back side of the wafer.
  • the front side of the chip is provided with a photosensitive area and pads around the photosensitive area; a transparent protection is formed on the front side of the chip Layer, the transparent protective layer covers the photosensitive area and the pad of the chip; cutting along the dicing groove to cut off the wafer and the transparent protective layer corresponding to the dicing groove, thereby obtaining Single chip.
  • forming a transparent protective layer on the front surface of the chip includes forming the transparent protective layer on the front surface of the chip by spin coating, dispensing or printing, and curing the transparent protective layer.
  • the curing of the transparent protective layer includes: curing the transparent protective layer by means of ultraviolet irradiation or baking.
  • the packaging method before forming the through hole at the position corresponding to the pad on the back of the chip, the packaging method further includes: providing a substrate on a side of the transparent protective layer away from the chip; grinding the chip The back surface, so that the thickness of the chip is less than or equal to a predetermined thickness; after electrically connecting the pad of the chip to the circuit board through the through hole, the packaging method further includes: removing the substrate.
  • forming a through hole at a position corresponding to the pad on the back surface of the chip includes: setting the state of the chip such that the side having the pad is located below; corresponding to the back surface of the chip A through hole is formed at the position of the pad, and all or part of the pad is exposed from the through hole.
  • the size of the through hole from the pad side to the back side of the chip is the same; or, the size of the through hole from the pad side to the back side of the chip gradually increases.
  • the electrically connecting the pad of the chip to the circuit board through the through hole includes: forming a metal rewiring layer in the through hole, one end of the metal rewiring layer and the The pad of the chip is electrically connected, and the other end of the metal rewiring layer is electrically connected to the circuit board.
  • forming the metal rewiring layer in the through hole includes: forming a first mask layer on the back surface of the chip and the area of the through hole, and corresponding to the first mask layer A first opening is formed at the position of the pad; a first seed layer is formed on the surface of the first mask layer away from the chip; a second mask layer is formed on the surface of the first seed layer away from the chip And forming a second opening in the second mask layer; forming the metal rewiring layer in the second opening; removing the second mask layer and the metal rewiring layer The first seed layer.
  • the packaging method further includes: facing away from the chip at the metal rewiring layer A first barrier layer is provided on the surface, and a third opening is formed on the first barrier layer; a solder ball is provided in the third opening, and the solder ball is electrically connected to the circuit board.
  • a semiconductor package device including: a chip, the chip includes a front side and a back side, the front side of the chip is provided with a photosensitive area and located Pads around the photosensitive area; through holes are provided in the chip corresponding to the pads, and the through holes correspond to the pads in one-to-one correspondence; a transparent protective layer is located on the front of the chip and covers the chip The photosensitive area and the pad; the circuit board, and the pad of the chip are electrically connected through the through hole.
  • the transparent protective layer is formed by spin coating, dispensing or printing.
  • the transparent protective layer is a material cured by ultraviolet irradiation or baking.
  • the material of the transparent protective layer includes an inorganic transparent material and / or an organic transparent material
  • the inorganic transparent material includes at least one of silicon nitride and silicon oxynitride
  • the organic transparent material includes polysiloxane
  • the through holes have the same size from the side of the pad to the back side of the chip.
  • the size of the through hole from the side of the pad to the back side of the chip gradually increases.
  • the packaged device further includes: a metal rewiring layer located on the back surface of the chip and extending into the through hole, one end of the metal rewiring layer is electrically connected to the pad, the metal The other end of the rewiring layer is electrically connected to the circuit board.
  • the packaged device further includes: a first mask layer between the back of the chip and the metal rewiring layer, and the first mask layer is provided with a first position corresponding to the position of the pad An opening; a first seed layer located between the first mask layer and the metal rewiring layer, and the pad, the first seed layer, and the metal rewiring layer are electrically connected.
  • the packaged device further includes: a first barrier layer located on a side of the metal rewiring layer away from the chip, and a third opening formed on the first barrier layer; a solder ball located on the first The three openings are electrically connected to the metal rewiring layer and the circuit board.
  • the packaged device further includes: a first barrier layer located on a side of the metal rewiring layer away from the chip, and a third opening formed in the first barrier layer; a second seed layer covering the The third opening is provided on the side of the first barrier layer away from the chip; the under-ball metal layer is provided on the side of the second seed layer away from the chip; the solder ball is provided on the The metal layer under the ball is away from the side of the chip; wherein, the solder ball, the metal layer under the ball, the second seed layer, and the metal rewiring layer are electrically connected.
  • the transparent protective layer is formed directly on the front of the chip.
  • this method can control the thickness of the transparent protective layer, compared with the traditional The way of setting transparent glass, the thickness of the transparent protective layer is less than the thickness of the transparent glass, which can reduce light refraction, reflection and energy loss, etc., and improve the sensitivity of the chip; on the other hand, because the transparent protective layer is formed directly on the front of the chip, transparent The probability of the protective layer detaching from the front of the chip is low, which further reduces the dust-free requirements for the use environment.
  • FIG. 1 is a schematic flowchart of an embodiment of a semiconductor chip packaging method of this application.
  • FIG. 2 is a schematic flowchart of an embodiment of step S101 in FIG. 1;
  • FIG. 3 is a schematic structural diagram of an embodiment of a semiconductor package device corresponding to steps S201-S203 in FIG. 2;
  • FIG. 4 is a schematic structural view of an embodiment of a semiconductor package device corresponding to steps S102-S103 in FIG. 1;
  • FIG. 5 is a schematic flowchart of an implementation manner of step S103 in FIG. 1;
  • FIG. 6 is a schematic structural diagram of an embodiment of a semiconductor package device of the present application.
  • FIG. 7 is a schematic structural diagram of another embodiment of a semiconductor package device of the present application.
  • FIG. 1 is a schematic flowchart of an embodiment of a semiconductor chip packaging method according to the present application.
  • the packaging method includes:
  • a chip is provided.
  • the chip includes a front side and a back side.
  • the front side of the chip is provided with a photosensitive area and a pad around the photosensitive area, and a transparent protective layer is formed on the front side of the chip.
  • the transparent protective layer covers the photosensitive area and the pad of the chip.
  • the photosensitive area of the chip is a more important part of the semiconductor packaging device. If the photosensitive area is exposed, external particles may easily pollute the photosensitive area and affect the imaging effect of the photosensitive area. Therefore, it is necessary to protect the photosensitive area of the chip of.
  • FIG. 2 is a schematic flowchart of an embodiment of step S101 in FIG. 1, and FIG. 3 is an implementation of a semiconductor package device corresponding to steps S201-S203 in FIG. Schematic diagram of the structure.
  • the above step S101 specifically includes:
  • a wafer 1 is provided, the wafer 1 is provided with a plurality of chips 10 arranged in a matrix, and a scribe groove 12 is provided between the chips 10, the wafer 1 includes a front surface 14 and a back surface 16, and the front surface 14 of the chip 10 is the wafer 1
  • the front surface 14 of the chip 10, the back surface 16 of the chip 10, that is, the back surface 16 of the wafer 1, the front surface 14 of the chip 10 is provided with a photosensitive region 100 and a pad 102 located around the photosensitive region 100.
  • a transparent protective layer 18 is formed on the front surface 14 of the chip 10, and the transparent protective layer 18 covers the photosensitive region 100 and the pad 102 of the chip 10.
  • the transparent protective layer 18 also covers the area corresponding to the dicing groove 12; of course, in other application scenarios, the transparent protective layer 18 may also cover only the photosensitive of the chip 10
  • the region 100 and the pad 102 do not cover or only partially cover the area corresponding to the scribe groove 12.
  • the method of forming the transparent protective layer 18 may be: forming the transparent protective layer 18 on the front surface 14 of the chip 10 by spin coating, dispensing, or printing, and curing the transparent protective layer 18, using the above method to form
  • the thickness of the transparent protective layer 18 can reach the micron level. Compared with the traditional way of setting transparent glass, the thickness of the transparent protective layer 18 is smaller than the thickness of the transparent glass, which can reduce light refraction, reflection and energy loss, etc. effect.
  • the material of the transparent protective layer 18 may be an inorganic transparent material, for example, silicon nitride, silicon oxynitride, etc., or an organic transparent material, for example, polysiloxane, etc.
  • the method of curing the transparent protective layer 18 may be ultraviolet irradiation or high-temperature baking.
  • the specific method may be determined according to the initiator added to prepare the transparent protective layer 18. If the initiator is a photoinitiator (for example, , 2-hydroxy-2-methyl-1-phenylacetone, 1-hydroxycyclohexyl phenyl ketone, etc.), using ultraviolet irradiation; if the initiator is a thermal initiator (for example, benzoyl peroxide Etc.), use high-temperature baking.
  • the manner of cutting the dicing groove 12 may be any one of the prior art, which will not be described in detail here.
  • the transparent protective layer 18 is formed on the wafer 1 first, and then cut into single chips 10.
  • the wafer 1 may be cut into single chips 10 first.
  • the transparent protective layers 18 are formed one by one for the single chip 10, which is not limited in this application.
  • S102 Through holes 20 are formed on the back surface 16 of the chip 10 at positions corresponding to the pads 102, and the pads 102 correspond to the through holes 20 one by one, so that the pads 102 are exposed from the through holes 20.
  • the method provided by the present application further includes: setting a substrate on the side of the transparent protective layer 18 away from the chip 10; grinding the back surface 16 of the chip 10 to make the chip 10
  • the thickness is less than or equal to the predetermined thickness.
  • the side of the transparent protective layer 18 away from the chip 10 may be fixed to the substrate through a removable adhesive film or the like.
  • the thickness of the wafer directly taken from the packaging and testing factory is generally large. Therefore, in this embodiment, the back surface 16 side of the chip 10 needs to be ground to make the thickness less than or equal to a predetermined thickness, for example, the predetermined thickness is 100um
  • the thickness of the chip 10 after grinding is 50um, 60um, 80um, etc.
  • the material of the chip 10 is generally silicon. Since the silicon itself has poor conductivity, in order to achieve the purpose of electrically connecting the pad 102 to the subsequent circuit board, the back of the chip 10 can be 16
  • the through hole 20 is formed.
  • the state of the chip 10 may be set so that the side having the pad 102 is located below; then the through hole 20 is formed at a position of the chip 10 facing away from the pad 102.
  • a plasma etching method may be used to form a through hole 20 on the back surface 16 of the chip 10 at a position corresponding to the pad 102, and all or part of the pad 102 is exposed from the through hole 20.
  • the through hole 20 may also be formed in other forms, which is not limited in this application.
  • a passivation layer such as silicon dioxide, is provided on the side of the pad 102 that is in contact with the front surface of the chip 10. After forming the through hole 20, a second etching is required to remove the passivation layer on the pad 102 .
  • the size of the through-hole 20 from the side of the pad 102 to the back surface 16 of the chip 10 is the same.
  • the size of the through-hole 20 may also be other ways, for example, the through-hole 20
  • the dimension from the side of the pad 102 to the back surface 16 of the chip 10 may also gradually increase, and all or part of the pad 102 is exposed from the through hole 20.
  • S103 The pad 102 of the chip 10 is electrically connected to the circuit board 25 through the through hole 20.
  • the above step S103 specifically includes: forming a metal rewiring layer 28 in the through hole 20, one end of the metal rewiring layer 28 is electrically connected to the pad 102 of the chip 10, and the metal rewiring layer 28 The other end is electrically connected to the circuit board 25.
  • FIG. 5 is a schematic flowchart of an implementation manner of step S103 in FIG. 1.
  • the above step S103 specifically includes:
  • a first mask layer 22 is formed in the area of the back surface 16 of the chip 10 and the through-hole 20, and a first opening 220 is formed at the position of the first mask layer 22 corresponding to the pad 102.
  • a layer of first mask layer 22 is first coated on the surface of the back surface 16 of the chip 10 and the area of the through hole 20, and then the first mask layer is exposed by exposure development or other means
  • the film layer 22 forms a first opening 220 corresponding to the position of the pad 102 so that the pad 102 is exposed.
  • the material of the first mask layer 22 is one or more of photoresist, silicon oxide, silicon nitride, and amorphous carbon.
  • the material of the first seed layer 24 is one or a mixture of titanium, aluminum, copper, gold, and silver.
  • the process of forming the first seed layer 24 may be a sputtering process or physical Vapor deposition process.
  • S403 Form a second mask layer 26 on the surface of the first seed layer 24 away from the chip 10, and form a second opening 260 on the second mask layer 26.
  • a second mask layer 26 is first coated on the surface of the first seed layer 24 away from the chip 10, and then the second mask layer is exposed or developed by exposure or other means. 26 forms a second opening 260, which is located above the pad 102.
  • the material of the second mask layer 26 is one or more of photoresist, silicon oxide, silicon nitride, and amorphous carbon.
  • a metal rewiring layer 28 is formed in the second opening 260.
  • a metal rewiring layer 28 may be formed in the second opening 260 using an electroplating process.
  • the material of the metal rewiring layer 28 is copper or other suitable metals.
  • the height of the metal rewiring layer 28 is the same as the depth of the second opening 260; of course, in other embodiments, the height of the metal rewiring layer 28 may also be lower than the depth of the second opening 260.
  • the second mask layer 26 may be removed by a photolithography process to expose the first seed layer 24; then, a wet etching process or a dry etching process may be used. The process removes the exposed portion of the first seed layer 24, leaving only the first seed layer 24 under the metal redistribution layer 28, wherein the pad 102, the first seed layer 24, and the metal redistribution layer 28 are electrically connected.
  • a first barrier layer 21 is provided on the surface of the metal rewiring layer 28 facing away from the silicon wafer base layer, and a third opening 210 is formed on the first barrier layer 21;
  • the material of the first barrier layer 21 has insulating properties.
  • the third opening 210 may be formed on the first barrier layer 21 by photolithography or other etching methods.
  • a solder ball 23 is provided in the third opening 210.
  • the solder ball 23 may be directly provided in the third opening 210.
  • the solder ball 23 is implanted in the third opening 210 by using a ball implanter.
  • the material of the solder ball 23 is tin or tin alloy.
  • the solder ball 23 and the metal rewiring layer 28 are electrically connected; in another application scenario, a metal layer under the ball can also be formed on the metal rewiring layer 28, and then the ball is implanted on the metal layer under the ball.
  • a second seed layer can be formed on the surface of the first barrier layer away from the chip.
  • the second seed layer can be sputtered: first form a titanium layer, and then sputter a copper layer on the titanium layer;
  • the second seed layer forms a third mask layer away from the surface of the chip, and a fourth opening is formed on the third mask layer corresponding to the third opening;
  • a metal layer under the ball is formed in the fourth opening, the material of the metal layer under the ball It can be metal copper, which can be formed by electroplating; remove the third mask layer and the corresponding second seed layer under the third mask layer; form a solder ball on the corresponding position of the metal layer under the ball, which can be passed through a ball planting machine The solder ball is dropped to the position of the corresponding metal layer under the ball, and then formed by reflow; wherein, the solder ball, the metal layer under the ball, the second seed layer, and the metal rewiring layer are electrically connected.
  • solder ball 23 is electrically connected to the circuit board 25.
  • the solder ball 23 and the circuit board 25 can be electrically connected by means of thermal reflow.
  • the packaging method provided by the present application further includes removing the substrate.
  • the chip 10 and the circuit board 25 are electrically connected in the above manner.
  • the chip 10 and the circuit board 25 may be electrically connected in other ways.
  • the metal rewiring layer 28 is formed, the The metal rewiring layer 28 is electrically connected to the circuit board 25.
  • the method provided by the present application further includes: filling the area between the transparent protective layer 18 and the circuit board 25 with a plastic encapsulant to form The plastic encapsulation layer does not cover the transparent protective layer 18 corresponding to the photosensitive area 100 of the chip 10.
  • a protective adhesive film may be provided on the side of the transparent protective layer 18 away from the circuit board 25 to control the height of the plastic encapsulation layer so that the distance between the plastic encapsulation layer and the circuit board 25 is equal to or less than that between the transparent protective layer 18 and the circuit board 25 distance.
  • the semiconductor chip packaging device prepared by the above semiconductor chip packaging method is further described below.
  • FIG. 6 is a schematic structural diagram of an embodiment of a semiconductor package device of the present application.
  • the semiconductor package device includes:
  • the chip 10, the chip 10 includes a front side 14 and a back side 16, the front side 14 of the chip 10 is provided with a photosensitive area 100 and a pad 102 around the photosensitive area 100;
  • the vias correspond to the pads 102 one by one; in an application scenario, the vias can be formed by plasma etching, and the vias have the same size in the direction from the pad 102 side to the back surface 16 of the chip 10. In another application scenario, the size of the via hole gradually increases from the side of the pad 102 to the back surface 16 of the chip 10, and all or part of the pad 102 is exposed from the through hole.
  • the transparent protective layer 18 is located on the front side 14 of the chip 10 and covers the photosensitive region 100 and the pad 102 of the chip 10; specifically, the transparent protective layer 18 can be formed by spin coating, dispensing or printing, and the transparent protective layer 18 is ultraviolet
  • the material cured by irradiation or baking, for example, the material may be an inorganic transparent material or an organic transparent material, which is not limited in this application.
  • the circuit board 25 is electrically connected to the pad 102 of the chip 10 through a through hole.
  • a metal rewiring layer 28 may be introduced into the semiconductor package device, and the chip 10 and the circuit board 25 are electrically connected through the metal rewiring layer 28.
  • the semiconductor package device provided in this application further includes a metal rewiring layer 28 located on the back surface 16 of the chip 10 and extending into the through hole. One end of the metal rewiring layer 28 is electrically connected to the pad 102 The other end of the metal redistribution layer 28 is electrically connected to the circuit board 25.
  • the above semiconductor device further includes: a first mask layer 22 located between the back surface 16 of the chip 10 and the metal rewiring layer 28, and the first mask layer 22 corresponds to soldering A first opening (not shown) is provided at the position of the disc 102; a first seed layer 24 is located between the first mask layer 22 and the metal rewiring layer 28, and the pad 102, the first seed layer 24, and the metal rewiring Layer 28 is electrically connected.
  • the chip 10 and the circuit board 25 may be electrically connected by providing a solder ball 23.
  • the semiconductor package device provided by the present application further includes: a first barrier layer 21 located on a side of the metal rewiring layer 28 away from the chip 10, and a third opening (not shown) is formed on the first barrier layer 21 (Marked); the solder ball 23 is located in the third opening and is electrically connected to the metal rewiring layer 28 and the circuit board 25.
  • the manner of providing solder balls in the foregoing embodiments may be other, for example, by providing a metal layer under the ball.
  • FIG. 7 is a schematic structural diagram of another embodiment of a semiconductor package device according to the present application, and the same parts as those in the foregoing embodiments are not described herein again.
  • the semiconductor package device provided in this embodiment further includes: a first barrier layer 21 located on a side of the metal rewiring layer 28 away from the chip 10, and a third opening (not labeled) formed on the first barrier layer 21;
  • the second seed layer 40 covers the third opening and is disposed on the side of the first barrier layer 21 away from the chip 10;
  • the under-ball metal layer 42 is disposed on the side of the second seed layer 40 away from the chip 10;
  • the solder ball 23 is disposed
  • the under-ball metal layer 42 is away from the side of the chip 10; wherein, the solder ball 23, the under-ball metal layer 42, the second seed layer 40, and the metal rewiring layer 28 are electrically connected.
  • the transparent protective layer is formed directly on the front side of the chip.
  • this method can control the thickness of the transparent protective layer, compared with the traditional way of setting transparent glass
  • the thickness of the transparent protective layer is less than the thickness of the transparent glass, which can reduce light refraction, reflection and energy loss, etc., and improve the sensitivity of the chip; on the other hand, because the transparent protective layer is formed directly on the front of the chip, the transparent protective layer and the front of the chip The probability of detachment is low, which in turn reduces the dust-free requirements of the use environment.

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Abstract

本申请公开了一种半导体芯片封装方法及封装器件，所述封装方法包括：提供芯片，所述芯片包括正面和背面，所述芯片的正面设置有感光区和位于感光区周围的焊盘，且所述芯片的正面形成有透明保护层，所述透明保护层覆盖所述芯片的所述感光区和所述焊盘；在所述芯片的背面对应所述焊盘的位置形成通孔，且所述焊盘与所述通孔一一对应，以使得所述焊盘从所述通孔中露出；将所述芯片的所述焊盘透过所述通孔与电路板电连接。通过上述方式，本申请能够提高芯片的感光效果。

Description

一种半导体芯片封装方法及封装器件 技术领域
本申请涉及半导体技术领域，特别是涉及一种半导体芯片封装方法及封装器件。
背景技术
具有感光区的芯片是摄像设备十分重要的组成部分，为保护芯片的感光区，常用的封装方法包括：在芯片的感光区的上方增加透明玻璃盖板以保护芯片的感光区。
本申请的发明人在长期研究过程中发现，一方面，由于透明玻璃盖板厚度一般较厚，光线穿透透明玻璃时会发生折射、反射和能量损失等，会使芯片的感光效果变差；另一方面，透明玻璃盖板与芯片之间通过胶连接，使用较长时间后，胶容易脱落，外界灰尘容易进入芯片的感光区，进而影响芯片的感光效果。
发明内容
本申请主要解决的技术问题是提供一种半导体芯片封装方法及封装器件，能够提高芯片的感光效果。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种半导体芯片封装方法，所述封装方法包括：提供芯片，所述芯片包括正面和背面，所述芯片的正面设置有感光区和位于感光区周围的焊盘，且所述芯片的正面形成有透明保护层，所述透明保护层覆盖所述芯片的所述感光区和所述焊盘；在所述芯片的所述背面对应所述焊盘的位置形成通孔，且所述焊盘与所述通孔一一对应，以使得所述焊盘从所述通孔中露出；将所述芯片的所述焊盘透过所述通孔与电路板电连接。
其中，所述提供芯片包括：提供圆片，所述圆片设有多个矩阵排列的所述芯片，所述芯片之间设有划片槽，所述圆片包括正面及背面，所述芯片的正面即所述圆片的正面，所述芯片的背面即所述圆片的背面，所述芯片的正面设置有感光区和位于感光区周围的焊盘；在所述芯片的正面形成透明保护层，所述透明保护层覆盖所述芯片的感光区和焊盘；沿所述划片槽进行切割，以切割掉 所述划片槽对应的所述圆片和所述透明保护层，进而获得单颗芯片。
其中，在所述芯片的正面形成透明保护层，包括：在所述芯片正面利用旋涂、点胶或印刷的方式形成所述透明保护层，并使所述透明保护层固化。
其中，所述使所述透明保护层固化包括：利用紫外线照射或者烘烤的方式使所述透明保护层固化。
其中，所述在所述芯片的背面对应所述焊盘的位置形成通孔之前，所述封装方法还包括：在所述透明保护层远离所述芯片的一侧设置基板；研磨所述芯片的背面，以使得所述芯片的厚度小于等于预定厚度；所述将所述芯片的所述焊盘透过所述通孔与电路板电连接之后，所述封装方法还包括：去除所述基板。
其中，所述在所述芯片的背面对应所述焊盘的位置形成通孔，包括：设置所述芯片的状态使其具有所述焊盘的一侧位于下方；在所述芯片的背面对应所述焊盘的位置形成通孔，所述焊盘的全部或者部分从所述通孔中露出。
其中，所述通孔从所述焊盘一侧至所述芯片的背面方向尺寸相同；或者，所述通孔从所述焊盘一侧至所述芯片的背面方向尺寸逐渐增大。
其中，所述将所述芯片的所述焊盘透过所述通孔与电路板电连接，包括：在所述通孔内形成金属再布线层，所述金属再布线层的一端与所述芯片的所述焊盘电连接，所述金属再布线层的另一端与所述电路板电连接。
其中，所述在所述通孔内形成金属再布线层，包括：在所述芯片的所述背面以及所述通孔的区域形成第一掩膜层，并在所述第一掩膜层对应所述焊盘的位置形成第一开口；在所述第一掩膜层远离所述芯片的表面形成第一种子层；在所述第一种子层远离所述芯片的表面形成第二掩膜层，并在所述第二掩膜层上形成第二开口；在所述第二开口内形成所述金属再布线层；去除所述第二掩膜层以及所述金属再布线层以外的所述第一种子层。
其中，所述去除所述第二掩膜层以及所述金属再布线层以外的所述第一种子层，之后，所述封装方法还包括：在所述金属再布线层背对所述芯片的表面设置第一阻挡层，并在第一阻挡层上形成第三开口；在所述第三开口内设置焊球，所述焊球与所述电路板电连接。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种半导体封装器件，所述封装器件包括：芯片，所述芯片包括正面和背面，所述芯片的正面设置有感光区和位于感光区周围的焊盘；所述芯片对应所述焊盘的位置设置有通孔，所述通孔与所述焊盘一一对应；透明保护层，位于所述芯片的正面 且覆盖所述芯片的所述感光区和所述焊盘；电路板，与所述芯片的所述焊盘透过所述通孔电连接。
其中，所述透明保护层由旋涂、点胶或印刷的方式形成。
其中，所述透明保护层为经紫外线照射或者烘烤的方式固化后的材质。
其中，所述透明保护层的材质包括无机透明材质和/或有机透明材质，所述无机透明材质包括氮化硅、氮氧化硅中至少一种，所述有机透明材质包括聚硅氧烷。
其中，所述通孔从所述焊盘一侧至所述芯片的所述背面方向尺寸相同。
其中，所述通孔从所述焊盘一侧至所述芯片的所述背面方向尺寸逐渐增大。
其中，所述封装器件还包括：金属再布线层，位于所述芯片的所述背面且延伸入所述通孔中，所述金属再布线层的一端与所述焊盘电连接，所述金属再布线层的另一端与所述电路板电连接。
其中，所述封装器件还包括：第一掩膜层，位于所述芯片的背面与所述金属再布线层之间，且所述第一掩膜层对应所述焊盘的位置设置有第一开口；第一种子层，位于所述第一掩膜层与所述金属再布线层之间，且所述焊盘、所述第一种子层、所述金属再布线层电连接。
其中，所述封装器件还包括：第一阻挡层，位于所述金属再布线层远离所述芯片的一侧，且所述第一阻挡层上形成有第三开口；焊球，位于所述第三开口内，且与所述金属再布线层、所述电路板电连接。
其中，所述封装器件还包括：第一阻挡层，位于所述金属再布线层远离所述芯片的一侧，且所述第一阻挡层上形成有第三开口；第二种子层，覆盖所述第三开口，且设置在所述第一阻挡层远离所述芯片的一侧；球下金属层，设置于所述第二种子层远离所述芯片的一侧；焊球，设置于所述球下金属层远离所述芯片的一侧；其中，所述焊球、所述球下金属层、所述第二种子层、所述金属再布线层电连接。
本申请的有益效果是：区别于现有技术的情况，本申请所提供的封装方法中透明保护层是直接在芯片正面形成，一方面，该方式可以控制透明保护层的厚度，相对于传统的设置透明玻璃的方式，透明保护层的厚度小于透明玻璃的厚度，进而可以减少光线折射、反射和能量损失等，提高芯片的感光效果；另一方面，由于透明保护层直接在芯片正面形成，透明保护层与芯片正面脱离的概率较低，进而降低对使用环境的无尘要求。
【附图说明】
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，其中：
图1是本申请半导体芯片封装方法一实施方式的流程示意图；
图2是图1中步骤S101一实施方式的流程示意图；
图3是图2中步骤S201-S203对应的半导体封装器件一实施方式的结构示意图；
图4是图1中步骤S102-S103对应的半导体封装器件一实施方式的结构示意图；
图5是图1中步骤S103一实施方式的流程示意图；
图6是本申请半导体封装器件一实施方式的结构示意图；
图7是本申请半导体封装器件另一实施方式的结构示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，图1为本申请半导体芯片封装方法一实施方式的流程示意图，该封装方法包括：
S101：提供芯片，芯片包括正面和背面，芯片的正面设置有感光区和位于感光区周围的焊盘，且芯片的正面形成有透明保护层，透明保护层覆盖芯片的感光区和焊盘。
具体地，芯片的感光区是半导体封装器件中较为重要的部分，若感光区裸露，外界颗粒物容易对感光区造成污染，影响感光区的成像效果，因此，对芯片的感光区进行保护是十分必要的。
在一个实施方式中，请一并参阅图2和图3，其中，图2为图1中步骤S101一实施方式的流程示意图，图3为图2中步骤S201-S203对应的半导体封装器 件一实施方式的结构示意图。上述步骤S101具体包括：
S201：提供圆片1，圆片1设有多个矩阵排列的芯片10，芯片10之间设有划片槽12，圆片1包括正面14及背面16，芯片10的正面14即圆片1的正面14，芯片10的背面16即圆片1的背面16，芯片10的正面14设置有感光区100和位于感光区100周围的焊盘102。
S202：在芯片10的正面14形成透明保护层18，透明保护层18覆盖芯片10的感光区100和焊盘102。
具体地，在一个应用场景中，如图3b所示，透明保护层18还覆盖划片槽12对应的区域；当然，在其他应用场景中，也可使透明保护层18仅覆盖芯片10的感光区100和焊盘102，而不覆盖或者仅部分覆盖划片槽12对应的区域。
在另一个应用场景中，形成透明保护层18的方法可以是：在芯片10正面14利用旋涂、点胶或印刷的方式形成透明保护层18，并使透明保护层18固化，采用上述方法形成透明保护层18的厚度可以达到微米级别，相对于传统的设置透明玻璃的方式，透明保护层18的厚度小于透明玻璃的厚度，进而可以减少光线折射、反射和能量损失等，提高芯片10的感光效果。透明保护层18的材质可以是无机透明材质，例如，氮化硅、氮氧化硅等，也可以是有机透明材质，例如，聚硅氧烷等。另外，使透明保护层18固化的方式可以是紫外线照射或者高温烘烤的方式，具体采用何种方式，可以根据制备透明保护层18所添加的引发剂决定，若引发剂为光引发剂(例如，2-羟基-2-甲基-1-苯基丙酮、1-羟基环己基苯基甲酮等)，则利用紫外线照射的方式；若引发剂为热引发剂(例如，过氧化苯甲酰等)，则利用高温烘烤的方式。
S203：沿划片槽12进行切割，以切割掉划片槽12对应的圆片1和透明保护层18，进而获得单颗芯片10。
具体地，切割划片槽12的方式可以是现有技术中任一种，在此不再详述。
上述实施方式中是先在圆片1上统一形成透明保护层18后，再切割成单颗芯片10的方法，当然，在其他实施方式中，也可以将圆片1先切割成单颗芯片10后，针对单颗芯片10逐个形成透明保护层18，本申请对此不作限定。
S102：在芯片10的背面16对应焊盘102的位置形成通孔20，且焊盘102与通孔20一一对应，以使得焊盘102从通孔20中露出。
具体地，在一个应用场景中，在该步骤S102之前，本申请所提供的方法还包括：在透明保护层18远离芯片10的一侧设置基板；研磨芯片10的背面16， 以使得芯片10的厚度小于等于预定厚度。具体地，透明保护层18远离芯片10的一侧可以通过可去除胶膜等与基板固定。另外，一般从封测厂直接拿取的圆片厚度较大，因此在本实施例中，需要将芯片10的背面16一侧进行研磨，以使得其厚度小于等于预定厚度，例如预定厚度为100um，研磨后芯片10的厚度为50um、60um、80um等。
在另一个应用场景中，请参阅图4a，芯片10的材质一般为硅，由于硅本身导电性较差，因此为达到焊盘102与后续电路板电连接的目的，可在芯片10的背面16形成通孔20。在一个实施方式中，可先设置芯片10的状态使其具有焊盘102的一侧位于下方；然后在芯片10的背对焊盘102的位置形成通孔20。在一个应用场景中，可利用等离子体蚀刻的方式在芯片10的背面16对应焊盘102的位置形成通孔20，焊盘102的全部或者部分从通孔20中露出。当然在其他应用场景中，也可采用其他形式形成通孔20，本申请对此不作限定。另外，焊盘102与芯片10正面接触的一侧设置有钝化层，例如二氧化硅等，在上述形成通孔20后，还需进行二次蚀刻，以去除掉焊盘102上钝化层。在另一个应用场景中，通孔20从焊盘102一侧至芯片10的背面16方向尺寸相同，当然，在其他应用场景中，通孔20的尺寸也可为其他方式，例如，通孔20从焊盘102一侧至芯片10的背面16方向尺寸也可逐渐增大，焊盘102的全部或者部分从通孔20中露出。
S103：将芯片10的焊盘102透过通孔20与电路板25电连接。
具体地，在一个实施方式中，上述步骤S103具体包括：在通孔20内形成金属再布线层28，金属再布线层28的一端与芯片10的焊盘102电连接，金属再布线层28的另一端与电路板25电连接。
在一个应用场景中，请一并参阅图4和图5，图5为图1中步骤S103一实施方式的流程示意图，上述步骤S103具体包括：
S401：在芯片10的背面16以及通孔20的区域形成第一掩膜层22，并在第一掩膜层22对应焊盘102的位置形成第一开口220。
具体地，请参阅图4b，在一个实施方式中，首先在芯片10的背面16以及通孔20区域的表面涂覆一层第一掩膜层22，接着通过曝光显影或者其他手段将第一掩膜层22对应焊盘102的位置形成第一开口220，使得焊盘102露出。在一个应用场景中，第一掩膜层22的材料为光刻胶、氧化硅、氮化硅、无定形碳其中的一种或几种。
S402：在第一掩膜层22远离芯片10的表面形成第一种子层24。
具体地，请参阅图4c，第一种子层24的材料为钛、铝、铜、金、银其中的一种或几种的混合物，形成第一种子层24的工艺可以为溅射工艺或物理气相沉积工艺。
S403：在第一种子层24远离芯片10的表面形成第二掩膜层26，并在第二掩膜层26上形成第二开口260。
具体地，请参阅图4d，在一个实施方式中，首先在第一种子层24远离芯片10的表面涂覆一层第二掩膜层26，接着通过曝光显影或者其他手段在第二掩膜层26形成第二开口260，第二开口260位于焊盘102上方。在一个应用场景中，第二掩膜层26的材料为光刻胶、氧化硅、氮化硅、无定形碳其中的一种或几种。
S404：在第二开口260内形成金属再布线层28。
具体地，请参阅图4e，在一个实施方式中，可以利用电镀工艺在第二开口260内形成金属再布线层28，金属再布线层28的材料为铜或其他合适的金属。在本实施方式中，金属再布线层28的高度与第二开口260的深度相同；当然，在其他实施方式中，金属再布线层28的高度也可低于第二开口260的深度。
S405：去除第二掩膜层26以及金属再布线层28以外的第一种子层24。
具体地，请参阅图4f，在一个实施方式中，可以先利用光刻工艺将第二掩膜层26去除，暴露出的第一种子层24；然后利用湿法刻蚀工艺或干法刻蚀工艺去除暴露出的部分第一种子层24，仅保留位于金属再布线层28下方的第一种子层24，其中，焊盘102、第一种子层24、金属再布线层28电连接。
S406：在金属再布线层28背对硅晶圆基层的表面设置第一阻挡层21，并在第一阻挡层21上形成第三开口210；
具体地，请参阅图4g，第一阻挡层21的材质具有绝缘特性，在一个实施方式中，可以利用光刻或者其他刻蚀的方式在第一阻挡层21上形成第三开口210。
S407：在第三开口210内设置焊球23。
具体地，请参阅图4h，可以直接在在第三开口210内设置焊球23，例如，利用植球机在第三开口210内植焊球23，焊球23的材质为锡或者锡合金。其中，焊球23和金属再布线层28电连接；在另一个应用场景中，还可以在金属再布线层28上形成球下金属层，然后在球下金属层上进行植球，本申请对此不作限定。例如，可在第一阻挡层远离芯片的表面形成第二种子层，第二种子层可以采用溅射的方法：先形成一层钛层，再在钛层上溅射一层铜层；在第二种子层 远离芯片的表面形成第三掩膜层，并在第三掩膜层上对应第三开口的位置形成第四开口；在第四开口内形成球下金属层，球下金属层的材质可以是金属铜，其可采用电镀的方式形成；去除第三掩膜层及第三掩膜层下方对应的第二种子层；在球下金属层对应位置上形成焊球，可以通过植球机将焊球落到对应的球下金属层的位置，再经过回流形成；其中，焊球、球下金属层、第二种子层、金属再布线层电连接。
S408：焊球23与电路板25电连接。
具体地，请参阅图4i，可利用热回流的方式将焊球23与电路板25电连接。当芯片10的透明保护层18一侧设置有基板时，在上述步骤S408之后，本申请所提供的封装方法还包括去除基板。
通过上述方式使得芯片10与电路板25电连接，当然在其他实施方式中，芯片10与电路板25电连接的方式也可为其他，例如，在上述形成金属再布线层28后，可直接将金属再布线层28与电路板25电连接。
在另一个实施方式中，为增强半导体封装器件的防水性能，在上述步骤S103之后，本申请所提供的方法还包括：将透明保护层18与电路板25之间的区域填充塑封料，以形成塑封层，塑封层不覆盖芯片10的感光区100对应的透明保护层18。例如，可以在透明保护层18远离电路板25一侧设置保护胶膜，以控制塑封层的高度，使得塑封层与电路板25之间的距离等于或者小于透明保护层18与电路板25之间的距离。
下面对利用上述半导体芯片封装方法所制备获得的半导体芯片封装器件做进一步说明。
请参阅图6，图6为本申请半导体封装器件一实施方式的结构示意图。该半导体封装器件包括：
芯片10，芯片10包括正面14和背面16，芯片10的正面14设置有感光区100和位于感光区100周围的焊盘102；芯片10对应焊盘102的位置设置有通孔(未标示)，通孔与焊盘102一一对应；在一个应用场景中，通孔可以通过等离子蚀刻的方式形成，通孔从焊盘102一侧至芯片10的背面16方向尺寸相同。在另一个应用场景中，通孔从焊盘102一侧至芯片10的背面16方向尺寸逐渐增大，焊盘102的全部或者部分从通孔中露出。
透明保护层18，位于芯片10的正面14且覆盖芯片10的感光区100和焊盘102；具体地，透明保护层18可由旋涂、点胶或印刷的方式形成，透明保护层 18为经紫外照射或者烘烤的方式固化后的材质，例如，其材质可以是无机透明材料或者有机透明材料，本申请对此不作限定。
电路板25，与芯片10的焊盘102透过通孔电连接。
在一个实施方式中，可在半导体封装器件中引入金属再布线层28，通过金属再布线层28电连接芯片10与电路板25。具体地，请继续参阅图6，本申请所提供的半导体封装器件还包括金属再布线层28，位于芯片10的背面16且延伸入通孔中，金属再布线层28的一端与焊盘102电连接，金属再布线层28的另一端与电路板25电连接。
在另一个实施方式中，请继续参阅图6，上述半导体器件还包括：第一掩膜层22，位于芯片10的背面16与金属再布线层28之间，且第一掩膜层22对应焊盘102的位置设置有第一开口(未标示)；第一种子层24，位于第一掩膜层22与金属再布线层28之间，且焊盘102、第一种子层24、金属再布线层28电连接。
在又一个实施方式中，还可采取设置焊球23的方式将芯片10与电路板25电连接。请再次参阅图6，本申请所提供的半导体封装器件还包括：第一阻挡层21，位于金属再布线层28远离芯片10的一侧，且第一阻挡层21上形成有第三开口(未标示)；焊球23，位于第三开口内，且与金属再布线层28、电路板25电连接。
在又一个实施方式中，上述实施例中设置焊球的方式还可为其他，例如，通过设置球下金属层的方式。具体地，请参阅图7，图7为本申请半导体封装器件另一实施方式的结构示意图，其与上述实施例中相同的部分在此不再赘述。本实施例中所提供的半导体封装器件还包括：第一阻挡层21，位于金属再布线层28远离芯片10的一侧，且第一阻挡层21上形成有第三开口(未标示)；第二种子层40，覆盖第三开口，且设置在第一阻挡层21远离芯片10的一侧；球下金属层42，设置于第二种子层40远离芯片10的一侧；焊球23，设置于球下金属层42远离芯片10的一侧；其中，焊球23、球下金属层42、第二种子层40、金属再布线层28电连接。
总而言之，区别于现有技术的情况，本申请所提供的封装方法中透明保护层是直接在芯片正面形成，一方面，该方式可以控制透明保护层的厚度，相对于传统的设置透明玻璃的方式，透明保护层的厚度小于透明玻璃的厚度，进而可以减少光线折射、反射和能量损失等，提高芯片的感光效果；另一方面，由 于透明保护层直接在芯片正面形成，透明保护层与芯片正面脱离的概率较低，进而降低对使用环境的无尘要求。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种半导体芯片封装方法，其特征在于，所述封装方法包括：
    提供芯片，所述芯片包括正面和背面，所述芯片的正面设置有感光区和位于感光区周围的焊盘，且所述芯片的正面形成有透明保护层，所述透明保护层覆盖所述芯片的所述感光区和所述焊盘；
    在所述芯片的所述背面对应所述焊盘的位置形成通孔，且所述焊盘与所述通孔一一对应，以使得所述焊盘从所述通孔中露出；
    将所述芯片的所述焊盘透过所述通孔与电路板电连接。
  2. 根据权利要求1所述的封装方法，其特征在于，所述提供芯片包括：
    提供圆片，所述圆片设有多个矩阵排列的所述芯片，所述芯片之间设有划片槽，所述圆片包括正面及背面，所述芯片的正面即所述圆片的正面，所述芯片的背面即所述圆片的背面，所述芯片的正面设置有感光区和位于感光区周围的焊盘；
    在所述芯片的正面形成透明保护层，所述透明保护层覆盖所述芯片的感光区和焊盘；
    沿所述划片槽进行切割，以切割掉所述划片槽对应的所述圆片和所述透明保护层，进而获得单颗芯片。
  3. 根据权利要求1或2所述的封装方法，其特征在于，在所述芯片的正面形成透明保护层，包括：
    在所述芯片正面利用旋涂、点胶或印刷的方式形成所述透明保护层，并使所述透明保护层固化。
  4. 根据权利要求3所述的封装方法，其特征在于，所述使所述透明保护层固化包括：
    利用紫外线照射或者烘烤的方式使所述透明保护层固化。
  5. 根据权利要求1所述的封装方法，其特征在于，
    所述在所述芯片的背面对应所述焊盘的位置形成通孔之前，所述封装方法还包括：在所述透明保护层远离所述芯片的一侧设置基板；研磨所述芯片的背面，以使得所述芯片的厚度小于等于预定厚度；
    所述将所述芯片的所述焊盘透过所述通孔与电路板电连接之后，所述封装方法还包括：去除所述基板。
  6. 根据权利要求1所述的封装方法，其特征在于，所述在所述芯片的背面 对应所述焊盘的位置形成通孔，包括：
    设置所述芯片的状态使其具有所述焊盘的一侧位于下方；
    在所述芯片的背面对应所述焊盘的位置形成通孔，所述焊盘的全部或者部分从所述通孔中露出。
  7. 根据权利要求6所述的封装方法，其特征在于，
    所述通孔从所述焊盘一侧至所述芯片的背面方向尺寸相同；或者，所述通孔从所述焊盘一侧至所述芯片的背面方向尺寸逐渐增大。
  8. 根据权利要求1所述的封装方法，其特征在于，所述将所述芯片的所述焊盘透过所述通孔与电路板电连接，包括：
    在所述通孔内形成金属再布线层，所述金属再布线层的一端与所述芯片的所述焊盘电连接，所述金属再布线层的另一端与所述电路板电连接。
  9. 根据权利要求8所述的封装方法，其特征在于，所述在所述通孔内形成金属再布线层，包括：
    在所述芯片的所述背面以及所述通孔的区域形成第一掩膜层，并在所述第一掩膜层对应所述焊盘的位置形成第一开口；
    在所述第一掩膜层远离所述芯片的表面形成第一种子层；
    在所述第一种子层远离所述芯片的表面形成第二掩膜层，并在所述第二掩膜层上形成第二开口；
    在所述第二开口内形成所述金属再布线层；
    去除所述第二掩膜层以及所述金属再布线层以外的所述第一种子层。
  10. 根据权利要求9所述的封装方法，其特征在于，所述去除所述第二掩膜层以及所述金属再布线层以外的所述第一种子层，之后，所述封装方法还包括：
    在所述金属再布线层背对所述芯片的表面设置第一阻挡层，并在第一阻挡层上形成第三开口；
    在所述第三开口内设置焊球，所述焊球与所述电路板电连接。
  11. 一种半导体封装器件，其特征在于，所述封装器件包括：
    芯片，所述芯片包括正面和背面，所述芯片的正面设置有感光区和位于感光区周围的焊盘；所述芯片对应所述焊盘的位置设置有通孔，所述通孔与所述焊盘一一对应；
    透明保护层，位于所述芯片的正面且覆盖所述芯片的所述感光区和所述焊 盘；
    电路板，与所述芯片的所述焊盘透过所述通孔电连接。
  12. 根据权利要求11所述的封装器件，其特征在于，所述透明保护层由旋涂、点胶或印刷的方式形成。
  13. 根据权利要求11所述的封装器件，其特征在于，所述透明保护层为经紫外线照射或者烘烤的方式固化后的材质。
  14. 根据权利要求11所述的封装器件，其特征在于，所述透明保护层的材质包括无机透明材质和/或有机透明材质，所述无机透明材质包括氮化硅、氮氧化硅中至少一种，所述有机透明材质包括聚硅氧烷。
  15. 根据权利要求11所述的封装器件，其特征在于，所述通孔从所述焊盘一侧至所述芯片的所述背面方向尺寸相同。
  16. 根据权利要求11所述的封装器件，其特征在于，所述通孔从所述焊盘一侧至所述芯片的所述背面方向尺寸逐渐增大。
  17. 根据权利要求11所述的封装器件，其特征在于，所述封装器件还包括：
    金属再布线层，位于所述芯片的所述背面且延伸入所述通孔中，所述金属再布线层的一端与所述焊盘电连接，所述金属再布线层的另一端与所述电路板电连接。
  18. 根据权利要求17所述的封装器件，其特征在于，所述封装器件还包括：
    第一掩膜层，位于所述芯片的背面与所述金属再布线层之间，且所述第一掩膜层对应所述焊盘的位置设置有第一开口；
    第一种子层，位于所述第一掩膜层与所述金属再布线层之间，且所述焊盘、所述第一种子层、所述金属再布线层电连接。
  19. 根据权利要求18所述的封装器件，其特征在于，所述封装器件还包括：
    第一阻挡层，位于所述金属再布线层远离所述芯片的一侧，且所述第一阻挡层上形成有第三开口；
    焊球，位于所述第三开口内，且与所述金属再布线层、所述电路板电连接。
  20. 根据权利要求18所述的封装器件，其特征在于，所述封装器件还包括：
    第一阻挡层，位于所述金属再布线层远离所述芯片的一侧，且所述第一阻挡层上形成有第三开口；
    第二种子层，覆盖所述第三开口，且设置在所述第一阻挡层远离所述芯片的一侧；
    球下金属层，设置于所述第二种子层远离所述芯片的一侧；
    焊球，设置于所述球下金属层远离所述芯片的一侧；
    其中，所述焊球、所述球下金属层、所述第二种子层、所述金属再布线层电连接。
PCT/CN2019/082309 2018-11-12 2019-04-11 一种半导体芯片封装方法及封装器件 WO2020098212A1 (zh)

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