CN102655166A - 一种用于功率器件击穿保护的栅漏箝位和静电放电保护电路 - Google Patents

一种用于功率器件击穿保护的栅漏箝位和静电放电保护电路 Download PDF

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CN102655166A
CN102655166A CN2012101816107A CN201210181610A CN102655166A CN 102655166 A CN102655166 A CN 102655166A CN 2012101816107 A CN2012101816107 A CN 2012101816107A CN 201210181610 A CN201210181610 A CN 201210181610A CN 102655166 A CN102655166 A CN 102655166A
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power device
grid
drain
clamp
semiconductor power
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CN102655166B (zh
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苏毅
安荷·叭剌
伍时谦
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

一种位于半导体衬底上的半导体功率器件，由多个晶体管单元组成，每个晶体管单元都有一个源极、一个栅极以及一个控制源极和栅极之间电流传输的漏极。这种半导体还包括一个栅漏箝位终端，串联在栅极和漏极之间，还包括多个背对背多晶硅二极管，串联在一个硅二极管上，在半导体衬底中，硅二极管含有平行掺杂纵栏，其中平行掺杂纵栏带有一个预设的缝隙。掺杂纵栏还包括一个U形弯管纵栏，将设置在U形弯管下方并包围U形弯管的深掺杂井，与平行掺杂纵栏末端连接在一起。

Description

一种用于功率器件击穿保护的栅漏箝位和静电放电保护电路
本案是分案申请
原案名称：一种用于功率器件击穿保护的栅漏箝位和静电放电保护电路
原案申请号：201010105906.1
原案申请日：2010年1月20日。
技术领域
本发明主要涉及半导体功率器件的设计和制造。更具体地说，本发明是关于栅漏箝位与静电放电保护电路相结合、用于功率器件击穿保护的一种新型结构，通过这种结构，能够获得更小的晶片尺寸、降低漏电流、更好地控制栅漏箝位击穿电压以及更低的生产成本。
背景技术
传统的用于制造带有击穿和静电放电保护电路的半导体功率器件的结构，仍然存在局限性。通常采用将多个栅漏稳压二极管置于晶粒周围。这些栅漏稳压二极管的制作方法可与栅源静电放电二极管用同样方法制造。这种结构会增加晶片尺寸，进而增加功率器件的制作成本。另一方面的技术难题来自于栅漏稳压二极管巨大的宽度。在这种结构中，漏电流Idss与稳压二极管的宽度成正比。稳压二极管越宽，就越难将漏电流限制在10微安以下，然而要使用这种功率器件，多数情况都要求漏电流在10微安以下。 
图1为传统半导体功率器件中经常使用的栅漏箝位的俯视图。栅漏箝位电压是由器件周围的多个稳压二极管110提供的。因此，如图所示，这些稳压二极管在晶片上占据了很大的面积。此外，正如上文提到的那样，这些形成在周围边缘的稳压二极管宽度很宽，会导致漏源漏电流Idss急剧升高，对箝位电路的性能造成不良的影响。  
 栅漏箝位和栅极晶体管一起工作，使场效应管形成开路，用于在漏源电压达到雪崩击穿之前，将场效应管保护起来，避免造成永久损害。正如美国专利5,365,099中所述，栅漏箝位仅与背对背多晶硅二极管一同起作用。背对背多晶硅二极管通常由P条纹和N条纹交替制成。但是，这种器件的缺陷在于多晶硅二极管占据了过多空间，其中每个条纹宽度约为5微米，才能承受高达6伏的击穿电压，
Shen等人在美国专利5,536,958中提出，一种通过一个集成肖特基二极管与多个背对背多晶硅二极管相连的有更好的电压保护的半导体器件，用于限制栅极和漏极终端之间可能升高的电势。在美国专利5,536,958的另一个实施例中，并不是在肖特基二极管中，而是在衬底中形成接触区，接触背对背二极管，接触区承载部分电压，通过夹断效应，由衬底承载剩余电压。此结构可以承载导电模式中的多余电压，而不是雪崩模式中的电压。另外，在1993年5月举行的功率半导体器件和集成电路国际研讨会上，Yamazaki等人提出通过集成含有多晶硅稳压二极管的绝缘栅双极晶体管（IGBT）结构与一个硅雪崩二极管，形成一种过电压保护电路。文中还指出，这种将多晶硅二极管与肖特基二极管或硅二极管组合的器件，仅能用于高击穿电压。另外，这种类型的箝位器件的击穿电压比较难控制。因此，在控制良好的低击穿电压时与硅二极管一起应用，通过空间有效结构，增补背对背多晶硅二极管，它们的栅漏箝位功能仍不可用。原有技术制造的栅漏箝位方法存在的另一问题是，在硅二极管末端的击穿电压比硅二极管其他区域的击穿电压更低。在达到所需的击穿电压之前，允许电流通过，这将对栅漏箝位的性能造成不良影响。由于在P-N结末端的电场较高，击穿电压也因此降低。
一个含有多晶硅二极管的栅漏箝位占据了很大的空间。正如之前介绍那样，传统的含有多晶硅二极管、用硅或肖特基二极管增补的栅漏箝位很难控制控制击穿电压。因此，有必要研发一种能够克服上述难题与局限的先进结构，用于半导体功率器件上的静电放电以及栅漏箝位电路。
发明内容
因此，本发明一方面在于提出了一种在半导体功率器件上，结合栅漏箝位的静电放电保护电路的新型改进结构，通过形成栅漏稳压二极管、硅二极管和小栅极电阻器的组合，用于功率金属氧化物半导体场效应管击穿保护。栅漏稳压二极管仅位于晶片的一侧。因此，晶片尺寸与传统设计相比有减小。又由于栅漏稳压二极管的宽度很小，漏电流Idss很低。与通过多晶硅静电放电二极管处理的传统功率金属氧化物半导体场效应管相比，它不需要另外的掩膜。可以在不增加成本的情况下，增加用于静电保护的栅源稳压二极管。本发明的另一方面在于，提出了一种在更小的晶片尺寸上，低成本地获得低漏电流Idss、低栅源箝位阻抗的方法。本发明的另一方面在于，获得了很好控制的栅漏箝位击穿电压，可用于低压器件应用。
本发明的一个较佳实施例提出了一个位于半导体衬底上的半导体功率器件，其中半导体衬底含有多个晶体管单元，每个晶体管都有一个源极和一个漏极，以及一个控制源极和漏极之间传输电流的栅极。此半导体还包括一个栅漏嵌位电路，串联在栅极和漏极之间，还包括与一个硅二极管串联的多个背对背多晶硅二极管，其中硅二极管包括在半导体衬底中的平行掺杂纵栏，平行掺杂纵栏带有一个预定义的间隙。在另一个典型实施例中，掺杂纵栏的间隙范围在2至5微米之间，以便获得63至75伏的击穿电压。在另一个典型实施例中，掺杂纵栏还包括一个将平行掺杂纵栏连接在一起的U形（如上所示）弯管。在另一个可选实施例中，与平行掺杂纵栏的导电类型相同的掺杂井，设置在纵栏末端下方及周围，在底部井中包住U形弯管，底部井确保掺杂纵栏末端的击穿电压不低于纵栏其余位置的击穿电压。在另一个典型实施例中，背对背多晶硅二极管的一端，通过浮动金属，串联到硅二极管上，另一端串联到栅极金属上；其中栅极金属通过栅极电阻Rg与栅极电极（栅极垫）相连，并直接接触栅极浇道沟道。在另一个典型实施例中，栅漏箝位终端仅设置在半导体衬底边缘附近的一侧，半导体功率器件位于半导体衬底上。在另一个典型实施例中，栅源箝位终端仅设置在半导体衬底边缘附近的一侧，用于设置一个栅极垫，通过多个延伸过去的栅极浇道连接栅极。在另一个典型实施例中，半导体衬底还包括一个设置在硅二极管下方的深掺杂井。在另一个典型实施例中，半导体衬底还包括接触开口，在硅二极管掺杂纵栏上方开口，用接触金属填充，用于连接到硅二极管上，在半导体衬底中形成掺杂纵栏。在另一个典型实施例中，其中用于连接硅二极管的接触金属为浮动金属，连接在背对背多晶硅二极管和硅二极管的掺杂纵栏之间。在另一个典型实施例中，半导体衬底还包括一个浮动井（可选用深井），设置在半导体衬底边缘周围的沟道终止附近。在另一个典型实施例中，背对背二极管在多晶硅层中含有多个交替掺杂区，设置在半导体衬底上方的绝缘层顶部。在另一个典型实施例中，此半导体功率器件还包括一个带有栅源背对背稳压二极管的栅源静电放电保护电路。在另一个典型实施例中，栅漏箝位终端和栅源静电放电保护电路无需另外的生产掩膜。形成栅漏箝位稳压二极管所使用的掩膜与栅源静电放电结构相同。
本发明还提出了一种箝位栅漏电压的方法，用于形成在含有多个晶体管单元的半导体衬底上的半导体功率器件，每个晶体管单元都有一个包围在本体区中的源极、和一个漏极、以及一个控制源极和漏极之间传输电流的栅极。本方法还包括通过形成多个串联到硅二极管上的背对背二极管，在栅极和漏极之间，形成互联栅漏嵌位电路，其中硅二极管在半导体衬底中含有掺杂区，并将背对背二极管连接到栅极上。在一个典型实施例中，本方法还包括在半导体衬底中，形成掺杂纵栏作为掺杂区，半导体衬底起硅二极管的作用，连接到背对背二极管上。在另一个典型实施例中，本方法还包括形成掺杂纵栏作为掺杂区，连接到纵栏的一个末端上，通过U形弯管掺杂区，起硅二极管的作用，连接到背对背二极管上。
附图说明
图1为传统器件一角的俯视原理图，以展示传统栅漏箝位的结构特点；
图2为本发明的一种改良栅漏嵌位电路的电路图；
图3A为带有改良栅漏箝位的金属氧化物半导体场效应管器件的俯视图，图3B-1和3B-2为图3A中器件的左下角的爆炸图，图3C和图3D为图3B-2分别沿A-A横截面和B-B横截面的横截面视图；
图4为本发明的一个可选实施例沿图3B-2 的A-A的横截面视图；
图4A为本发明的一个可选实施例的俯视图；
图4B为本发明的一个可选实施例沿图4A的C-C的横截面视图；
图5为带有改良栅漏箝位以及栅源静电放电保护电路的金属氧化物半导体场效应管器件的俯视图；
图6为带有改良栅漏箝位以及带有栅极金属可选装置的栅源静电放电保护电路的金属氧化物半导体场效应管器件的俯视图；
图7A-7I表示带有改良栅漏箝位的金属氧化物半导体场效应管器件的制作方法的一系列横截面视图。
具体实施方式
图2为本发明的金属氧化物半导体场效应管器件100的击穿保护电路的电路图。金属氧化物半导体场效应管器件带有栅极电极101、源极电极102以及漏极电极103。栅漏嵌位电路采用以带有寄生电阻Rz2 115的多晶硅二极管110表示的栅漏稳压二极管对、硅二极管120以及小栅极电阻Rg125的组合，对功率金属氧化物半导体场效应管起击穿保护的作用。稳压二极管对110由背对背稳压二极管组成。击穿保护电路除了含有栅漏嵌位电路之外，还含有一个栅源静电放电保护电路，栅源静电放电保护电路包括带有寄生电阻Rz1 115的栅源稳压二极管对130。图3A-D还说明，栅漏稳压二极管对110，仅形成在晶片的一侧。因此，晶片尺寸要比传统的设计小得多。栅漏箝位电路电连接到设置在衬底底部表面上的漏极电极103上，其中电连接方式已广为人知，在此不再详细说明。由于栅漏稳压二极管110的宽度减小了，因此漏电流Idss很低。在不产生多余费用的基础上，可以通过增加栅源稳压二极管对130，进行静电放电保护。相对于传统制作工艺，制作栅漏箝位的工艺中，为功率金属氧化物半导体场效应管提供静电放电保护，无需额外的掩膜工艺。
图3A为本发明带有改良栅漏箝位电路的半导体晶片的俯视图。图3B-1和3B-2为图3A的左下角的爆炸图，图3C和3D分别为图3B-2沿A-A和B-B的横截面视图。图3A、3B-1和3B-2中没有表示出氧化层和钝化层，以免产生混淆。图3B-2与图3B-1表示的是同一区域，所不同的是图3B-2中的金属层表示为透明的，以便清楚说明多晶硅二极管110和硅二极管120。图3B-1表示多晶硅二极管110和硅二极管120的外形轮廓。栅漏箝位电路仅形成在晶片的一侧，减少了在晶片上占据的面积，使更多的晶片区域可作为有源区使用。栅极电极101，例如栅极垫，通过栅极电阻Rg125连接到栅极金属111上。栅极金属111包围着源极金属102，并直接连接到栅极浇道沟道131上。栅极金属111和源极金属102由金属垫分割开。栅极金属111连接到栅漏多晶硅二极管110的一侧。多晶硅二极管110通过浮动金属118连接到硅二极管120的另一侧。浮动金属118将硅二极管120与多晶硅二极管110串联起来。如图3C所示，硅二极管为一个PN结，硅二极管植入物与本体区的导电类型相同，例如对于n-沟道场效应管，导电类型为P-型。在这种情况下，二极管的N侧为外延层145，外延层145位于衬底150上，起金属氧化物半导体场效应管器件的漏极作用。在另一侧，外延层145和衬底150有时统称为半导体衬底。沟道终止区160形成在半导体晶片的边缘处。
穿过氧化层中的接触开口121，作为衬底中的植入区形成硅二极管120。浮动井140提供隔离。浮动井140在硅二极管120周围形成一个环。用于形成硅二极管120的植入区以及浮动井140的导电类型与金属氧化物半导体场效应管的本体区导电类型相同。沟道终端160、浮动井140、硅二极管120和栅极浇道沟道131都形成在晶片的外延层145中。外延层145形成在衬底150上方。此附图并没有按照实际比例表示。外延层145和衬底150的导电类型与源极相同，并作为金属氧化物半导体场效应管的漏极。漏极电极103连接到衬底150的底部。硅二极管120含有两个平行掺杂纵栏，其间隔距离为预设的缝隙d。在一个较佳实施例中，平行掺杂纵栏还包括一个U形弯管122（图3B-1和3B-2），将纵栏的末端连接在一起。锐角和拐角都使电场升高，降低击穿电压。因此，区域末端的击穿电压比其余地方的低，导致漏电流、过早开启等不良后果。U形弯管122有助于减少这种后果，使击穿电压更加稳定、易于控制。在一个典型实施例中，如图3D所示，硅二极管120的平行掺杂纵栏末端还被尾井140-1包围。尾井140-1的导电类型与硅二极管120的平行条纹的导电类型相同，但掺杂浓度较低，将硅二极管120末端的击穿电压升高到所需击穿电压之上，来进一步增强对击穿电压的控制。这样一来，硅二极管的末端就不会出现漏电流、过早开启等上述问题。U形弯管122和尾井140-1能够很好地控制整体击穿电压。硅二极管的间隔可用于调节击穿电压。由于电场的变化，间隔越大，击穿电压越小，反之亦然。例如，2微米的间隔对应的整体击穿电压为75V，5微米的间隔对应的整体（稳压＋硅）击穿电压为63.7V。仅对于硅二极管的击穿电压而言，2微米的间隔对应的击穿电压为44.5V，4微米的间隔对应的击穿电压为35.6V。
图4表示本发明的一个可选实施例的横截面视图。与图3D类似，本图也是沿图3B-2的A-A横截面。在该实施例中，植入硅二极管120之前，先通过接触开口120-1和120-2进行浅硅刻蚀。刻蚀过程使多余的拐角和边缘深入到平行掺杂纵栏中，硅二极管120的电场增大，击穿电压降低。接触区（硅二极管的阳极区）深度很浅，经过植入和扩散后约为0.1-0.2微米。如上所述，二极管浅接触区的击穿电压较低。
图4A为本发明的一个可选实施例的俯视图，图4B为图4A沿C-C的横截面视图。大部分与图3B-2和3D类似，不同的是其中硅二极管120’仅有一个单一纵栏，而不是两个平行纵栏。硅二极管120’纵栏的末端带有一个尾井140-1，用于改善对于硅二极管120’的击穿电压的控制。无论二极管的设计结构如何，密封深井中的二极管末端都可以改善对击穿电压的控制，对本领域的技术人员而言，这种方法是显而易见的。例如，二极管可以含有一个、两个或多个纵栏。另外，纵栏的末端也可以不连接在U型弯管中，就封闭在尾井140-1中。浮动井140和尾井可以形成为深约2微米的深井。浮动井和尾井不一定必须是深井，其深度可以与普通本体区深度相同。作为示例，带有单一深井保护环的器件，其中保护环距离硅二极管120的间隔为4微米，其击穿电压为97V。
图5为本发明的一个可选实施例的俯视原理图。半导体晶片带有一个栅漏箝位电路，以及一个栅源静电放电保护电路130。静电放电保护电路130的技术已广为人知。对于本领域的技术人员，栅源保护电路130显然可以用栅漏箝位的制作工艺形成，因此无需增加成本。图6表示本发明的另一个可选实施例的俯视图。大部分与图5类似，不同的是栅极金属111’含有一个附加部分111-1’，这个附加部分111-1’使沟道栅漏电流流经栅极电阻Rg125。
图7A至7I为一系列横截面视图，表示制备改良栅漏箝位的方法。图7A开始在衬底750上设置一个外延层745。栅极沟道（图中没有表示出）和栅极浇道731都形成在外延层745中。然后在氧化层715上生长一个多晶硅层730，并形成如图7B所示的图案。多晶硅层730掺杂的导电类型与金属氧化物半导体场效应管的本体区中的导电类型相同。使用本体掩膜和本体植入物723，形成本体区722和浮动井区740，以及如图7C-D所示的尾井740-1。在图7D中，通过扩散植入物，形成浮动井区740、尾井740-1以及本体区722。如果浮动井740和尾井740-1为深井，那么就需要另外的掩膜和扩散来形成它们。也可以在形成多晶硅层730和氧化层715之前，形成本体区722、浮动井区740以及尾井740-1。
在图7E中，利用源极掩膜植入并形成源极区（图中没有表示出）、多晶硅层730中的条纹724以及沟道终端760。由于多晶硅层730带有交替P、N型条纹，因此形成栅漏箝位的背对背稳压二极管710。由氧化物等形成的绝缘层725沉积并形成图案，以形成如图7F所示的接触开口732。在图7G中，使用本体接触植入，通过接触开口721形成本体接触（图中没有表示出）以及硅二极管720，然后通过图7H所示的金属沉积和形成图案，形成顶部金属层：源极金属（图中没有表示出）、栅极金属721以及浮动金属718。在图7I中，沉积背部金属，形成栅极金属703。本领域的技术人员应明白，与带有背对背多晶硅二极管的标准栅源静电放电保护电路的制备工艺相比，改良的栅漏箝位并没有增加额外的工艺。因此，在不增加生产成本的基础上，可以在带有栅源静电放电保护电路的金属氧化物半导体场效应管器件上，形成栅漏箝位。
尽管上述内容已经详细说明了本发明现有的较佳实施例，但这些内容并不应作为局限。本领域的技术人员在阅读上述说明后，无疑将容易地做出各种改变和修正。例如，可以使用其他导电材料代替多晶硅。采用N-和P-沟道金属氧化物半导体场效应管以及轻掺杂漏金属氧化物半导体场效应管技术。因此，应通过所附的权利要求书来界定本发明真实意图，将其理解为包括范围内全部改变和修正。

Claims (7)

1.一个位于半导体衬底上的半导体功率器件由多个沟道金属氧化物半导体场效应管单元组成，其特征在于，半导体功率器件还包括：
一个串联在所述的栅极和所述的漏极之间的栅漏箝位终端，包括在一侧串联在一个硅二极管上的多个背对背多晶硅二极管，在所述的半导体衬底中，硅二极管含有至少一个掺杂纵栏，其中多个背对背多晶硅二极管在另一侧连接到一个栅极金属上，栅极金属与栅极浇道沟道直接接触；
所述的栅漏箝位终端仅设置在支撑着所述的半导体功率器件的所述半导体衬底一个边缘附近的一侧。
2.如权利要求1所述的半导体功率器件，其特征在于，还包括：
设置在下方的尾井包围了所述的至少一个掺杂纵栏的末端，其中尾井的导电类型与掺杂纵栏的导电类型相同，掺杂浓度低于掺杂纵栏的掺杂浓度。
3.一种箝位半导体功率器件的栅漏电压的方法，该半导体功率器件位于半导体衬底上，并含有多个晶体管单元，每个晶体管单元都有一个围绕在本体区中的源极和一个漏极，以及一个控制源极和漏极之间传输电流的栅极，其特征在于，此方法还包括：
通过形成多个背对背多晶硅二极管，在第一边串联到硅二极管上，在所述的半导体衬底中，硅二极管含有至少一个掺杂纵栏，并在第二边通过一个栅极电阻连接到栅极电极上，以便在所述的栅极和所述的漏极之间，相互连接栅漏箝位终端；所述的栅漏箝位终端仅设置在支撑着所述的半导体功率器件的所述半导体衬底一个边缘附近的一侧。
4.如权利要求3所述的箝位半导体功率器件的栅漏电压的方法，其特征在于，还包括以下步骤：
在所述的半导体衬底中，形成平行掺杂纵栏，起所述的硅二极管的作用，其中平行掺杂纵栏带有预设的缝隙，用于控制击穿电压。
5.如权利要求4所述的箝位半导体功率器件的栅漏电压的方法，其特征在于，形成所述的平行掺杂纵栏的所述的步骤还包括将掺杂纵栏的末端用一个U-型弯管连接在一起。
6.如权利要求3所述的箝位半导体功率器件的栅漏电压的方法，其特征在于，还包括以下步骤：
在所述的至少一个掺杂纵栏末端的下方，形成一个尾井，其中尾井的导电类型与掺杂纵栏的导电类型相同，掺杂浓度低于掺杂纵栏的掺杂浓度。
7.如权利要求3所述的箝位半导体功率器件的栅漏电压的方法，其特征在于，与带有背对背多晶硅二极管的标准栅源静电放电保护电路的半导体功率器件的制造工艺相比，所述的方法并没有增加额外的工艺。
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