CN109119465A - 用于嵌入式存储器应用的横向扩散mosfet - Google Patents

用于嵌入式存储器应用的横向扩散mosfet Download PDF

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CN109119465A
CN109119465A CN201810669738.5A CN201810669738A CN109119465A CN 109119465 A CN109119465 A CN 109119465A CN 201810669738 A CN201810669738 A CN 201810669738A CN 109119465 A CN109119465 A CN 109119465A
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CN109119465B (zh
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蒂埃里·姚
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Cypress Semiconductor Corp
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Abstract

本申请涉及用于嵌入式存储器应用的横向扩散MOSFET。例如，提供一种特别适用于密集间距环境如集成存储器应用中的线驱动器的横向扩散MOSFET LDMOS设备架构。在一个实施方案中，例示性高压MOSFET设备包括：主体(第一导电类型的半导体)；源极区(第二导电类型的半导体)，所述源极区位于源极有效区域处并且在主体内或邻近主体定位；漂移区(第二导电类型的轻掺杂半导体)，所述漂移区邻近主体定位；以及栅极，所述栅极覆盖主体的至少一部分和漂移区的至少一部分以在源极区与漂移区之间形成可控沟道。为了增大漏极击穿电压，漂移区的宽度尺寸形成为充分小以使耗尽区延伸穿过漂移区的整个宽度。

Description

用于嵌入式存储器应用的横向扩散MOSFET
技术领域
本公开一般来讲涉及集成电路电子器件，并且更具体地，涉及适用于驱动嵌入式存储器阵列的横向扩散MOSFET。
背景技术
金属氧化物半导体场效应晶体管(MOSFET)是通常用于打开和关闭电源的半导体器件。MOSFET包括源极区、漏极区以及在源极区与漏极区之间延伸的主体。主体由薄介电层与栅极电极隔离，使得施加到栅极电极的电压可控制是否在源极区与漏极区之间形成导电沟道。当施加栅极电压并形成导电沟道时，MOSFET使电流能够通过设备(漏极区与源极区之间)，并受到导通状态电阻的影响。当不存在导电沟道时，设备阻止电流流动，直到达到漏极击穿电压。
理想的是，使导通状态电阻尽可能小，并同时使漏极击穿电压尽可能高，但传统上，这些参数必须彼此有所取舍。通过使用所谓的横向扩散MOSFET(LDMOS)设备，这种取舍约束已被弱化(但未消除)。此类设备在漏极侧采用轻掺杂，为宽的耗尽层提供高阻断电压。但耗尽层也从设备横向地延伸，设备必须隔开更远以保持击穿电压。这种间隔要求限制了此类设备在诸如嵌入式存储器之类的狭窄环境中的实用性。
发明内容
根据本申请的一个方面，提供了一种高压MOSFET设备，其特征在于：主体，所述主体为第一导电类型的半导体；源极区，所述源极区位于源极有效区域处并且在所述主体内或邻近所述主体定位，所述源极区为第二导电类型的半导体；漂移区，所述漂移区为所述第二导电类型的轻掺杂半导体，所述漂移区邻近所述主体定位；以及栅极，所述栅极覆盖主体的至少一部分和漂移区的至少一部分以在源极区与漂移区之间形成可控沟道，其中漂移区的被栅极覆盖的部分与半导体材料交界，从而在可控沟道关闭时形成具有相反地偏置的PN结的耗尽区，并且其中漂移区的宽度尺寸充分小以使耗尽区延伸穿过漂移区的整个宽度。
在一个实施方案中，高压MOSFET设备的特征在于漂移区的宽度尺寸充分小以允许耗尽区的各部分相遇，以便充分地耗尽漂移区的自由载子。
在一个实施方案中，高压MOSFET设备的特征还在于：第二导电类型的漏极区，所述漏极区定位在漂移区内并且充分地掺杂以提供与漏极触点的欧姆连接。
在一个实施方案中，高压MOSFET设备的特征在于漏极触点的宽度尺寸大于漏极区的宽度尺寸。
在一个实施方案中，高压MOSFET设备的特征在于漏极区的宽度尺寸小于漂移区的宽度尺寸，并且其中漏极触点的宽度尺寸大于漂移区的宽度尺寸。
在一个实施方案中，高压MOSFET设备的特征在于栅极具有覆盖源极有效区域的栅极触点。
在一个实施方案中，高压MOSFET设备的特征在于：第二导电类型的漏极区，所述漏极区定位在漂移区内并且充分地掺杂以提供与漏极触点的欧姆连接；以及栅极氧化物，所述栅极氧化物将栅极与主体和漂移区隔开；隔离体，所述隔离体在所述栅极与所述漏极区之间提供绝缘间隙，其中所述隔离体在具有氧化物填充物的所述漂移区中包括沟槽；以及横向扩散体，所述横向扩散体在源极区与可控沟道之间形成桥，其中源极区充分地掺杂以提供与源极触点的欧姆连接。
根据本申请的另一方面，提供了一种具有高压驱动器的存储器设备，所述存储器设备的特征在于：存储器阵列，所述存储器阵列具有单元间距；高压驱动器的并排阵列，以不超过单元间距两倍的方式沿存储器阵列的一侧布置。高压驱动器中的每一个在第一导电类型的半导体堆积体中包括：第一导电类型的中度掺杂区域，所述中度掺杂区域用于充当主体；源极有效区域处的源极区，所述源极区为第二导电类型的半导体并且在所述主体内或邻近所述主体定位；漂移区，所述漂移区为所述第二导电类型的轻掺杂半导体，所述漂移区邻近所述主体定位；以及栅极，所述栅极覆盖主体的至少一部分和漂移区的至少一部分以在源极区与漂移区之间形成可控沟道。相邻高压驱动器的源极有效区域之间的横向间隔小于相邻高压驱动器的漂移区之间的横向间隔。
在一个实施方案中，存储器设备的特征在于在高压驱动器的每一个中：漂移区的被栅极覆盖的部分与半导体材料交界，从而在可控沟道关闭时形成具有相反地偏置的PN结的耗尽区；并且漂移区的宽度尺寸充分小以使耗尽区延伸穿过漂移区的整个宽度。
在一个实施方案中，存储器设备的特征在于高压驱动器中的每一个还包括：第二导电类型的漏极区，所述漏极区定位在漂移区内并且充分地掺杂以提供与漏极触点的欧姆连接，漏极触点的宽度尺寸大于漂移区的宽度尺寸。
附图说明
在附图中：
图1示出了高压MOSFET设备的布局的平面图；
图2示出了根据至少一个实施方案的高压MOSFET设备的布局的平面图；
图3A、3B和3C是例示性高压MOSFET设备的剖视图；
图4示出了根据至少一个实施方案的高压MOSFET设备400的布局的平面图；
图5是根据至少一个实施方案的高压MOSFET设备500的布局的平面图；并且
图6是根据至少一个实施方案的高压MOSFET设备的阵列的布局的平面图。
应当理解，附图和对应的详细描述并不限制本公开，而是相反，为理解落在所附权利要求书范围内的所有修改形式、等同形式和替代形式提供基础。
术语
在以下描述中，术语“本征”、“轻度掺杂”、“中度掺杂”和“重度掺杂”以及“退化”用于指示相对的掺杂程度。这些术语不旨在指示确定的数值范围，而是旨在(在计算尺上)指示大概的范围，所述范围的上限值和下限值可被允许在任一方向上以4的因数变化。在硅的上下文中，术语“本征”指示1014原子/cm3或更少的掺杂物浓度。“轻度掺杂”指示介于1014原子/cm3与1016原子/cm3之间的范围内的浓度。“中度掺杂”指示介于1016原子/cm3与1018原子/cm3之间的闭区间范围内的浓度。“重度掺杂”指示介于1018原子/cm3与1020原子/cm3之间的范围内的浓度。“退化”指示足以提供与金属触点的欧姆(非整流)连接的掺杂水平(通常大于1020原子/cm3)。需注意的是，对于除硅之外的半导体，这些范围可能不同。
具体实施方式
图1示出了高压MOSFET设备100的布局的平面图。高压MOSFET设备100包括有效区域102、有效区域104和栅极112。有效区域102(或源极有效区域)对应于源极区。例如，源极区在有效区域102处。源极区提供与源极触点106的欧姆连接并且在设备处于导电状态时用作沟道的电荷载子源。有效区域104(或漏极有效区域)对应于漏极区。例如，漏极区在有效区域104处。漏极区从沟道接收电荷载子并提供与漏极触点108的欧姆连接。有效区域104由轻掺杂漂移区110围绕。
在有效区域102和104处，较薄氧化物定位在表面处(例如，硅表面处)。这种较薄氧化物也被称为栅极氧化物。在有效区域102和104之外(例如，在场区域处)，较厚氧化物(也称为场氧化物)定位在表面处。有效区域102和104处的较薄氧化物使得来自导体(例如，栅极112)的电场能够吸引衬底中的电荷载子(例如，以形成沟道或更高浓度的电荷载子)。相比之下，场氧化物充分厚以防止电场(例如，来自覆盖的导体)影响衬底的电荷载子。
主体150延伸到有效区域102与104之间栅极112的下方。当形成时，沟道位于主体150的表面上。沟道对应于栅极112与有效区域102之间的重叠，漂移区110除外。当不受栅极112影响时，主体150为第一导电类型的半导体。源极区和漏极区为第二类型的半导体。漂移区110为也是第二类型的轻掺杂半导体。例如，如果主体150为p型半导体，那么源极区和漏极区为n型半导体，并且漂移区110为轻掺杂的n型半导体。又如，如果主体150为n型半导体，那么源极区和漏极区为p型半导体，并且漂移区110为轻掺杂的p型半导体。
栅极112覆盖主体150和漂移区110的至少一部分。栅极112包括与栅极触点114的欧姆连接。栅极112用于在主体150中形成可控沟道。如先前所述，可控沟道对应于栅极112与有效区域102之间的重叠，漂移区110除外。更详细地讲，假定源极触点106接地，向栅极112施加(例如，经由栅极触点114)的正电压形成支持漏极到源极电流流动的导电沟道。在LDMOS中，在有效区域102和104的表面上发生漏极到源极电流流动。当栅极电压低于阈值电压时，导电沟道消失。在这种情况下，漏极到源极电压差形成。主体150与漂移区110之间的p-n界面变成相反地偏置，从而形成宽的耗尽区，使得设备100能够在不击穿的情况下耐受大的漏极到源极电压。
如图1所示，漂移区110的宽度尺寸(w1)大于有效区域102的宽度尺寸(w2)以在横向方向上适应宽的耗尽区域。这样，漂移区110扩展超出有效区域102的宽度并且扩展设备的有效宽度，从而对其他此类设备施加不期望的间隔要求。此外，可以承受的漏极到源极电压可能只有12V到15V。虽然这个范围内的电压对于诸如逻辑EEPROM的应用而言可能是充分的，但这些电压对于诸如更高密度的EEPROM的其他应用而言可能是不充分的。当例如使用LDMOS设备来为存储器设备(例如，EEPROM设备)的单元供电时，多个LDMOS设备沿存储器阵列的一侧布置。在这个配置中，漂移区(例如，参见漂移区110)的宽度显著影响LDMOS设备自身的间距。例如，相邻LDMOS设备的间距可以大于具有高密度位单元的EEPROM的间距。因此，诸如设备100的LDMOS设备可能与具有相对较小间距的存储器设备(例如，嵌入式高密度存储器，诸如EEPROM或闪存存储器)不兼容。
根据下文提出的至少一个实施方案，漂移区的宽度被配置成相对较窄。例如，在至少一些实施方案中，漂移区的宽度小于对应于源极的有效区域的宽度。可以实现对于特定应用(例如，更高密度的EEPROM)而言充分的击穿电压。此外，漂移区的宽度的减小导致LDMOS设备自身的尺寸减小。当此类LDMOS设备用于为存储器设备的单元供电时，LDMOS设备的间距可能更接近由LDMOS设备驱动的位单元的间距。尺寸的这种减小可能有助于降低将存储器嵌入CMOS平台的成本。
图2示出了根据至少一个实施方案的高压MOSFET设备200的布局的平面图。高压MOSFET设备200包括有效区域202、有效区域204和栅极212。有效区域202(或源极有效区域)对应于源极区(例如，参见图3A的源极区302)。例如，源极区在有效区域202处。源极区提供与源极触点206的欧姆连接。有效区域204(或漏极有效区域)对应于漏极区(例如，参见图3A的漏极区314)。例如，漏极区在有效区域204处。漏极区提供与漏极触点208的欧姆连接。有效区域204在周围的漂移区210中。
在有效区域202和204处，较薄氧化物定位在表面处(例如，硅表面处)。这种较薄氧化物也被称为栅极氧化物。在有效区域202和204之外(例如，在场区域处)，较厚氧化物(也称为场氧化物)定位在表面处。有效区域202和204处的较薄氧化物使得来自导体(例如，栅极212)的电场能够吸引衬底中的电荷载子(例如，以形成沟道或更高浓度的电荷载子)。相比之下，场氧化物充分厚以防止电场(例如，来自覆盖的导体)影响衬底的电荷载子。
主体250延伸到有效区域202与204之间栅极212的下方。当形成时，沟道位于主体250的表面上。沟道对应于栅极212与有效区域202之间的重叠，漂移区210除外。当不受栅极212影响时，主体250为第一导电类型的半导体。源极区和漏极区为第二类型的半导体。漂移区210为也是第二类型的轻掺杂半导体。例如，如果主体250为p型半导体，那么源极区和漏极区为n型半导体，并且漂移区210为轻掺杂的n型半导体。又如，如果主体250为n型半导体，那么源极区和漏极区为p型半导体，并且漂移区210为轻掺杂的p型半导体。
栅极212覆盖主体250和漂移区210的至少一部分。栅极212包括与栅极触点214的欧姆连接。栅极212用于在主体250中形成可控沟道。如先前所述，可控沟道对应于栅极212与有效区域202之间的重叠，漂移区210除外。更详细地讲，假定源极触点206接地，向栅极212施加(例如，经由栅极触点214)的正电压形成支持有效区域202和204之间的漏极到源极电流流动的n型导电沟道。当栅极电压低于阈值电压时，导电沟道消失。在这种情况下，漏极到源极电压差形成。主体250与漂移区210之间的p-n界面变成相反地偏置，从而形成耗尽区，使设备200能够在不击穿的情况下耐受大的漏极到源极电压。
在图1的高压MOSFET设备100中，w1(漂移区110的宽度尺寸)大于w2(有效区域102的宽度尺寸)。根据至少一个实施方案，漂移区210形成得更窄。较窄的漂移区210使耗尽层能够在p-n界面相反地偏置时充分延伸穿过漂移区的整个宽度，从而从该区移除载子并提供横向RESURF(减小的表面场)效应，由此提高设备200的击穿电压(例如，提高到约25V的电压)。例如，在至少一个具体实施方案中，漂移区210的宽度减小到制造工艺(例如，光刻)所允许的宽度。
图2示出了较窄漂移区210的示例。在图2的示例中，漂移区210形成得更窄，使得漂移区210的宽度尺寸(w3)小于有效区域202的宽度尺寸(w4)。
将参考图3A、3B和/或3C的剖视图更详细地描述漂移区210和其他特征的相对较窄宽度。
图2的线A-A’指出图3A所示剖视图的区。参考图3A，源极区302邻近源极触点206。在至少一个实施方案中，源极区302充分地掺杂以提供与源极触点206的欧姆连接。源极区302定位在由主体250形成的阱内。源极区302邻近栅极212定位。
横向扩散体312位于源极区302与主体250之间。当在主体250中形成导电沟道时，横向扩散体312在源极区302与可控沟道之间形成导电桥。
如先前参考图2所述，栅极212覆盖主体250和漂移区210的至少一部分。栅极212提供与栅极触点214的欧姆连接。在至少一个实施方案中，栅极触点214覆盖有效区域202以进一步减小设备宽度。
栅极氧化物304将栅极212与主体250和漂移区210隔开。当可控沟道关闭时，主体250与漂移区210之间的界面形成具有相反地偏置的PN结的耗尽区。隔离体306位于栅极氧化物304与主体250之间。隔离体306在栅极212与主体250之间提供绝缘间隙。如图3A所示，隔离体306在具有氧化物填充物的漂移区210中包括沟槽。绝缘端盖308和310设置在栅极212的相对端处。
漂移区210和漏极区314定位在由主体250形成的阱内。例如，漏极区314定位在漂移区210内。漏极区314为与源极区302相同的导电类型并且充分地掺杂以提供与漏极触点208的欧姆连接。因此，设备200的漏极具有轻掺杂漂移区，该轻掺杂漂移区将导电沟道电连接到漏极触点208。
在至少一个实施方案中，漂移区210的宽度尺寸充分小以使耗尽区延伸穿过漂移区的整个宽度。这样，漂移区210的宽度被配置成使得漂移扩散可充分耗尽，以便提供较高的击穿电压。例如，当漂移区210充分窄时，那么PN结竖直地延展。当PN结在中间相遇时，那么耗尽可以更充分地发生。
继续参考图3A，所示设备200的漏极缺少源/漏(SD)扩散，这通常被提供来在漏极触点208与漏极扩散之间形成电阻连接。标准SD扩散可以提供对于期望的高击穿电压而言太高的分布式载子浓度。相反，在至少一个实施方案中，作为用于形成LDD桥312的更浅、更轻的横向掺杂剂扩散(LDD)步骤的一部分，形成漏极连接区域314。
将继续参照图3B描述漂移区210的较窄宽度。图2的线B-B’指出图3B所示剖视图的区域。
参考图3B，绝缘端盖320和322设置在栅极212的相对端处。在场氧化物306-1与场氧化物306-2之间的区域中，漂移区210的宽度(w5)小于有效区域202的宽度(w6)。由于漂移区210的狭窄度，从漂移区210的两侧(例如，参见侧210a，210b)延伸出的耗尽区可以在中间相遇以完全耗尽漂移区中的自由载子。为了实现这种期望的效果，漂移区210的宽度至少部分基于漂移区中的掺杂程度。
图2的线C-C’指出图3C所示剖视图的区域。如图3C所示，在至少一个实施方案中，漏极区314的宽度尺寸小于漂移区210的宽度尺寸。另外，在至少一个实施方案中，漏极触点208的宽度尺寸小于漏极区314的宽度尺寸。该配置可能会产生不希望的高漏极接触阻抗。
在至少另一个实施方案中，漏极触点208的宽度尺寸大于有效区域204的宽度尺寸，并且可以甚至大于漂移区210的宽度。图4示出了根据这个实施方案的示例的高压MOSFET设备400的布局的平面图。
在图4的示例中，漏极触点408的宽度尺寸大于有效区域204的宽度尺寸。此外，漏极触点408的宽度大于漂移区210的宽度。以这种方式配置的漏极触点便于更好地控制漏极电阻。而且，较宽(或细长)漏极触点408的使用可以有助于减少由漏极触点408与有效区域204的未对准引起的电位变化。
图5是根据至少一个实施方案的高压MOSFET设备500的布局的平面图。MOSFET设备500与先前参考图2所述的MOSFET设备200类似。MOSFET设备500，200之间的一个区别在于栅极触点(例如，栅极触点214)的定位。在MOSFET设备200中，栅极触点214被定位成覆盖有效区域202，漂移区210除外。这样，栅极触点214被置于可控沟道上。这有助于减小设备200的尺寸，因为栅极触点214相对于有效区域202的横向位移可能会增加宽度开销。然而，在某些情况下(例如，当MOSFET设备的尺寸减小不需要那么大时)，栅极触点可定位成使得它不覆盖有效区域202。例如，栅极触点214可远离有效区域202横向地定位，如图5所示。
图6是根据至少一个实施方案的高压MOSFET设备600-1，600-2的阵列的布局的平面图。设备600-1，600-2可以各自与图2的MOSFET设备200类似。另选地，设备600-1，600-2可以各自与图4的MOSFET设备400(或图5的MOSFET设备500)类似。在图6的示例中，为了简单起见，示出了两个高压驱动器。然而，应当理解，高电压的数量可以大于2。
在至少一个实施方案中，MOSFET设备600-1，600-2的阵列沿存储器阵列(例如，EEPROM存储器阵列)的一侧布置。在这种情况下，MOSFET设备600-1，600-2可以不超过存储器阵列中的存储器单元的间距两倍的方式布置。相应的MOSFET设备600-1,600-2的漂移区610-1，610-2以横向间隔s1隔开。类似地，相应的MOSFET设备600-1,600-2的有效区域602-1，602-2以横向间隔s2隔开。漂移区的宽度的减小(例如，如先前参考各种实施方案所述)有助于减小这些设备阵列中的MOSFET设备600-1，600-2的间距。此外，随着漂移区宽度的减小，横向间隔s2变得小于横向间隔s1。这样，MOSFET设备600-1，600-2可以被定位成彼此更靠近，同时仍然保持横向间隔s1大于特定值(或阈值)。因此，MOSFET设备600-1，600-2的间距可以更密切地近似于存储器阵列中的存储器单元(例如，高密度阵列中的EEPROM单元)的间距。
除了别的之外，前述公开内容还提供了一种特别适用于密集间距环境如集成存储器应用中的线驱动器的横向扩散MOSFET(LDMOS)设备架构。在一个实施方案中，例示性高压MOSFET设备包括：主体(第一导电类型的半导体)；源极区(第二导电类型的半导体)，所述源极区位于源极有效区域处并且在主体内或邻近主体定位；漂移区(第二导电类型的轻掺杂半导体)，所述漂移区邻近主体定位；以及栅极，所述栅极覆盖主体的至少一部分和漂移区的至少一部分以在源极区与漂移区之间形成可控沟道。漂移区的被栅极覆盖的部分与半导体材料交界，从而在可控沟道关闭时形成具有相反地偏置的PN结的耗尽区。为了增大漏极击穿电压，漂移区的宽度尺寸形成为充分小以使耗尽区延伸穿过漂移区的整个宽度。
在一个实施方案中，一种例示性存储器设备包括：存储器阵列，所述存储器阵列具有单元间距；以及高压驱动器的并排阵列，其以不超过单元间距两倍的方式沿存储器阵列的一侧布置。高压驱动器中的每一个在第一导电类型的半导体堆积体中包括：第一导电类型的中度掺杂区域，其用于充当主体；源极有效区域处的源极区，所述源极区为第二导电类型的半导体并且在所述主体内或邻近所述主体定位；漂移区，所述漂移区为所述第二导电类型的轻掺杂半导体，所述漂移区邻近所述主体定位；以及栅极，所述栅极覆盖主体的至少一部分和漂移区的至少一部分以在源极区与漂移区之间形成可控沟道。相邻高压驱动器的源极有效区域之间的横向间隔小于相邻高压驱动器的漂移区之间的横向间隔。
前述实施方案中的每一个可以结合下列一个或多个特征以任何合适的组合来使用：1.漂移区的宽度尺寸充分小以允许耗尽区的各部分相遇，以便充分地耗尽漂移区的自由载子。2.漂移区的宽度尺寸小于源极有效区域的宽度尺寸。3.第二导电类型的漏极区定位在漂移区内并且充分地掺杂以提供与漏极触点的欧姆连接。4.漏极触点的宽度尺寸大于漏极区的宽度尺寸。5.漏极区的宽度尺寸小于漂移区的宽度尺寸，并且漏极触点的宽度尺寸大于漂移区的宽度尺寸。6.栅极具有覆盖源极有效区域的栅极触点。7.源极区也充分地掺杂以提供与源极触点的欧姆连接。8.栅极氧化物，该栅极氧化物将栅极与主体和漂移区隔开。9.隔离体，该隔离体在栅极与漏极区之间提供绝缘间隙。10.隔离体在具有氧化物填充物的漂移区中包括沟槽。11.横向扩散体，该横向扩散体在源极区与可控沟道之间形成桥。12.第一导电类型是p型并且第二导电类型是n型。13.第一导电类型是n型并且第二导电类型是p型。
上述描述还假设使用硅作为半导体材料，但本领域技术人员将认识到，上述方法也可与其他半导体材料诸如碳、锗和砷化镓一起使用。
一旦完全理解了上述公开的内容，对于本领域技术人员来说这些和许多其他修改形式、等价形式和替代形式就将变得显而易见。旨在使以下权利要求书被解释为在适用情况下包含所有此类修改形式、等价形式和替代形式。

Claims (10)

1.一种高压MOSFET设备，其特征在于具有：
主体，所述主体为第一导电类型的半导体；
源极区，所述源极区位于源极有源区域处并且在所述主体内或邻近所述主体定位，所述源极区为第二导电类型的半导体；
漂移区，所述漂移区为所述第二导电类型的轻掺杂半导体，所述漂移区邻近所述主体定位；以及
栅极，所述栅极覆盖所述主体的至少一部分和所述漂移区的至少一部分以在所述源极区与所述漂移区之间形成可控沟道，
其中所述漂移区中被所述栅极覆盖的部分与半导体材料交界，从而在所述可控沟道关闭时形成具有相反地偏置的PN结的耗尽区，并且其中所述漂移区的宽度尺寸充分小以使所述耗尽区延伸穿过所述漂移区的整个宽度。
2.根据权利要求1所述的高压MOSFET设备，其特征在于所述漂移区的所述宽度尺寸充分小以允许所述耗尽区的各部分相遇，以便充分地耗尽所述漂移区的自由载子。
3.根据权利要求1所述的高压MOSFET设备，其特征还在于：
所述第二导电类型的漏极区，所述漏极区定位在所述漂移区内并且充分地掺杂以提供与漏极触点的欧姆连接。
4.根据权利要求3所述的高压MOSFET设备，其特征在于所述漏极触点的宽度尺寸大于所述漏极区的宽度尺寸。
5.根据权利要求4所述的高压MOSFET设备，其特征在于所述漏极区的所述宽度尺寸小于所述漂移区的所述宽度尺寸，并且其中所述漏极触点的所述宽度尺寸大于所述漂移区的所述宽度尺寸。
6.根据权利要求1所述的高压MOSFET设备，其特征在于所述栅极具有覆盖所述源极有源区域的栅极触点。
7.根据权利要求1所述的高压MOSFET设备，其特征在于：
所述第二导电类型的漏极区，所述漏极区定位在所述漂移区内并且充分地掺杂以提供与漏极触点的欧姆连接；以及
栅极氧化物，所述栅极氧化物将所述栅极与所述主体和所述漂移区隔开；
隔离体，所述隔离体在所述栅极与所述漏极区之间提供绝缘间隙，其中所述隔离体在具有氧化物填充物的所述漂移区中包括沟槽；以及
横向扩散体，所述横向扩散体在所述源极区与所述可控沟道之间形成桥，
其中所述源极区充分地掺杂以提供与源极触点的欧姆连接。
8.一种具有高压驱动器的存储器设备，所述存储器设备的特征在于：
存储器阵列，所述存储器阵列具有单元间距；
高压驱动器的并排阵列，以不超过所述单元间距两倍的方式沿所述存储器阵列的一侧布置，所述高压驱动器中的每一个在第一导电类型的半导体堆积体中包括：
所述第一导电类型的中度掺杂区域，所述中度掺杂区域用于充当主体；
源极有源区域处的源极区，所述源极区为第二导电类型的半导体并且在所述主体内或邻近所述主体定位；
漂移区，所述漂移区为所述第二导电类型的轻掺杂半导体，所述漂移区邻近所述主体定位；以及
栅极，所述栅极覆盖所述主体的至少一部分和所述漂移区的至少一部分以在所述源极区与所述漂移区之间形成可控沟道，
其中相邻高压驱动器的源极有源区域之间的横向间隔小于所述相邻高压驱动器的漂移区之间的横向间隔。
9.根据权利要求8所述的存储器设备，其特征在于在所述高压驱动器的每一个中：
所述漂移区中被所述栅极覆盖的部分与半导体材料交界，从而在所述可控沟道关闭时形成具有相反地偏置的PN结的耗尽区；并且
所述漂移区的宽度尺寸充分小以使所述耗尽区延伸穿过所述漂移区的整个宽度。
10.根据权利要求8所述的存储器设备，其特征在于在所述高压驱动器中的每一个还包括：
所述第二导电类型的漏极区，所述漏极区定位在所述漂移区内并且充分地掺杂以提供与漏极触点的欧姆连接，所述漏极触点的宽度尺寸大于所述漂移区的宽度尺寸。
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