CN103681864A - 半导体器件和用于制作半导体器件的方法 - Google Patents
半导体器件和用于制作半导体器件的方法 Download PDFInfo
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Abstract
一种半导体器件包括晶体管,其包括源极区域,漏极区域,和栅极电极。栅极电极被设置在布置于半导体衬底的顶部表面中的第一沟槽中。该器件进一步包括控制电极。该控制电极被设置在布置于半导体衬底的顶部表面中的第二沟槽中。该第二沟槽具有与第一沟槽的第一形状不同的第二形状。
Description
技术领域
本公开涉及半导体器件并且涉及用于制作这种半导体器件的方法。
背景技术
功率MOSFET(金属氧化物半导体场效应晶体管)是高击穿电压半导体器件的实例,其被用于开关功率源,逆变器器件等。例如,功率MOSFET被认为以低欧姆负载切换高电压,以便具有非常小的切换和传导损耗。当被关断时具有小的导通电阻(Ron)和高的击穿电压的功率MOSFET是所希望的。例如,当被关断时,功率MOSFET应该承受得住数十至数百伏的漏极到源极电压Vds。作为另外的实例,功率MOSFET传导非常大的电流,在低电压降Vds下在大约10到20V的栅极-源极电压下,所述电流可以高达数百安培。
正在寻找具有改进的晶体管特性的半导体器件。特别地,希望提供具有增加的电流效率(Ron×A),较陡的亚阈值斜率,较好的沟道控制和较低的泄漏电流的半导体器件。此外,希望提供用于制作这种半导体器件的简单工艺。
发明内容
根据实施例,一种半导体器件包括晶体管,其包含源极区域,漏极区域,栅极电极,该栅极电极被设置在布置于半导体衬底的顶部表面中的第一沟槽中,和控制电极,该控制电极被设置在布置于半导体衬底的顶部表面中的第二沟槽中,该第二沟槽具有与第一沟槽的第一形状不同的第二形状。
根据实施例,一种半导体器件,其包括多个晶体管单元,晶体管单元中的每个包括源极区域,漏极区域,和被设置在布置于半导体衬底的顶部表面中的沟槽中的栅极电极,不同晶体管单元的栅极电极被互相电耦合,不同晶体管单元的源极区域被互相电耦合,并且不同晶体管单元的漏极区域被互相电耦合,其中对于在沟槽之间的横向距离d,满足下面的公式:
d ≤ 2 * Wm,
其中Wm表示形成在与栅极电极相邻的半导体衬底中的表面耗尽区域的最大宽度。
根据实施例,一种制作半导体器件的方法包括通过下述来形成晶体管:形成源极区域,漏极区域,栅极电极,通过在半导体衬底的顶部表面中形成第一沟槽来形成该栅极电极,并且形成控制电极,形成该控制电极包括在半导体衬底的顶部表面中形成第二沟槽。
在阅读下面的详细描述时,并且在浏览附图时,本领域技术人员将认识到另外的特征和优点。
附图说明
附图被包括以提供对本发明实施例更多的理解并且被并入和构成本说明书的一部分。附图示出本发明的实施例并且与描述一起用来解释原理。本发明其它的实施例和预期优点中的许多将被容易地认识到,因为通过参照下面详细的描述,它们变得更好理解。附图中的元件不必要相对于彼此成比例。相似的参考数字指代相应的相似部件。
图1A示出根据实施例的半导体器件的截面图;
图1B是根据实施例的半导体器件的不同截面图;
图1C示出根据实施例的半导体器件的平面图;
图2示出根据另一实施例的半导体器件的截面图;
图3A和3B分别示出根据另一实施例的半导体器件的截面图;
图4A至4F示出当制作根据实施例的半导体器件时根据不同的加工阶段的半导体器件的截面图;和
图5A和5B示意地示出制作半导体器件的方法。
具体实施方式
在下面的详细描述中,参考附图,这些附图构成了该详细描述的一部分,在这些图中借助图示示出了可以实施本发明的特定实施例。在这方面,方向性的术语,例如:“顶部”、“底部”、“前”、“后”、“前面”、“后面”等等,是参考所描述的图的方向来使用的。由于本发明的实施例的部件可被定位在许多不同的方向上,因此方向性的术语仅用于说明的目的,并且决不是限制性的。应当理解可以利用其它实施例,并且可以在不脱离由权利要求限定的范围的情况下做出结构或逻辑改变。
实施例的描述不是限制性的。具体地,下文描述的实施例中的元件可以与不同实施例中的元件相结合。
在下面描述中使用的术语“晶片”,“衬底”,或者“半导体衬底”可以包括具有半导体表面的任何基于半导体的结构。晶片和结构应被理解为包括硅,绝缘体上硅(SOI),蓝宝石上硅(SOS),掺杂和未掺杂的半导体,由基本半导体基础支撑的硅外延层,和其它半导体结构。半导体不需要是基于硅的。半导体也可以是硅-锗,锗,或者砷化镓。
附图和描述通过在掺杂类型“n”或者“p”旁边标明“-”或“+”来说明相对掺杂浓度。例如“n-”表示比“n”掺杂区域的掺杂浓度更低的掺杂浓度,而“n+”掺杂区域具有比“n”掺杂区域更高的掺杂浓度。相同的相对掺杂浓度的掺杂区域不必要具有相同的绝对掺杂浓度。例如,两个不同的“n”掺杂区域可以具有相同或者不同的绝对掺杂浓度。在附图和描述中,为了更好地理解,掺杂部分经常被指定为是“p”或者“n”掺杂的。如被清楚地理解的,该指定绝不旨在是限制性的。只要实现了被描述的功能性,掺杂类型可以是任意的。此外,在所有实施例中,掺杂类型可以被反过来。
如在本说明书中使用的,术语“耦合的”和/或“电耦合的”不意在表示该元件必须被直接耦合在一起—在“耦合的”或者“电耦合的”元件之间可以提供插入元件。术语“电连接的”旨在描述在被电连接在一起的元件之间的低欧姆电连接。
如本文使用的,术语“具有”,“容纳”,“包括”,“包含”等是开放式的术语,其表明声称的元件或者特征的存在,但不排除另外的元件或者特征。冠词“一”,“一个”和“该”旨在包括复数以及单数,除非上下文清楚地另外表明。
如在本说明书中使用的术语“横向的”和“水平的”旨在描述与半导体衬底或者半导体本体的第一表面平行的方向。这可以是例如晶片或者管芯的表面。
如在本说明书中使用的术语“垂直的”旨在描述被布置为垂直于半导体衬底或者半导体本体的第一表面的方向。
图1A示出半导体器件90的实例的截面图。半导体器件90包括晶体管,其包括源极区域20,漏极区域40和栅极电极60。该栅极电极60被设置在布置于半导体衬底1的顶部表面10中的第一沟槽65中,该栅极电极60通过栅极介电材料61与相邻的本体区域30绝缘。半导体器件90进一步包括控制电极70,该控制电极70被设置在布置于半导体衬底1的表面10中的第二沟槽150中。漏极区域40被设置在半导体衬底1的背面120上。源极区域20被设置为相邻于半导体衬底1的顶部表面10。
第一沟槽65具有第一形状,并且第二沟槽150具有第二形状,该第二形状与第一形状不同。例如,第一沟槽65的深度t1可以比第二沟槽150的深度t2更大,该第一和第二深度相对于半导体衬底1的顶部表面10被垂直地测量。可替代地或者另外地,第一沟槽65的宽度w1可以与第二沟槽150的宽度w2不同。在第一沟槽65的第一形状和第二沟槽150的第二形状之间的差别不归因于可能由沟槽制作引起的偏移,其与非故意的偏移相关。更确切地,该差别是由针对第一和第二沟槽65,150所使用的不同的制作条件引起的。
另一控制电极70可以与栅极电极60连接或者可以被保持在不同的电势处。例如,另一控制电极70可以被接地。另一控制电极70利用绝缘层71与相邻的半导体材料绝缘。
当例如通过施加正的栅极电压被接通时,在本体区域30和栅极介电材料61之间的边界处形成反型层。因此,在该边界处形成导电沟道31。因此,晶体管通过漂移区95处于从源极区域20到漏极区域40的导电状态中。在关断的情况下,没有反型层被形成并且晶体管不处在导电状态中。此外,当晶体管处在导电状态中时,在与反型层相邻的本体区域30中形成耗尽层。例如,本体区域30的宽度可以被选择,使得当施加相应于晶体管的阈值电压的栅极电压时,在栅极电极60的边界附近形成的耗尽层和在控制电极70的边界附近形成的耗尽层互相接触。
因此,当施加相应于阈值电压的栅极电压时,本体区域30可以被完全耗尽。此外,由于两个相邻的导电沟道,可以提供较高电流效率。例如,沟道可以互相作用并且因而可导致所谓的“体反型(bulk inversion)”,其将进一步提高性能。因此,实现了增大的RonхA的乘积。已经证明了例如当半导体器件90在30V,40V或者50V的电压下操作时,该效果对较低电压等级来说是显著的。此外,对沟道31的静电控制被进一步改善。因此,可以避免不期望有的短沟道效应。因此,沟道31可以被制作得更短,由此Ron可以被进一步降低并且栅极电容可以被降低。此外,已经表明电流-电压特性的亚阈值斜率可以被改进并且可被大致与栅极氧化层61的厚度无关地形成。
在较高温度(>150℃)处,半导体器件90具有较低泄漏电流。为了实现相同的阈值电压,在本体区域30内的掺杂浓度应该比在传统器件中更高。因此寄生双极晶体管的电流增益较低,导致器件90抵抗寄生双极作用的较高鲁棒性。而且,阈值温度可以被规定为是较高的。
根据实施例,场板80可以被设置在栅极沟槽65内。场板80可以被设置在栅极电极60的下面并且可以与栅极电极60绝缘。此外,场板80可以通过绝缘层81与漂移区95绝缘。在图1A中示出的布置中,场板80中的每个被设置在栅极沟槽65内的栅极电极60中的每个的下面,而没有场板80被设置在另一控制电极70的下面。
根据实施例,相邻场板80之间的间距比在栅极电极60和相邻的控制电极70之间的距离更大。总体上,绝缘层81的厚度比栅极介电材料61的厚度更大。根据实施例,场板80具有与栅极电极60的几何形状或维度不同的几何形状或维度。根据实施例,场板80可以被电耦合到在相同沟槽65中的栅极电极60。根据在图1A中示出的实施例,场板80被设置在栅极电极60中的每个的下面并且没有场板被设置在控制电极70的下面。换句话说,场板80被设置在第一沟槽65中的每个中。根据更多的实施例,场板80可以被布置在每n个第n个第一沟槽65中,其中n等于或者大于2,例如,每第2个,第3个,第4个或者第5个第一沟槽65。
在图1A中示出的布置中,另一控制电极70被设置在沟槽150中,所述沟槽延伸到比栅极电极60中的每个的较低侧更大的深度。而且,该另一控制电极70延伸到比栅极电极60的较低侧更深的深度。场板80的较低侧可以被设置在栅极电极60的较低侧的下面。栅极沟槽65可以延伸到比控制电极70的沟槽150更大的深度。
根据实施例,晶体管可以被实施为超结晶体管或者超结器件。例如,多列不同掺杂的部分可被布置在漂移区中,并且所述列可以沿着漂移区的方向延伸。在这种超结或者补偿器件中,可以使用较高的掺杂浓度。因此,当晶体管在导通状态中时,由于可能使用的较高的掺杂浓度,存在另外的载流子,从而导致降低的导通电阻。当晶体管在截止状态中时,这些载流子被相反导电类型的载流子局部地补偿,使得实现高的击穿电压。
根据不同的实施例,在与栅极电极60相邻的绝缘材料61和与另一电极70相邻的绝缘材料71之间的半导体材料的宽度d比栅极电极60的深度t1或者另一控制电极70的深度t2短得多。根据这个解释,半导体材料的宽度d指的是在半导体本体区域30中在栅极电极60和另一控制电极70之间测量的最短宽度。此外,在晶体管的阈值电压处,在栅极电极60和另一控制电极70之间的沟道31的半导体材料被完全地耗尽。换句话说,当将相应于阈值电压的栅极电压施加到栅极电极60时,在第一和第二沟槽65,150之间的横向距离小于在栅极电极60和相邻的衬底材料之间的界面处的耗尽区域的宽度的两倍。满足下面的公式:
d ≤ 2 * Wm,其中Wm表示在与栅极电极60相邻的半导体衬底1中形成的表面耗尽区域的最大宽度。通常,Wm由下面的公式给定:
其中εS表示半导体材料的介电常数(对于硅是11.9*ε0),k表示玻耳兹曼常数(1.38066 *10-23J/K),T表示温度,ln表示自然对数,NA表示半导体本体30的杂质浓度,ni表示本征载流子浓度(在27°C对于硅是1.45 *1010),并且q表示基本电荷(1.6 * 10-19 C)。
通常,假定在相应于阈值电压的栅极电压处耗尽区的宽度对应于耗尽区的最大宽度。例如,沿着半导体衬底1的顶部表面10,在相邻的第一和第二沟槽65,150之间的半导体材料的宽度可以是大约20到130nm,例如40到120nm。
常规地,在包括场板80的相邻栅极沟槽65之间的距离或者间距已经被参数确定,所述参数已被设置用于优化场板80的功能。并入设置在具有与栅极电极60的第一沟槽65的形状不同形状的第二沟槽150中的控制电极70,使得引入另外的沟道区域成为可能。因此,与在常规栅极电极之间的距离相比,在控制电极70和栅极电极60之间的距离可被减小。此外,每一面积的沟道区域的数目可以被增加。根据实施例,可以提供每一场板80两个沟道区域(并且因而提供相应的面积)。
栅极电极60被设置在相对于图的被描绘的平面的垂直方向上延伸的沟槽65中。以相似的方式,第二沟槽150可以在垂直于图的被描绘的平面的方向上延伸。根据实施例,第二沟槽150可以在相对于这个图的被描绘的平面垂直的方向上被分段。因此,可以在绝缘材料71和相邻的半导体材料的界面处形成更多的沟道。
在图1A中示出的实例中,衬底1是n掺杂的,并且源极和漏极区域20,40也是n掺杂的。源极和漏极区域20,40的掺杂浓度可以比衬底1的掺杂浓度更高。沟道31是p掺杂的。
图1B示出半导体器件的截面图,其中本体接触22被形成以便与本体区域30接触。本体接触22包括与源极部分20的导电类型不同的导电类型的掺杂部分。由于本体接触22的存在,本体区域30可以与源极电势连接以便抑制当晶体管被设置到截止状态时可能由于撞击电离引起的寄生双极效应。具体地,当晶体管在截止状态中时,从晶体管减去空穴。
图1C示出半导体器件的平面图。如被示出的,本体接触22被形成为横断顶部氧化层62,72的条带。图1A的截面图取在I和I’之间,而图1B的截面图取在II和II’之间。
根据另一实施例,这种半导体器件可以被实现在所谓的“主动漂移区”FET中,其中串联连接的多个第二晶体管与第一晶体管串联连接。在这种情况下,在0V栅极电压下的导通电流被改善,使得改善的特性被示出。
图2示出实现ADZFET(“主动漂移区FET”)的半导体器件200的截面图。半导体器件200包括第一晶体管210和多个第二晶体管2201到220n,每个第二晶体管220具有源极区域221,漏极区域222和栅极电极224。第二晶体管2201到220n被串联耦合以形成串联电路。根据实施例,串联的第二晶体管2201到220n用作第一晶体管210的漂移区219。根据这个实施例,漂移区219沿着半导体衬底250的水平表面251延伸。第一晶体管210和多个第二晶体管2201到220n被至少部分地设置在包括掩埋的掺杂层252的半导体衬底250中。第二晶体管220中的每个的源极区域221或者漏极区域222被设置在掩埋层252中。因为串联的第二晶体管2201到220n用作第一晶体管210的漂移区219,并且第二晶体管220可被相应的栅极电极224中的每个控制,半导体器件200也被称作“主动漂移区场效应晶体管(ADZFET)”。
第一晶体管210和多个第二晶体管2201到220n被设置成与衬底表面251相邻。第一晶体管210的沟道213以及第二晶体管220的沟道223在横断半导体衬底250的水平表面251的第一方向上延伸。例如,沟道213和223可以垂直于半导体衬底250的水平表面251。第二晶体管220的栅极电极224被设置在可相对于半导体衬底251垂直地延伸的栅极凹槽中。第一晶体管210和多个第二晶体管2201到220n通过第一隔离沟槽217和多个第二隔离沟槽227而互相绝缘。第一隔离沟槽217和多个第二隔离沟槽227被填充有绝缘材料。第一和第二隔离沟槽217,227延伸到在掩埋层252下面的深度。例如,第一和第二隔离沟槽217,227可以在衬底250的深度方向上延伸。
图2的实施例示出一种布置,根据该布置,第一和第二晶体管210,220中的每个由并联连接的三个晶体管单元来实现。每个晶体管单元中的晶体管可以具有共同的栅极电极。此外,源极部分221被晶体管互连228电耦合。如将被清楚地理解的,第一和第二晶体管210,220中的每个可以包括任意数目的晶体管单元,并且对于第一和第二晶体管210,220,该数目可以是不同的。根据实施例,在相应于形成第一和第二晶体管210,220中的任一个的不同晶体管单元的栅极电极之间的距离可以被选择使得当施加相应于阈值电压的栅极电压时,在相邻的栅极电极之间的本体区域被完全耗尽。因此,在不同晶体管单元的栅极电极之间的距离等于或者小于2×(当施加相应于阈值电压的栅极电压时在与栅极电极相邻的本体区域295中形成的耗尽区的宽度)。根据该实施例,相邻的晶体管单元的栅极电极用作控制电极。
在图2中所示的实施例中,利用第一接触沟槽216和晶体管互连228将第一漏极部分212与设置在第二晶体管布置的左手侧的第二晶体管2201的源极部分221连接。而且,利用第二接触沟槽226和晶体管互连228将设置在第二晶体管的左手侧的晶体管2201的漏极区域222与下一晶体管的源极部分221连接。换句话说,第二晶体管被串联连接,在相邻的晶体管之间的接触通过第二接触沟槽226和晶体管互连228来实现。晶体管互连228可以通过在半导体衬底250的第一表面251上设置的导电层的分段来实现。
第二接触沟槽226接触其中设置了第一和第二漏极区域212,222的掩埋层252。例如,第一接触沟槽216可以与第一晶体管210的第一漂移区241相邻设置。第二接触沟槽226可以与第二晶体管220的第二漂移区240相邻设置。此外,第一接触沟槽216可以与第一隔离沟槽217相邻设置。第二接触沟槽226可以与第二隔离沟槽227相邻设置。根据该布置,接触沟槽216,226与相邻的漂移区绝缘,并且接触沟槽216,226和隔离沟槽217,227的加工可以被进一步简化。
利用晶体管互连228和衬底接触218将第一晶体管210的源极区域211与衬底250连接。
例如,第一晶体管210可以被实施为具有第一沟道213的所谓的增强FET,所述第一沟道具有与第一和第二漏极部分211,212的掺杂类型不同的掺杂类型。增强场效应晶体管在n沟道FET的情况下具有正的阈值电压,或者在p沟道FET的情况下具有负的阈值电压。增强场效应晶体管在零栅极电压下被设置到截止状态。而且,第二晶体管220可以被实施为耗尽场效应晶体管,其意味着第二晶体管220在n沟道FET的情况下具有低于0V的阈值电压,或者在p沟道FET的情况下具有超过0V的阈值电压。耗尽场效应晶体管在零栅极电压下被设置到导通状态。沟道223被掺杂有与第二源极和漏极部分221,222相同的掺杂类型。
在图2中示出的实例中,衬底250是p掺杂的,并且源极区域211,221和漏极区域212,222是n掺杂的。例如,漏极区域212,222可以通过n+掺杂的掩埋层来被实施。根据该实例,第一晶体管210的沟道213是p掺杂的并且第二晶体管220的沟道223是轻度n掺杂的。
在图2中示出的布置中,第一和第二晶体管210,220中的每个被实施为所谓的垂直半导体器件。源极部分221可以与半导体衬底250的第一表面251相邻地设置。栅极沟槽被设置在半导体衬底250的第一表面251中。栅极电极224被设置在栅极沟槽内,该栅极电极224通过栅极介电材料225与相邻的本体区域254绝缘。沟道区域223与栅极电极224相邻设置。第二晶体管220的本体区域254包括第二沟道223,并且因而具有与源极和漏极区域221,222相同的导电类型。例如,本体区域254的各部分与第二漂移区240相邻设置。
例如,当通过施加正的栅极电压被接通时,在第一沟道区域213和栅极介电材料215之间的边界处形成反型层。因此,晶体管210通过第一漂移区241处于从第一源极区域211到第一漏极区域212的导电状态中。在关断的情况下,没有反型层被形成并且晶体管210不在导电状态中。
此外,当正的或者零电压被施加到第二栅极电极224,在第二沟道区域223和第二栅极介电材料225之间的边界处可以形成积累层。因此,利用被施加的正的或者零栅极电压,第二晶体管220处在从第一源极区域221到第二漏极区域222的导电状态中。在关断的情况下,第二晶体管220被设置在非导电状态中。因此,通过适当的电路设计,当第一晶体管处在导通状态中时,第二晶体管将被设置在导通状态中,从而降低了导通电阻。当第一晶体管210处在截止状态中时,第二晶体管220将被设置在截止状态中,从而增加了击穿电压。
如在图2中示出的,串联的第一晶体管210和多个第二晶体管220与半导体衬底250的第一表面251相邻地形成。此外,第一和第二漏极区域212,222中的每个被形成为在半导体衬底250内的掩埋层。因此,第一和第二晶体管210,220中的每个被实施为垂直器件。因此,半导体器件的Ron×面积的乘积可被进一步改善。而且,由于在图2中示出的布置,在晶体管序列下面的全部区域可以被用作漂移区219,由此击穿电压被进一步增加。换句话说,半导体器件包括第一晶体管和多个第二晶体管的串联连接,根据其,当第一晶体管处在导通状态中时,第二晶体管处在导通状态中,并且当第一晶体管处在截止状态中时,第二晶体管处在截止状态中。另外,第一和第二晶体管被实施为垂直功率器件。因此,所得到的半导体器件具有改善的特性。
总之,在图2中示出的实施例涉及一种半导体器件,其包括具有第一漂移区的第一晶体管,和多个第二晶体管,每个第二晶体管包括源极区域,漏极区域和栅极电极,其中第二晶体管被串联电耦合以形成电耦合到第一晶体管的串联电路,该第一和多个第二晶体管被至少部分地设置在包括掩埋掺杂层的半导体衬底中,其中第二晶体管的源极或者漏极区域被设置在掩埋掺杂层中。第二晶体管中的每个包括并联连接的至少两个晶体管单元。形成部分第二晶体管的晶体管单元中的每个的栅极电极被设置在栅极沟槽中,所述栅极沟槽被设置在半导体衬底的表面内。在相邻的栅极沟槽之间的距离小于2×Wm,Wm由上面给定的公式定义。
图3A示出另外的实施例。在图3A中示出的半导体器件300包括多个晶体管单元315,晶体管单元315中的每个包括源极区域320,漏极区域340,和被设置在布置于半导体衬底301的顶部表面310中的沟槽375中的栅极电极360。不同晶体管单元315的栅极电极360被互相电耦合,不同晶体管单元315的源极区域320被互相电耦合,并且不同晶体管单元315的漏极区域340被互相电耦合。因此,晶体管单元315被并联电耦合。当相应于晶体管的阈值电压的栅极电压被施加到栅极电极360时,在沟槽375之间的横向距离d等于或者小于在与栅极电极360相邻的半导体本体395中形成的耗尽区的宽度的长度的两倍。例如,在沟槽之间的距离d可以是120nm或者更小,诸如100nm或者更小。例如,在沟槽375之间的距离d可以是在18和120nm之间。
例如,可以通过栅极电介质361使栅极电极360与相邻的半导体材料301绝缘。可以利用导电材料325使源极区域320电耦合。晶体管单元315中的每个进一步包括被设置在半导体本体395和漏极区域340之间的漂移区385。源极区域320被设置成与半导体衬底301的顶部表面310相邻,并且漏极区域340被设置在半导体衬底301的背面处。
根据在图3B中示出的实施例,多个晶体管单元315包括第一和第二晶体管单元316,317。第一晶体管单元316包括第一栅极电极365,并且第二晶体管单元317包括第二栅极电极370。第一和第二栅极电极365,370相互不同。例如,第一栅极电极365被设置在第一沟槽376中并且第二栅极电极370被设置在第二沟槽377中,并且第一沟槽376可以具有与第二沟槽377的第二维度不同的第一维度。例如,第一沟槽376可以延伸到比第二沟槽377的深度t2更大的深度t1。另外地或者可替代地,第一沟槽376可以具有与第二沟槽377的宽度w2不同的宽度w1。更进一步地,第一沟槽376的截面形状可以与第二沟槽377的截面形状不同。在第一和第二栅极电极365,370之间的差别或者在第一和第二沟槽376,377之间的差别不归因于可能由栅极电极或者沟槽制作而引起的偏移,其与非故意的偏移有关。更确切地,该差别是由用于第一和第二栅极电极365,370的不同制作条件,或者由用于第一和第二沟槽376,377的不同制作条件引起的。
根据另外的实施例,场板可以被设置在第一沟槽376中,并且没有场板被设置在第二沟槽377中。在图1A和1B中示出场板80的实例。例如,场板可以被电耦合到第一栅极电极365或者可以被绝缘并可以被保持在不同的电势处。
图4A至4F示出当制作半导体器件90时半导体衬底100的截面图。例如,n掺杂的硅晶片可以是半导体器件的起始材料。然而,应清楚地理解被使用的掺杂类型可以被反过来。在半导体衬底100的表面110上,形成氮化硅(SiN)层130。在下面的加工步骤期间,SiN层130用作硬掩模。参考数字120表示半导体衬底100的背面。此后,执行标准加工步骤以便制作包括栅极电极的垂直MOSFET,所述栅极电极被设置在形成于衬底表面110中的沟槽中。具体地,沟槽65被蚀刻到半导体衬底110中。绝缘材料81,61被形成在沟槽的侧壁上并且沟槽被填充有导电材料80,60。例如,导电材料60,80可以是多晶硅并且绝缘材料可以是氧化硅。例如,导电材料60形成栅极电极并且导电材料80形成所得到的功率MOSFET器件的场板。在加工之后,在半导体衬底的顶部上的多晶硅材料160不被回蚀。因此,如在图4B中示出的,氮化硅材料130的条带和多晶硅材料160的条带被设置在衬底表面的上方,多晶硅材料160的条带和氮化硅130的条带形成所得到的结构的表面。
此后,实施氧化步骤使得在多晶硅填料160的表面处形成氧化硅。因此,如在图4C中所示,氧化硅162的条带和氮化硅硬掩模层130的条带形成所得到结构的表面。
从衬底表面110去除氮化硅层130并且多晶硅填料160形成突出的部分。例如,这可以通过在热磷酸中蚀刻完成。然后,通过普通的工艺沉积另外的氮化硅层。氮化硅层140的厚度依照将在稍后的加工步骤中形成的沟槽150的所需厚度来选择。在沉积氮化硅层140之后,执行隔离物蚀刻工艺。例如,由于隔离物蚀刻工艺,氮化硅层在水平方向上比在垂直方向上以更高的蚀刻速率被蚀刻。因此,在多晶硅材料的侧壁处形成隔离物140。当在水平方向上被测量时,由于专门的加工,设置在多晶硅插塞160中的每个的左手侧和右手侧的隔离物140将具有相同的宽度。
此后,使用氮化硅隔离物140和氧化硅材料162作为蚀刻掩模,沟槽150被蚀刻在衬底表面110中。例如,沟槽150可以被蚀刻以延伸到比已经形成在半导体衬底100中的栅极电极60更大的深度。图4D示出所得到结构的实例。
然后,执行氧化步骤以便沿着沟槽150的侧壁形成栅极氧化层151。在下面的步骤中,导电材料例如多晶硅152被填充在沟槽150中,其后是凹进蚀刻步骤以便多晶硅材料152的表面是在与多晶硅材料160的表面相同的高度。图4E示出所得到结构的实例。
此后,从多晶硅材料160的表面除去氧化硅材料162并且通过已知工艺蚀刻氮化硅隔离物140。在下一个步骤中,沉积氧化硅层155。因此,如在图4F中示出的,半导体衬底100的表面被氧化硅层155覆盖。
即使当栅极电极60以40到200nm的小的间距被设置时,由于氮化硅隔离物层的使用,沟槽150相对于其中存在栅极电极60的沟槽65以自对准的方式被设置。因此,沟槽150被设置在其中存在栅极电极60的沟槽65之间的距离的中心处。此外,在右手侧的半导体材料的宽度等于在沟槽150的左手侧的半导体材料的宽度。如被清楚地理解的,代替氮化硅材料,任何其它适合的牺牲材料可被用于形成隔离物140。然后,接触和金属化层和线可以被形成,这是常规的。
图5A示意地示出根据实施例的制作半导体器件的方法。如被示出的,制作半导体器件的方法包括通过下述来形成晶体管:形成源极区域,漏极区域,栅极电极,通过在半导体衬底的顶部表面中形成第一沟槽(S101)来形成栅极电极,并且形成控制电极,形成控制电极包括在半导体衬底的顶部表面中形成第二沟槽(S102)。
根据实施例,在形成第一沟槽(S101)之后执行形成第二沟槽(S102)。根据另一实施例,第二沟槽150相对于第一沟槽65的位置以自对准的方式被形成。例如,这可以通过在第一沟槽65中填充填充材料(S201)以便填充材料从半导体衬底100的顶部表面110突出来完成,该突出的填充材料160具有侧壁165。例如,该填充材料可以是用于形成栅极电极的导电材料。可替代地,该填充材料可以是任意的牺牲材料。此后,另一牺牲材料的隔离物可以与该突出的填充材料160相邻地形成(S202)。图5B示出这种方法的实施例。
根据实施例,使用突出的填充材料160和隔离物140作为蚀刻掩模,在半导体衬底100的顶部表面中蚀刻(S102)第二沟槽150。然后,根据已知的加工方法,半导体器件被进一步加工。
虽然本发明的实施例已经在上面被描述,显然可以实施更多的实施例。例如,更多的实施例可以包括在权利要求中阐述的特征的任何子组合或者在上面给定的实例中描述的元件的任何子组合。因此,所附权利要求的该精神和范围不局限于本文包含的实施例的描述。
Claims (21)
1.一种半导体器件,包括:
晶体管,其包括源极区域,漏极区域,和栅极电极,该栅极电极被设置在布置于半导体衬底的顶部表面中的第一沟槽中;和
控制电极,其被设置在布置于所述半导体衬底的顶部表面中的第二沟槽中,所述第二沟槽具有与所述第一沟槽的第一形状不同的第二形状。
2.根据权利要求1的半导体器件,进一步包括设置在所述栅极电极下面的场板,并且其中没有场板被设置在所述控制电极下面。
3.根据权利要求1的半导体器件,其中所述源极区域与所述半导体衬底的所述顶部表面相邻设置,并且所述漏极区域被设置在所述半导体衬底的背面处,所述半导体器件进一步包括与所述栅极电极相邻的本体区域和被设置在所述漏极区域和所述本体区域之间的漂移区。
4.根据权利要求3的半导体器件,进一步包括多列不同掺杂部分,其被布置在漂移区中并且相对于所述半导体衬底的顶部表面垂直地延伸,使得形成超结器件。
5.根据权利要求1的半导体器件,其中在所述第一和第二沟槽之间的横向距离被选择成使得当相应于所述晶体管的阈值电压的电压被施加到所述栅极电极时,与栅极电极相邻的本体区域被完全耗尽。
6.根据权利要求1的半导体器件,其中在所述第一和第二沟槽之间的距离小于所述第一或第二沟槽的深度。
7.根据权利要求1的半导体器件,其中所述第一沟槽比所述第二沟槽具有更大的深度。
8.根据权利要求1的半导体器件,其中所述控制电极延伸到比所述栅极电极的深度更大的深度,所述深度是从所述半导体衬底的顶部表面测量的。
9.一种半导体器件,包括:
多个晶体管单元,所述晶体管单元中的每个包括源极区域,漏极区域,和被设置在布置于半导体衬底的顶部表面中的沟槽中的栅极电极;
其中不同晶体管单元的所述栅极电极被互相电耦合,不同晶体管单元的所述源极区域被互相电耦合,并且不同晶体管单元的所述漏极区域被互相电耦合;并且
其中对于在所述沟槽之间的横向距离d,满足d ≤ 2 * Wm,
其中Wm表示在与所述栅极电极相邻的半导体衬底中形成的表面耗尽区域的最大宽度。
10.权利要求9的半导体器件,其中所述多个晶体管单元包括第一和第二晶体管单元,所述第一晶体管单元包括第一栅极电极,所述第二晶体管单元包括第二栅极电极,并且其中所述第一栅极电极的形状与所述第二栅极电极的形状是不同的。
11.权利要求10的半导体器件,其中所述第一栅极电极被设置在第一沟槽中并且所述第二栅极电极被设置在第二沟槽中,所述第一沟槽具有与所述第二沟槽的第二尺寸不同的第一尺寸。
12.权利要求10的半导体器件,其中所述第一栅极电极被设置在第一沟槽中并且所述第二栅极电极被设置在第二沟槽中,场板被设置在所述第一沟槽中,并且没有场板被设置在所述第二沟槽中。
13.权利要求9的半导体器件,其中在相邻沟槽之间的横向距离小于120nm。
14.一种制作半导体器件的方法,包括:
通过形成源极区域,漏极区域,和栅极电极来形成晶体管,其中所述栅极电极通过在所述半导体衬底的顶部表面中形成第一沟槽来形成;并且
通过在所述半导体衬底的顶部表面中形成第二沟槽来形成控制电极。
15.权利要求14的方法,其中所述第二沟槽在形成所述第一沟槽之后被形成。
16.权利要求15的方法,其中相对于所述第一沟槽,所述第二沟槽以自对准方式被形成。
17.权利要求14的方法,其中所述第一沟槽被形成为具有比所述第二沟槽更大的深度。
18.权利要求14的方法,其中所述第一和第二沟槽被形成为具有小于120nm的距离。
19.根据权利要求17的方法,其中形成所述栅极电极进一步包括:
在所述第一沟槽中填充填充材料,使得所述填充材料从所述半导体衬底的顶部表面突出,该突出的填充材料具有侧壁;并且
形成与所述侧壁相邻的牺牲材料的隔离物。
20.根据权利要求19的方法,其中所述填充材料是导电材料。
21.根据权利要求19的方法,进一步包括使用该突出的填充材料和该隔离物作为蚀刻掩模,在所述半导体衬底的顶部表面中蚀刻所述第二沟槽。
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