CN110718585A - Ldmos器件及其制造方法 - Google Patents

Ldmos器件及其制造方法 Download PDF

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CN110718585A
CN110718585A CN201910830811.7A CN201910830811A CN110718585A CN 110718585 A CN110718585 A CN 110718585A CN 201910830811 A CN201910830811 A CN 201910830811A CN 110718585 A CN110718585 A CN 110718585A
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field plate
plate contact
metal layer
contact
drain
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艾瑞克·布劳恩
乔伊·迈克格雷格
郑志星
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

公开了一种LDMOS器件及其制造方法。LDMOS器件包括位于衬底中的源区和漏区以及位于衬底上的栅极，该栅极横向位于源区和漏区之间。LDMOS器件还包括位于衬底上的栅极和漏区之间区域的场板和位于场板上的场板接触。场板接触包括上表面，上表面在纵向上包括第一部分和第二部分。场板接触的上表面还电气接触场板接触金属层，该场板接触金属层覆盖场板接触的第一部分而不覆盖场板接触的第二部分。这样，减小了场板接触金属层的面积，从而便减小了场板接触金属层和漏极金属层之间边缘场，进而减小了两者之间的寄生电容。这样，峰值电场得到有效降低，或者说，LDMOS器件的击穿电压被有效提高。

Description

LDMOS器件及其制造方法
技术领域
本发明涉及横向扩散金属氧化物半导体(Laterally Diffused Metal OxideSemiconductor，LDMOS)器件，尤其涉及LDMOS器件的场板接触(field plate contact)和场板接触金属层(field plate contact metal layer)。
背景技术
目前，各种结构的场板广泛应用在半导体器件中，以在电压给定的情况 下有效地降低峰值电场，或者说以在临界电场达到时有效提高击穿电压。图 1示出传统LDMOS器件00的部分结构的俯视图。如图1所示，LDMOS器 件00包括位于场板(未示出)上方的场板接触01和位于场板接触01上方的 场板接触金属层02。其中，场板接触01在纵向上和漏极接触03平行。漏极 接触金属层04位于漏极接触03上方。场板接触01在横向上包括边缘E1和 E2，且场板接触金属层02从边缘E1延伸至边缘E2，以实现场板接触01和 外加电压之间的电气连接。
上述结构的一个缺点在于，由于场板接触金属层02和漏极接触金属层04 相平行，会产生边缘场(fringing fields)，而边缘场使得场板接触金属层02和 漏极接触金属层04之间产生寄生电容，从而造成LDMOS器件在开关时产生 功耗，其效率降低。
因此，需要提出一种LDMOS器件以至少解决上述问题。
发明内容
依据本发明实施例的一个方面，提出了一种LDMOS器件，包括：位于 衬底中的源区和漏区；位于衬底上的栅极，所述栅极横向位于源区和漏区之 间；位于衬底上的场板，所述位于栅极和漏区之间；位于场板上的场板接触， 其中，场板接触包括上表面，上表面在纵向上包括第一部分和第二部分；以 及和场板接触的上表面电气接触的场板接触金属层，其中，场板接触金属层 覆盖场板接触的第一部分且不覆盖场板接触的第二部分。
依据本发明实施例的又一个方面，提出了一种LDMOS器件的制造方法， 包括：在衬底中形成漂移区且在衬底上形成栅极；在衬底中形成体区，其中， 部分体区位于栅极下方；在漂移区中形成漏区且在体区中形成源区；在衬底 上的栅极和漏区之间的区域形成场板；在场板上形成场板接触，其中，场板 接触包括上表面，所述上表面在纵向上包括第一部分和第二部分；以及在场 板接触上形成场板接触金属层，其中，场板接触金属层覆盖场板接触的第一 部分而不覆盖场板接触的第二部分。
利用本发明实施例提出的LDMOS器件，其场板接触用来在漏极金属层 附近形成更低的电势，从而更有效地使通常出现在栅电极的漏极侧的强电场 向N+型掺杂漏区方向靠近而远离栅电极。这样，峰值电场得到有效降低，或 者说，LDMOS器件的击穿电压被有效提高。
场板接触金属层用于在场板接触和外加电压之间形成电气连接。传统的 大尺寸场板接触金属层会形成边缘场，从而在平行的漏极金属层和场板接触 金属层之间形成寄生电容。在本发明公开的器件结构中，场板接触金属层具 有最小尺寸，可以帮助降低边缘场，从而降低和场板接触金属层相关的寄生 电容，例如，显著降低平行的漏极金属层和场板接触金属层之间形成的寄生 电容；降低场板接触金属层和其附近的金属、聚合物、硅导体等等之间所形 成的寄生电容。降低这些寄生电容可以降低LDMOS器件在开关时的功耗和提高增益效率。
另外，本发明公开的器件结构消除了金属-金属线，且减小了场板接触金 属层面积从而消除了间隔限制，使得漏极接触和场板接触之间的间隙可以更 小。因此，本发明公开的LDMOS器件可以具有更小的漏极-源极单元，从而 具有更低的电阻和更低的欧姆损耗。
另一方面，由于场板接触金属层116对降低LDMOS器件100的电场或 提高其击穿电压不起作用，因此，减小场板接触金属层116的面积不会影响 LDMOS器件100的击穿电压或导通电阻方面的性能。
附图说明
图1示出传统LDMOS器件00的部分结构的俯视图。
图2A和2B示出依据本发明一实施例的新型LDMOS器件100。
图3示出依据本发明一实施例的LDMOS器件制造方法300。
具体实施方式
下面将详细描述本发明的具体实施例，应当注意，这里描述的实施例只 用于举例说明，并不用于限制本发明。在以下描述中，为了提供对本发明的 透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见 的是：不必采用这些特定细节来实行本发明。在其他实例中，为了避免混淆 本发明，未具体描述公知的电路、材料或方法。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的 提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本 发明至少一个实施例中。因此，在整个说明书的各个地方出现的短语“在一 个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或 示例。此外，可以以任何适当的组合和、或子组合将特定的特征、结构或特 性组合在一个或多个实施例或示例中。此外，本领域普通技术人员应当理解， 在此提供的示图都是为了说明的目的，并且示图不一定是按比例绘制的。应当理解，当称“元件”“连接到”或“耦接”到另一元件时，它可以是直接连接或 耦接到另一元件或者可以存在中间元件。相反，当称元件“直接连接到”或“直 接耦接到”另一元件时，不存在中间元件。相同的附图标记指示相同的元件。 这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。
本发明公开了新型LDMOS(Laterally Diffused Metal Oxide Semiconductor，横向扩散金属氧化物半导体)器件和制造该LDMOS器件的方法的各种实施 例。在仔细阅读本发明内容后，本领域技术人员应当理解，本发明的 LDMOS器件及其制造方法可以应用于多种器件，包括但不限于逻辑器件、 存储器件等等。接下来，将参考图2A-2B和图3，对本发明的各个实施例进 行详细阐释。
图2A和2B示出依据本发明一实施例的新型LDMOS器件100。具体地， 图2A示出LDMOS器件100的剖面图，而图2B示出LDMOS器件100的部 分结构的俯视图。如图2A所示，LDMOS器件100示例性包括半导体衬底 101，例如，具有主体(bulk)或者绝缘衬底硅(silicon-on-insulator，SOI) 结构的硅衬底。本领域技术人员应当理解，根据具体应用需求，衬底101也 可以包括除硅材料以外的其他材料。在图1所示实施例中，LDMOS器件100 还示例性地包括可以用传统技术制造在衬底101中的P型阱区域102、N型掺 杂漂移区103、N+型掺杂源区104、N+型掺杂漏区105和P+型掺杂阱106。
本领域技术人员应当理解，上述N型LDMOS器件100所包括的各个部 分的掺杂类型仅是示例性的，本发明所公开的器件结构还适用于P型LDMOS 器件，P型LDMOS器件各个部分的掺杂类型与N型LDMOS器件各个相应 部分的掺杂类型相反。
图示LDMOS器件100还进一步包括栅极。栅极包括栅绝缘层107、栅电 极108和侧壁隔离区109。栅极通常横向位于源区104和漏区105之间以在栅 电极108下面建立起沟道。本领域技术人员应当理解，在一实施例中， LDMOS器件100也可以不包括侧壁隔离区109；在又一实施例中，LDMOS 器件100的栅极可以包括更多结构区域，例如多个金属硅化物(metalsilicide) 区域。
如图2A所示，LDMOS器件100还进一步包括位于N型掺杂漂移区103 上且位于N+型掺杂漏区105和栅极之间的场板110，例如硅化物材质 (silicide)的场板。在图2A所示实施例中，场板110向N+掺杂源区105延 伸但与N+掺杂源区105隔离开，且场板110的一部分位于栅电极108的一部 分之上。在另一实施例中，根据具体设计，场板110可以一直延伸至N+型掺 杂漏区105直至与N+型掺杂漏区105相接触。在又一实施例中，场板110不 必位于栅电极108之上。在一些应用中，场板110可以具有比传统场板更大 的厚度以保证位于场板110上的场板接触113(后文将详细描述)不会碰到 下面的N型掺杂漂移区103。
在一个实施例中，LDMOS器件100可以包括位于衬底101和场板110之 间的场板阻止层以隔离场板110和衬底101。在一个实施例中，场板阻止层 可以是氧化物材质的垫片层，例如，二氧化硅层。
LDMOS器件100还可以进一步包括和源区104电气连接的源极接触111、 和漏区105电气连接的漏极接触112以及和场板110电气连接的场板接触113。 在图2A所示实施例中，源极接触111还位于部分P+型掺杂阱106之上。进 一步地，LDMOS器件100还包括位于源极接触111之上的源极金属层114、 位于漏极接触112之上的漏极金属层115和位于场板接触113之上的场板接 触金属层116。源极接触111和源极金属层114连接低电压(“VLOW”)，漏 极接触112和漏极金属层115连接高电压(“VHIGH”)。在一个实施例中，低 电压VLOW可以是零伏而高电压VHIGH为数十伏。当然，根据具体应用不同， 低电压VLOW和高电压VHIGH也会不同。在图示实施例中，源极接触111和源 极金属层114电气连接至源区104和P+型掺杂阱106以将源区104和P+型掺 杂阱106连接至相同低电压上。然而，本领域技术人员应当理解，在其他实 施例中，P+型掺杂阱106可以不与源区104共享源极接触111和源极金属层 114，而是具有自己单独的接触和位于单独接触之上的单独的金属层，该单 独的接触和金属层连接至另一相对于漏极接触112和漏极金属层115所加电 压来说更低的电压上，该另一低电压有别于源极接触111和源极金属层114 所连接的电压。
图2B示出图2A中LDMOS器件100的俯视图。如图2B所示，漏极接 触112、漏极金属层115、场板接触113、场板接触金属层116、源极接触111 和源极金属层114均位于衬底101上(在图2B中未示出)。图2B还示出栅 电极108以便说明。所示源极金属层114、漏极金属层115和场板接触金属层 116在图2B中用虚线表示以便示出源极金属层114下方的源极接触111、漏 极金属层115下方的漏极接触112以及场板接触金属层116下方的场板接触 113。图2B中并未示出LDMOS器件100的所有结构，以避免混淆和简化说 明。如图2A和2B所示，场板接触金属层116电气连接至场板接触113。在 所示实施例中，场板接触金属层116在纵向上覆盖场板接触113的一部分而 不是覆盖整个场板接触113，场板接触113的剩余部分是裸露的，未被场板 接触金属层116所覆盖。如图2A和2B所示，源极金属层114横向上超出源 极接触111的两个边缘，场板接触金属层116横向上超出场板接触113的两 个边缘，漏极金属层115横向上超出漏极接触112的两个边缘。然而，在另 一实施例中，源极金属层114可以在横向上刚好延伸至源极接触111的两个 边缘，场板接触金属层116可以在横向上刚好延伸至场板接触113的两个边 缘，漏极金属层115可以在横向上刚好延伸至漏极接触112的两个边缘。在 另一实施例中，源极金属层114横向上在源极接触111的两个边缘以内，场 板接触金属层116横向上在场板接触113的两个边缘以内，漏极金属层115 横向上在112的两个边缘以内。场板接触金属层116具有满足场板接触金属 层116和外加电压之间能够进行电气连接所允许的最小尺寸，该最小尺寸小 于覆盖整个场板接触的场板接触金属层的最小尺寸。在一个实施例中，该最 小尺寸由LDMOS器件100的物理限制(例如，场板接触113和场板接触金 属层116的电子迁移和电阻)而限定。在一个实施例中，场板接触113具有 长方形上表面，其包括横向边缘E1和E2，而场板接触金属层116在纵向上 从边缘E1向边缘E2延伸但不与边缘E2相接触。相反，如图2B所示，源极 金属层114在纵向上从漏极接触112的一端一直延伸至漏极接触112的另一 端，类似地，漏极金属层115在纵向上从源极接触111的一端一直延伸至源 极接触111的另一端。当然，在其他实施例中，源极金属层114在纵向上不 必延伸至漏极接触112的另一端，类似的，漏极金属层115在纵向上不必延 伸至源极接触111的另一端。
本领域技术人员应当理解，图2A和2B所示的LDMOS器件100仅包括 一块场板接触113，然而，在其他实施例中，场板接触可以包括多块独立的 结构，而场板接触金属层电气连接至该多块独立的结构。
在LDMOS器件100中，场板接触113用来在漏极金属层115附近形成 更低的电势，从而更有效地使通常出现在栅电极108的漏极侧的强电场向N+ 型掺杂漏区105方向靠近而远离栅电极108。这样，峰值电场得到有效降低， 或者说，LDMOS器件100的击穿电压被有效提高。
场板接触金属层116用于在场板接触113和外加电压之间形成电气连接。 传统的大尺寸场板接触金属层会形成边缘场，从而在平行的漏极金属层和场 板接触金属层之间形成寄生电容。在本发明公开的器件结构中，场板接触金 属层116具有最小尺寸，可以帮助降低边缘场，从而降低和场板接触金属层 116相关的寄生电容，例如，显著降低平行的漏极金属层115和场板接触金属 层116之间形成的寄生电容；降低场板接触金属层116和其附近的金属、聚 合物、硅导体等等之间所形成的寄生电容。降低这些寄生电容可以降低 LDMOS器件100在开关时的功耗和提高增益效率。
另外，本发明公开的器件结构消除了金属-金属线，且减小了场板接触金 属层面积从而消除了间隔限制，使得漏极接触和场板接触之间的间隙可以更 小。因此，本发明公开的LDMOS器件100可以具有更小的漏极-源极单元， 从而具有更低的电阻和更低的欧姆损耗。
另一方面，由于场板接触金属层116对降低LDMOS器件100的电场或 提高其击穿电压不起作用，因此，减小场板接触金属层116的面积不会影响 LDMOS器件100的击穿电压或导通电阻方面的性能。
图3示出依据本发明一实施例的LDMOS器件制造方法300。如图3所 示，器件制造方法300包括步骤301-307。具体地，在步骤301中，在衬底中 形成漂移区并在衬底上形成栅极。在步骤302中，在衬底中形成体区，该体 区的一部分位于栅极下方。在步骤303中，在漂移区中形成漏区且在体区中 形成源区。在步骤304中，在衬底上方形成场板阻止层，该场板阻止层形成 于栅极和漏区之间。在一个实施例中，场板阻止层可以是氧化物材质的垫片层，例如，二氧化硅层。在步骤305中，在场板阻止层上形成场板。在另一 实施例中，器件制造方法300可以不包括步骤304，而步骤305包括在衬底上 形成场板，该场板形成于栅极和漏区之间。在步骤306中，在场板上形成场 板接触，其中，场板接触包括上表面，该上表面在纵向上包括第一部分和第 二部分。在一个实施例，场板接触接近漏极接触。在另一实施例中，场板接 触包括多个独立的结构，而场板接触金属层电气连接至该多个独立的结构。 在步骤307中，在场板接触上形成场板接触金属层，其中，场板接触金属层 覆盖场板接触的第一部分。在一个实施例中，场板接触的上表面为长方形而 场板接触的第一部分为从长方形的一个边缘沿纵向延伸的部分。在另一实施 例中，场板接触金属层具有最小尺寸，该最小尺寸为LDMOS器件的物理限 制下所允许的最小尺寸。该最小尺寸小于覆盖整个场板接触区域的场板接触 金属层的最小尺寸。在一个实施例中，LDMOS器件的物理限制由场板接触 金属层与外加电压之间的电气连接的要求所限定。在另一实施例中，场板接 触金属层覆盖场板接触的一部分。
在一个实施例中，器件制造方法300还包括在漏区上形成漏极接触和在 漏极接触上形成漏极金属层，其中，漏极接触和场板接触相隔离开，而漏极 金属层和场板接触金属层相隔离开。在一个实施例中，器件制造方法300还 包括在源区上形成源极接触以及在源极接触上形成源极金属层，其中，源极 接触和栅极隔离开，源极金属层和场板接触金属层相隔离开。
虽然已参照几个典型实施例描述了本发明，但应当理解，所用的术语是 说明和示例性、而非限制性的术语。由于本发明能够以多种形式具体实施而 不脱离发明的精神或实质，所以应当理解，上述实施例不限于任何前述的细 节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利 要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (14)

1.一种LDMOS器件，包括：
位于衬底中的源区和漏区；
位于衬底上的栅极，所述栅极横向位于源区和漏区之间；
位于衬底上的场板，所述位于栅极和漏区之间；
位于场板上的场板接触，其中，场板接触包括上表面，上表面在纵向上包括第一部分和第二部分；以及
和场板接触的上表面电气接触的场板接触金属层，其中，场板接触金属层覆盖场板接触的第一部分且不覆盖场板接触的第二部分。
2.如权利要求1所述的LDMOS器件，其中，场板接触的上表面为矩形形状，且上表面的第一部分为从矩形形状的一条边缘沿纵向延伸的部分。
3.如权利要求1所述的LDMOS器件，其中，场板接触接近漏极接触。
4.如权利要求1所述的LDMOS器件，其中，场板接触包括多个独立结构，且场板接触金属层电气连接至所述多个独立结构。
5.如权利要求1所述的LDMOS器件，其中，LDMOS器件包括位于场板和衬底之间的场板阻止层，所述场板阻止层位于栅极和漏区之间。
6.如权利要求1所述的LMDOS器件，其中，LDMOS器件还包括：
位于漏区上且与场板接触相隔离开的漏极接触；以及
电气连接至漏极接触的漏极金属层，其中，漏极金属层和场板接触金属层相隔离开。
7.如权利要求1所述的LMDOS器件，其中，LDMOS器件还包括：
位于源区上且与栅极相隔离开的源极接触；以及
和源极接触电气连接的源极金属层。
8.如权利要求1所述的LDMOS器件，其中，场板接触金属层具有LDMOS器件的物理限制下所允许的最小尺寸，且其中，LDMOS器件的物理限制由场板接触金属层和外加电压之间的电气连接要求所决定。
9.如权利要求8所述的LDMOS器件，其中，LDMOS器件的物理限制包括场板接触和场板接触金属层的电阻和电子迁移。
10.一种LDMOS器件的制造方法，包括：
在衬底中形成漂移区且在衬底上形成栅极；
在衬底中形成体区，其中，部分体区位于栅极下方；
在漂移区中形成漏区且在体区中形成源区；
在衬底上的栅极和漏区之间的区域形成场板；
在场板上形成场板接触，其中，场板接触包括上表面，所述上表面在纵向上包括第一部分和第二部分；以及
在场板接触上形成场板接触金属层，其中，场板接触金属层覆盖场板接触的第一部分而不覆盖场板接触的第二部分。
11.如权利要求10所述的制造方法，其中，场板接触的上表面为矩形形状，且上表面的第一部分为从矩形形状的一条边缘沿纵向延伸的部分。
12.如权利要求10所述的制造方法，还包括：
在漏区上形成漏极接触，其中，漏极接触和场板接触相隔离开；以及
在漏极接触上形成漏极金属层，其中，漏极金属层和场板接触金属层相隔离开。
13.如权利要求10所述的制造方法，其中，场板接触包括多个独立结构，且场板接触金属层电气连接至所述多个独立结构。
14.如权利要求10所述的制造方法，还包括在衬底上位于栅极和漏区之间的区域形成场板阻止层，其中，场板形成于场板阻止层之上。
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