CN105742365A - 射频ldmos晶体管及其制作方法 - Google Patents
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Abstract
本发明提供一种射频LDMOS晶体管,包含:P型外延层、背面金属电极、P阱、P+sinker区、N?漂移区、多晶硅栅极、栅氧化层,多晶硅栅极的上方右侧设有法拉第罩,法拉第罩包括阶梯状金属层和多个块状金属层,法拉第罩与半导体表面之间设有二氧化硅介质层;本发明还提供一种射频LDMOS晶体管的制作方法,包括步骤:形成P型外延层、P+sinker区、多晶硅栅极、P阱、N+源极、轻掺杂N?漂移区、N+漏极,淀积二氧化硅介质层,淀积金属层形成阶梯型金属层以及块状金属层,构成法拉第罩;本发明覆盖在漂移区上方的源场板面积更小,可以在不增加栅漏电容的前提下有效地减少器件的源漏电容,提高器件的频率特性,使电场分布更加均匀,并降低栅边缘的电场强度。
Description
技术领域
本发明涉及半导体器件,具体是一种射频应用的LDMOS场效应晶体管及其制作方法。
背景技术
射频LDMOS(Laterally Double-Diffused Metal Oxide Semiconductors,横向双扩散晶体管)场效应晶体管是一种应用范围广的射频器件,具有线性度好、功率增益高、耐压高、匹配性能好、效率高和输出功率大等优点。广泛应用于无线通信、移动基站、卫星通信、雷达和导航等领域。
在大功率射频LDMOS器件应用中,一般希望器件具有大的击穿电压、大的输出功率和高的频率特性。在射频LDMOS设计过程中,这要求器件具有大的击穿电压、低的导通电阻和小的寄生参数。常规的射频LDMOS结构如图1所示。为了提高击穿电压,优化器件频率特性,增大输出功率,在漂移区上部采用法拉第罩是简单有效的方法。法拉第罩可以有效屏蔽寄生栅漏电容Cgd,从而有效提高器件的增益。传统的法拉第罩降低了寄生电容Cgd,同时由于接地的法拉第罩覆盖在漂移区上方增加了源漏电容Cds,Cds增加会降低器件的效率,影响了器件的频率特性,传统源场板优化电场的要求又使接地的法拉第罩不能做的太短,这就使源漏电容Cds进一步增加,使器件频率特性变差。
发明内容
鉴于以上所述现有技术的缺点,本发明的目的在于一种射频应用的LDMOS场效应晶体管及其制作方法,在不降低击穿电压且不增加栅漏电容Cgd的条件下降低源漏电容Cds。
本发明技术方案如下:
一种射频LDMOS晶体管,包含:在P+衬底上方的P型外延层、P+衬底下方的背面金属电极、P型外延层内部的P阱、P阱左侧的P+sinker区、P阱右侧的N-漂移区,P阱中N+区构成N+源极,N-漂移区中N+区构成N+漏极,所述P阱中N+源极右侧上方至N-漂移区左侧上方设有多晶硅栅极,多晶硅栅极下方设有栅氧化层,P+sinker和N+源极的上方设有源极金属,N+漏极的上方设有漏极金属,所述多晶硅栅极的上方右侧设有法拉第罩,所述法拉第罩包括阶梯状金属层和沿多晶硅栅极方向排布的多个块状金属层,所述法拉第罩与半导体表面之间设有二氧化硅介质层。
作为优选方式,所述块状金属层与阶梯状金属层是一次成型的整体。
作为优选方式,所述块状金属层沿多晶硅栅极方向等间距设置。等间距设置可以使沿多晶硅栅极方向的漂移区电场分布具有周期性。
作为优选方式,所述二氧化硅介质层厚度为如果二氧化硅介质层太厚频率特性会变差,击穿电压降低,如果二氧化硅介质层太薄击穿电压也会降低。
本发明还提供一种所述的射频LDMOS晶体管的制作方法,包括以下步骤:
a、在P+衬底上形成P型外延层;
b、在P型外延层中通过离子注入形成P+sinker区;
c、在半导体表面生长一层栅介质二氧化硅,并淀积多晶硅,刻蚀所述多晶硅为栅极形状从而形成多晶硅栅极;
d、采用离子注入及高温推结形成P阱,在所述P阱中通过离子注入形成N+源极,采用离子注入形成轻掺杂N-漂移区,在所述轻掺杂N-漂移区中通过离子注入形成N+漏极9;
e、在所述半导体表面淀积二氧化硅介质层;
f、在所述介质层上淀积金属层,通过刻蚀工艺形成位于多晶硅栅极上方右侧的阶梯型金属层以及N-漂移区上方的沿多晶硅栅极方向分布的块状金属层,构成法拉第罩;
g、淀积金属,刻蚀,形成源极金属和漏极金属。
本发明的有益效果为:本发明中的法拉第罩结构包括阶梯状金属层和多个块状金属层,与传统结构相比,该结构覆盖在漂移区上方的源场板面积更小,因此可以在不增加栅漏电容的前提下有效地减少器件的源漏电容,提高器件的频率特性,并且通过调节分布式金属场板中的块状金属的长度和之间的间距,可以有效调节下方漂移区电场,使电场分布更加均匀,并降低栅边缘的电场强度,从而可以提高击穿电压。本发明所采用的方法与传统结构器件制造方法相比,只需改变金属场板的刻蚀掩模版形状,不需要增加额外的工艺步骤。
附图说明
图1是现有技术中普通的射频LDMOS结构示意图;
图2是本发明的射频LDMOS晶体管结构示意图;
图3是在P+衬底上形成P型外延层的示意图;
图4是形成P+sinker区的示意图;
图5是形成多晶硅栅极的示意图;
图6是形成P阱和N型轻掺杂漂移区以及在P阱中形成N+源极,在N型轻掺杂区中形成N+漏极的示意图;
图7是淀积二氧化硅介质层的示意图;
图8是淀积金属层的示意图;
图9是刻蚀金属形成法拉第罩和金属电极之后的示意图。
图中1为P+衬底,2为P型外延层,3为栅氧化层,4为多晶硅栅极,5为P阱,6为N-漂移区,7为N+源极,8为P+sinker区,9为N+漏极,10为二氧化硅介质层,11为法拉第罩,12为源极金属,13为漏极金属,14为背面金属电极,20为未经刻蚀的二氧化硅介质层,21为未经刻蚀的法拉第罩金属层,110为阶梯状金属层,111为块状金属层。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
如图2和图9所示,一种射频LDMOS晶体管,包含:在P+衬底1上方的P型外延层2、P+衬底1下方的背面金属电极14、P型外延层2内部的P阱5、P阱左侧的P+sinker区8、P阱右侧的N-漂移区6,P阱中N+区构成N+源极7,N-漂移区中N+区构成N+漏极9,所述P阱中N+源极右侧上方至N-漂移区左侧上方设有多晶硅栅极4,多晶硅栅极下方设有栅氧化层3,P+sinker和N+源极的上方设有源极金属12,N+漏极的上方设有漏极金属13,所述多晶硅栅极4的上方右侧设有法拉第罩11,所述法拉第罩包括阶梯状金属层110和沿多晶硅栅极方向排布的多个块状金属层111,所述法拉第罩与半导体表面之间设有二氧化硅介质层10。
所述块状金属层111与阶梯状金属层110是一次成型的整体。
所述块状金属层沿多晶硅栅极方向等间距设置。等间距设置可以使沿多晶硅栅极方向的漂移区电场分布具有周期性。在其他实施例中也可以非等间距设置。
所述二氧化硅介质层厚度为如果二氧化硅介质层太厚频率特性会变差,击穿电压降低,如果二氧化硅介质层太薄击穿电压也会降低。
本实施例还提供一种所述的射频LDMOS晶体管的制作方法,包括以下步骤:
a、在P+衬底1上形成P型外延层2;如图3所示;
b、在P型外延层2中通过离子注入形成P+sinker区8;如图4所示;
c、在半导体表面生长一层栅介质二氧化硅,并淀积多晶硅,刻蚀所述多晶硅为栅极形状从而形成多晶硅栅极;如图5所示;
d、采用离子注入及高温推结形成P阱5,在所述P阱中通过离子注入形成N+源极7,采用离子注入形成轻掺杂N-漂移区6,在所述轻掺杂N-漂移区6中通过离子注入形成N+漏极9;如图6所示;
e、在所述半导体表面淀积未经刻蚀的二氧化硅介质层20;如图7所示;
f、在所述介质层上淀积未经刻蚀的法拉第罩金属层21,如图8所示;通过刻蚀工艺形成位于多晶硅栅极上方右侧的阶梯型金属层以及N-漂移区上方的沿多晶硅栅极方向分布的块状金属层,构成法拉第罩;
g、淀积金属,刻蚀,形成源极金属和漏极金属。如图9所示。
本发明能够有效改善改善N型轻掺杂漂移区的电场分布,从而可以在保持击穿电压和Cgd不变条件下降低寄生电容Cds,提高器件的频率特性。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。
Claims (5)
1.一种射频LDMOS晶体管,包含:在P+衬底(1)上方的P型外延层(2)、P+衬底(1)下方的背面金属电极(14)、P型外延层(2)内部的P阱(5)、P阱左侧的P+sinker区(8)、P阱右侧的N-漂移区(6),P阱中N+区构成N+源极(7),N-漂移区中N+区构成N+漏极(9),所述P阱中N+源极右侧上方至N-漂移区左侧上方设有多晶硅栅极(4),多晶硅栅极下方设有栅氧化层(3),P+sinker和N+源极的上方设有源极金属(12),N+漏极的上方设有漏极金属(13),其特征在于:所述多晶硅栅极(4)的上方右侧设有法拉第罩(11),所述法拉第罩包括阶梯状金属层(110)和沿多晶硅栅极方向排布的多个块状金属层(111),所述法拉第罩与半导体表面之间设有二氧化硅介质层(10)。
2.根据权利要求1所述的的射频LDMOS晶体管,其特征在于:所述块状金属层(111)与阶梯状金属层(110)是一次成型的整体。
3.根据权利要求1所述的的射频LDMOS晶体管,其特征在于:所述块状金属层沿多晶硅栅极方向等间距设置。
4.根据权利要求1所述的射频LDMOS晶体管,其特征在于:所述二氧化硅介质层厚度为
5.权利要求1至4任意一项所述的射频LDMOS晶体管的制作方法,其特征在于包括以下步骤:
a、在P+衬底(1)上形成P型外延层(2);
b、在P型外延层(2)中通过离子注入形成P+sinker区(8);
c、在半导体表面生长一层栅介质二氧化硅,并淀积多晶硅,刻蚀所述多晶硅为栅极形状从而形成多晶硅栅极;
d、采用离子注入及高温推结形成P阱,在所述P阱中通过离子注入形成N+源极(7),采用离子注入形成轻掺杂N-漂移区,在所述轻掺杂N-漂移区中通过离子注入形成N+漏极(9);
e、在所述半导体表面淀积二氧化硅介质层;
f、在所述介质层上淀积金属层,通过刻蚀工艺形成位于多晶硅栅极上方右侧的阶梯型金属层以及N-漂移区上方的沿多晶硅栅极方向分布的块状金属层,构成法拉第罩;
g、淀积金属,刻蚀,形成源极金属和漏极金属。
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