WO2021042771A1 - 场极板及横向扩散金属氧化物半导体器件 - Google Patents

场极板及横向扩散金属氧化物半导体器件 Download PDF

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WO2021042771A1
WO2021042771A1 PCT/CN2020/092257 CN2020092257W WO2021042771A1 WO 2021042771 A1 WO2021042771 A1 WO 2021042771A1 CN 2020092257 W CN2020092257 W CN 2020092257W WO 2021042771 A1 WO2021042771 A1 WO 2021042771A1
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field plate
hollow
cross
section
field
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PCT/CN2020/092257
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English (en)
French (fr)
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高桦
金华俊
陈淑娴
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无锡华润上华科技有限公司
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Publication of WO2021042771A1 publication Critical patent/WO2021042771A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • This application relates to the field of semiconductors, in particular to a field plate, and also to a laterally diffused metal oxide semiconductor device.
  • the drain terminal adopts a field plate structure to ensure the breakdown voltage and on-resistance of the device.
  • the field plate is in the active area between the drain and gate.
  • the upper part is flat as a whole, but the strongest impact ionization position of the device surface electric field is below the boundary of the polysilicon gate, which makes the device surface trap more charges, which leads to a small SOA interval of the device, relatively poor HCI characteristics, and a current path
  • the breakdown of the device in the on state is smaller. Therefore, on the basis of ensuring the breakdown voltage and on-resistance of the device, it is also necessary to improve the hot carrier injection (HCI) characteristics and the safe operating area (SOA interval) of the device to obtain the optimal characteristics of the device.
  • HCI hot carrier injection
  • SOA interval safe operating area
  • a new field plate and a laterally diffused metal oxide semiconductor device are provided.
  • a field plate includes a field plate part, the field plate is also formed with a hollow part, and the hollow part includes at least one hollow unit located between the field plate parts, and each hollow unit runs along the field The width direction of the plate is distributed, and the field plate is located above the drift zone.
  • a laterally diffused metal oxide semiconductor device including:
  • a substrate on which a source region, a drain region, a drift region, and a gate are formed;
  • a metal silicide barrier layer, the metal silicide barrier layer is located above part of the drift region and part of the gate;
  • the field plate is located above the metal silicide barrier layer.
  • Figure 1 is a top view of a conventional field plate corresponding device
  • Figure 2a is a top view of a device corresponding to the field plate in embodiment 1;
  • FIG. 2b is a top view of the corresponding device of the field plate in Embodiment 2;
  • FIG. 2c is a top view of the corresponding device of the field plate in Embodiment 3;
  • 2d is a top view of the corresponding device of the field plate in Embodiment 4.
  • 2f is a top view of the corresponding device of the field plate in Embodiment 6;
  • 2g is a top view of the corresponding device of the field plate in Embodiment 7;
  • 2h is a top view of the corresponding device of the field plate in Embodiment 8.
  • FIG 3 is a cross-sectional view of a laterally diffused metal oxide semiconductor device in an embodiment.
  • FIG. 1 it is a top view of the LDMOS device corresponding to the traditional field plate.
  • the device includes a field plate 102 that is tiled on a part of the gate 104 in the width direction, which is located on the side of the gate 104 and is horizontal to the edge of the gate.
  • the adjacent source region 106, the substrate 108, and the field plate 102 have a drain region 110 with a certain interval.
  • the traditional field plates are laid flat in the width direction to ensure the breakdown voltage and on-resistance of the device, but the SOA interval of the device is small, the HCI characteristic is relatively poor, and the current path makes the breakdown of the device in the on state more Small, the device does not get the optimal characteristics.
  • this application provides a new field plate.
  • a field plate which includes a field plate portion, and a hollow portion is formed on the field plate.
  • the hollow portion includes at least one hollow unit located between the field plate portions, each The hollow cells are distributed along the width direction of the field plate, and the field plate is located above the drift zone.
  • the field plate part includes one of a polysilicon field plate, a metal field plate, and an electrode field plate.
  • Electrodes For high-end and large-sized devices that use electrode field plates, they cannot be the same as the deposited metal field plates.
  • the thickness of the medium under the field plates may be the same, which may cause the device characteristics to change, which may lead to device failure or deterioration.
  • Slots or engraved holes are used to form hollow cells of different shapes on the field plate, exposing the dielectric layer under the field plate to achieve process stability.
  • the field plate portion includes a high-resistivity resistive field plate.
  • the cross section of each hollow unit formed on the field plate is polygonal, and the cross section of each hollow unit is the same or different in size.
  • the hollow part at least includes a hollow unit whose cross section is one of a hexagon, a pentagon, a quadrilateral, a circle, and an ellipse.
  • the cross-section of each hollow unit of the field plate can be designed in different shapes according to actual requirements, as long as the electric field can be uniformly distributed.
  • the hollow cells are evenly distributed in the width direction of the field plate, and the cross section of the field plate is greater than or equal to one edge with the hollow cells.
  • the cross section of the field plate portion 202 is comb-shaped, and the comb-tooth shape has strengthening teeth 201 along the width direction of the field plate and along the length of the field plate.
  • the comb teeth 203 in the direction, the hollow units 205 are located between the comb teeth 203, the cross section of each hollow unit 205 is a long strip structure with different widths, and the distance between adjacent hollow units 205 is the same.
  • the distribution of hollow elements 205 of different sizes on the field plate can be designed according to actual requirements.
  • the width of the strengthening teeth 201 along the length direction of the field plate decreases as the length of the hollow element 205 increases.
  • the cross section of each hollow unit is a long strip with the same width, and the distance between adjacent hollow units is the same or different.
  • the cross section of each hollow unit can be selected in different shapes as required, as long as the electric field can be uniformly distributed.
  • the cross section of the field plate has two, three, or four edges with hollow cells, and the hollow cells are randomly distributed in the width direction of the field plate, as long as the electric field can be uniformly distributed.
  • the hollow unit penetrates two opposite edges of the cross section of the field plate in the length direction, and the cross section of the hollow unit is rectangular.
  • the field plate includes a field plate portion 302 and a hollow unit 303 formed on the field plate.
  • the hollow unit 303 penetrates two opposite edges of the cross section of the field plate.
  • the cross section of the plate portion 302 is a rectangular structure, and the hollow units 303 are evenly distributed in the width direction of the field plate.
  • the cross-sections of the hollow cells are the same or different, and the cross section of the field plate has one, three, or four edges with hollow cells, and the hollow cells are randomly distributed in the width direction of the field plate, as long as It is sufficient that the electric field can be uniformly distributed.
  • the field plate includes a field plate portion 402 and a hollow unit 403 formed on the field plate.
  • the cross section of the hollow unit 403 is rectangular, and each hollow unit 403 is located on the field plate. Evenly distributed in the width direction, the cross-sectional size of each hollow unit 403 is different. In other embodiments, the cross-sectional size of each hollow unit 403 is the same. In the actual product design process, due to the size of the field plate or the position distribution of the hollow unit on the field plate, the edge position of the cross section of the field plate is the hollow unit.
  • the field plate includes a field plate portion 502 and a hollow unit 503 formed on the field plate.
  • the cross section of the hollow unit 503 is square, and the cross section of the field plate has a There are hollow cells 503 at the edge, and the hollow cells 503 are distributed stepwise in the field plate, and are regularly distributed in the width direction of the field plate.
  • the cross-sections of the hollow units are the same or different, and the cross-section of the field plate has two, three, or four edges with hollow units.
  • the hollow cells are randomly distributed in the width direction of the field plate, as long as the electric field can be uniformly distributed.
  • the field plate includes a field plate portion 602 and a hollow unit 603 formed on the field plate.
  • the hollow unit 603 is located at two opposite edges of the cross section of the field plate.
  • the cross section of the unit 603 is square, and the hollow units 603 are evenly distributed in the width direction of the field plate.
  • the cross-sections of the hollow cells are the same or different, and the cross section of the field plate has one, three, or four edges with hollow cells.
  • the hollow cells are randomly distributed in the width direction of the field plate, as long as the electric field can be uniformly distributed.
  • the field plate includes a field plate portion 702 and a hollow unit 703 formed on the field plate, and the hollow unit 703 is located at two opposite edges of the cross section of the field plate.
  • the cross section of the hollow unit 703 is a pentagon, and the hollow units 703 are regularly distributed in the width direction of the field plate.
  • the cross-sectional size of each hollow unit is the same or different.
  • the hollow cells are randomly distributed in the width direction of the field plate, and the cross section of the field plate has one, two, three, or four edges with hollow cells as long as the electric field can be uniformly distributed.
  • the field plate includes a field plate portion 802 and a hollow unit 803 formed on the field plate.
  • the hollow unit 803 is located at two opposite edges of the cross section of the field plate.
  • the cross section of the unit 803 is hexagonal, and the hollow units 803 are regularly distributed in the width direction of the field plate.
  • the cross-sectional size of each hollow unit is the same or different.
  • the hollow cells are randomly distributed in the width direction of the field plate, as long as the electric field can be uniformly distributed.
  • the hollow cells are evenly distributed in the width direction of the field plate, and the hollow cells do not exist on the edge of the cross section of the field plate.
  • the field plate includes a field plate portion 902 and a hollow unit 903 formed on the field plate.
  • the cross section of the hollow unit 903 is circular, and the cross section edge of the field plate There are no hollowed-out units 903, and the hollowed-out units 903 are regularly distributed in the width direction of the field plate.
  • the cross-sectional size of each hollow unit is the same or different.
  • the distribution of the hollow cells on the field plate is such that the number of the hollow cells decreases along the length direction of the field plate. For example, there are fewer hollow cells near the source region, and more hollow cells far away from the source region; or there are more hollow cells near the source region and fewer hollow cells far away from the source region.
  • the distribution of the hollow cells on the field plate is at least one of a honeycomb shape and a stepped shape.
  • the distribution of the hollow cells in the width direction of the field plate can be designed according to actual requirements, as long as the electric field can be uniformly distributed.
  • the above-mentioned field plate includes a field plate part, the field plate is further formed with a hollow part, and the hollow part includes at least one hollow unit located between the field plate parts, and each hollow unit extends along the width direction of the field plate
  • the field plate is located above the drift zone, and the ON state breakdown voltage of the field plate without the field plate is higher than that with the field plate.
  • the hollow cells distributed along the width direction of the field plate make the field in the field plate
  • the withstand voltage of the device does not increase the process cost or process steps, and the surface electric field in the width and direction of the field plate is better optimized, so as to optimize the on-state characteristics (on-state characteristics) of the device while keeping the device off.
  • the effect of the off-state characteristic (off-state characteristic) improves the HCI characteristic of the device and increases the SOA interval of the interval.
  • a laterally diffused metal oxide semiconductor device including:
  • the substrate 302 has a source region 304, a drain region 306, a drift region 308, and a gate 309 formed on the substrate 302.
  • the metal silicide barrier layer 310 is located above a part of the drift region 308 and a part of the gate 309.
  • the field plate 312, which is located above the metal silicide barrier layer 310, is the field plate described in any of the above embodiments.
  • the laterally diffused metal oxide semiconductor device further includes an oxide layer structure 314 partially located under the field plate 312.
  • the laterally diffused metal oxide semiconductor device further includes a contact hole, a through hole, a metal plug, and a metal interconnection layer.
  • the laterally diffused metal oxide semiconductor device further includes a body region 316 provided in the substrate 302.
  • the body region 316 is located outside the drift region 308 and is spaced apart from the drift region.
  • the body region and the drift region have opposite conductivity types.
  • the laterally diffused metal oxide semiconductor device includes a field plate composed of a field plate part and a hollow part formed on the field plate, and the hollow part includes at least A hollow cell located between the field plate portions.
  • the device includes a field plate located above a portion of the gate 204, a source region 206 on the side of the gate 204 and horizontally adjacent to the edge of the gate, a substrate 208, and
  • the field plate has drain regions 210 spaced apart in the width direction.
  • the shape of the cross section of each hollow unit formed on the field plate and the distribution of each hollow unit in the width direction of the field plate can be determined according to actual needs, design rules of the process, and changes in device characteristics. As long as the electric field can be uniformly distributed.
  • the field plate in the above-mentioned laterally diffused metal oxide semiconductor device includes a field plate part and a hollow part formed on the field plate, and the hollow part includes at least one part located between the field plate parts and along the width direction of the field plate. Distributed hollow cells, the field plate is located above the drift zone.
  • the potential lines on the surface of the device are evenly distributed through the hollow cells distributed along the width of the field plate, which better optimizes the width direction and the silicon lining
  • the distribution of potential lines at the end faces of the two ends of the bottom intersection; the field plate width and direction are better optimized without losing the on-resistance of the device, ensuring the withstand voltage of the device, and without increasing the process cost or process steps.
  • the surface electric field on the upper surface achieves the effect of optimizing the on-state characteristics (on-state characteristics) of the device and maintaining the off-state characteristics (off-state characteristics), improving the HCI characteristics of the device and increasing the SOA interval of the interval.

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Abstract

本申请涉及一种场极板及一种横向扩散金属氧化物半导体器件。场极板包括场极板部分(202)，场极板上还形成有镂空部分，镂空部分包括大于等于一个位于场极板部分(202)之间并沿场极板的宽度方向分布的镂空单元(205)，场极板位于漂移区的上方。

Description

场极板及横向扩散金属氧化物半导体器件
相关申请的交叉引用
本申请要求于2019年09月02日提交中国专利局、申请号为2019108225650、发明名称为“场极板及横向扩散金属氧化物半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体领域，特别是涉及一种场极板，还涉及一种横向扩散金属氧化物半导体器件。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
对于横向扩散金属氧化物半导体(LDMOS)器件，漏端采用场极板结构等来保证器件的击穿电压和导通电阻，如图1所示，场极板在漏栅之间的有源区上方整体平铺，但这样器件表面电场的碰撞电离最强的位置在多晶硅栅极边界下方，使得器件表面捕获更多的电荷从而导致器件SOA区间小、HCI特性相对较差，并且电流的路径使得器件在on态下的击穿更小。所以，在保证器件击穿电压和导通电阻的基础上，还需要提高器件的热载流子注入(HCI)特性和安全工作区区间(SOA区间)，以使器件得到最优的特性。
发明内容
根据本申请的各种实施例，提供一种新的场极板及一种横向扩散金属氧化物半导体器件。
一种场极板,包括场极板部分,所述场极板上还形成有镂空部分，所述镂空部分包括大于等于一个位于场极板部分之间的镂空单元，各所述镂空单元沿场极板的宽度方向分布，以及所述场极板位于漂移区的上方。
一种横向扩散金属氧化物半导体器件，包括：
衬底，所述衬底上形成有源极区、漏极区、漂移区、栅极；
金属硅化物阻挡层，所述金属硅化物阻挡层位于部分漂移区和部分栅极的上方；以及
上述场极板，所述场极板位于金属硅化物阻挡层上方。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为传统的场极板对应器件的俯视图；
图2a为实施例1中场极板对应器件的俯视图；
图2b为实施例2中场极板对应器件的俯视图；
图2c为实施例3中场极板对应器件的俯视图；
图2d为实施例4中场极板对应器件的俯视图；
图2e为实施例5中场极板对应器件的俯视图；
图2f为实施例6中场极板对应器件的俯视图；
图2g为实施例7中场极板对应器件的俯视图；
图2h为实施例8中场极板对应器件的俯视图；
图3为一实施例中横向扩散金属氧化物半导体器件的剖面图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
如图1所示，为传统场极板对应的LDMOS器件的俯视图，器件包括宽度方向上平铺在部分栅极104上方的场极板102，位于栅极104一侧且与栅极边缘水平相邻的源极区106，衬底108，与场极板102具有一定间隔的漏极区110。
传统场极板在宽度方向上平铺，保证了器件的击穿电压和导通电阻，但是器件的SOA区间小、HCI特性相对较差，并且电流的路径使得器件在on态下的击穿更小，器件得不到最优的特性。
针对上述问题，本申请提供了一种新的场极板。
在其中一个实施例中，提供一种场极板,包括场极板部分,场极板上还形成有镂空部分，所述镂空部分包括大于等于一个位于场极板部分之间的镂空单元，各镂空单元沿所述场极板的宽度方向分布，以及所述场极板位于漂移区 的上方。
在其中一个实施例中，场极板部分包括多晶硅场极板、金属场极板、电极场板中的一种。
对于低档位小尺寸的器件，在工艺上很难做出窄条状的场极板，但采用分段(如图2e)的场极板结构，就能保证工艺的稳定性和可实施性。
对于高档位大尺寸并采用电极场板的器件，不能如同淀积金属场板一样，场板下方的介质厚度一样，可能导致器件特性发生变化，进而导致器件失效或者变差等，故可以通过挖槽或刻孔的方式在场极板上形成不同形状的镂空单元，露出场极板下方的介质层，来实现工艺上的稳定性。
在其中一个实施例中，场极板部分包括高电阻率阻性场极板。
在其中一个实施例中，场极板上形成的各镂空单元的横截面为多边形，各镂空单元的横截面大小相同或不同。
在其中一个实施例中，镂空部分至少包括横截面为六边形、五边形、四边形、圆形、椭圆形中的一种的镂空单元。在其他实施例中，可以根据实际需求将场极板各镂空单元的横截面设计为不同的形状，只要能实现电场的均匀分布即可。
在其中一个实施例中，各镂空单元在场极板的宽度方向上均匀分布，所述场极板的横截面大于等于一个边缘存在所述镂空单元。
如图2a所示，在其中一个实施例中，场极板部分202的横截面为梳齿状，所述梳齿状具有沿场极板宽度方向的强化齿201和沿所述场极板长度方向的梳齿203，所述各镂空单元205位于梳齿203之间，各镂空单元205的横截面为宽度具有差异的长条状结构且相邻镂空单元205之间的间距相同，在其他实施例中，可以根据实际需求设计不同尺寸的镂空单元205在场极板上的 分布，此时强化齿201沿场极板长度方向的宽度随镂空单元205的长度增加而减小。
在其中一个实施例中，各镂空单元的横截面为宽度相同的长条状，相邻镂空单元之间的间距相同或不同。在其他实施例中，可以各镂空单元的横截面根据需要选取不同的形状，只要能实现电场的均匀分布即可。在其他实施例中，场极板的横截面有二个、三个或四个边缘存在镂空单元，各镂空单元在场极板的宽度方向上随机分布，只要能实现电场的均匀分布即可。
在其中一个实施例中，镂空单元在长度方向上贯穿场极板横截面的两个相对边缘，所述镂空单元的横截面为长方形。
如图2b所示，在其中一个实施例中，场极板包括场极板部分302和场极板上形成的镂空单元303，镂空单元303贯穿场极板横截面的两个相对边缘，场极板部分302的横截面为的长方形结构，各镂空单元303在场极板的宽度方向上均匀分布。在其他实施例中，各镂空单元的横截面大小相同或不同，场极板的横截面有一个、三个或四个边缘存在镂空单元，各镂空单元在场极板的宽度方向上随机分布，只要能实现电场的均匀分布即可。
如图2c所示，在其中一个实施例中，场极板包括场极板部分402和场极板上形成的镂空单元403，镂空单元403的横截面为长方形，各镂空单元403在场极板的宽度方向上均匀分布，各镂空单元403的横截面大小不同。在其它实施例中，各镂空单元403的横截面大小相同。在实际产品设计过程中，因场极板的尺寸或镂空单元在场极板上的位置分布，场极板横截面的边缘位置部分为镂空单元。
如图2d所示，在其中一个实施例中，场极板包括场极板部分502和场极板上形成的镂空单元503，镂空单元503的横截面为正方形，场极板的横截 面有一个边缘存在镂空单元503，各镂空单元503在场极板内呈阶梯状分布，且在场极板的宽度方向上规律分布。在其他实施例中，各镂空单元的横截面大小相同或不同，场极板的横截面有两个、三个或四个边缘存在镂空单元。在其他实施例中，各镂空单元在所述场极板的宽度方向上随机分布，只要能实现电场的均匀分布即可。
如图2e所示，在其中一个实施例中，场极板包括场极板部分602和场极板上形成的镂空单元603，镂空单元603部分位于场极板横截面的相对两个边缘，镂空单元603的横截面为正方形，所述各镂空单元603在场极板的宽度方向上均匀分布。在其他实施例中，各镂空单元的横截面大小相同或不同，场极板的横截面有一个、三个或四个边缘存在镂空单元。在其他实施例中，镂空单元在场极板的宽度方向上随机分布，只要能实现电场的均匀分布即可。
如图2f所示，在其中一个实施例中，场极板包括场极板部分702和场极板上形成的镂空单元703，镂空单元703部分位于所述场极板横截面的相对两个边缘，镂空单元703的横截面为五边形，各镂空单元703在场极板的宽度方向上规律分布。在其他实施例中，各镂空单元的横截面大小相同或不同。在其他实施例中，镂空单元在场极板的宽度方向上随机分布，场极板的横截面有一个、两个、三个或四个边缘存在镂空单元只要能实现电场的均匀分布即可。
如图2g所示，在其中一个实施例中，场极板包括场极板部分802和场极板上形成的镂空单元803，镂空单元803部分位于场极板横截面的相对两个边缘，镂空单元803的横截面为六边形，所述各镂空单元803在场极板的宽度方向上规律分布。在其他实施例中，各镂空单元的横截面大小相同或不同。在其他实施例中，镂空单元在场极板的宽度方向上随机分布，只要能实现电 场的均匀分布即可。
在其中一个实施例中，各镂空单元在场极板的宽度方向上均匀分布，所述场极板的横截面边缘不存在所述镂空单元。
如图2h所示，在其中一个实施例中，场极板包括场极板部分902和场极板上形成的镂空单元903，镂空单元903的横截面为圆形，场极板的横截面边缘不存在镂空单元903，所述各镂空单元903在场极板的宽度方向上规律分布。在其他实施例中，各镂空单元的横截面大小相同或不同。
在其中一个实施例中，镂空单元在场极板上的分布为所述镂空单元的数量沿所述场极板的长度方向减少。例如接近源极区位置镂空单元少，远离源极区位置镂空单元多；或接近源极区位置镂空单元多，远离源极区位置镂空单元少。
在其中一个实施例中，各镂空单元在场极板上的分布至少为蜂窝状、阶梯状中的一种。在其他实施例中，可以根据实际需求设计各镂空单元在场极板宽度方向上的分布，只要能实现电场的均匀分布即可。
上述场极板包括场极板部分，所述场极板上还形成有镂空部分，所述镂空部包括至少一个位于场极板部分之间的镂空单元，各镂空单元沿场极板的宽度方向分布，所述场极板位于漂移区的上方，不加场极板比添加场极板的ON态击穿电压高，通过沿场极板宽度方向分布的各镂空单元使得场极板中的场极板部分之间穿插有镂空部分，使得器件表面的电势线均匀分布，更好的优化了宽度方向和硅衬底相交两端端面处电势线的分布；在不损失器件的导通电阻，保证器件的耐压情况，也不增加工艺成本或工艺步骤的前提下，更好的优化了场极板宽度分方向上的表面电场，达到优化器件开态特性(on态特性)的同时保持器件关态特性(off态特性)的效果，改善了器件的HCI 特性，增大了区间的SOA区间。
如图3所示，在其中一个实施例中，提供一种横向扩散金属氧化物半导体器件，包括：
衬底302，衬底302上形成有源极区304、漏极区306、漂移区308、栅极309。
金属硅化物阻挡层310，所述金属硅化物阻挡层310位于部分漂移区308和部分栅极309的上方。
场极板312，所述场极板312位于金属硅化物阻挡层310上方，为上述任一实施例所述的场极板。
如图3所示，在其中一个实施例中，横向扩散金属氧化物半导体器件还包括部分位于场极板312下方的氧化层结构314。
在其中一个实施例中，横向扩散金属氧化物半导体器件还包括接触孔、通孔、金属塞、金属互连层。
如图3所示，在其中一个实施例中，横向扩散金属氧化物半导体器件还包括在衬底302中设置的体区316，体区316位于漂移区308的外侧，并与漂移区间隔，其中，体区和漂移区具有相反的导电类型。
如图2a-图2h所示，在其中一实施例中，所述横向扩散金属氧化物半导体器件包括由场极板部分和场极板上形成的镂空部分组成的场极板，镂空部分包括至少一个位于场极板部分之间的镂空单元，器件包括位于部分栅极204上方的场极板，位于栅极204一侧且与栅极边缘水平相邻的源极区206，衬底208，与场极板在宽度方向具有一定间隔的漏极区210。在其它实施例中，可以根据实际需要、工艺的设计规则和器件特性的变化量来确定设置场极板上形成的各镂空单元的横截面的形状及各镂空单元在场极板宽度方向的分 布，只要能实现电场的均匀分布即可。
上述横向扩散金属氧化物半导体器件中的场极板包括场极板部分和场极板上形成的镂空部分，所述镂空部分包括至少一个位于场极板部分之间并沿场极板的宽度方向分布的镂空单元，所述场极板位于漂移区的上方。由于不加场极板比添加场极板的ON态击穿电压高，通过沿场极板宽度方向分布的各镂空单元使得器件表面的电势线均匀分布，更好的优化了宽度方向和硅衬底相交两端端面处电势线的分布；在不损失器件的导通电阻，保证器件的耐压情况，也不增加工艺成本或工艺步骤的前提下，更好的优化了场极板宽度分方向上的表面电场，达到优化器件开态特性(on态特性)并保持关态特性(off态特性)的效果，改善了器件的HCI特性，增大了区间的SOA区间。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种场极板,包括场极板部分,所述场极板上还形成有镂空部分，所述镂空部分包括大于等于一个位于所述场极板部分之间的镂空单元，各所述镂空单元沿所述场极板的宽度方向分布，以及所述场极板位于漂移区的上方。
  2. 根据权利要求1所述的场极板，其中所述场极板部分包括多晶硅场极板、金属场极板、电极场板中的一种。
  3. 根据权利要求1所述的场极板，其中所述场极板部分包括高电阻率阻性场极板。
  4. 根据权利要求1所述的场极板，其中各所述镂空单元的横截面为多边形。
  5. 根据权利要求1所述的场极板，其中所述镂空部分至少包括横截面为六边形、五边形、四边形、圆形、椭圆形中的一种的镂空单元。
  6. 根据权利要求1所述的场极板，其中各所述镂空单元在所述场极板的宽度方向上均匀分布，所述场极板的横截面大于等于一个边缘存在所述镂空单元。
  7. 根据权利要求1所述的场极板，其中各镂空单元的横截面为宽度相同的长条状，相邻镂空单元之间的间距相同或不同。
  8. 根据权利要求1所述的场极板，其中各所述镂空单元在所述场极板的宽度方向上均匀分布，所述场极板的横截面边缘不存在所述镂空单元。
  9. 根据权利要求1所述的场极板，其中所述镂空单元在所述场极板上的分布为所述镂空单元的数量沿所述场极板的长度方向减少。
  10. 根据权利要求1所述的场极板，其中所述场极板部分的横截面为梳齿状，所述梳齿状具有沿所述场极板宽度方向的强化齿和沿所述场极板长度 方向的梳齿，各所述镂空单元位于所述梳齿之间。
  11. 根据权利要求10所述的场极板，其中各镂空单元的横截面为宽度具有差异的长条状结构，且相邻镂空单元之间的间距相同。
  12. 根据权利要求1所述的场极板，其中所述镂空单元在长度方向上贯穿所述场极板横截面的两个相对边缘，所述镂空单元的横截面为长方形。
  13. 根据权利要求1所述的场极板，其中各所述镂空单元在所述场极板上的分布至少包括蜂窝状、阶梯状中的一种。
  14. 一种横向扩散金属氧化物半导体器件，包括：
    衬底，所述衬底上形成有源极区、漏极区、漂移区、栅极；
    金属硅化物阻挡层，所述金属硅化物阻挡层位于部分所述漂移区和部分所述栅极的上方；以及
    场极板，所述场极板位于所述金属硅化物阻挡层上方，为权利要求1-13任一项所述的场极板。
  15. 根据权利要求14所述的器件，其中所述器件还包括部分位于所述场极板下方的氧化层结构。
PCT/CN2020/092257 2019-09-02 2020-05-26 场极板及横向扩散金属氧化物半导体器件 WO2021042771A1 (zh)

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