JP2019517148A - 最適化層を有する炭化ケイ素金属−酸化物−半導体(mos)デバイスにおける電界シールディング - Google Patents
最適化層を有する炭化ケイ素金属−酸化物−半導体(mos)デバイスにおける電界シールディング Download PDFInfo
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- JP2019517148A JP2019517148A JP2018561261A JP2018561261A JP2019517148A JP 2019517148 A JP2019517148 A JP 2019517148A JP 2018561261 A JP2018561261 A JP 2018561261A JP 2018561261 A JP2018561261 A JP 2018561261A JP 2019517148 A JP2019517148 A JP 2019517148A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 230000005684 electric field Effects 0.000 title abstract description 33
- 229910010271 silicon carbide Inorganic materials 0.000 title description 37
- 229910044991 metal oxide Inorganic materials 0.000 title 1
- -1 silicon carbide metal oxide Chemical class 0.000 title 1
- 238000005457 optimization Methods 0.000 claims abstract description 96
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 38
- 239000002019 doping agent Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 17
- 230000000873 masking effect Effects 0.000 claims description 12
- 230000005669 field effect Effects 0.000 claims description 5
- 230000001788 irregular Effects 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 230000007774 longterm Effects 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 description 28
- 238000013461 design Methods 0.000 description 20
- 230000008569 process Effects 0.000 description 8
- 239000000758 substrate Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000001413 cellular effect Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 210000000746 body region Anatomy 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000002547 anomalous effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
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Abstract
Description
4 第1の表面
6 第2の表面
10 MOSFETデバイス
12 ドレインコンタクト
14 基板層
16 ドリフト領域
18 ウェル領域
20 ソース領域
22 ソースコンタクト
24 誘電体層
26 ゲート電極
28 チャネル領域
29 JFET領域
30 コンタクト抵抗(Rs)
32 チャネル抵抗(Rch)
34 抵抗Racc
36 JFET抵抗(RJFET)
38 ドリフト抵抗(Rdrift)
39 ボディ領域
40 基板抵抗(Rsub)
41 ストリップデバイス
42 ソースコンタクト領域
43 チャネル長(Lch)
44 ボディコンタクト領域
45 チャネル領域からオーミック領域までの長さ(Lch_to_ohm)
47 オーミック領域の幅(Wohm)
49 JFET領域の幅(WJFET)
50 正方形デバイスセル
51 整列したレイアウト
54 六角形デバイスセル
55 整列したレイアウト
60 距離、幅
65 中心
66 斜めの矢印
68 辺
69 角
3000 半導体デバイス(MOSFET)
3002 最適化層
3003 表面
3004 深さ
3005 第1の深さ
3006 ウェル領域の深さ
3007 底部
3010 デバイスレイアウト
3014 SROL
3016 幅
3018 斜めの矢印
3020 グラフ
3022 第1の曲線
3024 第2の曲線
3030 グラフ
3032 第1の曲線
3034 第2の曲線
3040 グラフ
3042 曲線
3044 曲線
3046 グラフ
3047 直線
3048 曲線
3050 デバイスレイアウト
3052 隣接するデバイスセル
3060 デバイスレイアウト
3062 隣接するデバイスセル
3080 デバイスレイアウト
3082 隣接するデバイスセル
3100 デバイスレイアウト
3102 隣接するデバイスセル
3120 デバイスレイアウト
3122 隣接するデバイスセル
3140 デバイスレイアウト
3142 隣接するデバイスセル
3160 デバイスレイアウト
3162 隣接するデバイスセル
Claims (24)
- 第1の導電型を有する半導体デバイス層(2)内に少なくとも部分的に配置された複数のデバイスセル(50、54)であって、前記複数のうちの各デバイスセルが、
第1の導電型を有するドリフト層(16)と、
前記半導体デバイス層の表面から前記ドリフト層まで拡がりかつ前記第1の導電型を有する最適化層(3002)であり、前記最適化層が前記ドリフト層の平均ドーピング濃度よりも大きな平均ドーピング濃度を有する、最適化層と、
前記最適化層内に少なくとも部分的に配置された前記第1の導電型を有するソース領域(20)と、
前記ソース領域に隣接して前記最適化層内に少なくとも部分的に配置された第2の導電型を有するチャネル領域(28)と、
前記複数のデバイスセルの前記チャネル領域同士に間の前記最適化層内に配置され、前記第1の導電型で第2のドーピング濃度を有するJFET領域(29)であり、前記JFET領域が前記デバイスセルのウェル領域(18)と隣り合うデバイスセル(50、54)のウェル領域の平行部分との間に平行JFET幅(49)を有する、JFET領域と、
を備える、複数のデバイスセルと、
前記第1の導電型で前記第1のドーピング濃度を有する前記最適化層内に配置された複数のシールディング領域(SROL)(3014)であって、前記複数のSROLが前記複数のデバイスセルの隣り合うデバイスセルの前記チャネル領域同士の間の前記JFET領域の一部分内に少なくとも部分的に配置される、前記最適化層内に配置された複数のシールディング領域と
を具備する、デバイス(10)。 - 前記最適化層の前記平均ドーピング濃度が、前記ドリフト層の前記平均ドーピング濃度よりも2倍と15倍との間で大きい、請求項1記載のデバイス。
- 前記複数のSROLの各々が、前記ドリフト層のドーピング濃度と実質的に同じであるドーパント濃度を有する、請求項1記載のデバイス。
- 前記最適化層が、前記半導体デバイス層の表面(4)のところの第1のドーパント濃度から前記半導体デバイス層の前記表面から第1の深さのところの第2の濃度までの間でドーピング濃度が増加するレトログレードドーピングプロファイルを有し、かつ前記第1の深さと前記半導体層の前記ドリフト領域との間で前記第2の濃度を維持し、前記第2のドーパント濃度が、前記第1のドーパント濃度よりも4倍と10倍との間で大きい、請求項1記載のデバイス。
- 前記第1の深さが0.15μmと0.3μmとの間であり、前記第2のドーパント濃度が5x1015cm−3と5x1016cm−3との間であり、第3のドーパント濃度が5x1016cm−3と1x1017cm−3との間である、請求項4記載のデバイス。
- 前記第2のドーパント濃度が、前記チャネル領域の平均ドーパント濃度の20%未満である、請求項4記載のデバイス。
- 前記半導体層が、炭化ケイ素(SiC)半導体デバイス層である、請求項1記載のデバイス。
- 前記複数のSROLの各々が、前記複数のデバイスセルのうちの少なくとも1個のデバイスセルの前記ウェル領域の一部分と重なる、請求項1記載のデバイス。
- 前記複数のSROLの各々が、前記複数のデバイスセルのうちの少なくとも2個のデバイスセルの前記ウェル領域の一部分と重なる、請求項8記載のデバイス。
- 前記複数のSROLの各々が、前記複数のデバイスセルのうちの少なくとも3個のデバイスセルの前記ウェル領域の一部分と重なる、請求項9記載のデバイス。
- 前記複数のSROLが、前記複数のデバイスセルの前記ソース領域の一部分とさらに重なる、請求項8記載のデバイス。
- 前記複数のSROLが、前記複数のデバイスセルの前記ウェル領域とは重ならない、請求項1記載のデバイス。
- 前記複数のSROLが、前記複数のデバイスセルの各々の面積のほぼ1%とほぼ30%との間を占有する、請求項1記載のデバイス。
- 前記複数のSROLが、前記複数のデバイスセルの各々の前記面積のほぼ5%とほぼ20%との間を占有する、請求項13記載のデバイス。
- 前記複数のSROLが、前記複数のデバイスセルの各々の前記面積のほぼ7%とほぼ15%との間を占有する、請求項14記載のデバイス。
- 前記複数のSROLの各々が、ほぼ0.5μmとほぼ5μmとの間であるそれぞれの幅を有する、請求項1記載のデバイス。
- 前記それぞれの幅が、ほぼ1μmとほぼ3μmとの間である、請求項16記載のデバイス。
- 前記複数のSROLが、実質的に三角形、円形、卵形、六角形、長方形、または不規則な形状を有する、請求項1記載のデバイス。
- 前記デバイスが、金属−酸化物−半導体電界トランジスタ(MOSFET)、絶縁ゲートバイポーラトランジスタ(IGBT)、または絶縁ベースMOS制御サイリスタ(IBMCT)である、請求項1記載のデバイス。
- 半導体層(2)の表面(4)の一部分をマスキングするステップであって、前記半導体層が第1の導電型の初期ドーピング濃度を有する、マスキングするステップと、
最適化層(3002)を形成するために前記第1の導電型のドーパントを用いて前記半導体層をドーピングするステップであって、前記最適化層が前記半導体層の前記表面の中へと第1の深さ拡がり、前記初期ドーピング濃度よりも大きなピークドーピング濃度を有し、前記初期ドーピング濃度を有する前記最適化層内の複数のシールディング領域(SROL)(3014)を含む、ドーピングするステップと、
前記最適化層内に複数のデバイスセル(50、54)のウェル領域(18)およびソース領域(20)を注入するステップであって、前記ウェル領域が前記半導体層の前記表面の中へと前記第1の深さよりも小さい第2の深さ拡がり、前記ウェル領域が前記複数のデバイスセルのチャネル領域を画定し、前記複数のSROLが、前記複数のデバイスセルの隣り合うデバイスセルの前記チャネル領域の一部分同士の間に配置される、注入するステップと
を含む、製造方法。 - 前記最適化領域の前記ピークドーピング濃度が、注入後の前記ウェル領域内のドーピング濃度の少なくとも20%小さい、請求項20記載の方法。
- 前記最適化層を形成するために前記半導体層をドーピングするステップが、ドーピングするステップの前に前記半導体層の一部分をマスキングするステップであって、前記半導体層の前記マスキングした部分が前記最適化層を形成した後には前記複数のSROLを形成する、マスキングするステップを含む、請求項20記載の方法。
- マスキングするサブステップが、パターニングしたフォトレジスト層を使用してマスキングすることを含み、ドーピングするステップが、500℃未満の温度で前記ドーパントを用いて前記半導体層に注入することを含む、請求項22記載の方法。
- マスキングするステップが、ハードマスク材料を使用して前記半導体層の前記一部分をマスキングするステップであって、前記ハードマスク材料が、酸化ケイ素(SiO2)、窒化ケイ素(SiNx)、金属、またはこれらの組み合せからなる、前記半導体層の前記一部分をマスキングするステップを含む、請求項22記載の方法。
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