JP2019517149A - チャネル領域拡張部を用いた炭化ケイ素金属酸化物半導体(mos)デバイスセルにおける電界シールド - Google Patents
チャネル領域拡張部を用いた炭化ケイ素金属酸化物半導体(mos)デバイスセルにおける電界シールド Download PDFInfo
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- JP2019517149A JP2019517149A JP2018561262A JP2018561262A JP2019517149A JP 2019517149 A JP2019517149 A JP 2019517149A JP 2018561262 A JP2018561262 A JP 2018561262A JP 2018561262 A JP2018561262 A JP 2018561262A JP 2019517149 A JP2019517149 A JP 2019517149A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 230000005684 electric field Effects 0.000 title abstract description 37
- 229910010271 silicon carbide Inorganic materials 0.000 title description 87
- 229910044991 metal oxide Inorganic materials 0.000 title description 2
- -1 silicon carbide metal oxide Chemical class 0.000 title 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 87
- 238000000034 method Methods 0.000 claims description 55
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 210000000746 body region Anatomy 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 5
- 230000007774 longterm Effects 0.000 abstract description 6
- 238000013461 design Methods 0.000 description 24
- 230000001413 cellular effect Effects 0.000 description 16
- 239000000758 substrate Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Abstract
Description
4 第1の表面
6 第2の表面
10 半導体デバイス
12 ドレインコンタクト
14 基板層
16 ドリフト層
18 ウェル領域
20 ソース領域
22 ソースコンタクト
24 誘電体層
26 ゲート電極
28 チャネル領域
29 JFET領域
30 コンタクト抵抗
38 ドリフト抵抗
39 ボディ領域
40 基板抵抗
41 ストライプセルデバイス
42 ソースコンタクト領域
43 チャネル長
45 チャネル領域からオーミック領域までの長さ
44 ボディコンタクト領域
47 オーミック領域の幅
49 JFET領域の幅
50 正方形デバイスセル
51 レイアウト
52 レイアウト
54 六角形デバイスセル
55 レイアウト
60 距離
64 矢印
65 中心
66 矢印
68 側面
69 コーナー
70 グラフ
72 第1の曲線
74 第2の曲線
80 グラフ
82 第1の曲線
84 第2の曲線
86 グラフ
87 第1の曲線
88 第2の曲線
88 曲線
1090 デバイスレイアウト
1092 正方形デバイスセル
1094 チャネル領域拡張部
1096 幅
1098 矢印
1100 デバイスレイアウト
1110 デバイスレイアウト
1120 デバイスレイアウト
1122 矩形デバイスセル
1130 デバイスレイアウト
1140 デバイスレイアウト
1150 デバイスレイアウト
1160 デバイスレイアウト
1170 デバイスレイアウト
1180 デバイスレイアウト
1182 六角形デバイスセル
1190 デバイスレイアウト
1200 デバイスレイアウト
1202 第1の列
1204 第2の列
1210 デバイスレイアウト
1212 第1の列
1214 第2の列
1220 デバイスレイアウト
1230 デバイスレイアウト
1240 デバイスレイアウト
1242 六角形デバイスセル
1250 デバイスレイアウト
1260 デバイスレイアウト
1262 デバイスセル
1264 チャネル領域拡張部
1266 ソース領域拡張部
1270 デバイスレイアウト
1280 デバイスレイアウト
1282 デバイスセル
1284 チャネル領域拡張部
1286 ソース領域拡張部
Claims (20)
- 第1の導電型を有する半導体デバイス層(2)内に少なくとも部分的に配置された複数のデバイスセル(1092、1122、1182、1242、1262、1282)であって、前記複数のデバイスセル(1092、1122、1182、1242、1262、1282)のそれぞれが、
前記デバイスセル(1092、1122、1182、1242、1262、1282)の中心の近くに配置された第2の導電型を有するボディ領域(39)と、
前記デバイスセル(1092、1122、1182、1242、1262、1282)の前記ボディ領域(39)に隣接して配置された前記第1の導電型を有するソース領域(20)と、
前記デバイスセル(1092、1122、1182、1242、1262、1282)の前記ソース領域(20)に隣接して配置された前記第2の導電型を有するチャネル領域(28)と、
前記デバイスセル(1092、1122、1182、1242、1262、1282)の前記チャネル領域(28)に隣接して配置された前記第1の導電型を有するJFET領域(29)であり、前記デバイスセル(1092、1122、1182、1242、1262、1282)の前記チャネル領域(28)と、前記複数のデバイスセル(1092、1122、1182、1242、1262、1282)のうちの隣り合うデバイスセルのチャネル領域(28)の平行な部分との間に平行なJFET幅(49)を有する、JFET領域(29)と、
を備える、
複数のデバイスセル(1092、1122、1182、1242、1262、1282)を備え、
前記複数のデバイスセル(1092、1122、1182、1242、1262、1282)のうちの少なくとも1つのデバイスセルが、前記少なくとも1つのデバイスセルのチャネル領域拡張部(1094、1264、1284)と前記第2の導電型を有する前記隣り合うデバイスセルの領域(28)との間の距離(60)が前記平行なJFET幅(49)以下となるように、前記少なくとも1つのデバイスセルの前記チャネル領域(28)から外に向かって前記JFET領域(29)内へと延出する前記第2の導電型を有するチャネル領域拡張部(1094、1264、1284)を備える、
デバイス。 - 前記半導体デバイス層(2)が炭化ケイ素(SiC)半導体デバイス層である、請求項1記載のデバイス。
- 前記少なくとも1つのデバイスセルの前記チャネル領域拡張部(1094、1264、1284)と前記第2の導電型を有する前記隣り合うデバイスセルの前記領域(28)との間の前記距離(60)が前記平行なJFET幅(49)よりも小さい、請求項1記載のデバイス。
- 前記少なくとも1つのデバイスセルの前記チャネル領域拡張部(1094、1264、1284)がおよそ0.1μm〜およそ2μmの幅(1096)を有する、請求項1記載のデバイス。
- 前記少なくとも1つのデバイスセルの前記チャネル領域拡張部(1094、1264、1284)の前記幅(1096)がおよそ0.1μm〜およそ1μmである、請求項4記載のデバイス。
- 前記複数のデバイスセル(1092、1122、1182、1242、1262、1282)のうちの少なくとも2つのデバイスセルがそれぞれのチャネル領域拡張部(1094、1264、1284)を含み、前記少なくとも2つのデバイスセルの前記チャネル領域拡張部(1094、1264、1284)が互いに向かって延出し、互いにオーバラップする、請求項1記載のデバイス。
- 前記少なくとも1つのデバイスセルの前記チャネル領域拡張部(1094、1264、1284)が前記少なくとも1つのデバイスセルの前記チャネル領域(28)の長さ(Lch)(43)の2倍よりも大きい幅(1096)を有し、前記少なくとも1つのデバイスセルが前記少なくとも1つのデバイスセルの前記チャネル領域拡張部(1094、1264、1284)と同じ方向に前記デバイスセルの前記ソース領域(20)から延出するソース領域拡張部(1266、1286)を備える、請求項1記載のデバイス。
- 前記複数のデバイスセル(1092、1122、1182、1242、1262、1282)のうちの少なくとも2つのデバイスセルがそれぞれのチャネル領域拡張部(1094、1264、1284)およびそれぞれのソース領域拡張部(1266、1286)を含み、前記少なくとも2つのデバイスセルの前記チャネル領域拡張部(1094、1264、1284)が互いに向かって延出し、互いにオーバラップする、請求項7記載のデバイス。
- 前記少なくとも2つのデバイスセルの前記ソース領域拡張部(1266、1286)も互いに向かって延出し、互いにオーバラップする、請求項8記載のデバイス。
- 前記少なくとも1つのデバイスセルの前記チャネル領域拡張部(1094、1264、1284)が前記少なくとも1つのデバイスセルの前記チャネル領域(28)のすべてのコーナー(69)を通っては延出しない、請求項1記載のデバイス。
- 前記チャネル領域拡張部(1094、1264、1284)が可変幅(1096)を有する、請求項1記載のデバイス。
- 前記少なくとも1つのデバイスセルに隣接して配置された前記複数のデバイスセル(1092、1122、1182、1242、1262、1282)の1つまたは複数のデバイスセルがそれぞれのチャネル領域拡張部(1094、1264、1284)を含まず、1つまたは複数のデバイスセルのJFET領域(29)の最も広い部分が前記少なくとも1つの隣接するデバイスセルの前記チャネル領域拡張部(1094、1264、1284)によってシールドされている、請求項1記載のデバイス。
- 前記少なくとも1つのデバイスセルの前記チャネル領域拡張部(1094、1264、1284)が前記デバイスセルの前記チャネル領域(28)の少なくとも1つのコーナー(69)および少なくとも1つの側面(68)から延出する、請求項1記載のデバイス。
- 前記複数のデバイスセル(1092、1122、1182、1242、1262、1282)のそれぞれが実質的に正方形、六角形、細長い矩形形状、または細長い六角形形状を有する、請求項1記載のデバイス。
- 電界効果トランジスタ(FET)、絶縁ゲートバイポーラトランジスタ(IGBT)、または絶縁ベースMOS制御サイリスター(IBMCT)である、請求項1記載のデバイス。
- 第1の導電型を有する半導体層に、前記第1の導電型を有するソース領域(20)を注入するステップと、
前記半導体層に、第2の導電型を有するウェル領域(18)を注入して、前記ソース領域(20)に隣接してチャネル領域(28)を形成するステップと、
前記半導体層に、前記デバイスセル(1092、1122、1182、1242、1262、1282)の前記チャネル領域(28)からJFET領域(29)内へと延出する前記第2の導電型を有するチャネル領域拡張部(1094、1264、1284)を注入するステップであって、前記デバイスセル(1092、1122、1182、1242、1262、1282)の前記チャネル領域拡張部(1094、1264、1284)と、前記第2の導電型を有する隣り合うデバイスセル(1092、1122、1182、1242、1262、1282)の一部との間の距離(60)が、前記デバイスセル(1092、1122、1182、1242、1262、1282)の前記チャネル領域(28)の平行な部分と前記隣り合うデバイスセル(1092、1122、1182、1242、1262、1282)のチャネル領域(28)との間の距離以下である、ステップと、を含む、
デバイスセル(1092、1122、1182、1242、1262、1282)を製造する方法。 - 前記ウェル領域(18)が前記チャネル領域拡張部(1094、1264、1284)と同時に注入される、請求項16記載の方法。
- 前記ウェル領域(18)を注入するステップが、前記チャネル領域(28)の長さ(Lch)(43)の2倍以上である前記チャネル領域拡張部(1094、1264、1284)の幅(1096)を画定するステップを含み、前記ソース領域(20)から前記チャネル領域拡張部(1094、1264、1284)と同じ方向に延出する前記第1の導電型を有するソース領域拡張部(1266、1286)を注入するステップを含む、請求項16記載の方法。
- 前記ソース領域拡張部(1266、1286)が前記ソース領域(20)と同時に注入される、請求項18記載の方法。
- 前記ソース領域(20)が前記ウェル領域(18)の後に注入される、請求項18記載の方法。
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