CN102386112B - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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Publication number
CN102386112B
CN102386112B CN201110208148.0A CN201110208148A CN102386112B CN 102386112 B CN102386112 B CN 102386112B CN 201110208148 A CN201110208148 A CN 201110208148A CN 102386112 B CN102386112 B CN 102386112B
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China
Prior art keywords
wirings
chip mounting
chip
many
wiring
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Expired - Fee Related
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CN201110208148.0A
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Chinese (zh)
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CN102386112A (zh
Inventor
黑田宏
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Renesas Electronics Corp
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Renesas Electronics Corp
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  • Die Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
CN201110208148.0A 2010-08-31 2011-07-20 半导体器件的制造方法 Expired - Fee Related CN102386112B (zh)

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Application Number Priority Date Filing Date Title
JP2010193161A JP5503466B2 (ja) 2010-08-31 2010-08-31 半導体装置の製造方法
JP2010-193161 2010-08-31

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CN102386112A CN102386112A (zh) 2012-03-21
CN102386112B true CN102386112B (zh) 2015-12-16

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US (1) US8574963B2 (enExample)
JP (1) JP5503466B2 (enExample)
KR (1) KR101811063B1 (enExample)
CN (1) CN102386112B (enExample)
TW (1) TWI525719B (enExample)

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Publication number Priority date Publication date Assignee Title
JP5618873B2 (ja) * 2011-03-15 2014-11-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6118652B2 (ja) * 2013-02-22 2017-04-19 ルネサスエレクトロニクス株式会社 半導体チップ及び半導体装置
CN105247666B (zh) * 2013-07-10 2017-12-01 三菱电机株式会社 半导体装置及其制造方法
KR102079795B1 (ko) * 2013-07-19 2020-02-21 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 화상형성장치 및 칩
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