CN102386112A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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Publication number
CN102386112A
CN102386112A CN2011102081480A CN201110208148A CN102386112A CN 102386112 A CN102386112 A CN 102386112A CN 2011102081480 A CN2011102081480 A CN 2011102081480A CN 201110208148 A CN201110208148 A CN 201110208148A CN 102386112 A CN102386112 A CN 102386112A
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many
jointing material
chip
installation area
wirings
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CN102386112B (zh
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黑田宏
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本发明公开了一种半导体器件的制造方法，在经由粘合材料将半导体芯片安装到布线基板上时，可防止空洞的产生。本发明的制造方法包括芯片焊接工序，即经由粘合材料将半导体芯片安装到布线基板(40)的芯片安装区域(20a)上。所述布线基板(40)具有形成在核心层的上表面上的多条布线(第一布线)(23a)及多条虚拟布线(第二布线)(23d)。所述芯片安装区域(20a)配置在多条布线(23a)、多条虚拟布线(23d)上。另外，芯片焊接工序包括将粘合材料配置到芯片安装区域(20a)的粘合材料配置区域上的工序。而且，在芯片焊接工序中，多条虚拟布线(23d)分别沿着粘合材料的扩散方向延伸。

Description

半导体器件的制造方法
技术领域
本发明公开了一种半导体器件的制造方法，特别涉及一种在布线基板上安装半导体芯片的工序有效的技术。
背景技术
在日本公开特许公报特开2002-190488号公报(专利文献1)中公开了以下的半导体器件技术，即在布线基板上安装了半导体芯片的半导体器件中，设置有布线用的导体图案及在设置了导体图案之外的区域内设置有虚拟用的导体图案。
在日本公开特许公报特开2008-218848号公报(专利文献2)中，公开了以下的半导体器件技术，即在经由贴膜将半导体芯片安装到布线基板上的半导体器件中，在布线基板的芯片安装区域内设置有实布线图案和虚布线图案。
专利文献1日本特开2002-190488号公报
专利文献2日本特开2008-218848号公报
发明内容
在将半导体芯片安装到布线基板上的半导体器件的制造技术中，具有使用膏状粘合材料(芯片粘合材料)进行安装的技术。本案发明者对使用膏状粘合材料将半导体芯片安装到布线基板上的技术进行了研究，结果发现了以下问题。
随着对半导体器件的薄型化要求，安装到布线基板上的半导体芯片的厚度也出现了薄型化的倾向。因此，在将极薄的半导体芯片安装到布线基板上时，如果膏状粘合材料用量过多，将被挤出到半导体芯片的外围，而被挤压出的粘合材料将有一部分溢到半导体芯片的表面(与安装到布线基板的面相反一侧的面)上。而防止出现上述现象的对策就是尽量减少粘合材料的使用量。但是，由于在布线基板的上表面(安装有半导体芯片的面)上形成有多条布线，且存在相邻布线间的间距不均衡的部分，所以降低了上表面的平坦度。由此，明确了出现以下现象的原因，即由于半导体芯片和布线基板之间的粘合材料的湿润性(填充性)低(不好)，从而导致半导体芯片和布线基板之间出现空洞(间隙)。
接着，本案发明人对于专利文献1及专利文献2所公开的通过在布线基板的上表面形成虚布线图案来提高布线基板平坦度的技术进行了验证。结果发现，设置有虚布线图案的布线基板的上表面的平坦度比没设置有虚布线图案时的平坦度高。但是，如前所述，由于近年来半导体芯片的厚度已比上述的专利文献提交申请时的厚度变薄了，所以粘合材料的使用量也随之变少了。因此，在如上所述的半导体器件的制造方法中，仅在布线基板上形成虚布线图案已不能完全抑制空洞的出现。
本发明的目的在于，提供一种使用膏状粘合材料将半导体芯片安装在布线基板上时抑制空洞出现的技术。
本发明的所述内容及所述内容以外的目的和新特征在本说明书的描述及附图说明中写明。
下面简要说明关于本专利申请书中所公开的发明中具有代表性的实施方式的概要。
作为本案发明的方式之一的半导体器件的制造方法包括芯片焊接工序，即通过具有流动性的粘合材料将半导体芯片安装到布线基板的芯片安装区域上的工序。所述布线基板具有：形成在核心层的上表面上的多条第一及第二布线，形成在所述核心层的所述上表面且与所述多条第一布线电连接的多条焊接引线，以及形成于所述核心层的所述上表面且覆盖所述多条第一及第二布线的上表面侧绝缘膜。另外，所述芯片安装区域包括所述多条第一及第二布线。芯片焊接工序包括将所述粘合材料配置到所述芯片安装区域中的粘合材料配置区域上的工序。芯片焊接工序包括将配置于所述粘合材料配置区域上的所述粘合材料扩散到所述粘合材料配置区域外围的工序。而且，在所述芯片焊接工序中，所述多条第二布线分别沿着所述粘合材料扩散的方向延伸。
下面简要说明关于本专利申请书所公开的发明中根据具有代表性的实施方式所获得的效果。
即，按照本专利申请书一实施方式的方法，在通过膏状粘合材料将半导体芯片安装到布线基板上时可抑制空洞的产生。
附图说明
图1所示的是对植入了本发明一实施方式中的半导体器件的摄影系统的动作的模式说明图。
图2所示的是本发明一实施方式中半导体器件的上表面侧的内部结构的平面图。
图3所示的是沿图2的A-A线剖开的剖面图。
图4所示的是除掉图1所示的半导体芯片及上表面侧的绝缘膜(阻焊膜)后在核心层上表面侧形成的布线图例的平面图。
图5所示的是说明图1～图3中的半导体器件的组装流程的说明图。
图6所示的是图5的基材准备工序中所准备的布线基板的整体结构的平面图。
图7所示的是将图6的B部扩大后扩大平面图。
图8所示的是在图7所示的一个器件区域中，除掉上表面侧的绝缘膜(阻焊膜)后在核心层的上表面侧形成的布线图例的扩大平面图。
图9所示的是图5的芯片焊接工序的第一粘合材料配置工序的扩大平面图。
图10所示的是沿图9的C-C线剖开的扩大剖面图。
图11所示的是沿图9的D-D线剖开的扩大剖面图。
图12所示的是将半导体芯片安装到图10所示的布线基板的芯片安装区域上的工序的扩大剖面图。
图13所示的是膏状粘合材料在图12所示的E部中扩散的模式说明图。
图14所示的是膏状粘合材料在图9所示的芯片安装区域中平面扩散方向的模式说明图。
图15所示的是在图5的芯片焊接工序中的第二粘合材料配置工序的扩大平面图。
图16所示的是沿着图15的C-C线剖开的扩大剖面图。
图17所示的是将半导体芯片安装到图16的布线基板的芯片安装区域上的工序的扩大剖面图。
图18所示的是图5所示的引线焊接工序的突起电极形成工序的扩大剖面图。
图19所示的是将图18的F部进一步扩大后的扩大剖面图。
图20所示的是将图5所示的引线焊接工序进行扩大后的扩大剖面图。
图21所示的是在封装工序所用的成型模具上配置布线基板并供给封装用树脂的状态的扩大剖面图。
图22所示的是在用封装用树脂填满图21所示的膜槽内后，使封装用树脂硬化后的状态的扩大剖面图。
图23所示的是在布线基板上接合了多个焊球的状态的扩大剖面图。
图24所示的是对图23所示的布线基板及封装体进行划片的工序的扩大剖面图。
图25所示的是对应于图9的变形例的扩大平面图。
图26所示的是对应于图11的变形例的扩大剖面图。
图27所示的是对应于图2的变形例的平面图。
图28所示的是在图27所示的半导体器件的制造方法中，芯片焊接工序中的粘合材料配置工序的扩大平面图。
图29所示的是在图28所示的芯片安装区域的下层形成的虚拟布线的配置例的模式说明图。
图30所示的是对应于图27的变形例的平面图。
图31所示的是沿图30的G-G线剖开的剖面图。
图32所示的是对应于图8所示的布线基板的第一比较例即布线基板的上表面侧的布线图的扩大平面图。
图33所示的是对应于图8所示的布线基板的第二比较例即布线基板的上表面侧的布线图的扩大平面图。
符号说明
1                            摄像元件
2、81、82                    半导体器件
3                            画像处理LSI(半导体器件)
11                           粘合材料
11a                          膏状粘合材料
11b                          粘合材料配置区域
12、80                       半导体芯片
12a                          AFE芯片
12b                          VDR芯片
12c                          表面(上表面、主面)
12d                          背面(下表面、主面)
12e                          侧面
12f                          绝缘膜(钝化膜)
13、13a、13b                 焊线(导电性材料)
14                           封装体
14a                          封装用树脂
20                           布线基板
20a、20b、20C                芯片安装区域
21                           核心层
21a                        上表面(表面)
21b                        下表面(背面)
22                         端子(焊接引线)
23                         布线图
23a、23b                   布线
23c                        导通孔布线(布线)
23d                        虚拟布线(布线)
23e                        供电线
23f                        虚布线图案
24                         焊盘
25                         导通孔
26                         绝缘膜
26a                        开口部
26b                        沟部(锡堤部)
27                         绝缘膜
27a                        开口部
28                         焊接材料
31、31a、31b、
31d、31e                   焊垫(电极垫)
32                         金球焊
33                         焊线
34                         突起电极
35                         焊接材料
40、90、91                 布线基板
40a                        器件区域
40b                        框体(框部)
45                         喷嘴
45a                        吐出口
50                         划片刀
51                             树脂薄膜(切割带)
60                             固定夹具
61                             毛细管
71                             成型模具
72                             上模具
72a                            下表面
72b                            膜槽
73                             下模具
73a                            上表面
ADC                            A/D转换电路
CDS                            噪声降低电路
HDR                            水平驱动
PGA                            增益放大电路
TG                             定时信号发生器
VDR                            垂直驱动型驱动器
具体实施方式
在以下实施方式中，为了方便，在必要时将几个部分或将实施方式分割进行说明，除了需要特别说明的以外，这些都不是彼此独立且无关系的，而是与其它一部分或者全部的变形例、详细内容及补充说明等相互关联的。本专利申请书原则上省略掉重复的说明。另外，实施方式中提及各构成要素时，除了特别说明及原理上已经明确限定了特定的数量以及从前后文的叙述中已明确非为必须要素时，并非指必须要素。
在实施形态等的叙述上，对于材料及构成等方面，除了写明了仅限于所述材料外，“由A构成”“具有A”“包括A”等的表述还指主要构成要素除了A以外还有其他要素。如关于成分的叙述时为“以A为主要成分，还包括X”的意思。例如，提到“硅材料”时，并不是限定于纯硅材料，而是还可包括如SIGe(锗硅合金)以及其他以硅为主要成分的多元合金及其它添加物等材料。另外，除了特别说明的以外，镀金、Cu层、镀镍等也非限定为纯金、纯铜、纯镍等材料，而是还包括以金、铜、镍等为主要成分的材料。
另外，在以下实施方式中提及特定的数值、数量等时，除了特别说明及原理上已经明确限定了特定的数量等除外，所述的特定数并非指固定的数量，而是可大于等于所述特定数或可小于等于所述特定数。
为了说明实施方式的所有图中，原则上对具有同一功能的构件采用同一或类似的符号以及参考符号，并省略掉重复的说明。
另外，在实施方式所用的图中，为了使图面简单易懂，有时会省略掉剖面图的剖面线或者给平面图加上剖面线。
在以下的实施方式中，以本案发明人已进行具体研究的DSC(Digital still camera：数字照相机)或DVC(Digital video camera：数字视频摄录机)、以及带有照相功能的移动电话等嵌入了摄像装置(摄影系统)的半导体器件作为SIP型半导体器件的一例进行说明。
<摄像装置(摄影系统)>
图1所示的是嵌入了本实施方式中的半导体器件的摄影系统的动作的模式说明图。
图1中，本实施方式的摄像装置(摄影系统)例如具有CCD(ChargeCoupled Device：电荷耦合装置)、CMOS(Complementary Metal OxideSemiconductor：互补金属氧化物半导体)等的摄像元件(摄像传感器)1、以及与摄像元件1电连接的半导体器件2。摄像元件1具有将光线转换为电子的光电二极管以及将电子作为电信号读出的扫描电路。另外，半导体器件2还具有AFE(Analog Front End：模拟前端)电路，所述AFE电路具有控制摄像元件1的功能以及将从摄像元件1输出的电信号进行处理的功能。
半导体器件2具有控制摄像元件1的功能。具体地说就是，半导体器件2具有驱动数字电路即定时信号发生器TG及摄像元件1的驱动电路，并通过定时信号发生器TG生成的控制信号来驱动驱动器，通过所述驱动电路便可驱动如CCD光电传感器等的摄像元件(图像呈阵列状排列的摄像器件)1。
为了驱动摄像元件1，需要通过电压(驱动电压)不同的两种驱动电路来施加驱动电压。首先，通过AFE电路中的定时信号发生器TG进行控制信号的脉冲输出。AFE电路中从定时信号发生器TG输出的控制信号例如使用3.3V的电源。也就是说输出3.3V型的控制信号。
电压不同的两种驱动电路之一即水平驱动型HDR通过所述3.3V型的控制信号将电压施加到摄像元件1并驱动摄像元件1。另外，另一个驱动电路即垂直驱动型VDR通过比水平驱动型HDR的电压更高的控制信号来驱动摄像元件1。例如，本实施方式中使用5V电源，通过电平位移器将从定时信号发生器TG输入的3.3V型的控制信号转换为使用5V电源的控制信号(5V的信号)并进行输出，以驱动摄像元件1。
摄像元件1中，多个光电二极管呈阵列状排列，其将照射到所述光电二极管上的光转换为电荷。也就是说，将投影到光电二极管上的图像转换为电荷。在摄像装置中，经光电二极管转换后的电荷作为电信号进行信号处理并显示为图像。此时，摄像元件1中设有扫描电路，用于从呈阵列状排列的光电二极管依次输出电荷。通过电荷的移动传送而使图像转换为电信号(模拟图像信号)。并通过水平驱动型HDR或垂直驱动型VDR输出的控制信号(如定时脉冲等)控制所述扫描电路的驱动。
对于从摄像元件1输出的电信号(模拟图像信号)，通过半导体器件2中的AFE电路除去电路噪声、进行增益放大以及进行A/D转换等处理，以使其转换为数字信号。因此，AFE电路具有噪声降低电路CDS、增益放大电路PGA以及A/D转换电路ADC等。然后，经由形成有图像处理电路的LSI(Large Scale Integration：大规模集成电路)即半导体器件3输出并进一步进行图像处理后，提供给显示设备进行显示或供给存储装置进行存储。
下面详细说明本实施方式中的半导体器件2。在上述摄像系统中，所述半导体器件2为一种具有控制摄像元件1的系统和对从摄像元件1输出的电信号进行处理的系统的半导体器件(半导体封装体)。
<半导体器件>
下面通过图1～图4对图1所示的半导体器件2的结构进行说明。本实施方式适用于BGA(Ball Grid Array：球门阵列封装)型的半导体器件，图2所示的是所述BGA的上表面侧的内部结构的平面图，图3所示的是沿图2的A-A线剖开的剖面图。图4所示的是除掉图1所示的半导体芯片及上表面侧的绝缘膜(阻焊膜)后形成在核心层的上表面侧的布线图例的平面图。
本实施方式中的半导体器件2包括：具有上表面21a的布线基板20，经由粘合材料(芯片粘合材料)11分别安装于布线基板(基材)20的上表面21a上的多个(本实施方式中为2个)半导体芯片12(AFE芯片12a和VDR芯片12b)，与多个半导体芯片12和布线基板20分别电连接的多条焊线(导电性材料)13，以及封装体(封装树脂)14，用于封装多个半导体芯片12及多条焊线13。
多个半导体芯片12中，VDR芯片12b中形成有具有图1所说明的电平位移器的垂直驱动型电路VDR。AFE芯片12a中形成有除了垂直驱动型电路VDR之外的其他AFE电路，如水平驱动型电路HDR、定时信号发生器TG、噪声降低电路CDS、增益放大电路PGA以及A/D转换电路ADC等以3.3V型的电源驱动的电路。如上所述，本实施方式中的半导体器件2内置有2种半导体芯片，通过将所述2种半导体芯片电连接，便构成了图1所示的摄像装置的控制系统。也就是说，半导体器件2是一种在一个半导体器件内安装了多种半导体芯片来构筑系统的SIP(System in Package：系统化封装)型的半导体器件。
接下来对半导体器件2的基材即布线基板20进行说明。布线基板20包括具有上表面(芯片安装面、表面)21a和位于上表面21a的相反一侧的下表面(安装面、背面)21b的核心层(绝缘层、内核绝缘层)21。核心层21例如由以玻璃环氧树脂等为绝缘层的树脂基板构成。
如图4所示，核心层21的上表面21a上形成有多个端子(焊接引线、电极垫)22，分别与多个端子22电连接的多条布线(上表面侧布线)23a，以及不与端子22电连接的多条虚拟布线(布线、上表面侧布线)23d。另外，图中虽未示出，但是端子22的表面上形成有电镀层，如本实施方式中为在镍(NI)膜上层积金(Au)膜。此外，如图3所示，核心层21的下表面21b上形成有多个焊盘(端子、电极垫)24，以及分别与多个端子22电连接的多条布线(下表面侧布线)23b。图中虽未示出，焊盘24的表面上形成有电镀层，如本实施方式中为镍(NI)膜。如图3所示，核心层21中形成有导通孔(孔)25，所述导通孔(孔)25从上表面21a与下表面21b中的一个面朝向另一个面形成。多条布线23a和多条布线23b经由形成于所述导通孔25内的导体即布线(导通孔内布线、导通孔内导体)23c分别电连接。端子22、布线23a、23b、23c、虚拟布线23d、以及焊盘24例如分别由铜(Cu)形成。如图4所示，布线23a具有从端子22向芯片安装区域20a延伸的线形部和与该线形部一体形成的圆形部。所述圆形部形成于图3所示的导通孔25上，为与导通孔布线23c电连接的连接部(导通孔上的布线部)。本实施方式中，除了特意区分进行说明时除外，布线23a包括所述线形部及圆形部。
另外，如图2及图3所示，核心层21的上表面21a上形成有由绝缘性树脂形成的绝缘膜(上表面侧绝缘膜、阻焊膜)26，所述绝缘膜26覆盖多条布线23a及虚拟布线23d(请参照图3)。绝缘膜26中，在与多个端子22重合的位置上分别形成有多个开口部26a，在所述开口部26a中端子22从绝缘膜26露出。如图3所示，与绝缘膜26一样，核心层21的下表面21b也形成有由绝缘性树脂构成的绝缘膜(下表面侧绝缘膜、阻焊膜)27。所述绝缘膜27覆盖多条布线23b。在绝缘膜27中与多个焊盘24重合的位置上分别形成有多个开口部27a，焊盘24在开口部27a中从绝缘膜27露出。多个焊盘24的露出部分别与多个焊接材料(焊球)28连接，其中，在将半导体器件2安装到图中未示出的安装基板时，所述多个焊接材料(焊球)28成为外部电极端子。
图3示出了布线基板20的一例，即在核心层21的上表面21a及下表面21b都形成有布线图且具有2层布线层的布线基板。但是，布线基板20的布线层数不仅限于2层，还可以是所谓的多层布线基板，如核心层21内还可形成有多层布线层(布线图)。此时，由于可以增加布线的迂回空间，所以对于引脚数多的半导体器件尤其有效。
核心层21的上表面21a及下表面21b(即布线基板20的上表面及下表面)的平面形状为四角形，如本实施方式中为边长为5MM的正方形。
另外，布线基板20在核心层21的上表面21a侧具有多个芯片安装区域20a。本实施方式中为具有安装AFE芯片12a的芯片安装区域20b和安装VDR芯片12b的芯片安装区域20C。多个芯片安装区域20a被并列配置。也就是说，半导体器件2为将多个半导体芯片排列配置的平置型半导体器件。多个芯片安装区域20a各自为四角形的平面形状，本实施方式中为长方形。将芯片安装区域20b、20C以各自的长边互为对边的方式进行排列布置。换言之就是，芯片安装区域20b的第一长边和芯片安装区域20C的第二长边互为对边。
如图4所示，形成于核心层21的上表面21a上的多条布线23a及多条虚拟布线23d分别形成在芯片安装区域20b、20C的下层(从平面上看在重合的位置上)。换言之就是，芯片安装区域20b、20C配置于多条布线23a及多条虚拟布线23d上。通过将多条布线23a引出到芯片安装区域20b、20C的下层，就可将核心层21的上表面21a有效地利用为布线23a的迂回布线空间。将多条虚拟布线23d安装到芯片安装区域20b、20C的下层的理由是为了抑制及防止在粘合材料(芯片粘合材料)11上产生空洞，在后述说明半导体器件2的制造方法时还将进行详细说明。另外，关于形成于核心层21的上表面21a上的布线23a及虚拟布线23d的平面布局(布置图)，也将在说明半导体器件2的制造方法时进行详细说明。
在各芯片安装区域20a的外围分别形成有沟部(凹部、锡堤部)26b。所述沟部26b是通过除掉绝缘膜26的一部分而形成，且以包围各芯片安装区域20a外围的方式形成。本实施方式中，在形成沟部26b的区域中，除掉绝缘膜26而使布线23a的一部分露出于沟部26b中。
接下来对在布线基板20上安装半导体芯片12的方法进行说明。本实施方式中的2个半导体芯片12(VDR芯片12b和AFE芯片12a)分别具有表面(主面、上表面)12c、位于表面12c相反一侧的背面(主面、下表面)12d、以及位于所述表面12c和背面12d之间的侧面12e。
半导体芯片12的平面形状(表面12c、背面12d的形状)略呈四角形，本实施方式中为长方形。具体的例子如，AFE芯片12a为1.58MM×3.25MM、VDR芯片12b为1.58MM×3.58MM的平面形状。本实施方式中的2个半导体芯片为平面上排列配置。具体的如图2所示，以一个半导体芯片12的长边与另一个半导体芯片12的长边互为对边(并列)的方式配置各半导体芯片12。如前所述，将多个半导体芯片12在平面上排列配置时，通过将各半导体芯片12设为长方形，且各自的长边互为对边的方式进行设置，就可抑制整个半导体器件(半导体封装)的平面尺寸的增加，从而可实现半导体器件的小型化。如上所述，本实施方式中虽将布线基板20的平面形状设置为正方形，但也可将其设置为长方形形状。在布线基板20为长方形形状时，通过将布线基板20的平面形状中的长边与短边的比(短边的长度/长边的长度)设为大于半导体芯片12中的长边和短边的比(短边的长度/长边的长度)，就可抑制整个半导体器件的平面尺寸的增加，从而可实现半导体器件的小型化。另外，从半导体器件的薄型化的观点来看，已将本实施方式中的2个半导体芯片12削薄为相同的厚度，如分别为0.15MM。
半导体芯片12的表面12c上分别形成有多个焊垫(电极垫)31。多个焊垫31沿着半导体芯片12的各边且并列配置在表面12c上的外缘部侧。另外，半导体芯片12的表面12c侧分别形成有二极管或晶体管等多个半导体元件(电路元件)，并经由图中未示出的形成于半导体元件上的布线(布线层)分别与多个焊垫31电连接。如前所述，通过使形成于表面12c侧的半导体元件与多个焊垫电连接的布线形式，就可使半导体芯片分别构成如上所述的驱动电路等电路。
半导体芯片12的基材(半导体基板)例如可由硅(SI)构成。另外，表面12c上还形成有绝缘膜，且多个焊垫31各自的表面通过形成于所述绝缘膜的开口部而从绝缘膜露出。
所述焊垫31由金属构成，例如，本实施方式中为由铝(AL)构成。而且，在所述焊垫31的表面还形成有电镀膜，如本实施方式中为经由镍(NI)膜而形成金(Au)膜的多层结构。
多个半导体芯片12经由多条焊线13分别与布线基板20电连接(连接芯片-布线基板之间)。具体地说就是，焊线13a的一端与半导体芯片12的焊垫31a连接，另一端与布线基板20的端子22连接。本实施方式中，多个半导体芯片12经由焊线13b直接电连接。具体地说就是，焊线13b的一端与一个半导体芯片12(例如本实施方式中为AFE芯片12a)的焊垫31b连接，焊线13b的另一端与另一个半导体芯片12(例如本实施方式中为VDR芯片12b)的焊垫31b连接。另外，连接到将半导体芯片12彼此连接(芯片-芯片之间的连接)的焊线13b上的焊垫31b在四角形半导体芯片12的四个边中，沿着互为对边且相邻的边(本实施方式中为长边)配置。由此，可缩短焊线13b的长度(即缩短传输距离)。
本实施方式中，在AFE芯片12a和VDR芯片12b之间并没形成有端子22，端子22以包围所述半导体芯片12的外围的形式进行配置。由于可缩短并列配置的半导体芯片12之间的距离，因此可抑制整个半导体器件的平面尺寸的增加，从而实现半导体器件的小型化。但是，端子22的配置图并不仅限于图2所示的布置方式，例如，也可配置在AFE芯片12a和VDR芯片12b之间。
图2所示的2个半导体芯片12中作为外部端子的焊垫31彼此的数量不同。具体是AFE芯片12a所具有的焊垫31的数量比VDR芯片12b所具有的焊垫31的数量多。这是由于AFE芯片12a和VDR芯片12b是由不同电路形成的不同类型的半导体芯片12的缘故，所以所需外部端子的数量也各不相同。因此，AFE芯片12a的4个边中，配置在与VDR芯片12b的长边互为对边的一侧上的焊垫31的一部分，经由焊线13与端子22电连接。
在半导体芯片12的背面12d与布线基板20的核心层21的上表面21a互为相对面的状态下，经由粘合材料11将多个半导体芯片12分别粘接固定在布线基板20的芯片安装区域20a上。粘合材料11例如可由环氧类的热硬化性树脂构成，并覆盖半导体芯片12的整个背面12d，而且，延伸到位于外侧的沟部26b的边沿部。
另外，在布线基板20的上表面21a侧形成封装体14，并通过封装体14将多个半导体芯片12及多条焊线13进行封装(树脂封装)。
<半导体器件的制造工序>
下面说明本实施方式中半导体器件2的制造工序。本实施方式中的半导体器件2按照图5所示的组装流程制成。图5所示的是图1～图3中的半导体器件的组装流程的说明图。有关各工序的内容，通过图6～图24进行详细说明。
1.基材(布线基板)准备工序：
首先，准备图6所示的布线基板40，这就是图5所示的基材准备工序S1。图6所示的是在图5所示的基材准备工序中准备的布线基板整体构造的平面图，图7所示的是将图6的B部扩大后的扩大平面图。图8所示的是在图7所示的一个器件区域中，除掉上表面侧的绝缘膜(阻焊膜)后形成于核心层的上表面侧的布线图例的扩大平面图。
如图6所示，本实施方式中使用的布线基板40在框体(框部)40b的内侧具有多个器件区域40a。具有多个器件区域40a，意味着布线基板40即是所谓的多数个可断开板。
如图7所示，各器件区域40a具有：多个芯片安装区域20a和排列配置在芯片安装区域20a外围的多个端子(焊接引线)22，所述多个芯片安装区域20a由安装了AFE芯片12a(请参照图2)的芯片安装区域20b和安装了VDR芯片12b(请参照图2)的芯片安装区域20C构成。即，从平面上看，芯片安装区域20a被多个端子22包围。芯片安装区域20b、20C的平面形状为对应安装半导体芯片12(请参照图2)的平面形状而分别为四角形的形状，本实施方式中为长方形。另外，芯片安装区域20b、20C各自所具有的4个边中，各自的长边以互为对边的方式进行配置。也就是说，芯片安装区域20b的第一长边和芯片安装区域20C的第二长边互为对边。另外，从平面上看，芯片安装区域20b、20C之间没形成有端子22。由此，可将芯片安装区域20b、20C的间隔靠近配置，因此，可将使器件区域40a的平面尺寸缩小为如图2所示的半导体器件2的平面尺寸。
另外，如图8所示，多个端子22分别与布线23a电连接。具体地说就是，多个端子22的内侧(芯片安装区域20a侧)的端部分别与多条布线23a连接，而布线23a从端子22朝向芯片安装区域20a的方向延伸。端子22的外侧(器件区域40a的外缘侧)的端部与供电线23e连接，供电线23e从端子22朝着器件区域40a的外侧延伸。所述多条供电线23e通过电解电镀法在核心层21的上表面形成布线23a、虚拟布线23d、以及端子22时供给电源的供电线。本实施方式中，布线23a、虚拟布线23d以及端子22就是通过使用了所述供电线的电解电镀法形成的镀层。如前所述，将多条布线23a一直拉到芯片安装区域20a内，通过有效利用核心层21的上表面21a的空间，即使在增加端子数时，也可防止或抑制半导体器件平面尺寸的增加，从而可有效地对布线23a进行迂回布线。另外，图8所示的虚拟布线23d虽不与供电线23e连接，但可通入如下的方法来形成。即，如作为形成方法的一例，在整个核心层21的上表面21a上层积有基础导体膜(例如铜膜，图中未示出)、基础导体膜上的镀膜(图中未示出)的状态下，通过电解电镀法以图1所示的布线23a、虚拟布线23d及端子22的图案形成镀层后，通过除掉基础导体膜便可形成虚拟布线23d。有关多条虚拟布线23d的配置图及形状，将在后述的芯片焊接工序中进行详细说明。
另外，如图7所示，核心层21的上表面21a被绝缘膜26所覆盖。绝缘膜26上形成有开口部，该开口部中露出多个端子22。另外，在图7所示的端子22和芯片安装区域20a之间，以及在芯片安装区域20b、20C之间，可以防止在之后的芯片焊接工序中，供给芯片安装区域20a的膏状粘合材料从被供给的部分向外围过度湿扩散而形成有成为锡堤部的沟部26b，所述的沟部26b以包围芯片安装区域20b、20C的外围的方式形成。本实施方式中，不只是芯片安装区域20b、20C分别独立地形成沟部26b，而是在芯片安装区域20a之间还形成有一个沟部26b。也就是说，沟部26b为一体地形成，在芯片安装区域20b、20C之间，作为锡堤部的沟部26b兼用作芯片安装区域20b、20C。如上所述，通过在芯片安装区域20b、20C之间形成一个沟部26b，就可缩小芯片安装区域20b、20C之间的间隔，因此可缩小器件区域40a的平面尺寸，即可实现图2所示的半导体器件2的小型化。所述沟部26b中，布线23a的一部分从绝缘膜26露出。
2.半导体芯片的准备工序：
在图5所示的半导体芯片的准备工序S2中，准备图2所示的多个半导体芯片12。本工序中准备具有多个芯片区域的半导体晶片，例如，准备由硅构成的半导体晶片(图中未示出)。随后，使划片刀(图中未示出)沿着半导体晶片的切割线将半导体晶片进行切割，以取得图2所示的多个半导体芯片12(晶片切割工序)。具体的就是准备在多个芯片区域分别形成有具备图2所示的AFE芯片12a的电路等的半导体晶片、以及在多个芯片区域形成有具备图2所示的VDR芯片12b的电路等的半导体晶片。接着，将各半导体晶片进行切割，以取得多个AFE芯片12a和多个VDR芯片12b。本实施方式中，例如，在所述的晶片切割工序中，使用宽度不同的多种(例如2种)划片刀按多个步骤(例如2个步骤)将半导体晶片进行切割(分段式切割方式)。具体的做法是，首先，通过具有第一宽度的划片刀将半导体晶片切屑一部分(第一步骤)。接着，使用具有比第一宽度窄的第二宽度的划片刀切割第一步骤中剩下的部分，切割成多个半导体芯片12。使用如上所述的分段式切割方式，就可如图3所示，对半导体芯片12的表面12c侧的外缘部进行倒角加工。本实施方式中，倒角加工的形状为图3所示的阶梯状的倒角形状。换言之就是，半导体芯片12的表面12c侧的外缘部形成有阶梯部。
3.芯片焊接工序：
接下来对图5所示的芯片焊接工序S3进行说明。图9所示的是图5的芯片焊接工序中的第一粘合材料配置工序的扩大平面图，图10所示的是沿着图9的C-C线剖开的扩大剖面图，图11所示的是沿着图9的D-D线剖开的扩大剖面图。
如图9及图10所示，第一粘合材料的配置工序就是配置膏状粘合材料(膏状芯片粘合材料)11a的工序。膏状粘合材料11a例如为包含热硬化性树脂的膏状粘合材料，在这些树脂硬化(热硬化)之前具有流动性。另外，本实施方式中所使用的粘合材料虽然具有流动性，但也具有一定程度的粘度(例如，在20℃的温度条件下粘度为20～150PA·S)，例如，粘度比一般呈液态的水(H2O)的粘度(在20℃的温度条件下粘度为1×10-3PA·S)高。本工序中，在具有各器件区域40a的芯片安装区域20b、20C中的一个涂上膏状粘合材料11a并进行配置。多个芯片安装区域20a中，不限定膏状粘合材料11a的配置顺序，但在本实施方式中，配置在安装有VDR芯片12b(请参照图2)的芯片安装区域20C上。
具体的做法如图10及图11所示，通过喷嘴45在覆盖着布线基板40上表面21a的绝缘膜26上涂布膏状粘合材料11a。本实施方式中，使用从吐出口45a分歧为多个喷嘴45将膏状粘合材料11a涂布在芯片安装区域20a(粘合材料配置区域11b)中的多处。例如，如图11所示，在本实施方式中，使用从0.2MMφ的圆形的吐出口45a分歧出6个喷嘴45。各吐出口45a的配置间距(中心间距离)例如为0.55MM，而且，如图9所示，沿着芯片安装区域20a四个边中互为对边的两个短边中央的中央线(假想线)以略等间隔进行配置。此时，被配置为多个膏状粘合材料11a分别跨过中央线(假想线)且在芯片安装区域20a的内侧(与在之后的工序中安装的半导体芯片重合的区域的内侧)。作为将膏状粘合材料11a配置在芯片安装区域20a上的多处的配置方法(多点涂布方式)的变形例(详细内容请参照后述的变形例1)，例如可使用扫描吐出口45a无分歧的喷嘴，并将膏状粘合材料11a进行带状涂布的方法(带状涂布方式)。但是，因可在短时间内涂布膏状粘合材料11a，所以优选图9所示的对多处进行涂布的方法。即，从提高制造效率的观点出发，优选图9所示的多点涂布方式。
在将如本实施方式所述的薄的(如0.15MM)半导体芯片12(请参照图2)安装到布线基板40上时，如果膏状粘合材料11a用量过多，从半导体芯片12的外围挤出的膏状粘合材料11a的一部分将溢出到半导体芯片12的表面12c(请参照图2)上。为了抑制如前所述的膏状粘合材料11a的溢出，优选减少膏状粘合材料11a的配置量(涂布量)的方法，例如，本实施方式中，配置在一个芯片安装区域20a中的膏状粘合材料11a的总量(总配置量)为0.1MG左右。即，如图11所示，如从喷嘴45的吐出口45a分歧出6个时，从各吐出口45a涂布的膏状粘合材料11a分别约为0.017MG。另外，在随后的安装半导体芯片的工序中，由于将半导体芯片安装到布线基板时所产生的重量而使膏状粘合材料11a的一部分溢出到配置的部分的外围。因此，为了抑制膏状粘合材料11a的溢出，本实施方式中，不是将膏状粘合材料11a几乎涂满整个芯片安装区域20a，而是如图9所示，从所安装的半导体芯片的外缘部(外延部)朝向内侧在彼此隔开的区域(粘合材料涂布区域11b)上涂布(配置)膏状粘合材料11a。
如图3所示，为了将半导体芯片12紧固安装在布线基板20上，优选将膏状粘合材料11a扩散到整个芯片安装区域20a上。因此，如本实施方式所述，在减少膏状粘合材料11a的配置量时，以下的配置方法尤其有效。即，如图9所示，将膏状粘合材料11a配置在连接芯片安装区域20a的四个边中互为对边的短边中央的中央线上，而且，将膏状粘合材料11a配置在沿着中央线延伸的粘合材料配置区域11b上(忽略所述多点涂布方式与带状涂布方式的区别)。换言之就是，在本工序中，将膏状粘合材料11a配置在从芯片安装区域20a的一个短边侧朝向与之互为对边的另一短边的配置方法尤其有效。由此，便可形成粘合材料配置区域11b沿着芯片安装区域20a的长边延伸的带状平面形状。因此，在将使膏状粘合材料11a扩散到粘合材料配置区域11b外围的芯片安装区域20a的工序中，膏状粘合材料11a将主要沿着芯片安装区域20a的长边扩散，从而可缩小膏状粘合材料11a的移动距离(从粘合材料配置区域11b到芯片安装区域20a的外缘部的距离)。因此，可抑制在芯片安装区域20a内出现无膏状粘合材料11a覆盖的区域(造成空洞产生原因的区域)。
将半导体芯片紧固到布线基板等基材上的粘合材料，除了本实施方式中所述的膏状粘合材料以外，还可使用事先将形成为胶卷状的粘结带贴到半导体芯片背面的带状类粘合材料。如前所述的事先贴到半导体芯片背面的胶卷状的粘结带被称为DAF(Die Attach Film：芯片贴膜)。
但是，基于以下理由，本实施方式中采用了具有流动性的膏状粘合材料11a。覆盖布线基板40的上表面21a的绝缘膜26由比形成在上表面21a上的布线23a等构成的金属材料更柔软的树脂材料构成。因此，绝缘膜26的表面(上表面)的平坦度比核心层21的平坦度低，且具有因形成在上表面21a上的布线23a等导体图案而造成的凹凸形状(例如请参照图11)。另外，本实施方式中，为了确保布线路径的迂回布线，如前所述，布线23a延伸到芯片安装区域20a内。即，芯片安装区域20a内的绝缘膜26的表面(上表面)具有因布线23a等而造成的凹凸形状。如前所述，在芯片安装区域20a内的绝缘膜26的表面具有凹凸形状的状态下，通过DAF等粘结带紧固半导体芯片时，有可能在粘结带和绝缘膜26之间产生缝隙。另一方面，如果使用本实施方式所述的具有流动性的膏状粘合材料11a，就可将膏状粘合材料11a填充到因绝缘膜26表面而造成的凹凸形状中，由此可提高半导体芯片的背面和绝缘膜26的致密性。
接着，第一半导体芯片安装工序为将图12所示的半导体芯片12安装到布线基板40的芯片安装区域20a的工序。在本实施方式所述的第一粘合材料配置工序中，将VDR芯片12b安装到事先涂布了膏状粘合材料11a的芯片安装区域20C上。将半导体芯片12以背面12d与芯片安装区域20a的上表面21a互为相对面的方式安装到芯片安装区域20a上(面朝上安装)。图12所示的是将半导体芯片安装到图10所示的布线基板的芯片安装区域的工序的扩大剖面图，图13所示的是膏状粘合材料在图12所示的E部中扩散的模式说明图，图14所示的是膏状粘合材料在图9所示的芯片安装区域中平面扩散方向的模式说明图。
本工序中，使用图12所示的固定夹具60将在前述的半导体芯片的准备工序中准备的半导体芯片12送到芯片安装区域20a上。接着，使半导体芯片12的背面12d朝向布线基板40的上表面21a并靠近安装。具体的做法如通过图12及图13所示的固定夹具60从半导体芯片12的主面12c侧挤压，将半导体芯片12朝向布线基板40的上表面21a并进行挤压(施加负载(芯片负载))。此时，固定夹具60具有挤压夹具的作用。此时，由于膏状粘合材料11a具有如前所述的流动性，所以在将半导体芯片12朝向布线基板40挤压时(对膏状粘合材料11a施加负载(芯片负载))，在芯片安装区域20a中膏状粘合材料11a将从粘合材料配置区域11b(请参照图13、图14)向外围平面扩散(湿扩散)。换言之就是，在将半导体芯片12压向布线基板40时，膏状粘合材料11a将从与图14所示的本工序中安装的半导体芯片12重合的区域(从半导体芯片12的外缘部朝向内侧隔离的区域)向半导体芯片12的外侧扩散。
如果进行详细地说明，就是如图13及图14中的箭头所示，膏状粘合材料11a填充在形成在芯片安装区域20a的绝缘膜26的表面上的凹凸的间隙，并向粘合材料配置区域11b的外围扩散，一直扩散到比半导体芯片12背面12d的外缘部更靠外的外侧。另外，如图14所示，膏状粘合材料11a从设置在连接芯片安装区域20a的短边中央的中央线上的粘合材料配置区域11b，主要向芯片安装区域20a的两个长边扩散。而且，在芯片安装区域20a的两个短边附近，膏状粘合材料11a的一部分从粘合材料配置区域11b朝向芯片安装区域20a的短边扩散。另外，如本实施方式所述，以多点涂布方式配置膏状粘合材料11a时，如图14所示，在粘合材料配置区域11b内，膏状粘合材料11a的一部分朝向相邻配置的膏状粘合材料11a扩散。但是，相邻配置的膏状粘合材料11a将相互混合并形成为一体化后，将如图14所示朝向芯片安装区域20a的两条长边扩散。
如上所述，通过使膏状粘合材料11a湿扩散到比半导体芯片12的背面12d外缘部更外侧，由此可使膏状粘合材料11a几乎覆盖整个半导体芯片12的背面12d(例如，覆盖背面12d的90％以上)，所以可使半导体芯片12紧固在布线基板40(具体的是绝缘膜26)上。如果欲将半导体芯片12固定在布线基板40上，优选使膏状粘合材料11a完全覆盖半导体芯片12的整个背面12d的情况。
在此，为了抑制在半导体芯片12和绝缘膜26之间产生空洞(间隙)，就需要一种在膏状粘合材料11a在芯片安装区域20a上扩散时减少空洞产生的技术。即，需要一种将存在于半导体芯片12和芯片安装区域20a之间的气体高效排出到芯片安装区域20a外侧的技术。如上所述，从减少膏状粘合材料11a扩散时产生间隙的观点出发，图8所示的本实施方式中的虚拟布线23d的形状及配置为有效。下面参照本案发明人所探讨的比较例对其理由进行说明。
<比较例的探讨>
图32所示的是对于图8所示的布线基板的第一比较例即布线基板的上表面侧的布线图的扩大平面图，图33所示的是对于图8所示的布线基板的第二比较例即布线基板的上表面侧的布线图的扩大平面图。
首先，本案发明人进行了如下的操作。即在图32所示的比较例的布线基板90上实施所述第一粘合材料配置工序后，再如图12所示将半导体芯片12压向布线基板90(请参照图32)。其中，图32所示的布线基板90与图8所示的布线基板90在是否形成虚拟布线23d这一点上存在不同。结果明确了在多条布线23a之间的间距大的区域中，在半导体芯片12和布线基板90之间产生了空洞。
本案发明人认为产生上述空洞的原因是由于芯片安装区域20a内的绝缘膜26(请参照图12)表面的平坦度过低而引起的，为了提高平坦度而进行了如下探讨，即如图33所示，将由正方形的光点图形构成平面形状的多个虚布线图案23f用于配置在多条布线23a之间的布线基板91上。虚布线图案23f通过采用与图8所示的虚拟布线23d同样的方法形成。对于布线基板91，也采用图32所示的布线基板90时同样的方法，如图12所示，将半导体芯片12压向布线基板91(请参照图33)。但结果，在由光点图形构成的虚布线图案23f的周边也出现了空洞。本案发明人认为产生空洞的原因如下，即虚布线图案23f中，存在于芯片安装区域20a和半导体芯片12(请参照图12)之间的气体(如空气)的排出方向为不规则方向，所以无法充分排出气体。
<关于本实施方式的虚拟布线的形状及布局的说明>
从上述结果可知，在减少膏状粘合材料11a(请参照图14)的配置量时，为了提高绝缘膜26(请参照图14)表面的平坦度而仅是形成虚拟布线，将不能充分抑制空洞的产生。因此，本案发明人进一步作了如下探讨。即如图8所示，使多条虚拟布线23a分别沿着膏状粘合材料11a(请参照图14)的主要扩散方向延伸，由此便可较确实有效地抑制空洞的产生。
在形成了本实施方式所述的虚拟布线23a后，在覆盖虚拟布线23a的绝缘膜26的表面也因虚拟布线23a的平面形状而出现凹凸形状(如图13所示)。接着，如图9所示，在膏状粘合材料11a扩散到粘合材料配置区域11b的外围时，存在于半导体芯片12(请参照图12)和绝缘膜26之间的气体(如空气)更容易沿着绝缘膜26的表面的凹凸移动。因此，通过使多条虚拟布线23a分别沿着膏状粘合材料11a的扩散方向延伸，可以抑制残留在一部分芯片安装区域20a上的气体。换言之就是，将存在于绝缘膜26和半导体芯片12之间的气体(空气)诱导出来，并将所述气体挤到芯片安装区域20a的外侧。由此，可使膏状粘合材料11a(湿扩散)扩散到整个芯片安装区域20a。
本实施方式中，膏状粘合材料11a的扩散方向是指朝向图14所示的粘合材料配置区域11b的外围的方向。长方形的芯片安装区域20a所具有的四个边中，由于连接互为对边的短边中央的中央线上设有粘合材料配置区域11b，所以膏状粘合材料11a的扩散方向主要是从粘合材料配置区域11b朝向芯片安装区域20a的各长边的方向。因此，本实施方式中，多条虚拟布线23d分别沿着芯片安装区域20a的短边延伸。另外，如本实施方式所述，如为由长方形的平面形状构成的芯片安装区域20a时，通过将存在于半导体芯片12和绝缘膜26之间的气体挤向长边，可缩短移动距离。即易于将气体挤出。因此，通过使多条虚拟布线23d分别沿着芯片安装区域20a的短边延伸，可轻易将气体挤出。也就是说可抑制出现因气体残留而产生的空洞。
另外，在呈带状延伸的粘合材料配置区域11b的两个端部附近，膏状粘合材料11a从粘合材料配置区域11b朝向芯片安装区域20a的各短边扩散。例如，在图8所示的芯片安装区域20a的短边附近，朝向短边延伸的部分只延伸到芯片安装区域外缘为止的较短距离。此时，如果在短边附近形成虚拟布线23d时，如图8所示，多条虚拟布线23d中短边附近的一部分也可沿着芯片安装区域20a的长边延伸。但是，与沿着各长边扩散的膏状粘合材料11a的量相比，从粘合材料配置区域11b朝向芯片安装区域20a的各短边扩散的膏状粘合材料11a的量很少。另外，从呈带状延伸的粘合材料配置区域11b的端部到短边的距离非常短。因此，图8所示的变形例也可为所有的虚拟布线23d都沿着芯片安装区域20a的短边延伸的结构。
另外，在使膏状粘合材料11a扩散的工序(安装半导体芯片的工序)中，从缩短气体的移动距离的观点出发，优选多条虚拟布线23d都无弯曲部而为略呈直线型的形状。因为如果虚拟布线23d弯曲，芯片安装区域20a上的气体的移动距离就变长，从而使空洞产生的可能性更高。因此，从降低空洞产生的观点出发，优选多条虚拟布线23d都无弯曲的布置方式。但是，因受布线23a布局的限制，如果多条虚拟布线23d中都无弯曲部，有可能造成布线23a间的间隙扩大。此时，如图8所示，也可为虚拟布线23d具有弯曲部的结构。
另外，多条虚拟布线23d配置在芯片安装区域20a中多条布线23a间的距离较大的区域内。这是由于布线间间隙大的区域容易产生空洞的缘故。换言之就是，如果将配置了虚拟布线23d的虚拟布线配置区域和不配置虚拟布线23d的虚拟布线非配置区域两者与相邻的布线23a间的距离进行比较，虚拟布线配置区域的布线23a间的距离比虚拟布线非配置区域的布线23a间的距离大。本实施方式中，例如，如果将多条布线23a的各条布线设计上的线宽度设为L，将相邻的布线23a间设计上的间隔设为S，在布线布局上，对于产生3×S以上间隙的区域，在相邻的布线23a间配置一条或多条虚拟布线23d。另外，因在虚拟布线非配置区域中布线23a间的距离狭小，各布线23a朝向端子22延伸且横跨芯片安装区域20a内外而成，所以不易产生空洞。
另外，为了有效地诱导出芯片安装区域20a上的气体，优选多条虚拟布线23d分别连续形成。换言之就是，优选在虚拟布线23d延伸方向的延长线上不与别的虚拟布线23d相邻配置。再换言之，优选在相邻的布线23a间，多条虚拟布线23d的各条布线不被分断的情况。但是，如图8所示，在虚拟布线配置区域的间隙较宽时，可将延伸方向一致的多条虚拟布线23d略呈平行地排列配置。
另外，为了有效地诱导出芯片安装区域20a上的气体，优选多条虚拟布线23d的各布线的厚度与多条布线23a的各条布线的厚度相同。本实施方式中，由于所述布线23a和虚拟布线23d分别通过电解电镀法形成，所以可容易获得同样的厚度。另外，本实施方式中，多条虚拟布线23a各自的线宽度与多条布线23a各自的线宽度(具体地说是布线23a线形部的线宽度)相同。另外，作为变形例，也可为多条虚拟布线23a各自的线宽度小于多条布线23a各自的线宽度(具体地说是布线23a线形部的线宽度)的情况。
从平面上看，图8中多条虚拟布线23d配置在芯片安装区域20a内，而不延伸到芯片安装区域20a的外侧。根据本案发明人的实验证实，即使虚拟布线23d不似图8所示的延伸到芯片安装区域20a外侧也可抑制空洞的产生。但是，在与粘合材料配置区域11b(请参照图9)的距离较远的区域中，为抑制空洞的产生，优选虚拟布线23d延伸到芯片安装区域20a的外缘附近的结构。也可为虚拟布线23d延伸到芯片安装区域20a外侧的结构。
另外，为了使膏状粘合材料11a无间隙地扩散，也可将虚拟布线23d与布线23a连接。但是，为防止流经布线23a的电流的电特性降低，优选将虚拟布线23d和布线23a分离设置的设置方式，因此，本实施方式中，多条虚拟布线23d和多条布线23a分别为分离设置。
如上所述，本实施方式中，通过在芯片安装区域20a内形成图8所示的多条虚拟布线23d，即使减少了膏状粘合材料11a的配置量，也可使膏状粘合材料11a如图12所示地无间隙扩散。另外，为了使图面简单易懂，图12中将膏状粘合材料11a的厚度画得较厚，但膏状粘合材料11a例如可为约10μM左右的厚度，即使与半导体芯片12(150μM)相比也是极薄的厚度。因此，可以减少安装半导体芯片12时所需的膏状粘合材料11a的使用量，从而可节省资源。
另外，本实施方式中，由于在芯片安装区域20a的外围形成沟部26b，所以可以防止膏状粘合材料11a的一部分扩散到端子22。但是，如本实施方式所述，如果膏状粘合材料11a很薄地扩散时，将很难进行大范围的扩散，作为本实施方式的变形例，也可为没形成有沟部26b的形式。
接下来的第二粘合材料配置工序是指如图15及图16所示，在已经安装了半导体芯片12的芯片安装区域20a之外的芯片安装区域20a上配置膏状粘合材料11a的工序。本实施方式中是将膏状粘合材料11a配置在安装有AFE芯片12a(请参照图2)的芯片安装区域20b上。图15所示的是图5的芯片焊接工序的第二粘合材料配置工序的扩大平面图，图16所示的是沿图15的C-C线剖开的扩大剖面图。
由于本工序中所使用的构成膏状粘合材料11a的材料及配置(涂布)膏状粘合材料11a的位置及形状与所述的第一粘合材料配置工序相同，所以省略掉重复的说明。
接下来的第二安装半导体芯片的工序是指如图17所示，将半导体芯片12安装到布线基板40的芯片安装区域20a的工序。本实施方式中是将AFE芯片12a安装到芯片安装区域20b上。将半导体芯片12以半导体芯片12背面12d与芯片安装区域的上表面21a互为相对面的方式安装到芯片安装区域20a(面朝上安装)。图17所示的是将半导体芯片安装到图16所示的布线基板的芯片安装区域的工序的扩大剖面图。
由于本工序是以与所述第一安装半导体芯片的工序同样的步骤安装AFE芯片12a，所以不再进行重复的说明。另外，在将AFE芯片12a安装到芯片安装区域20b上时，相邻的芯片安装区域20C上已安装有VDR芯片12b。近年来，由于半导体芯片的厚度具有薄化的倾向，所以，本实施方式中的半导体芯片12的厚度可为0.15MM或比之更薄。因此，如果膏状粘合材料11a的配置量过多，配置在AFE芯片12a下的膏状粘合材料11a有可能湿扩散到安装了VDR芯片12b的芯片安装区域20C。因此，有可能出现膏状粘合材料11a的一部分溢出到VDR芯片12b的表面12c侧，从而出现膏状粘合材料11a覆盖VDR芯片12b的焊垫31的一部分或者全部的现象。但是，在本实施方式的所述第二粘合材料配置工序中，已尽量减少了膏状粘合材料11a的配置量。例如，配置在一个芯片安装区域20b中的膏状粘合材料11a的总量(总配置量)为0.1MG左右，且扩散到芯片安装区域20b中的膏状粘合材料11a的厚度约为10μM左右。因此，可以抑制配置在AFE芯片12a下的膏状粘合材料11a湿扩散到安装了VDR芯片12b的芯片安装区域20C。而且，本实施方式中，由于在芯片安装区域20b、20C之间形成有沟部26b，所以可确实防止膏状粘合材料11a扩散到安装了VDR芯片12b的芯片安装区域20C。另外，本实施方式中，与图8所示的芯片安装区域20C同样地，在芯片安装区域20b的下层配置有多条虚拟布线23d。因此，即使减少膏状粘合材料11a的配置量，也可使膏状粘合材料11a无间隙地扩散到整个芯片安装区域20b。由此，可防止及抑制空洞的产生。虚拟布线23d的理想形状及布局已在芯片安装区域20C中进行了说明，因此在此不再进行重复说明。
接下来的烘烤工序中，对安装了多个半导体芯片12的布线基板40进行加热，并使膏状粘合材料11a硬化。烘烤工序中，例如将安装了半导体芯片12的布线基板搬运到烘烤炉，再以超过膏状粘合材料11a的硬化温度的温度使其硬化。当膏状粘合材料11a的热硬化性树脂成分硬化后，就形成图3所示的粘合材料11，从而使半导体芯片12牢固地固定在绝缘膜26上。
另外，本实施方式中，在将多个VDR芯片12b安装到多个芯片安装区域20C后，实施第二粘合材料配置工序。理由是可以防止在切换所安装的半导体芯片12的种类时配置在芯片安装区域20a上的膏状粘合材料11a出现不良。但是，在使用可并列安装多种半导体芯片的芯片焊接装置时，也可更改本实施方式中说明的工序顺序。例如，在进行第一及第二粘合材料配置工序后，可进行第一及第二安装半导体芯片的工序。此时，为了安装多种半导体芯片12，虽然将导致芯片焊接装置的复杂化及大型化，但是可以一次性进行粘合材料配置工序。
另外，也可在所述第一安装半导体芯片的工序和第二粘合材料配置工序之间进行烘烤的工序。此时，可在VDR芯片12b已固定在绝缘膜26上的状态下实施第二安装半导体芯片的工序。但此时，由于在芯片焊接工序的过程中需增加搬运布线基板40的工序，为避免制造工序的繁琐化，优选如本实施方式所述的，在完成第二安装半导体芯片的工序后再进行烘烤工序。
4.引线焊接工序：
下面对图5所示的引线焊接工序S4进行说明。图18所示的是图5的引线焊接工序中的突起电极形成工序的扩大剖面图，图19所示的是进一步将图18的F部进行放大后的扩大剖面图。图20所示的是图5的引线焊接工序的扩大剖面图。
本实施方式中，将从半导体芯片12的绝缘膜(钝化膜)12f露出的焊垫31彼此连接，进行芯片-芯片间的连接。因此，图18及图19所示，突起电极形成工序就是在作为芯片-芯片间连接的第二接合侧的半导体芯片12(图17、图19所示的VDR12b)的焊垫31上形成金球焊(突起电极)32的工序。具体地说就是在如图19所示的引线焊接工序中，在作为第二接合侧的焊垫31e上形成金球焊32，而不在作为第一接合侧的焊垫31d上形成金球焊32。
形成金球焊32的方法中，可应用或适用引线焊接技术。本实施方式中，可通过图中未示出的电焊枪将如由金构成的焊线33的尖端形成为球状，通过毛细管61将之挤压并接合，再通过球焊法形成。为了将金球焊32与焊垫31e接合，可使用利用了热压方式及超音波振动的超音波方式、以及并用了这些方式的并用方式，本实施方式采用了并用方式。
接着，进行图20所示的引线焊接工序，即经由多条焊线13分别将两个芯片之间以及芯片与布线基板间进行电连接。在本工序的芯片-布线基板间的连接中，将半导体芯片12的焊垫31作为第一接合侧、将布线基板40的端子22作为第二接合侧，即所谓的正焊式进行引线焊接。另外，在进行芯片-芯片的连接时，将AFE芯片12a的焊垫31d作为第一接合侧、将VDR芯片12b的焊垫31e作为第二接合侧进行引线焊接。
引线焊接方式采用与所述突起电极形成工序同样的方式进行。下面参照图19进行说明。首先，通过图中未示出的电焊枪将例如由金构成的焊线33的尖端形成为球状，并通过毛细管61将之挤压到作为第一接合侧的焊垫31d。接合方式并用了前述的热压方式和超音波方式。接着，在送出焊线33的同时使毛细管61移动到第二接合侧并形成线圈形状，并将之接合到第二接合侧的金属(图19中为金球焊32)上。接合到第二接合侧后切断焊线33，由此可使两个半导体芯片12的焊垫31b之间经由焊线13进行电连接。毛细管在图中未示出，但在连接芯片与布线基板时，同样经由焊线13将图20所示的焊垫31a和端子22进行电连接。
另外，焊线13及金球焊32由金属构成，例如本实施方式中为由金(Au)构成。因此，如上所述，通过事先在半导体芯片12的焊垫31的表面形成金(Au)，就可提高焊线13和焊垫31之间的致密性。另外，如上所述，由于端子22的表面也形成有金(Au)膜，所以也可以提高焊线和端子22之间的致密性。
5.封装工序：
下面对图5所示的封装工序S5进行说明。图21所示的是在封装工序中所用的成型模具上配置布线基板，并供给封装用树脂的状态的扩大剖面图。图22所示的是，在图21所示的膜槽内填满封装用树脂后再使封装用树脂硬化的状态的扩大剖面图。
封装工序包括以下工序：准备成型模具的模具准备工序，在成型模具内配置安装了半导体芯片的布线基板的基材配置工序，使用成型模具夹住布线基板并夹紧的夹紧工序，向成型模具的膜槽内供给封装用树脂并形成封装体的封装体形成工序，以及从成型模具取出布线基板的基材取出工序。
下面通过本实施方式说明被称为MAP(Mold Allay Process)的制造方式。即在一个膜槽内配置具有按行列状配置的多个产品形成区域的布线基板，并对多个产品形成区域进行一次性封装。
首先，图21所示的模具准备工序中准备的成型模具71包括下表面72a并具有上模具(模具)72和下模具(模具)73。所述上模具(模具)72为在下表面72a侧形成有膜槽(凹部、凹陷部)72b，所述下模具(模具)73具有与下表面72a互为相对面的上表面73a。
膜槽72b由四角形的平面形状形成。上模具72中分别形成有沿着膜槽72b的1条边形成的多个栅极部(图中未示出)，以及沿着互为对边的边的多个排气阀部(图中未示出)。
在接下来的基材配置工序中，在成型模具71的下模具73上配置布线基板40。形成在与下模具73组合而成的上模具72上的膜槽72b具有比布线基板40中的多个器件区域40a更大的面积，本工序中，以一个膜槽72b内可装下多个器件区域40a的方式配置布线基板40。
其次，在夹紧工序中，缩短上模具72和下模具73间的距离，并用上模具72和下模具73夹紧布线基板40。
在接下来的封装体形成工序中，向膜槽72b内供给封装用树脂，并通过使其硬化而形成封装树脂。本工序中，通过传递模塑式形成封装树脂，所述传递模塑式为将配置在图中未示出的套筒部的树脂片进行加热并使其软化，再从栅部(图中未示出)向膜槽72b内供给封装用树脂的方式。树脂片例如可由热硬化性树脂即环氧树脂类树脂构成，具有在比硬化温度低的温度条件中，可通过加热使其软化，从而提高流动性的特性。因此，例如，在将通过图中未示出的柱塞进行软化的树脂片挤压入成型模具71内时，封装用树脂将从形成于成型模具71的栅部流入膜槽72b内(具体的是布线基板40的上表面21a侧)。而膜槽72b内的气体因封装用树脂的流入而产生的压力而从排气阀部(图中未示出)排出，膜槽72b内将被封装用树脂14a填满。结果，安装在布线基板40的上表面21a侧的多个半导体芯片12及多条焊线13将被封装用树脂14a封装。此时，由于封装用树脂14a也填满沟部26b，所以，在沟部26b中露出的布线23a也将被封装。
之后，通过对膜槽72b内进行加热，可使封装用树脂14a出现加热硬化(假硬化)，从而形成图22所示的封装体14。
接着，在基材取出工序中，将在上述封装工序中使用的成型模具71从图22所示的形成有封装体14布线基板40取出。
本工序中，将图22所示的上模具72的下表面72a和下模具73的上表面73a拉开，并取出形成了封装体14的一次性封装构造体。另外，本工序中还根据需要除去在所述的封装工序中产生的树脂溢出等。
6.烘烤工序：
下面说明图5所示的烘烤工序S6。
首先，将从成型模具71取出的布线基板40送到烘烤炉(图中未示出)内，并再次对布线基板40进行热处理。在成型模具71内被加热的封装用树脂14a中的硬化成分的一半以上(如70％左右)将成为硬化的状态，这就是所谓的假硬化状态。在此假硬化状态下，并非树脂中的所有硬化成分都硬化了，而仅是一半以上的硬化成分硬化了，此时，半导体芯片12及焊线13将被封装。但是，从提高封装体14的强度的稳定性的观点来看，优选将硬化成分完全硬化的状态，所以，在烘烤工序S6中，对假硬化的封装体14进行再加热，使其成为所谓的真硬化。如上所述，将使封装用树脂14a硬化的工序分两次进行，可对下一个送到成型模具71的布线基板40更快地实施封装工序。因此可提高制造效率。
7.植球工序：
下面说明图5所示的植球工序S7。图23所示的是在将多个焊球接合到布线基板上的状态的扩大剖面图。图23对应于按图9所示的C-C线剖开的剖面。
本工序中，将在图23所示的布线基板40的下表面21b侧形成的多个焊盘24分别安装多个焊接材料(焊球)28。具体是，首先，将图23所示的布线基板40的正反面倒置，并将多个焊接材料28分别配置到形成在布线基板40下表面21b侧的多个焊盘24上。接着，在配置了焊接材料28的布线基板40进行热处理(回流焊接)，使多个焊接材料28熔融且分别接合到多个焊盘24上。此时，如上所述，由于焊盘24的表面形成有电镀层，且由铜构成的焊盘24的表面为难于被氧化的状态，所以可抑制焊接材料28对于焊盘24的湿润性的降低。
另外，本工序中，为了使焊接材料28紧固接合到焊盘24上，如可使用被称为助焊剂的活性剂进行接合。如前所述使用助焊剂进行接合时，需在热处理后进行除去助焊剂成分的残渣的清洗作业。
8.划片工序：
下面说明图5所示的划片工序S8。图24所示的是将图23所示的布线基板及封装体进行划片工序的扩大剖面图。
本工序中，如图24所示，使切断夹具即划片刀50沿着器件区域40a的边界线(切割线)将布线基板40(请参照图23)及封装体14进行切割，将每个器件区域40a进行切割(划片)。通过本工序，可从一个布线基板获得图3所示的多个半导体器件2。
另外，例如，在所述植球工序S7后，将布线基板40的正反面倒置的状态下实施本工序，在下侧(即封装体14侧)贴有树脂薄膜(切割带)51的状态下从下表面21b侧开始进行切割。
之后，进行外观检查等必要的检查和实验后，便可制成半导体器件2。
以上按照实施方式具体地说明了本案发明人所作的发明，但是本发明并不受到所述实施方式的限定，在不超出其要旨的范围下能够进行种种变更，在此无需赘言。
<变形例1>
例如，在所述实施方式中，作为第一及第二粘合材料配置工序，如图11所示，使用吐出口45a已分歧为多个喷嘴45在芯片安装区域20a上(粘合材料和粘合材料配置区域11b上)的多处涂布膏状粘合材料11a的多点涂布方式进行了说明。但是，膏状粘合材料11a的涂布方式并不仅限于此，也可使用如图25及图26所示的带状涂布方式。图25所示的是相对于图9的变形例的扩大平面图，图26所示的是相对于图11的变形例的扩大剖面图。
图26所示的变形例中，将吐出口45a无分歧的喷嘴沿着图26中箭头所示的方向进行扫描，并使膏状粘合材料11a以带状进行涂布。此时，与所述实施方式中说明的多点涂布方式相比，将需要一定的扫描时间，所以从提高制造效率方面看，优选多点涂布方式。但是，带状涂布方式可使膏状粘合材料11a之间难于产生造成空洞产生原因的间隙。
<变形例2>
另外，在所述实施方式中，已对在各芯片安装区域20b、20C的下层配置多条虚拟布线23d的例子进行了说明，但是，也可为只在芯片安装区域20b、20C中的任意一个区域的下层形成多条虚拟布线23d的结构。此时，优选在后来安装的半导体芯片12的芯片安装区域20b上形成多条虚拟布线23d。通过在配置于多条虚拟布线23d上的芯片安装区域20b上后来安装AFE芯片12a(半导体芯片12)，可防止在已安装了VDR芯片12b(半导体芯片12)的表面12c上膏状粘合材料11a溢出。
<变形例3>
另外，在所述实施方式中，已对将多个半导体芯片12并列配置的例子进行了说明，但也可应用于在布线基板40上安装一个半导体芯片12的实施方式。此时，半导体芯片12的厚度越薄，膏状粘合材料11a就越有可能溢出到表面12c侧，但是在所述实施方式中所说明的芯片焊接工序中，通过应用一个半导体芯片12的安装工序，可防止以及抑制膏状粘合材料11a的溢出。
<变形例4>
另外，所述实施方式中，已对安装由长方形的平面形状构成的半导体芯片12的例子进行了说明，但也可应用于安装由图27所示的正方形的平面形状构成的半导体芯片80的半导体器件81。图27所示的是图2所示的变形例的平面图。图28所示的是在图27所示的半导体器件的制造方法中，芯片焊接工序的粘合材料配置工序的扩大平面图，图29所示的是形成在图28所示的芯片安装区域下层的虚拟布线的配置例的模式说明图。
图27所示的半导体器件81为图2所示的半导体器件2的变形例，在布线基板20的芯片安装区域20a上安装有一个由正方形的平面形状构成的半导体芯片80的方面，与半导体器件2存在不同。另外，半导体器件81中，在芯片安装区域20a的外围没形成有图2所示的沟部26b这一点上也存在不同。半导体芯片80例如为由图2所示的AFE芯片12a和VDR芯片12b一体形成的半导体芯片。
如上所述，在将正方形的半导体芯片80安装到布线基板上时，如图28所示，从减少膏状粘合材料11a的配置量的观点来看，将膏状粘合材料11a涂布到配置在连接芯片安装区域20a的各角部的两条对角线上的粘合材料配置区域11b的涂布方式(交叉涂布方式)最为有效。如上所述，通过交叉涂布方式来配置膏状粘合材料11a时，在接下来的半导体芯片安装工序中，膏状粘合材料11a将按图28中的箭头所示从粘合材料配置区域11b向芯片安装区域20a的外缘各边扩散。
因此，本变形例中，例如，如图29所示，通过使多条虚拟布线23d分别朝向芯片安装区域20a的四个边中距粘合材料配置区域11b最近的边延伸，由此，即使减少膏状粘合材料11a的配置量，也可抑制空洞的产生。这是由于通过缩短存在于半导体芯片80(请参照图27)和绝缘膜26之间的气体(例如空气)的移动距离，可易于将空气挤压到芯片安装区域20a的外侧的缘故。另外，虽然图29中未示出所述实施方式中所说明的多条布线23a，但实际上，在芯片安装区域20a的下层(核心层的上表面21a上)上配置有多条布线23a(请参照图8)。因此，多条虚拟布线23d选择形成在多条布线23a间距离大的区域中。另外，多条虚拟布线23d的形状及布局形态优选在所述实施方式的<关于本实施方式的虚拟布线的形状及布局的说明>中已进行说明，所以在此不再进行重复说明。
<变形例5>
另外，在所述变形例4中已对将半导体芯片80以所谓的面朝上的安装方式进行安装的形态进行了说明，但也可如图30及图31所示，将半导体芯片80以面朝下进行安装的方式也可适用于半导体器件82。图30所示的是相对于图27的变形例的平面图。图31所示的是沿着图30的G-G线剖开的剖面图。
图30及图31所示的半导体器件82为图27所示的半导体器件81的变形例，在使布线基板20的芯片安装区域20a与半导体芯片80的表面12c互为相对面的方式安装到布线基板20上这点上存在不同。也就是说，半导体器件82中，半导体芯片80是以面朝下的安装方式(倒装连接方式)进行安装的。如图30所示，由于面朝下的安装方式无需在背面12d侧形成图3所示的封装体14，可说是一种有利于半导体器件的薄型化的安装方式。另外，由于背面12d为露出的状态，所以即使在背面12d上再安装别的半导体芯片或堆积别的半导体器件，也可抑制整体厚度的增大。
另外，如图31所示，在面朝下的安装方式中，布线基板20的多个端子22形成在芯片安装区域20a内，半导体芯片80的焊垫31和端子22经由形成在焊垫31上的突起电极34电连接。具体地说就是，形成在端子22上的焊接材料35等的接合部材料和例如由金构成的突起电极34经由金-焊锡接合而被接合。如前所述的接合方式中，为了避免应力集中在焊垫31和端子22的接合部而产生接合不良，在半导体芯片80的表面12c和布线基板20(具体的说就是绝缘膜26)之间放入底部填充树脂以缓和应力的方法为有效的方法。
但是，为了使半导体芯片80的背面12d露出，从防止底部填充树脂迂回到半导体芯片80背面12d侧的观点出发，需要减少底部填充树脂的使用量。填充底部填充树脂的工序一般是将多个焊垫31和多个端子22接合后，填充于半导体芯片80和布线基板20之间，但如果底部填充树脂的量过少时，由于半导体芯片80和布线基板20之间的间隙狭小，所以填充时的静压将变大从而成为产生空洞的原因。而且，如果在底部填充树脂内产生空洞，将破坏应力缓和的平衡，从而导致应力集中在焊垫31和端子22的接合部而成为产生结合不良的原因。
因此，所述实施方式的芯片焊接工序中所说明的技术对防止在底部填充树脂内产生空洞为有效的技术。也就是说，通过将所述实施方式及变形例1～变形例4中所说明的粘合材料11及膏状粘合材料11a作为底部填充树脂，可以防止及抑制空洞的产生。另外，关于多条虚拟布线23d的形状及布局的优选形态，已在所述实施方式的<关于本实施方式的虚拟布线的形状及布局的说明>中进行了说明，所以在此不再进行重复说明。
产业上的可利性
本发明可应用于在布线基板上安装半导体芯片的半导体器件。

Claims (14)

1.一种半导体器件的制造方法，其特征在于，包括以下工序：
(a)准备布线基板的工序，所述布线基板包括：具有上表面及位于所述上表面相反一侧的下表面的核心层；形成在所述核心层的所述上表面上的多条第一布线及多条第二布线；形成在所述核心层的所述上表面上且与所述多条第一布线电连接的多条焊接引线；覆盖所述多条第一布线及所述多条第二布线，且以露出所述多条焊接引线的方式形成在所述核心层的所述上表面上的上表面侧绝缘膜；形成在所述核心层的所述下表面上，且与所述多条焊接引线分别电连接的多个焊盘；以及以露出所述多个焊盘的方式形成在所述核心层的所述下表面上的下表面侧绝缘膜；
(b)在第一芯片安装区域内的第一粘合材料配置区域配置具有流动性的第一粘合材料的工序，所述第一芯片安装区域设置在所述核心层的所述上表面上，且平面形状为长方形；
(c)经由所述第一粘合材料将第一半导体芯片安装到所述布线基板的所述第一芯片安装区域上，并使所述第一粘合材料扩散到所述第一粘合材料配置区域的外围的工序，其中，所述第一半导体芯片的平面形状为长方形且具有第一表面、形成在所述第一表面上的多个第一电极垫、以及位于所述第一表面的相反一侧的第一背面；
其中，所述第一芯片安装区域具有所述多条第一布线和所述多条第二布线，并在所述工序(b)中，将所述第一粘合材料配置在所述第一粘合材料配置区域中，该第一粘合材料配置区域配置在所述第一芯片安装区域中的、连接相互对置的2条短边各自中央的第一中央线上，且沿着所述第一中央线延伸，在所述工序(c)中，所述多条第二布线分别沿着所述第一粘合材料的扩散方向延伸。
2.根据权利要求1所述的半导体器件的制造方法，其特征在于，
所述多条第二布线的各条均不与所述多条第一布线及所述多条焊接引线连接。
3.根据权利要求2所述的半导体器件的制造方法，其特征在于，
所述多条第二布线分别沿着所述第一芯片安装区域的所述短边延伸。
4.根据权利要求3所述的半导体器件的制造方法，其特征在于，
所述多条第二布线各条的厚度与所述多条第一布线各条的厚度相同。
5.根据权利要求4所述的半导体器件的制造方法，其特征在于，
所述布线基板具有在所述核心层的所述上表面且在所述第一芯片安装区域的下层形成所述第二布线的第二布线配置区域和未形成所述第二布线的第二布线非配置区域，而且，所述第二布线配置区域中相邻的所述多条第一布线间的距离比所述第二布线非配置区域中相邻的所述多条第一布线间的距离大。
6.根据权利要求5所述的半导体器件的制造方法，其特征在于，
在所述多条第二布线的各条的延伸方向的延长线上不相邻地配置其他所述第二布线。
7.根据权利要求1所述的半导体器件的制造方法，其特征在于，
所述多条第二布线的一部分具有弯曲部。
8.根据权利要求1所述的半导体器件的制造方法，其特征在于，
所述多条第二布线的一部分分别朝向所述第一芯片安装区域的所述短边延伸。
9.根据权利要求1所述的半导体器件的制造方法，其特征在于，
在俯视观察时，所述多条第二布线配置在所述第一芯片安装区域内，且不延伸到所述第一芯片安装区域的外侧。
10.根据权利要求1所述的半导体器件的制造方法，其特征在于，
所述工序(c)中，以使所述第一半导体芯片的所述第一背面面向所述布线基板的所述第一芯片安装区域的方式安装所述第一半导体芯片。
11.根据权利要求1所述的半导体器件的制造方法，其特征在于，
所述工序(b)中，将所述第一粘合材料配置在所述第一粘合材料配置区域的多处。
12.根据权利要求1所述的半导体器件的制造方法，其特征在于，
所述工序(a)中所准备的所述布线基板，其平面形状为长方形，并具有配置在所述核心层的所述上表面侧的第二芯片安装区域，其中，以所述第二芯片安装区域的四个边中的一条长边与所述第一芯片安装区域的四个边中的一条长边互为对边的方式并列配置，
而且，还具有工序(d)和工序(e)，工序(d)是将第二粘合材料配置到所述第二芯片安装区域上的工序，工序(e)是经由所述第二粘合材料将第二半导体芯片安装到所述布线基板的所述第二芯片安装区域上的工序，其中，所述第二半导体芯片的平面形状为长方形，且所述第二半导体芯片具有第二表面、形成在所述第二表面上的多个第二电极垫、以及位于所述第二表面相反一侧的第二背面，
其中，所述工序(c)在所述工序(e)之后进行。
13.根据权利要求12所述的半导体器件的制造方法，其特征在于，
所述工序(a)中准备的所述布线基板，在所述第二芯片安装区域的下层形成所述多条第一布线及所述多条第二布线，所述工序(d)中，将所述第二粘合材料配置在第二粘合材料配置区域中，该第二粘合材料配置在连接所述第二芯片安装区域的四个边中对置的短边各自中央的第二中央线上，且沿着所述第二中央线延伸；
所述工序(e)包括使在工序(d)中配置的所述第二粘合材料扩散到所述第二粘合材料配置区域的外围的工序，
在所述工序(e)中，配置在所述第二芯片安装区域下层的所述多条第二布线分别沿着所述第一粘合材料的扩散方向延伸。
14.一种半导体器件的制造方法，其特征在于，包括以下工序：
(a)准备布线基板的工序，所述布线基板包括：具有上表面及位于所述上表面相反一侧的下表面的核心层；形成在所述核心层的所述上表面上的多条第一布线及多条第二布线；形成在所述核心层的所述上表面上且与所述多条第一布线电连接的多条焊接引线；覆盖所述多条第一布线及所述多条第二布线，且以露出所述多条焊接引线的方式形成在所述核心层的所述上表面上的上表面侧绝缘膜；形成在所述核心层的所述下表面，且与所述多条焊接引线分别电连接的多个焊盘；以及以露出所述多个焊盘的方式形成在所述核心层的所述下表面的下表面侧绝缘膜；
(b)在芯片安装区域内的粘合材料配置区域配置具有流动性的粘合材料的工序，所述芯片安装区域设置在所述核心层的所述上表面侧，且平面形状为四边形；
(c)经由所述粘合材料将半导体芯片安装到所述布线基板的所述芯片安装区域上，并使所述粘合材料扩散到所述粘合材料配置区域的外围的工序，其中，所述半导体芯片的平面形状为四边形且所述半导体芯片具有表面、形成于所述表面的多个电极垫、以及位于所述表面的相反一侧的背面；
其中，所述芯片安装区域具有所述多条第一布线及所述多条第二布线，所述多条第二布线的每一条朝向所述芯片安装区域的四个边中距所述粘合材料配置区域最近的边延伸。
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TW201209941A (en) 2012-03-01
JP5503466B2 (ja) 2014-05-28
TWI525719B (zh) 2016-03-11
KR20120021278A (ko) 2012-03-08
KR101811063B1 (ko) 2017-12-20

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