CN102265393A - 电气的或者电子的复合构件以及用于制造该复合构件的方法 - Google Patents
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Abstract
本发明涉及一种电气的或者电子的复合构件(1),所述复合构件(1)包括第一接合部件(2)以及至少一个第二接合部件(3)。按本发明规定,在所述第一和第二接合部件(2,3)之间容纳有开口多孔的烧结成形件(6,7),所述烧结成形件与第一和第二接合部件(2,3)牢固地连接。
Description
技术领域
本发明涉及一种按权利要求1的前序部分所述的电气的或者电子的复合构件以及一种按权利要求8所述的用于制造电气的或者电子的复合构件的方法。
背景技术
功率半导体,如JFET,MOSFET,IGBT或者二级管与功率电子的结构组件的线路支架的接合以及还有将线路支架接合到基板/降温器上典型地在软焊料技术中实现。根据新的欧盟立法,将来会禁止使用含铅的软焊料合金(Sn63Pb37和Sn5Pb95)。基于SnAgCu的无铅的软焊料合金能够作为代用合金仅仅有条件地得到使用,因为所述软焊料合金就其可靠性特别是在被动的和主动的温度交变负荷中受到限制。替代的高熔点的软焊料作为代用合金或者在使用中太脆(Bi97,5Ag2,5)或者太贵(Au80Sn20)。
作为替代的、高温稳定的以及高度可靠的接合技术,已知借助银膏直接烧结接合部件。这种技术被称为低温连接技术(NTV)。在此,在两个不同的实施方案之间是有区别的,也就是如在EP 2 246 26 B1中描述的银金属薄片的烧结,以及如在WO 2005/079353
A2中描述的银金属纳米颗粒的烧结。在烧结过程中,所述(烧结)颗粒不同于钎焊过程不会成为液体的状态,也就是说,其不会熔化。
在银金属薄片的烧结过程中,用于燃烧研磨蜡(Mahlwachse)的大气中的氧气需要大约240℃的温度以及大约40Mpa的高的过程压力。所述银金属纳米颗粒的烧结提供了这样的选则,即利用明显更小的从大约100kPa到5MPa之间的压力范围中的压力来实施烧结过程。如在银金属薄片的烧结过程中一样,在纳米颗粒的烧结过程中也需要氧气以及大约280℃的过程温度。此外所述已知的银金属纳米颗粒膏状成形件(Pastenformulierung)还包括比基于银金属薄片的膏状成形件还更高的有机成份(Organikanteil)、例如溶剂和/或接合剂。在所述已知的方法中,烧结膏直接施加在所述第一和/或第二接合部件上,紧接着所述接合部件在温度影响下彼此相对地挤压。在利用烧结膏进行过程控制时存在必须将大的气体体积通过烧结的层进行替换的困难;如此氧气必须到达接合位置并且所述溶剂以及燃烧的/氧化的有机物(Organik)必须具有排出的可能性。这样特别地在期望的较低的过程压力下导致加大的裂缝,特别是在大面积的接合的情况下。
发明内容
本发明的任务在于,提出一种电子的或者电气的复合构件以及一种用于这样的复合构件的制造方法,在该方法中在接合时能够避免形成裂缝。优选所述复合构件应该可以成本低廉地制造并且在温度交变负荷下是可靠的。
这个任务关于所述电子的或者电气的复合构件利用权利要求1中的特征来解决并且关于制造方法利用权利要求8的特征来解决。本发明的有利的改进方案在从属权利要求中给出。说明书、权利要求和/或附图中公开特征的至少两个特征的全部组合落入本发明的范围中。为了避免重复,按装置公开的特征适于作为按方法公开的特征并且可要求保护。按方法公开的特征同样也适于作为按装置公开的特征并且可要求保护。
本发明的思路在于,至少两个接合部件不像现有技术中一样直接借助烧结膏互相连接,也就是说彼此固定,而是所述接合部件在放弃烧结膏的情况下牢固地与事先制造的具有贯穿打开的孔隙结构(Porosität)的烧结成形件连接。在此优选要使用的烧结成形件(烧结薄膜)在接合部件的堆叠方向上的厚度延伸在大约10
和300之间或者更多。这样的烧结成形件拥有例如通过钎焊、熔焊或者粘接构造成的接合位置的已经集成的以及在接下来的与接合部件的接合过程中用于换气和排气的坚固的气体通道的优点。将所述多孔的烧结成形件作为插入部分或者说嵌入部分的使用积极地作用在用于接合所述接合部件与所述烧结成形件的接合过程中,特别是当大面积的接合部件如硅功率半导体与线路支架或者线路支架与降温器和烧结成形件相连接时。冲压格栅也能够通过烧结成形件连接。使用烧结成形件的另一个优点在于,所述接合位置的设计的自由度扩大了,因为所述烧结成形件能够比接合部件中的至少一个具有更大的面积、优选比两个接合部件都具有更大的面积,和/或所述接合部件能够明显地比在根据现有技术进行过程控制时,也就是在借助烧结膏直接烧结所述接合部件时更远地互相隔开。所述优点特别地在于提高了温度交变稳定性。
本发明能在电子的和/或电气的多种应用情况下使用。特别优选的是在功率电子的模块中的实现,所述模块例如对于许多能量变换的方式是必需的,所述能量变换的方式特别是机械的/电气的(发电机,整流器)、电气的/电气的(换流器,AC/AC,DC/DC)以及电气的/机械的(电驱动装置,逆变整流器(Wechselrichtung))。此外,相应地构造的功率电子模块能够为了整流在汽车发电机中使用以控制电驱动装置、用于DC/DC变换器、用于脉冲逆变整流器、用于混合动力/燃料电池/电驱动以及用于光电的逆变整流器等等。各个结构元件也能够附加地或者替代地以更高的消耗功率特别是在离散包装(Packages)的冲压格栅上按照本发明接合,各个结构元件然后例如对于不用铅的情况作为完全无铅的解决方案能够在电路板技术中使用。
特别优选的是,本发明在具有半导体激光二极管的构造中或者对于存储器以及传感器,特别是对于高温应用得以实现。其它的应用实例是用于雷达应用情形的半导体发光二极管与高频半导体。
完全特别优选的是所述复合构件的实施方式,在所述实施方式中所述烧结成形件是由银金属、特别是银金属薄片制造的和/或包括银金属、特别是银金属薄片。由银金属制造的或者包括银金属的烧结成形件鉴于较高的电和热的传导能力而具有优点。此外,银适合用于实现贯穿打开的构成气体通道的孔隙结构。
就所述至少两个接合部件与所述烧结成形件的接合而言存在不同的方案,其中,在本发明的范围中对于两个接合部件存在同样的方法或者不同的方法供选择。按照第一替代方案,第一和/或第二接合部件与所述烧结件烧结在一起,更确切地说不用附加的烧结膏地烧结在一起。为此必须使用仅仅足够的压力和温度,从而使得所述烧结成形件相对于至少一个接合部件进行连接,也就是说能够烧结。
替代地能够将至少一个接合部件优选两个接合部件与所述烧结成形件优选通过使用焊膏、焊接粉末或者焊接成形件(总体说来:焊接材料)进行钎焊。所述焊接材料在此通过温度影响转变为液体状态并且将所述烧结成形件与至少一个焊剂固件连接起来。完全特别优选的是,所述焊接材料例如是无铅的焊膏,其中然而也考虑使用含铅的焊膏,特别是标准焊膏。根据所述使用的烧结成形件的多孔的结构,该烧结成形件突出地适合实现结实的钎焊连接。这首先归因于带有所有的贯通的焊接材料的所述烧结成形件的良好的可湿润性,特别是当所述烧结成形件至少部分地由银金属特别是银金属薄片制成时。所述烧结成形件的“缓冲”效果明显地减轻了由机械热应力带来的特别是在后来使用所述电气的或电子的复合构件期间对纯粹的焊接材料产生破坏的影响。优选要使用的焊接材料特别是焊膏或者不仅涂在特别是压在或者分配在所述焊剂固件上而且涂在特别是压在或者分配在作为沉淀物使用的烧结成形件上,或者替代地仅仅涂在特别是压在或者分配在所述烧结成形件的两侧上,或者进一步替代地仅仅涂在特别是压在或者分配在所述烧结成形件的一侧上以及仅仅一个焊剂固件上。所述在钎焊过程中产生的气体能够最优化地通过由所述烧结成形件的孔隙结构构成的气体通道排出。也能够在本来的钎焊过程之前的用于装备SMD部件的焊膏压制过程以及在紧接着的反流钎焊(Reflow-Loten)中将焊接沉淀物施加在后来的接合位置上。在这种情况下仅仅在这些位置上还需要涂覆助焊剂。所述烧结成形件的多孔的结构在此带来了对于助焊剂系统的排气而言足够的方案。
将至少一个接合部件与所述烧结成形件连接的其它的方案在于,将所述接合部件与烧结成形件粘接特别是通过导电粘接(Leitkleben)在一起。在此进一步优选使用含银的(用银填充的)粘接剂,所述粘接剂在烧结成形件中找到理想的连接表面。
此外能够将所述接合部件的至少一个与所述烧结成形件通过熔焊,特别是摩擦熔焊、超声熔焊或者电阻熔焊进行连接。所述优选的含银的或者说由银制成的烧结成形件的上表面能够最优化地在熔焊过程中与至少一个接合部件、优选两个接合部件连接。
在构造所述第一和第二接合部件时最不同的方案,所述不同的方案导致最不同的复合构件。完全特别优选的是,所述第一接合部件是电子构件、优选半导体构件、完全特别优选是功率半导体,所述电子构件通过烧结成形件与所述第二焊接件、特别是线路支架(线路板)是可以连接的。同样可能的是,作为线路支架构造的第一接合部件通过烧结成形件与优选作为基板特别是铜制基板的第二接合部件相连接。优选将所述铜制的基板用作降温器或者与作为降温器使用的散热体连接。所述散热体(第一接合部件)也能够与基板(第二接合部件)通过烧结成形件互相连接。此外可以的是,通过烧结成形件至少一个接合线(Bonddraht)或者至少一个接合带(Bondbändchen)能够与其它的接合部件,特别是电子构件,优选半导体构件,特别是功率半导体构件或者线路支架(电构件)相连接,也就是说相接触。在此,所述烧结成形件使得可靠性提高。同样可以的是,所述第一接合部件例如是电气的构件,特别是冲压格栅(导电格栅),所述电气的构件通过烧结成形件与第二接合部件,特别是线路支架,更准确地说与所述线路支架的金属是可以连接的。到目前为止冲压格栅直接钎焊到线路板(线路支架)上,由此经常引起封闭的气孔/空心腔(缩孔)。此外,在已知的过程控制中接缝强烈波动,从而在温度载荷和温度交变载荷下的可靠性不能在每种情况下给出或者说被保证。其它的由权利要求得出的第一和第二接合部件的组合是可以实现的。
烧结成形件的使用不局限于只带有两个接合部件的复合组件。例如可设想的是,制造带有两个或者更多烧结成形件的复合构件,其中总是通过烧结成形件将至少两个接合部件互相固定在一起。通过这种方式能够制成出三明治形状的包括三个或更多接合部件的结构,其中所述接合部件以及烧结成形件优选在堆积方向上堆积。如此例如由功率半导体构成的第二接合部件能够在两个侧面各通过一个烧结成形件与构成第一或者说第二接合部件的线路支架相连接,从而所述功率半导体三明治状地容纳在所述线路支架之间,并且其中烧结成形件总是位于线路支架与功率半导体之间。所述三明治结构不必须强制地在工艺步骤中实现,而是也能够例如制成两级或者多级的。
本发明也涉及用于制造电子的或者电气的复合构件的方法,优选像之前描述的一样构造的复合构件。所述方法的核心是,将至少两个接合部件与开口多孔的烧结件(烧结薄膜)连接起来,优选通过放弃烧结膏直接烧结,通过借助焊接材料钎焊,特别是利用无铅的焊接材料,优选利用焊膏,借助粘接,特别是导电粘接,优选使用含银的粘接剂或者替代地通过熔焊,特别是摩擦熔焊、超声熔焊或者是电阻熔焊。按本发明的方法的优点在于,通过所述烧结成形件的连续的开口多孔的结构,在与所述焊剂固件连接的连接过程中产生的气体溢出,并且在需要时气体、如氧气能够导入焊剂位置,从而避免形成裂缝。优选实现从侧向也就是横向于所述焊剂固件的堆积方向实现气体排出以及的气体供给。
附图说明
本发明的其它优点、特征以及细节从接下来的对优选的实施例的描述中以及根据附图得出。
附图示出:
图1是功率电子的(leistungselektronisch)复合构件(这里指功率电子的结构组件/模块),
图2局部示出用于互相连接两个接合部件的烧结成形件,
图3示意性示出用于制造包括两个接合部件的电气的或电子的复合构件的制造过程,以及
图4示意性地示出利用三个接合部件和两个烧结成形件来制造电气的或者电子的复合构件的制造过程。
在图中相同的元件以及具有同样功能的元件利用同样的附图标记标示出来。
具体实施方式
图1示出了电子的复合构件1。所述复合构件包括第一接合部件2、第二接合部件3以及第三接合部件4。在示出的实施例中,所述第一接合部件2是功率半导体结构元件,这里指IGB晶体管。所述第二接合部件3是线路支架并且所述第三接合部件4是铜制的基板。所述铜制的基板又固定在散热体5(降温器)上。
在第一接合部件2与第二接合部件3之间在堆积方向S上利用大约50的厚度延伸布置有烧结成形件6。所述第一接合部件2以及第二接合部件3分别通过借助焊膏(替代地例如是焊接粉末或焊接成形件)的钎焊固定在所述烧结成形件6的两个相互背离的侧面上。所述烧结成形件6由银烧结材料形成。所述第二焊剂固件3又通过其它的烧结成形件7与所述第三接合部件4相连接,所述其它的烧结成形件像所述烧结成形件6一样地构造,其中,所述第三接合部件4以及所述第二固件3也各通过钎焊牢固地与所述其它的烧结成形件7连接。替代地,所述烧结成形件6,7的互相不同的成形方式(Ausformung)也是可能的。
在示出的实施例中,所述第三接合部件4和所述散热体5直接钎焊在一起。替代地(没有示出)在所述第三接合部件4与所述散热体5之间也能够设有烧结成形件,通过该烧结成形件所述第三接合部件4和所述散热体5例如通过不用烧结膏的直接烧结,通过钎焊、粘接或者熔焊固定在一起。
如图1进一步得出,在所述由基板构成的第三焊剂固件4上固定有塑料壳体8,所述塑料壳体8包围堆积布置结构,该堆积布置结构包括所述第一和第二焊剂固件2,3以及所述烧结成形件6。所谓的堆积布置结构被弹性的保护质量9包围。穿过所述保护质量连接导线10,11引导直到所述壳体8 的外侧上,所述连接导线通过所述烧结成形件6与所述第二焊剂固件3接触地固定在所述第二焊剂固件3(线路支架)上。
图2示出了烧结成形件6的结构,所述烧结成形件由银金属薄片(Silbermetall-Flakes)制造。从中能够识别出贯穿地打开的孔隙结构。该孔隙结构构成气体流通通道,通过所述气体流通通道气体能够从接合位置向外或者说向接合位置流动。所述气体优选从侧面溢出,也就是横向于堆积方向S(参看图1)从孔或者说从构成孔的所述气体通道溢出,由此,特别是在可能发生的钎焊过程中避免形成裂纹。
图3非常示意性地示出了用于制造在该附图平面右侧示出的电气的或者电子的复合构件1的制造过程。该复合构件包括在附图平面上部的第一接合部件2以及在附图平面下部的第二接合部件3,在所述第一接合部件和第二接合部件之间三明治状地容纳有烧结成形件6。所述第一接合部件2例如是芯片(Chip)并且所述第二接合部件3是线路支架。替代地可考虑的是,所述第一接合部件2是线路支架并且所述第二接合部件3是特别由铜制成的基板和/或散热体(降温器)。其它的从权利要求中得出的所述第一和第二接合部件2,3的组合是可替代地实现的。在示出的实施例中在所述烧结成形件6的两个平面侧上首先涂上作为沉淀物(Depot)的焊接材料12,特别是焊膏或者焊接成形件。在钎焊之前优选在接合位置上涂覆助焊剂。在堆积方向S上的堆积之后,将所述接合部件2,3、所述烧结成形件6以及焊接材料12提供给接合过程13,这里是指钎焊过程。用于钎焊所述焊接材料12的气体交换能够在所述烧结成形件6的整个多孔的体积上开始。
借助图3也可解释替代的接合过程。这样例如所述第二接合部件3能够是线路支架,特别是线路支架的金属,典型地是铜或者铜合金,并且所述第一接合部件2是典型地由铜或者铜合金制成的冲压格栅。粘合材料14特别是含银的粘合材料14能够例如压在或者分配(dispenst)在所述第二接合部件3上。在需要时,所述烧结成形件6已经能够在用于述第一接合部件2(冲压格栅)的对置面上带来粘合材料沉淀物。所述粘合材料14替代地在后置的过程中、例如分配过程中作为粘合材料沉淀物进行涂覆。紧接着将所述第一接合部件2放到所述粘合材料14上并且优选在温度和/或压力影响下进行硬化过程。所述粘合材料14或者说其组成部分能够通过所述烧结成形件的多孔的结构排气。
此外,替代地所述接合部件2,3的至少一个可以通过熔焊与所述烧结成形件6连接。所述熔焊过程能够但不是强制必须地借助辅助材料15实施。对于放弃辅助材料的情况,按图3的辅助材料沉淀物不是必须的。
图4在附图平面右侧示出了多部件式的电气的或者电子的复合构件1。所述复合构件1总共包括三个接合部件2,3,4,其中,在每两个接合部件2,3;3,4之间分别布置有烧结成形件6,7。例如,所述第一和第三接合部件2,4能够是线路支架并且所述位于中央的也就是说内部的接合部件3能够是功率半导体。所述三明治结构在共同的接合过程中并不是强制必须接合的,而是也可以实现两级的顺序的过程控制,例如首先是第一接合部件2、烧结成形件6、第二接合部件3并且然后紧接着是第三接合部件4,或者可替代地首先是所述第三接合部件4、所述另一个烧结成形件7、所述第二接合部件3并且然后是后置的所述第一接合部件2。
Claims (17)
1. 电气的或者电子的复合构件(1),其包括第一接合部件(2)以及至少一个第二固件(3),
其特征在于,
在所述第一和第二接合部件(2,3)之间容纳有开口多孔的烧结成形件(6,7),所述烧结成形件与所述第一和第二接合部件(2,3)牢固地连接。
2. 按权利要求1所述的复合构件,
其特征在于,
所述烧结成形件(6,7)由银金属、特别是银金属薄片制成和/或包括银金属、特别是银金属薄片。
3. 按权利要求1或2所述的复合构件,
其特征在于,
所述第一和/或第二接合部件(2,3)与所述烧结成形件(6)无附加的烧结膏地直接烧结在一起,或者特别是借助焊膏进行钎焊,或者熔焊,特别是超声熔焊,或者粘接。
4. 按上述权利要求中任一项所述的复合构件,
其特征在于,
所述第一接合部件(2)是电子构件,优选是半导体构件,特别是功率半导体构件,或者是线路支架,特别是线路支架的金属镀层,或者是冲压格栅,或者是接合线,或者是接合带,或者是基板。
5. 按上述权利要求中任一项所述的复合构件,
其特征在于,
所述第二接合部件(3)是电子构件,优选半导体构件,特别是功率半导体构件,或者是线路支架,特别是线路支架的金属镀层,或者是基板,优选铜制的基板,或者是散热体(5)。
6. 按上述权利要求中任一项所述的复合构件,
其特征在于,
在所述第一接合部件(2)与第三或者第四接合部件(4)之间容纳有其它的烧结成形件(7,6),和/或在所述第二接合部件(3)与第三或者第四接合部件之间容纳有其它的烧结成形件(7),所述烧结成形件优选不用烧结膏地直接与相邻的接合部件(2,3,4)烧结、钎焊、熔焊或者粘接在一起。
7. 按权利要求6所述的复合构件,
其特征在于,
所述第三和/或第四接合部件(4)是电子构件,优选是半导体构件,特别是功率半导体构件,或者是线路支架,特别是线路支架的金属镀层,或者是基板,优选铜制的基板,或者是散热体(5)。
8. 用于制造优选根据上述权利要求之一所述电气的或者电子的复合构件(1)的方法,在所述方法中第一和第二接合部件(2,3)与开口多孔的烧结成形件(6)牢固地连接。
9. 按权利要求8所述的方法,
其特征在于,
所述第一和第二接合部件(2,3)固定在所述烧结成形件(6,7)的两个互相背离的侧面上。
10. 按权利要求8或9所述的方法,
其特征在于,
所述第一和/或第二接合部件(2,3)不用焊膏地直接与所述烧结成形件(6,7)烧结,优选在共同的烧结区段中在温度和/或压力影响下烧结。
11. 按权利要求8到10中任一项所述的方法,
其特征在于,
所述第一和/或第二接合部件(2,3)特别是借助焊膏与所述烧结成形件(6,7)钎焊在一起。
12. 按权利要求11所述的方法,
其特征在于,
所述焊膏,优选附加地助焊剂,在接合之前涂在优选压在或者分配在所述第一接合部件(2)和/或所述第二接合部件(3)和/或所述烧结成形件(6,7)上。
13. 按权利要求8到12中任一项所述的方法,
其特征在于,
所述第一和/或第二接合部件(2,3)与所述烧结成形件(6)特别是利用或者不用辅助材料(15)地熔焊在一起。
14. 按权利要求8到13中任一项所述的方法,
其特征在于,
所述第一和/或第二接合部件(2,3)与所述烧结成形件(6)特别是利用或者不用辅助材料(15)地熔焊优选超声熔焊在一起。
15. 按权利要求8到14中任一项所述的方法,
其特征在于,
在所述第一接合部件(2)与第三或者第四接合部件(4)之间设有其它的烧结成形件(7,6),和/或在所述第二接合部件(3)与第三或者第四接合部件之间设有其它的烧结成形件(7,6),所述其它的烧结成形件优选直接与相邻的接合部件(2,3,4)烧结、钎焊、熔焊或者粘接在一起。
16. 按权利要求15所述的方法,
其特征在于,
所述其它的烧结成形件(7,6)在所述第一或者第二接合部件(2,3)上的固定以及所述烧结成形件(6,7)在所述第一和第二接合部件(2,3)上的固定在共同的工艺步骤中或在单独的工艺步骤中实施。
17. 按权利要求8到16中任一项所述的方法,
其特征在于,
烧结部分被分隔成多个烧结成形件(6,7)。
Applications Claiming Priority (3)
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DE102008055134.1 | 2008-12-23 | ||
DE102008055134A DE102008055134A1 (de) | 2008-12-23 | 2008-12-23 | Elektrisches oder elektronisches Verbundbauteil sowie Verfahren zum Herstellen eines elektrischen oder elektronischen Verbundbauteils |
PCT/EP2009/066518 WO2010072555A1 (de) | 2008-12-23 | 2009-12-07 | Elektrisches oder elektronisches verbundbauteil sowie verfahren zum herstellen eines elektrischen oder elektronischen verbundbauteils |
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US (1) | US20110304985A1 (zh) |
EP (1) | EP2382659A1 (zh) |
JP (1) | JP5602763B2 (zh) |
CN (1) | CN102265393A (zh) |
AU (1) | AU2009331707A1 (zh) |
DE (1) | DE102008055134A1 (zh) |
WO (1) | WO2010072555A1 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105633039A (zh) * | 2014-11-26 | 2016-06-01 | 意法半导体股份有限公司 | 具有引线键合和烧结区域的半导体器件及其制造工艺 |
CN107660308A (zh) * | 2015-06-01 | 2018-02-02 | 西门子公司 | 用于借助于开孔接触件的电镀式连接来使组件电接触的方法和相应的组件模块 |
CN114846598A (zh) * | 2019-12-26 | 2022-08-02 | 三菱电机株式会社 | 功率模块和电力变换装置 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102011083931A1 (de) * | 2011-09-30 | 2013-04-04 | Robert Bosch Gmbh | Schichtverbund aus einem elektronischen Substrat und einer Schichtanordnung umfassend ein Reaktionslot |
DE102011083926A1 (de) * | 2011-09-30 | 2013-04-04 | Robert Bosch Gmbh | Schichtverbund aus einer Trägerfolie und einer Schichtanordnung umfassend eine sinterbare Schicht aus mindestens einem Metallpulver und eine Lotschicht |
JP6287789B2 (ja) * | 2014-12-03 | 2018-03-07 | 三菱電機株式会社 | パワーモジュール及びその製造方法 |
DE102015113421B4 (de) * | 2015-08-14 | 2019-02-21 | Danfoss Silicon Power Gmbh | Verfahren zum Herstellen von Halbleiterchips |
US9655280B1 (en) * | 2015-12-31 | 2017-05-16 | Lockheed Martin Corporation | Multi-directional force generating line-replaceable unit chassis by means of a linear spring |
CN110447094B (zh) | 2017-03-30 | 2023-12-12 | 三菱电机株式会社 | 半导体装置及其制造方法、及电力变换装置 |
DE102017206930A1 (de) * | 2017-04-25 | 2018-10-25 | Siemens Aktiengesellschaft | Lotformteil zum Diffusionslöten, Verfahren zu dessen Herstellung und Verfahren zu dessen Montage |
DE102017217537B4 (de) | 2017-10-02 | 2021-10-21 | Danfoss Silicon Power Gmbh | Leistungsmodul mit integrierter Kühleinrichtung |
DE102020102876B4 (de) | 2020-02-05 | 2023-08-10 | Infineon Technologies Ag | Elektronisches Bauelement, Herstellungsverfahren dafür und Verfahren zur Herstellung eines elektronischen Moduls dieses aufweisend mittels eines Sinterverfahrens mit einer Opferschicht auf der Rückseitenmetallisierung eines Halbleiterdies |
EP4283662A1 (en) * | 2022-05-23 | 2023-11-29 | Hitachi Energy Switzerland AG | Method of attaching a terminal to a metal substrate structure for a semiconductor power module and semiconductor power module |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4856185A (en) * | 1986-12-22 | 1989-08-15 | Siemens Aktiengesellschaft | Method for fastening electronic components to a substrate using a film |
JPH0951060A (ja) * | 1995-08-09 | 1997-02-18 | Mitsubishi Materials Corp | パワーモジュール用基板の端子構造 |
US5654586A (en) * | 1993-05-07 | 1997-08-05 | Siemens Aktiengesellschaft | Power semiconductor component having a buffer layer |
US20030020159A1 (en) * | 2000-02-29 | 2003-01-30 | Herbert Schwarzbauer | Heat-conducting adhesive compound and a method for producing a heat-conducting adhesive compound |
CN101304017A (zh) * | 2007-05-12 | 2008-11-12 | 塞米克朗电子有限及两合公司 | 烧结的功率半导体基片及其制造方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CH387809A (de) * | 1961-11-17 | 1965-02-15 | Bbc Brown Boveri & Cie | Lötverbindung an einem Halbleiterelement |
DE3575829D1 (de) | 1985-10-30 | 1990-03-08 | Ibm | Synchronisiertes system fuer mehrere signalprozessoren. |
IN168174B (zh) * | 1986-04-22 | 1991-02-16 | Siemens Ag | |
US4965659A (en) * | 1987-06-30 | 1990-10-23 | Sumitomo Electric Industries, Ltd. | Member for a semiconductor structure |
DE4040753A1 (de) * | 1990-12-19 | 1992-06-25 | Siemens Ag | Leistungshalbleiterbauelement |
US5561321A (en) * | 1992-07-03 | 1996-10-01 | Noritake Co., Ltd. | Ceramic-metal composite structure and process of producing same |
US5527627A (en) * | 1993-03-29 | 1996-06-18 | Delco Electronics Corp. | Ink composition for an ultra-thick thick film for thermal management of a hybrid circuit |
DE59611448D1 (de) * | 1995-09-11 | 2007-12-06 | Infineon Technologies Ag | Verfahren zur Befestigung elektronischer Bauelemente auf einem Substrat durch Drucksintern |
US6717819B1 (en) * | 1999-06-01 | 2004-04-06 | Amerasia International Technology, Inc. | Solderable flexible adhesive interposer as for an electronic package, and method for making same |
JP2000349100A (ja) * | 1999-06-04 | 2000-12-15 | Shibafu Engineering Kk | 接合材とその製造方法及び半導体装置 |
JP2004298962A (ja) * | 2003-03-17 | 2004-10-28 | Mitsubishi Materials Corp | はんだ接合材及びこれを用いたパワーモジュール基板 |
KR20070033329A (ko) | 2004-02-18 | 2007-03-26 | 버지니아 테크 인터렉추얼 프라퍼티스, 인크. | 인터커넥트를 위한 나노 크기의 금속 페이스트 및 이의사용 방법 |
WO2005098942A1 (ja) * | 2004-04-05 | 2005-10-20 | Mitsubishi Materials Corporation | Ai/ain接合体、パワーモジュール用基板及びパワーモジュール並びにai/ain接合体の製造方法 |
DE102004056879B4 (de) * | 2004-10-27 | 2008-12-04 | Curamik Electronics Gmbh | Verfahren zum Herstellen eines Metall-Keramik-Substrates |
JP4770533B2 (ja) * | 2005-05-16 | 2011-09-14 | 富士電機株式会社 | 半導体装置の製造方法および半導体装置 |
CN101273450A (zh) * | 2005-09-28 | 2008-09-24 | 日本碍子株式会社 | 散热模块及其制造方法 |
DE102005047566C5 (de) * | 2005-10-05 | 2011-06-09 | Semikron Elektronik Gmbh & Co. Kg | Anordnung mit einem Leistungshalbleiterbauelement und mit einem Gehäuse sowie Herstellungsverfahren hierzu |
DE102006009159A1 (de) * | 2006-02-21 | 2007-08-23 | Curamik Electronics Gmbh | Verfahren zum Herstellen eines Verbundsubstrates sowie Verbundsubstrat |
JP4826426B2 (ja) * | 2006-10-20 | 2011-11-30 | 株式会社デンソー | 半導体装置 |
JP2008153470A (ja) * | 2006-12-18 | 2008-07-03 | Renesas Technology Corp | 半導体装置および半導体装置の製造方法 |
JP2009094385A (ja) * | 2007-10-11 | 2009-04-30 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
-
2008
- 2008-12-23 DE DE102008055134A patent/DE102008055134A1/de not_active Withdrawn
-
2009
- 2009-12-07 EP EP09764842A patent/EP2382659A1/de not_active Withdrawn
- 2009-12-07 CN CN2009801522006A patent/CN102265393A/zh active Pending
- 2009-12-07 JP JP2011542749A patent/JP5602763B2/ja not_active Expired - Fee Related
- 2009-12-07 US US13/141,947 patent/US20110304985A1/en not_active Abandoned
- 2009-12-07 WO PCT/EP2009/066518 patent/WO2010072555A1/de active Application Filing
- 2009-12-07 AU AU2009331707A patent/AU2009331707A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4856185A (en) * | 1986-12-22 | 1989-08-15 | Siemens Aktiengesellschaft | Method for fastening electronic components to a substrate using a film |
US5654586A (en) * | 1993-05-07 | 1997-08-05 | Siemens Aktiengesellschaft | Power semiconductor component having a buffer layer |
JPH0951060A (ja) * | 1995-08-09 | 1997-02-18 | Mitsubishi Materials Corp | パワーモジュール用基板の端子構造 |
US20030020159A1 (en) * | 2000-02-29 | 2003-01-30 | Herbert Schwarzbauer | Heat-conducting adhesive compound and a method for producing a heat-conducting adhesive compound |
CN101304017A (zh) * | 2007-05-12 | 2008-11-12 | 塞米克朗电子有限及两合公司 | 烧结的功率半导体基片及其制造方法 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105633039A (zh) * | 2014-11-26 | 2016-06-01 | 意法半导体股份有限公司 | 具有引线键合和烧结区域的半导体器件及其制造工艺 |
CN105633039B (zh) * | 2014-11-26 | 2018-10-12 | 意法半导体股份有限公司 | 具有引线键合和烧结区域的半导体器件及其制造工艺 |
CN109390308A (zh) * | 2014-11-26 | 2019-02-26 | 意法半导体股份有限公司 | 具有引线键合和烧结区域的半导体器件及其制造工艺 |
CN109390308B (zh) * | 2014-11-26 | 2023-02-10 | 意法半导体股份有限公司 | 具有引线键合和烧结区域的半导体器件及其制造工艺 |
CN107660308A (zh) * | 2015-06-01 | 2018-02-02 | 西门子公司 | 用于借助于开孔接触件的电镀式连接来使组件电接触的方法和相应的组件模块 |
US11037862B2 (en) | 2015-06-01 | 2021-06-15 | Siemens Aktiengesellschaft | Method for electrically contacting a component by galvanic connection of an open-pored contact piece, and corresponding component module |
CN114846598A (zh) * | 2019-12-26 | 2022-08-02 | 三菱电机株式会社 | 功率模块和电力变换装置 |
Also Published As
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JP2012513682A (ja) | 2012-06-14 |
AU2009331707A1 (en) | 2010-07-01 |
WO2010072555A1 (de) | 2010-07-01 |
US20110304985A1 (en) | 2011-12-15 |
DE102008055134A1 (de) | 2010-07-01 |
JP5602763B2 (ja) | 2014-10-08 |
EP2382659A1 (de) | 2011-11-02 |
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