CN101510537A - 包括将半导体芯片键合至铜表面的烧结接合部的模块 - Google Patents

包括将半导体芯片键合至铜表面的烧结接合部的模块 Download PDF

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CN101510537A
CN101510537A CNA2009100095231A CN200910009523A CN101510537A CN 101510537 A CN101510537 A CN 101510537A CN A2009100095231 A CNA2009100095231 A CN A2009100095231A CN 200910009523 A CN200910009523 A CN 200910009523A CN 101510537 A CN101510537 A CN 101510537A
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substrate
applies
bonding cream
bonding
semiconductor chip
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卡斯滕·古特
伊万·尼基廷
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及一种模块，该模块包括衬底和半导体芯片，该衬底包括第一铜表面。模块包括将半导体芯片直接键合至第一铜表面的第一烧结接合部。

Description

包括将半导体芯片键合至铜表面的烧结接合部的模块
技术领域
本发明涉及半导体封装技术领域。
背景技术
功率电子模块是在功率电子电路中使用的半导体封装。典型地，功率电子模块可使用在车载和工业应用中(例如在反相器(inverters)和整流器中)。典型地，包括在功率电子模块内的半导体元件是绝缘栅双极晶体管(IGBT)半导体芯片，或金属氧化物半导体场效应晶体管(MOSFET)半导体芯片。IGBT和MOSFET半导体芯片具有变化的电压和电流级。一些功率电子电路在半导体封装中还包括额外的半导体二极管(即储能二极管)，以用于过电压保护。
一般来说，使用两种不同的功率电子模块设计。一种设计用于较高功率应用，另一种设计用于较低功率应用。对于较高功率应用，功率电子模块典型地包括集成在单个衬底上的数个半导体芯片。典型的，衬底包括绝缘陶瓷衬底(例如Al2O3，AlN，Si3N4或者其它合适的材料)以使功率电子模块绝缘。使用纯的或者电镀的Cu，Al或者其它合适的材料来至少使陶瓷衬底的顶侧金属化，以提供半导体芯片的电子和机械接触。典型地，使用直接覆铜(DCB(directcopper bonding))或者活性金属钎焊(active metal brazing(AMB))工艺来将金属层键合(bonding或者说接合)至陶瓷衬底上。
典型地，使用Sn-Pb，Sn-Ag，Sn-Ag-Cu或者其它合适的焊料合金的软焊被用来将半导体芯片连接到金属化陶瓷衬底。典型的，将数个衬底键合至金属基板上。这样，陶瓷衬底的背侧也用纯的或者电镀的Cu，Al或者其它合适的材料来金属化以将衬底连接至金属基板。典型地，使用Sn-Pb，Sn-Ag，Sn-Ag-Cu或者其它合适的焊料合金的软焊可用来将衬底连接到金属基板。
对于较低功率应用，典型地，使用引线框架衬底(例如，纯铜衬底)来取代陶瓷衬底。根据应用情况，引线框架衬底典型地镀上Ni，Ag，Au和/或Pd。典型地，使用Sn-Pb、Sn-Ag、Sn-Ag-Cu或者其它合适的焊料合金的软焊被用来将半导体芯片连接至引线框架衬底。
对于高温应用，焊接接合部的低熔点(Tm＝180℃-220℃)成为功率电子模块的关键参数。在功率电子模块操作期间，半导体芯片下面的区域暴露于高温下。在这些区域中，环境温度中叠加了半导体芯片内部散发的热量。这导致了功率电子模块操作期间的热循环。典型地，对于热循环的可靠性，在150℃以上不能保证焊接接合部的可靠功能。在150℃以上，在几次热循环之后，焊料区域内部可能会形成裂纹。裂纹可能容易扩散至整个焊接区域并导致功率电子模块失效。
随着对在恶劣环境(例如，汽车应用)中使用功率电子器件的需求的增长和半导体芯片集成度的持续发展，外部和内部散热继续增加。因此，对于能够在内部和外部温度达到和超过200℃时运行的高温功率电子模块的需求也不断增长。另外，为降低高温功率电子模块的成本，应该避免使用将半导体芯片连接至衬底的贵金属表面和将衬底连接至金属基板的贵金属表面。
因为这些或者其它原因，所以需要本发明。
发明内容
一个实施例提供了一种模块。该模块包括衬底和半导体芯片，其中衬底包括第一铜表面。该模块包括第一烧结接合部(joint)，该第一烧结接合部将半导体芯片直接键合(bonding)至第一铜表面。
附图说明
附图被包括进来以提供对实施例的进一步理解，并且这些附图并入此说明书并构成其一部分。附图示出了实施例，并与描述一起用于解释实施例的原理。参考随后的详细说明可以更好地理解这些实施例，因而更好地认识到其它实施例和实施例的许多旨在实现的优点。图中的元件彼此并不必然成比例。同样的参考数字代表相应的类似部分。
图1示出了模块的一个实施例的横截面视图。
图2示出了模块的另一个实施例的横截面视图。
图3示出了被加以掩膜的衬底的一个实施例的横截面视图。
图4示出了被加以掩膜的衬底和键合膏或浆的一个实施例的横截面视图。
图5示出了烧结后的被加以掩膜的衬底、烧结接合部和半导体芯片的一个实施例的横截面视图。
图6示出了去除掩模后的被加以掩膜的衬底、烧结接合部和半导体芯片的一个实施例的横截面视图。
图7示出了低温连接(LTJ)工具的一个实施例的横截面视图。
具体实施方式
在下面的详细说明中，参考构成本文一部分的附图，在图中示出了可以实施本发明的具体实施例。在这点上，例如“顶部”、“底部”、“前面”、“背面”、“首”、“尾”等方向性术语是参照所描述的图中的方位来使用。因为实施例的各部件能够被设置为多个不同的方位，所以方向性术语是用于说明的目的而绝非用于限制。需要理解，可以使用其它实施例，且在不背离本发明的范围的情况下可以进行结构或逻辑上的改变。因此，下面的详细说明不是为了限制，并且本发明的范围由附加权利要求来限定。
需要理解，除非特别强调，否则本文描述的各示例性实施例的特征可以互相结合。
图1示出了模块100的一个实施例的横截面视图。在一个实施例中，模块100是高温(即，达到和超过200℃)低功率电子模块。功率电子模块100包括引线框架衬底102、烧结接合部104、半导体芯片106、键合线108、引线112和壳体110。引线框架衬底102包括Cu或者其它合适的材料。烧结接合部104将Cu引线框架衬底102直接连接到半导体芯片106，而不在Cu引线框架衬底102和半导体芯片106之间使用贵金属层。由于不使用贵金属层，所以功率电子模块100的成本相比典型的高温功率电子模块要低。
如本文中所使用的，术语“电连接”并不意味着这些元件必须直接连接在一起，并且在“电连接”的元件之间可以设置中间元件。
半导体芯片106通过键合线108电连接到引线112。键合线108包括Al、Cu、Al-Mg、Au或者其它合适的材料。在一个实施例中，使用超声波引线键合法将键合线108键合至半导体芯片106和引线112。在一个实施例中，引线框架衬底102的厚度在125μm-200μm范围之内。使用低温连接(LTJ)工艺来提供烧结接合部104，从而将引线框架衬底102连接到半导体芯片106。在不氧化Cu引线框架衬底102的表面的情况下形成烧结接合部104。壳体110包括模制材料或其它合适的材料。壳体110包围了引线框架衬底102、烧结接合部104、半导体芯片106、键合线108和引线112的一部分。
图2示出了模块120的另一个实施例的截面视图。在一个实施例中，模块120是高温(即，达到和超过200℃)高功率电子模块。功率电子模块120包括：金属基板124、烧结接合部126、包括金属表面或者层128和132的金属化陶瓷衬底130、烧结接合部134、半导体芯片136、键合线138、电路板140、控制触片142、电力触片144、填充物(potting)146和148，以及壳体150。
金属层128和132包括Cu或者其它合适的材料。烧结接合部126将Cu层128直接连接到金属基板124，而不在Cu层128和金属基板124之间使用贵金属。烧结接合部134将Cu层132直接连接到半导体芯片136，而不在Cu层132和半导体芯片136之间使用贵金属。由于不使用贵金属层，所以功率电子模块120的成本相比于典型的高温功率电子模块要低。
半导体芯片136通过键合线138(bond wire)电连接到Cu层132。键合线138包括Al、Cu、Al-Mg、Au或者其它合适的材料。在一个实施例中，使用超声波引线键合法来将键合线138键合至半导体芯片136和Cu层132。Cu层132电连接到电路板140和电力触片144(Power Contact)。电路板140电性连接到控制触片142。
壳体150包围烧结接合部126、包括Cu层128和132的金属化陶瓷衬底130、烧结接合部134、半导体芯片136、键合线138、电路板140、控制触片142的一部分，以及电力触片144的一部分。壳体150包括工业塑料或者其它合适的材料。壳体150被连接到金属基板124。在一个实施例中，使用单个金属化陶瓷衬底130从而不用金属基板124，并且壳体150直接连接到该单个金属化陶瓷衬底130。
填充材料146填充了壳体150内位于电路板140下方且位于烧结接合部126、包括Cu层128和132的金属化陶瓷衬底130、烧结接合部134、半导体芯片136、以及键合线138周围的区域。填充材料148填充了壳体150内位于电路板140上方且位于控制触片142的一部分和电力触片144的一部分周围的区域。填充材料146和148包括硅凝胶或者其它合适的材料。填充材料146和148防止了由于介电击穿而对功率电子模块120的损害。
下面的图3-6示出了将半导体芯片低温连接至包括Cu表面的衬底的实施例，例如，如前面参考图1所描述和说明的将半导体芯片106连接到引线框架衬底102，或如前面参考图2所描述和说明的将半导体芯片136连接到Cu层132。类似的工艺同样能够用于将包括Cu层的金属化衬底低温连接到金属基板，例如，如前面参考图2所描述和说明的将Cu层128连接到金属基板124。
图3示出了被掩蔽的(masked)衬底160的一个实施例的横截面视图。被掩蔽的衬底160包括金属化陶瓷衬底130和掩膜162，该衬底包括底部Cu层128和顶部Cu层132。底部Cu层128键合至陶瓷衬底130的底部。顶部Cu层132键合至陶瓷衬底130的顶部。Cu层128和132使用直接键合铜(direct copper bonding(DCB))工艺、活性金属钎焊(active metal brazing(AMB))工艺、或者其它合适工艺来键合至陶瓷衬底130。陶瓷衬底130包括Al2O3、AlN、Si3N4或者其它合适的材料。掩膜162形成在Cu层132上，从而暴露Cu层132的一部分164。掩膜162包括感光材料或其它合适的材料。
图4示出了被掩蔽的(masked)衬底160和键合膏或浆料166的一个实施例的横截面视图。键合膏或浆料166被施加在Cu层132的暴露的未掩蔽的部分164上。键合膏或浆料166提供了预定位半导体芯片的粘性表面。在烧结期间，键合膏或浆料166所覆盖的那部分Cu层132被保护而不受氧化。
键合膏或者浆料166包括有机成分，这些有机成分在50℃-200℃的温度范围内分解以提供分解产物而无残留物。另外，这些分解产物对Cu层132的表面没有任何氧化效应。分解产物对Cu层132的表面也没有任何钝化效应。有机成分的分解是缓慢且均匀的，而不是突发的。此外，在烧结期间释放的气体成分不会增加烧结层的多孔性。
键合膏或浆料166包括Ag微粒、Au微粒、Cu微粒、或者其它合适的材料。这些微粒的颗粒大小在1nm-20μm之间的范围内，例如1nm-1000nm、1nm-100nm、1μm-15μm、1μm-5μm、或者小于500nm。在一个实施例中，键合膏或者浆料166包括具有表面活性的附加成分。具有表面活性的成分包括例如松香或者合成替代品的树脂、随温度的上升而具有还原特性的有机酸，或者其它合适的成分。
图5示出了烧结后的被掩蔽的的衬底160、烧结接合部134和半导体芯片136的一个实施例的横截面视图。半导体芯片136位于键合膏或浆料166上。在一个实施例中，去除了掩膜162且Cu层132的暴露部分被覆盖了保护层以保护Cu层132的表面在烧结工艺期间不被氧化。保护层包括粘性箔，例如醯亚氨或特氟
Figure A200910009523D0012140649QIETU
、光敏箔、有机材料薄层，或其它合适的保护层。掩膜162或保护层保护Cu层132表面在温度高达烧结处理温度时不被氧化。
半导体芯片136在可加热压力下连接到Cu层132。根据覆料或灰浆166中材料的微粒大小，在100℃-450℃之间(例如在200℃-400℃之间)的温度和如箭头168所示的高达40Mpa的压强可用来烧结以形成烧结接合部134。在一个实施例中，对于直径在1μm-15μm之间的粒子，在200℃-250℃之间的温度和在20MPa-40MPa之间的压强可用来烧结以形成烧结接合部134。
图6示出了去除掩膜162或保护层之后的包括Cu层128和132的金属化陶瓷衬底130、烧结接合部134、和半导体芯片136的一个实施例的横截面视图。去除掩膜162或保护层，从而露出Cu层132。在烧结工艺期间，Cu层132的表面受保护而不被氧化。因此，没有使用额外的贵金属层来保护Cu层132不被氧化，从而降低了包括Cu层128和132的金属化陶瓷衬底130的成本。
图7示出了低温连接(LTJ)工具200的一个实施例的横截面视图。工具200包括壳体202、密封件204、气体入口/出口206、压杆(stamp)210、软衬垫212，和压力轴214。在一个实施例中，工具200是真空工具。在其它实施例中，只要环境气体是非氧化性的，工具200可以不是真空工具。工具200是防止要连接部件的表面被氧化的烧结工具。在一个实施例中，工具200包括气密性壳体202，其在压腔(press)关闭时密封样本。工具200包括气体入口/出口206以如箭头208所示排出空气和/或引入非氧化性气体环境。在一个实施例中，非氧化气体包括惰性气体环境，还原性气体环境或其它合适的气体环境。在一个实施例中，还原性气体环境包括合成气体(forming gas)，蚁酸(formic acid)，或其它合适的气体。还原性气体环境清洁并保护了Cu层132的暴露部分。
非氧化气体环境保护Cu层132在烧结处理期间不被氧化。因此，在烧结工艺期间，当使用工具200时，可以不用前面参考图5所描述和说明的掩膜162或保护层。为了将半导体芯片136连接到Cu层132且将Cu层128连接到金属基板124，首先，将键合膏或浆料施加至金属基板124和/或Cu层128上。然后，将包括Cu层128和132的金属化陶瓷衬底130放置在金属基板124上的键合膏或浆料上。
接下来，如前面参考图4所描述和说明的，将键合膏或浆料施加至Cu层132的未被掩蔽部分上和/或施加至半导体芯片136。然后，将半导体芯片136放置在金属化陶瓷衬底130上的键合膏或浆料上。壳体202放置在半导体芯片136和金属化陶瓷衬底130上，并通过密封件204与金属基板124密封。工具200加热键合膏或浆料，并且压力轴214如箭头216所示向软衬垫212施加压力。软衬垫212均匀地分散来自压力轴214的压力。软衬垫212将压杆210推到半导体芯片136上，从而形成将半导体芯片136连接到Cu层132的烧结接合部134和将Cu层128连接到金属基板124的烧结接合部126。
在一个实施例中，键合膏或浆料包括Ag、Au、Cu或其它合适的材料。根据键合膏或浆料中材料的微粒大小，工具200将键合膏或浆料加热到100℃-450℃范围内(例如200℃-400℃)的温度，并通过压力轴214在半导体芯片136上施加高达40MPa的压强，以形成烧结接合部134和烧结接合部126。在一个实施例中，对于直径在1μm-15μm之间的Ag微粒，工具200将键合膏或浆料加热到200℃-250℃范围内的温度，并施加20MPa-40MPa之间的压强以形成烧结接合部134和烧结接合部126。
实施例提供了Cu衬底或者Cu层与半导体芯片、金属基板或其他合适部件的低温连接。无需在Cu上使用贵金属就可以保护Cu的表面在烧结时不被氧化。这样，相比于典型的低温连接部件，此连接部件的生产成本更低，并且适合达到和超过200℃的高温应用。
虽然所说明的实施例基本上集中在功率电子模块，但是该实施例可适用于需要将部件低温连接至Cu的任何电路。
虽然在本文已经说明和描述了具体实施例，但本领域内的普通技术人员将可以意识到，在不脱离本发明范围的情况下，多种选择和/或等同实施例可以代替示出并描述的具体实施例。此申请旨在覆盖本文中讨论的具体实施例的任何修改或变化。因此，本发明旨在仅由权利要求和其等同物所限定。

Claims (25)

1.一种模块，包括：
衬底，包括第一铜表面；
半导体芯片；以及
第一烧结接合部，将所述半导体芯片直接键合至所述第一铜表面。
2.根据权利要求1所述的模块，其中，所述第一烧结接合部包括Ag、Au和Cu之一。
3.根据权利要求1所述的模块，其中，所述衬底包括引线框架衬底。
4.根据权利要求1所述的模块，其中，所述衬底包括陶瓷层和第二铜表面，并且
其中，所述第一铜表面是由键合至所述陶瓷层的第一侧的第一铜层提供，所述第二铜表面是由键合至所述陶瓷层的第二侧的第二铜层提供。
5.根据权利要求4所述的模块，还包括：
基板；以及
第二烧结接合部，其将所述基板直接键合至所述第二铜表面。
6.根据权利要求1所述的模块，其中，所述模块包括功率电子模块。
7.一种制造模块的方法，所述方法包括以下步骤：
提供包括铜表面的衬底；
掩蔽所述铜表面的一部分；
将键合膏施加至所述铜表面的未掩蔽部分；
将芯片施加至所述键合膏；以及
烧结所述键合膏，以提供将所述芯片连接至所述铜表面的接合部。
8.根据权利要求7所述的方法，其中，施加所述键合膏的步骤包括施加包含Ag、Au和Cu之一的键合膏。
9.根据权利要求7所述的方法，其中，施加所述键合膏的步骤包括施加包含颗粒尺寸小于500nm的微粒的键合膏。
10.根据权利要求7所述的方法，其中，施加所述键合膏的步骤包括施加包含颗粒尺寸在1nm到20微米范围之内的微粒的键合膏。
11.根据权利要求7所述的方法，其中，施加所述键合膏的步骤包括施加在室温下具有粘性表面的键合膏。
12.根据权利要求7所述的方法，其中，施加所述键合膏的步骤包括施加包含有机成分的键合膏，所述有机成分在50℃-200℃之间的温度范围内分解而没有残留物且不发生氧化效应。
13.根据权利要求7所述的方法，其中，施加所述键合膏的步骤包括施加包含有机成分的键合膏，所述有机成分的分解对所述铜表面没有钝化效应。
14.根据权利要求7所述的方法，其中，施加所述键合膏的步骤包括施加包含树脂和有机酸之一的键合膏。
15.根据权利要求7所述的方法，还包括：
在施加所述键合膏之后去除掩膜；以及
将保护层施加至所述铜表面的暴露部分。
16.根据权利要求15所述的方法，其中，施加所述保护层的步骤包括施加粘性箔和有机保护层之一。
17.根据权利要求7所述的方法，其中，所述烧结步骤包括在100℃-450℃的范围内的温度下以及高达40Mpa的压强下进行烧结。
18.一种制造模块的方法，所述方法包括以下步骤：
提供包括铜表面的衬底；
将所述键合膏施加至所述铜表面的一部分；
将半导体芯片施加至所述键合膏；以及
在非氧化性气体环境中烧结所述键合膏，以将芯片连接至所述铜表面。
19.根据权利要求18所述的方法，其中，所述烧结步骤包括在惰性气体环境和还原性气体环境之一中进行烧结。
20.根据权利要求18所述的方法，其中，施加所述键合膏的步骤包括施加包含有Ag、Au和Cu之一的键合膏。
21.根据权利要求18所述的方法，其中，提供所述衬底的步骤包括提供引线框架衬底。
22.根据权利要求18所述的方法，其中，提供所述衬底的步骤包括提供键合至铜层的陶瓷衬底。
23.一种工具，包括：
密封壳体，被配置为在关闭时密封样本，所述样本包括半导体芯片和铜表面；
气体入口或出口，被配置为在所述壳体内引入非氧化性气体环境；以及
压杆，被配置为形成将所述半导体芯片直接键合至所述铜表面的烧结接合部。
24.根据权利要求23所述的工具，其中，所述非氧化性气体环境包括还原性气体环境和惰性气体环境之一。
25.根据权利要求23所述的工具，其中，所述工具被配置为向所述样本施加在100℃-450℃的范围内的温度和高达40MPa的压强。
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