CN103681525A - 预烧结半导体芯片结构 - Google Patents
预烧结半导体芯片结构 Download PDFInfo
- Publication number
- CN103681525A CN103681525A CN201310317704.7A CN201310317704A CN103681525A CN 103681525 A CN103681525 A CN 103681525A CN 201310317704 A CN201310317704 A CN 201310317704A CN 103681525 A CN103681525 A CN 103681525A
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- Prior art keywords
- sintering
- substrate
- semiconductor chip
- combustion method
- dry combustion
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- 238000005245 sintering Methods 0.000 claims abstract description 140
- 239000000758 substrate Substances 0.000 claims abstract description 133
- 239000000463 material Substances 0.000 claims abstract description 80
- 239000002245 particle Substances 0.000 claims abstract description 56
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- 238000009841 combustion method Methods 0.000 claims description 73
- 238000000034 method Methods 0.000 claims description 52
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 18
- 229910052709 silver Inorganic materials 0.000 claims description 18
- 239000004332 silver Substances 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 15
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 239000002002 slurry Substances 0.000 description 6
- 239000011148 porous material Substances 0.000 description 4
- 238000009770 conventional sintering Methods 0.000 description 3
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- 238000005019 vapor deposition process Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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Abstract
将半导体芯片和干烧结料抵压在基片上形成一种烧结连接,所述干烧结料位于基片和半导体芯片之间,该干烧结料具有烧结颗粒和溶剂。在半导体芯片被压在基片上时,将基片加热至低于干烧结料的烧结温度,以在相邻烧结颗粒间形成局部烧结连接。局部烧结连接在烧结之前共同提供将半导体芯片固定至基片上的固定接合。在形成固定接合后,由干烧结料形成在半导体芯片与基片间的烧结连接。
Description
技术领域
本应用涉及烧结,更具体地,涉及形成具有高完整性的烧结连接。
技术背景
烧结是一种当加热时将粉粒之间致密的机械连接转化成颗粒之间固体冶金接合。烧结是一种广泛使用的芯片至基片连接技术,其使功率模块使用寿命增强而且功率密度强化。通过烧结形成的芯片-基片连接是基于微米或者纳米大小的颗粒的强化表面的金属相互扩散。这些金属颗粒通常在高温下,在有或没有施加电压的情况下被压缩。用于将芯片连接至基片的常用烧结浆料由有机络合物涂覆的银颗粒以及有机组分(诸如将银颗粒保持在一起的溶剂)组成。
传统烧结芯片贴装技术涉及用湿银浆料涂覆将芯片坚固地放置到基片上。湿银浆料的有机组份具有足够粘度,可以将芯片粘到基片上。然而,在后续的烧结过程中,在有机合成物蒸发时形成干的通路。这些通路严重损害了烧结银层的热性能和电性能。结果,无法满足,可靠性需求,尤其是模块的使用期限。
大多数溶剂能够在芯片放置到基片上之前,在升高的温度下通过干燥银浆料将溶剂从银浆料中除去。然而,在将芯片放置在基片上之前从烧结浆料中除去大多数溶剂很难使芯片固定在基片上的合适位置,因为烧结料一旦干燥粘附性不佳。在烧结过程后以及在将基片传送至烧结设备过程中,芯片必须保持在基片上合适的位置,由此证明在使用干燥烧结浆料时是有困难的。
发明内容
根据此处描述的实施例,通过干烧结料提供芯片在基片上的固定的位置,因此基片能够在芯片不会从位置移动出的同时被转移至烧结装置。
根据一个实施例的形成烧结连接的方法,该方法包括:将半导体芯片和干烧结料压在基片上,干烧结料位于基片和半导体芯片之间,该干烧结料包括烧结颗粒和溶剂;在半导体芯片压在基片上时,将基片加热至低于干烧结料的烧结温度,以形成相邻烧结颗粒间的局部烧结连接,局部烧结连接在烧结前提供了将半导体芯片固定至基片的固定接合;以及在形成固定接合后,由干烧结料形成半导体芯片和基片之间的烧结连接。
根据预烧结结构的一个实施例,预烧结结构包括基片,设置在基片上的半导体芯片,以及位于基片和半导体芯片之间的干烧结料。该干烧结料包括烧结颗粒和溶剂。该干烧结料具有大于20%的孔隙率。预烧结结构进一步包括相邻烧结颗粒之间的局部烧结连接,该局部烧结连接一起将半导体芯片固定在基片上,半导体芯片和基片之间没有形成完全烧结的连接。
根据一个形成预烧结连接的实施例的方法,该方法包括:在基片上或者附接至基片的半导体芯片上形成烧结料,该烧结料包括烧结颗粒和溶剂;在高于溶剂的蒸发温度时使得烧结料变干以形成一种干烧结料,该干烧结料具有降低的溶剂量;将半导体芯片和干烧结料抵压在基片上,该干烧结料位于基片和半导体芯片间;当将半导体芯片抵压在基片上时,将基片加热至低于干烧结料的烧结温度,以在相邻烧结颗粒间形成局部烧结连接,局部烧结连接在烧结前提供了将半导体芯片固定至基片的固定接合。
根据另一个形成预烧结连接的实施例的方法,该方法包括:在基片上或者附接至基片的半导体芯片上形成烧结料,该烧结料包括烧结颗粒和溶剂;在高于溶剂的蒸发温度下使得烧结料变干以形成一种干烧结料,该干烧结料具有降低的溶剂量;将半导体芯片和干烧结料压在基片上,该干烧结料位于基片和半导体芯片间;当半导体芯片抵压在基片上时,将基片加热至低于干烧结料的烧结温度以形成相邻烧结颗粒间的局部烧结连接,局部烧结连接在烧结前提供了将半导体芯片固定至基片的固定接合;以及在形成固定接合后,由干烧结料形成半导体芯片和基片之间的烧结连接。
本领域技术人员在阅读到以下的详细描述和看到附图时将会识别出额外的特征以及优势。
附图说明
附图中的部件并不一定是按照比例,而是强调阐释本发明的原理。此外,图中相同的参考标号指定对应的部分。在附图中:
图1示出了根据一个实施例的在预烧结过程中安装在基片上的芯片的透视图。
图2示出了根据另一个实施例的在预烧结过程中安装在基片上的芯片的透视图。
图3示出了根据一个实施例的预烧结结构的透视图,该预烧结结构包括通过局部烧结连接安装在基片上的芯片。
图4示出了在形成局部烧结连接后在烧结过程中图3的预烧结结构的透视图。
图5A至5C示出了芯片贴装工艺的不同阶段中包含在烧结料中的烧结颗粒的对应图。
具体实施方式
接下来的实施例要描述的是通过干烧结料将芯片安装到基片上,因此基片可以在芯片不从位置移出的情况下被转移至烧结装置。烧结浆料,多孔预制体(即为特定应用专门设计的焊接预制状),或多孔烧结层可以沉积在基片或芯片上。使烧结料变干以除去包含在烧结料中的大多数溶剂。在执行烧结之前将芯片和干烧结料定位到基片上,干烧结料位于芯片和基片间。为了充分地将芯片固定到基片上以传送至烧结设备,将基片预加热至低于烧结设备的温度下,例如低于银烧结料的200℃。在温度窗口内并在足够压力下,在芯片和基片之间能够实现足够的固定接合。通过预烧结干烧结料产生固定接合,在芯片和基片之间提供充分的粘结。在预烧结过程中,小烧结颗粒的反应表面彼此间形成局部烧结连接,以在没有完全烧结的连接情况下提供固定的芯片至基片连接。在后续的烧结步骤中,最终压缩成紧密的(烧结的)连接层。
更详细地,图1至图3示出了在半导体芯片100与基片102之间形成预烧结连接方法的实施例,因此基片102能够在芯片100没有从位置移出的情况下被传送至烧结设备。如图1至图3所示,基片102可以包括绝缘件104,如带有上和下金属化106的陶瓷件。通常,可以使用任意合适的基片。
图1示出了一个实施例,其中在附接至基片102的半导体芯片100的背面101形成烧结料108。在一些实施例中,烧结料108为银浆料、多孔银预制体或多孔银层。通常,烧结料108包括微米或纳米大小的烧结颗粒,有机成分包括溶剂。烧结颗粒可以是涂有蜡或者其它有机络合物的银颗粒、铜颗粒、金颗粒、钯颗粒等。图2示出了另一实施例,其中烧结料108形成于基片102上。在所有情况下,烧结料108能够喷射、气相沉积或印刷(如,丝网印刷)在芯片100的背面101上或基片102上。例如,在气相沉积过程中能够将金属颗粒沉积在芯片100或基片102上。另外,烧结料108可以是置于芯片100与基片102之间的金属浆料预制体。烧结料108能够覆盖芯片区或者大于芯片区。
在高于包含于烧结料108的溶剂的蒸发温度下将烧结料108变干,以形成干烧结料,该干烧结料具有减少的溶剂量。例如,对于很多类型的溶剂来说在120℃以上使干烧结料108变干以充分降低烧结料108中溶剂量。然而,干烧结料108中仍保留有足够的溶剂,因此当烧结颗粒施加到基片102或芯片100上时能充分彼此粘结,因此在施加后粘在芯片100或基片102上。在一实施例中,将烧结料108变干直至至少80%的溶剂从烧结料中除去。
在一个实施例中,如图1所示烧结料108为半导体芯片100上形成的金属浆料并且将芯片100加热至150℃至250℃之间以干燥金属浆料,并在半导体芯片100的背面101上形成干烧结料108。在另一个实施方式中,如图2所示的,在基片102上形成金属烧结浆料108,将基片102加热至150℃至250℃之间以干燥金属浆料并在基片102的侧面103形成干烧结料108。在另一个实施例中,烧结料108为放置于半导体芯片100与基片102之间的金属浆料预制体,将基片102加热至150℃至250℃之间的温度以干燥金属浆料预制体并形成干烧结料108。另外,芯片100或基片102可设置有已经施加的干烧结料108。
可用夹头110例如从晶片或一盘芯片中夹起芯片100,并在基片102上移动。如图1和图2中面向下的箭头所指,在烧结料108干后,夹头110将半导体芯片100压在基片102上,因此干烧结料108接触并位于基片102和芯片100之间。当半导体芯片100压在基片102上时,将基片102通过加热设备112加热至低于干烧结料108的烧结温度。在一实施例中,将基片102加热至包含在干烧结料108的溶剂的蒸发温度与材料108的烧结温度之间的温度。在将芯片100压在基片102上之前可预热基片102,在芯片定位过程中或在将芯片100压在基片102上之后加热。不论是哪种情况,在芯片100压在基片102上时,将基片102加热至低于干烧结料108的烧结温度的温度促成了在芯片100与基片102之间形成固定的预烧结接合114。预烧结接合114包括相邻烧结颗粒间的局部烧结连接(所谓的“颈部”)。局部烧结连接114为烧结颗粒的局部的区域,其中原子已经扩散并越过颗粒的边界,与烧结颗粒的局部化区域(或者颈部)融合在一起。
在一个实施例中,在加热基片102的过程中,在0.2N/mm2到5N/mm2的压力下将半导体芯片100压在基片102上以形成局部烧结连接。这样对于较大的芯片100能转化为大于100N的压力。通常,设计将芯片100带到基片102上的夹头110以克服在10N或更大的范围内的压力。随着芯片尺寸的增大压力升高。对于诸如IGBTs(绝缘栅双极晶体管)的高性能芯片100与千伏级的二极管,可能需要高于50N的压力。可以通过气动的、液压的、电力的系统或这类系统的组合施加压力。夹头110可具有扁平或结构表面111以容纳芯片100的正面布置(拓扑结构)。夹头110的材料可以在从软温度稳定材料到诸如钢合金这样的刚性金属范围内。夹头110施加稳定压力以在预烧结过程中在不损害芯片100的情况下安全地保持并定位芯片100。
在一个实施例中,包含在干烧结料108的烧结颗粒为银颗粒,并将基片102加热至100℃至200℃之间以形成局部烧结连接。在另一个实施例中,烧结颗粒包括铜,并在惰性气氛中,在有或没有少量氧气参与下形成局部烧结连接因此铜烧结颗粒不会氧化。局部烧结连接在烧结之前共同提供一个将半导体芯片100固定至基片102上的固定接合。这样,能够用干烧结料108代替湿浆料用来将芯片100固定在基片102上,以传送至烧结装置。
图3示出所得到的预烧结结构。干烧结料108被设置位于基片102与半导体芯片100间,并包括如以上所述的烧结颗粒和溶剂。在预烧结过程后干烧结料108的孔隙率大于20%,如在60%至80%之间。在芯片100与基片102之间形成固定的预烧结接合114,其包括相邻烧结颗粒间形成的局部烧结连接,该局部烧结连接共同地将半导体芯片100固定在基片102上,芯片100和基片102之间没有完全烧结的连接。就是说,存在于局部烧结连接中的粘合力足够大以在预烧结结构移动至烧结装置时保持芯片100。在预烧结过程中在形成局部烧结连接后,预烧结结构准备好传送至烧结装置。
图4示出在烧结过程中设置在预烧结工具基底116上的预烧结结构。在形成固定的预烧结接合114后,由干烧结料108形成半导体芯片100和基片102之间的完全烧结连接118。任何传统烧结设备和工艺可用于形成完全烧结连接118。在干烧结料108的烧结温度或大于该温度下执行加热,并按图4中面向下箭头指出的施加压力。当加热足够时,该烧结过程将任意剩下的紧密的机械连接和局部烧结连接转化为颗粒间的固体冶金连接。在一个实施例中,得到的烧结连接118的孔隙率小于20%。
图5A至5C图像描述了,在此处之前描述的预烧结和烧结过程中,包含在烧结料108中的烧结颗粒200的不同状态。为简化描述,省去了图5A至5C中的溶剂和涂层。
图5A示出在烧结料108施加至芯片100或基片102上然后变干后的烧结颗粒200。被涂覆的烧结颗粒200在相邻颗粒间基本上未显示有连接。空隙(细孔)202存在于颗粒200周围的开放空间。
图5B示出预烧结过程后完全烧结前的烧结颗粒200。局部烧结连接(所谓“颈部”)204沿着相邻颗粒200间的接触点形成。然而,在这一点上未形成完全烧结的连接,干烧结料108的孔隙率保持大于20%。局部烧结连接204的粘合力足够大以保持芯片100,因此能够将预烧结结构传送至烧结装置,而芯片不会从位置移出。
图5C示出在烧结过程完成后烧结颗粒200的状态。在烧结过程中细孔容量减小而且细孔202变得更光滑。细孔202最终被颗粒边界替代,烧结颗粒200的原子扩散并越过颗粒200的边界,与颗粒200融合在一起并生成一个固体件206,即在芯片100与基片102之间的完全烧结的连接118。
空间的相对术语如“在…之下”、“在…下面”、“下部”、“在...上”、“上部”等等,用于简化描述以解释相对于第二元件的一个元件的位置。这些术语旨在除了图中所描述的那些不同的方向外还包括半导体芯片的不同方向。此外,这些术语如“第一”和“第二”等等,也用于描述各种元件、区域、部分等,这些元件将不受上述表达限制。同类术语意在指明整个说明书中相同的元件。
如本文中所使用的,“具有”、“包含”、“包括”、“由…组成”等一类的术语是开放的术语,意在指明所述的元件或特征的存在性,而没有消除额外的元件或者特征。除非上下文另外明确表示,否则冠词“a”、“an”、以及“the“包含单数和复数。
考虑到上述变化及应用范围,应当理解为本发明不受上述说明书的限制,也不受附图的限制。相反,本发明仅受以上权利要求以及其法定等价物的权利要求的限制。
Claims (24)
1.一种形成烧结连接的方法,包括:
将半导体芯片与干烧结料抵压在基片上,所述干烧结料位于所述基片与所述半导体芯片之间,所述干烧结料包括烧结颗粒和溶剂;
当所述半导体芯片被抵压在所述基片上时,将所述基片加热至低于所述干烧结料的烧结温度,以在相邻所述烧结颗粒间形成局部烧结连接,所述局部烧结连接在烧结之前共同提供将所述半导体芯片固定到所述基片上的固定接合;以及
在形成所述固定接合后,由所述干烧结料形成所述半导体芯片和所述基片之间的烧结连接。
2.根据权利要求1所述的方法,其中,所述烧结颗粒包括银,而且所述基片被加热至100℃至200℃之间的温度以形成所述局部烧结连接。
3.根据权利要求1所述的方法,其中,所述烧结颗粒包括铜,并且在惰性气氛中,在有或者没有少量氧气的参与下形成所述局部烧结连接和所述烧结连接。
4.根据权利要求1所述的方法,其中,将所述基片加热至所述溶剂的蒸发温度和所述干烧结料的烧结温度之间的温度。
5.根据权利要求1所述的方法,其中,所述干烧结料为设置在所述半导体芯片或所述基片上的干银浆料、多孔银预制体或多孔银层中的其中一个。
6.根据权利要求1所述的方法,其中,在加热所述基片的过程中,在0.2N/mm2和5N/mm2之间的压力下将所述半导体芯片抵压在所述基片上。
7.根据权利要求1所述的方法,其中,在加热所述基片的过程中,在大于100N的力下将所述半导体芯片抵压在所述基片上以形成所述局部烧结连接。
8.根据权利要求1所述的方法,其中,所述烧结连接的孔隙率小于20%。
9.根据权利要求1所述的方法,其中,所述干烧结料的孔隙率在60%到80%之间。
10.一种预烧结结构,包括:
基片;
设置于所述基片上的半导体芯片;
位于所述基片和所述半导体芯片之间的干烧结料,所述干烧结料包括烧结颗粒和溶剂,并且所述干烧结料的孔隙率大于20%;以及
相邻的所述烧结颗粒之间的局部烧结连接,所述局部烧结连接共同地将所述半导体芯片固定在所述基片上,在所述半导体芯片和所述基片之间没有形成完全烧结的连接。
11.根据权利要求10所述的预烧结结构,其中,所述干烧结料为设置在所述半导体芯片或所述基片上的干银浆料、多孔银预制体或多孔银层中的其中一个。
12.根据权利要求10所述的预烧结结构,其中,所述烧结颗粒包括银、铜、金或钯的一种。
13.根据权利要求10所述的预烧结结构,其中,所述干烧结料的孔隙率在60%到80%之间。
14.一种形成预烧结连接的方法,包括:
在基片上或者附接至所述基片的半导体芯片上形成烧结料,所述烧结料包括烧结颗粒和溶剂;
在高于所述溶剂的蒸发温度下干燥所述烧结料,以形成一种干烧结料,所述干烧结料具有降低的溶剂量;
将所述半导体芯片与所述干烧结料抵压在所述基片上,所述干烧结料位于所述基片和所述半导体芯片之间;以及
当所述半导体芯片被抵压在所述基片上时,将所述基片加热至低于所述干烧结料的烧结温度,以在相邻的所述烧结颗粒间形成局部烧结连接,所述局部烧结连接在烧结之前共同提供将所述半导体芯片固定到所述基片上的固定接合。
15.根据权利要求14所述的方法,其中,所述烧结颗粒包括银,并且所述基片被加热至100℃至200℃之间的温度以形成所述局部烧结连接。
16.根据权利要求14所述的方法,其中,所述烧结颗粒包括铜,并在惰性气氛下形成所述局部烧结连接。
17.根据权利要求14所述的方法,其中,所述烧结料为银浆料。
18.根据权利要求14所述的方法,其中,在加热所述基片的过程中,在0.2N/mm2与5N/mm2之间的压力下将所述半导体芯片抵压在所述基片上以形成所述局部烧结连接。
19.根据权利要求14所述的方法,其中,在加热所述基片的过程中,在大于100N的力下将所述半导体芯片抵压在所述基片上,以形成所述局部烧结连接。
20.根据权利要求14所述的方法,其中,所述烧结料为在所述半导体芯片上形成的金属浆料,将所述半导体芯片加热至150℃到250℃之间的温度以干燥金属浆料,并在所述半导体芯片的一侧形成所述干烧结料,而且所述半导体芯片与所述干烧结料被抵压在所述半导体芯片一侧的所述基片上。
21.根据权利要求14所述的方法,其中,所述烧结料为在所述基片上形成的金属浆料,将所述基片加热至150℃到250℃之间的温度以干燥所述金属浆料并在所述基片的一侧形成所述干烧结料,而且所述半导体芯片与所述干烧结料被抵压在所述基片上的所述基片的所述一侧上。
22.根据权利要求14所述的方法,其中,所述烧结料为位于所述半导体芯片和所述基片之间的金属浆料预制体,而且将所述基片加热至150℃和250℃之间的温度以干燥金属浆料预制体并形成所述干烧结料。
23.根据权利要求14所述的方法,其中,所述干烧结料被干燥直至至少80%的所述溶剂从所述烧结料中被除去。
24.一种形成烧结连接的方法,包括:
在基片上或者附接至所述基片上的半导体芯片上形成烧结料,所述烧结料包括烧结颗粒和溶剂;
在高于所述溶剂的蒸发温度下干燥所述烧结料,以形成干烧结料,所述干烧结料具有降低的溶剂量;
将所述半导体芯片与所述干烧结料抵压在所述基片上,所述干烧结料位于所述基片和所述半导体芯片之间;
在所述半导体芯片被抵压在所述基片上时,将所述基片加热至低于所述干烧结料的烧结温度,以在相邻所述烧结颗粒间形成局部烧结连接,所述局部烧结连接在烧结之前共同提供将所述半导体芯片固定到所述基片上的固定接合;以及
在形成所述固定接合后,由所述干烧结料形成所述半导体芯片和所述基片之间的所述烧结连接。
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