CN116888732A - 功率模块、电气设备和用于制造功率模块的方法 - Google Patents
功率模块、电气设备和用于制造功率模块的方法 Download PDFInfo
- Publication number
- CN116888732A CN116888732A CN202180094091.8A CN202180094091A CN116888732A CN 116888732 A CN116888732 A CN 116888732A CN 202180094091 A CN202180094091 A CN 202180094091A CN 116888732 A CN116888732 A CN 116888732A
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- Prior art keywords
- solder
- region
- sintering
- intermediate layer
- sintered
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910000679 solder Inorganic materials 0.000 claims abstract description 199
- 238000005245 sintering Methods 0.000 claims abstract description 109
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 239000000463 material Substances 0.000 claims abstract description 50
- 238000002844 melting Methods 0.000 claims abstract description 41
- 230000008018 melting Effects 0.000 claims abstract description 37
- 238000005304 joining Methods 0.000 claims abstract description 27
- 238000007639 printing Methods 0.000 claims abstract description 7
- 238000010146 3D printing Methods 0.000 claims abstract description 5
- 238000000576 coating method Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 44
- 238000010438 heat treatment Methods 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 229910000510 noble metal Inorganic materials 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000005219 brazing Methods 0.000 claims description 3
- 239000011343 solid material Substances 0.000 abstract description 6
- 230000000930 thermomechanical effect Effects 0.000 abstract description 6
- 239000007787 solid Substances 0.000 abstract description 3
- 230000004907 flux Effects 0.000 description 13
- 238000005476 soldering Methods 0.000 description 10
- 238000003825 pressing Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 230000008901 benefit Effects 0.000 description 6
- 238000003466 welding Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonia chloride Chemical compound [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- JIAARYAFYJHUJI-UHFFFAOYSA-L zinc dichloride Chemical compound [Cl-].[Cl-].[Zn+2] JIAARYAFYJHUJI-UHFFFAOYSA-L 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 235000019270 ammonium chloride Nutrition 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 210000005069 ears Anatomy 0.000 description 1
- 239000011133 lead Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 235000005074 zinc chloride Nutrition 0.000 description 1
- 239000011592 zinc chloride Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Die Bonding (AREA)
Abstract
一种功率模块(1),包括:基板(2);导电的中间层(3),该中间层设置在基板(2)上且具有借助烧结制成的接合区域(4);和至少一个功率构件(5),该功率构件分别设置在中间层(3)和烧结的接合区域(4)上进而与其连接(特别是在功率构件(5)的负载连接处),并且该功率构件分别具有至少一个与中间层(3)连接的连接部位(6)(例如控制端子),其中,中间层(3)在相应的连接部位(6)的区域中具有借助焊料预制件制成的焊料区域(7),该焊料区域与相应的连接部位(6)连接并且与烧结的接合区域(4)间隔开或电绝缘。因此,在使用寿命测试中承受高热机械应力的大活性面能够经由烧结的结合区域(4)连接,该接合区域确保相应的功率构件(5)与基板(2)的尤其耐用的、可靠的和可负载的机械连接。在相应的连接部位(6)、例如晶体管的栅极处,热机械应力通常低得多,因此在那里在中间层(3)中能够使用焊料预制件来建立相应的功率构件(5)与基板(2)的连接,其中,这种焊料预制件能够以相对较低的成本获得。此外,一种电气设备(10)具有至少一个这种功率模块(1)。借助烧结制成的接合区域(4)能够借助于烧结预制件制造或借助于3D打印、借助于覆层方法或借助于丝网/模板印刷构成。在用于制造功率模块(1)的方法中,当焊料的熔化温度高于烧结温度时,能够将中间层(3)加热到焊料的熔化温度,或者当烧结温度高于焊料的熔化温度时,能够将中间层加热到烧结温度,其中,如果烧结温度对应地小于或大于焊料的熔化温度,用于借助烧结制成的接合区域(4)的烧结材料的层厚度(9)能够大于或小于用于相应的焊料区域(7)的焊料的层厚度(9)。替代地,焊料的熔化温度能够基本上与烧结温度相同,其中,用于借助烧结制成的接合区域(4)的烧结材料的层厚度(9)基本上能够等于用于相应的焊料区域(7)的焊料的层厚度(9)。烧结的接合区域(4)能够具有设计为实心材料的烧结芯(4”),该烧结芯在两侧上、即朝向功率构件(5)和朝向基板(2)分别具有烧结材料(4');也能够考虑分层的、烧结的接合区域(4),其中,烧结材料和实心材料以层的方式交替,例如烧结材料‑实心材料‑烧结材料‑实心材料‑烧结材料。
Description
技术领域
本发明涉及一种功率模块,功率模块包括基板、设置在基板上的并且具有借助烧结制成的接合区域的导电中间层和至少一个功率构件,该功率构件分别设置在中间层上并且该功率构件分别具有至少一个与中间层连接的连接部位。
此外,本发明涉及一种具有至少一个这种类型的相应的功率模块的相应的电气设备。
最后,本发明涉及一种用于制造这种功率模块的方法。
背景技术
在功率电子学的大量应用中使用这种设备或这种方法。
例如,为了改进高功率半导体中的使用寿命,在将芯片结合到DCB(直接键合铜)基板时越来越多地使用烧结技术。烧结库通常在模板印刷中借助烧结膏来制造。在此,尤其在端子面、即例如功率半导体的栅极结合部小的情况下难以制造湿层厚度超过120μm的库。如果必须在一个工序制造非常且非常小的库或彼此紧密相邻地制造,则这起主要作用。在此,典型的问题是层厚度不均匀、膏从孔中舀出、孔末端处有多余的膏(形成尖角或所谓的“狗耳”)、气穴和膏从孔中释放表现差。
至今为止,在印刷烧结膏时还没有存在上述问题的解决方案,这会导致技术可行性受限和/或可靠性损失。替代地,对于较大的面积,即大于1.6毫米×1.6毫米的面积,使用烧结预制件,然而该烧结预制件由于多孔烧结膏而在其上侧和下侧上无法任意小地制造或冲压。此外,烧结预制件通常价格昂贵并且通常仅从单一供应商处作为单一来源获得。
发明内容
本发明的目的是提供一种改进的功率模块、一种对应的电气设备和一种对应的方法,其特别地克服了所提到的缺点。
该目的的解决方案通过开始提出类型的功率模块通过以下方式来得到:中间层在相应的连接部位的区域中具有借助焊料预制件制成的焊料区域,该焊料区域与相应的连接部位连接。
此外,该目的的解决方案通过开始提出类型的电气设备通过以下方式来实现:即电气设备具有至少一个这样的所提出的功率模块。
此外,该目的的解决方案通过一种用于制造所提出的功率模块的方法通过以下方法步骤来实现:
-提供基板,
-将用于待烧结的接合区域的烧结材料和用于相应的焊料区域的焊料设置在基板上,以构成中间层,其中,用于相应的焊料区域的焊料作为焊料预制件在相应的功率构件的相应的连接部位的区域中提供,
-将相应的功率构件设置在接合区域和相应的焊料区域上或设置在中间层上,并且
-将中间层加热到焊料的熔化温度或加热到烧结温度。
所提出的功率模块包括:基板,导电的中间层设置在该基板上。该中间层具有接合区域。该接合区域的特征尤其在于:中间层在那里借助于烧结来制造。烧结已知是一种用于制造或改变材料的方法。在此,细粒的陶瓷或金属物质——通常在提高的压力下——被加热,其中,温度仍低于主要组分的熔化温度。功率构件设置在中间层上,该功率构件具有至少一个连接部位,以便尤其对功率构件经由相应的连接部位来供应电压或电流。在此,相应的连接部位与中间层连接,特别是电连接。
例如,烧结的接合区域能够具有设计为实心材料的烧结芯,该烧结芯在两侧上、即朝向功率构件和朝向基板分别具有烧结材料。附加地,还能够考虑分层的、烧结的接合区域,其中,烧结材料和实心材料以层的方式交替,例如烧结材料-实心材料-烧结材料-实心材料-烧结材料。
中间层附加地在相应的连接部位的区域中具有焊料区域,该焊料区域与相应的连接部位连接、尤其电连接。相应的焊料区域具有焊料,即连接材料,该连接材料通过焊料连接金属。焊料例如由不同金属的混合物或合金构成。为此,特别频繁地使用铅、锡、锌、银、锑和铜。在此,相应的焊料区域借助于焊料预制件制造。焊料预制件特别是焊料预成型件或焊料模制件,例如呈期望尺寸的长方体、柱体、环等,特别是由焊料合金构成。例如,这种焊料预制件能够以各种尺寸在带上或在托盘中交付,并且能够类似于SMD(“表面安装构件”)电阻或电容器进行处理。
作为功率构件,例如能够使用半导体构件或功率半导体,即尤其为基于例如硅、氮化镓或碳化硅且在功率电子装置中设计用于控制和开关高的电流和电压的构件,该电流和电压尤其是超过1安培的电流和超过约24伏特的电压。例如,这种构件是功率二极管、晶闸管、三端双向可控硅开关元件和诸如功率MOSFET、IGBT等的晶体管。此外,电阻、例如测量电阻能够用作功率构件。
这种功率构件通常是相对薄的构件,即基面的尺寸显著大于相应的功率构件垂直于基面的厚度。特别地,这种功率构件具有基本上平坦的上侧或下侧,例如因为其基本上是长方体或圆柱形的。特别地,功率构件的一侧平放在中间层上。
如上所述,中间层因此具有借助烧结制成的接合区域(下文中也称为“烧结的接合区域”)以及相应的焊料区域。如典型的功率构件那样,中间层也通常具有扁平长方体或柱体的形状,即具有——与中间层厚度相比——大的上侧和下侧。在此,中间层的上侧朝向相应的功率构件,并且中间层的下侧朝向基板。此外,烧结的接合区域优选地占据中间层的最大区域,使得相应的焊料区域相对小。
所提及的相应的连接部位特别地用作相应的功率构件的控制端子。相应的功率构件能够附加地具有另一连接部位,该另一连接部位朝向借助烧结制成的接合区域并且能够用作相应的功率构件的负载连接。原则上,也能够考虑多个这样的另外的连接部位,其能够分别用作为相应的功率构件的负载连接。
所解释的中间层设计方案具有多个优点。例如,相应的功率构件大部分经由中间层的烧结的接合区域与基板连接。特别地,烧结的接合区域创建在相应的功率构件与基板的尤其耐用的、可靠的和可负载的机械连接,该连接也经受住高的热机械应力,中间层在功率模块的寿命期间承受该应力。相反,借助较便宜的焊料预制件制造相应的在其处热机械应力显著更小的连接部位,使得相对于功率模块中完全烧结的中间层实现了成本优势。
在所提出的功率模块中尤其有利的是:所解释的中间层或者经由所解释的中间层进行的相应的功率构件与基板的连接能够特别便宜且简单地制造。这包括但不限于是因为:尤其在一个工作步骤中实现中间层的烧结的接合区域和相应的焊料区域的构成。这例如通过以下方式是可行的,即在借助烧结制成的接合区域的烧结的工作步骤期间,能够熔化焊料预制件,或者在焊接焊料区域的工作步骤期间能够烧结烧结材料。结果,在该工作步骤期间构成烧结的接合区域和相应的焊料区域。此外,作为优点得出:用于形成烧结的接合区域的烧结材料仅可受限制地被压缩,由此防止在该工作步骤期间在焊料预制件熔化期间焊料被不允许地排挤。
在本发明的一个有利的设计方案中,借助烧结制成的接合区域借助于烧结预制件制造。
烧结预制件特别是烧结预成型件或烧结模制件,例如由待烧结材料制成的长方体、柱体、环等。呈期望尺寸的长方体、柱体、环形等。例如,烧结预制件能够以常见尺寸在带上或在托盘中交付,并且能够类似于SMD(“表面安装构件”)电阻或电容器进行处理。
烧结预制件连同相应的焊料预制件的使用实现将相应的功率构件与基板的特别容易建立的连接。特别地,通过将烧结预制件与相应的焊料预制件组合能够在一个烧结或工作步骤中连接中间层的大的烧结的区域和小的焊接的区域,例如也没有附加地活化焊料。在此,烧结预制件可用于大的活性面,该烧结预制件对于中间层的最终厚度具有决定性作用。对于小的焊接过的面,例如在构成为晶体管的功率构件的栅极处,能够使用焊料预制件,该焊料预制件在烧结过程期间一起熔化。由于烧结预制件仅可被受限地压缩,在此能够防止焊料在烧结过程期间在小面上熔化时被不允许地排挤。
因此,在耐久性测试中承受高热机械应力的大活性面能够经由烧结的接合区域连接,该接合区域确保相应的功率构件和基板的特别耐用的、可靠的和可负荷的机械连接。在相应的连接部位处,例如晶体管的上述栅极处,热机械应力通常低得多,这就是为什么在那里在中间层中能够使用焊料预制件来建立相应的功率构件与基板的连接的原因。如所提及的那样,这种焊料预制件能够以相对较低的成本获得。
在本发明的一个替代的有利的设计方案中,借助烧结制成的接合区域接组合也3D打印、借助于覆层方法或借助于丝网/模板印刷构成。
替代于使用烧结预制件,中间层的待烧结的材料还能够借助于3D打印、借助于覆层方法或借助于丝网/模板印刷构成,或者附接或设置在基板上。该替代的方法相对于使用烧结预制件能够具有以下优点:即能够实现烧结的接合区域的特别精细或甚至复杂的几何形状。例如,借助于这种替代方法能够实现具有带有多个连接部位的复杂的功率构件的功率模块或具有多个(这种)功率构件的功率模块。
还能够考虑的是:对于功率模块使用一个或多个烧结预制件和一个或多个所提及的替代的方法,以制造一个或多个烧结的接合区域。
在本发明的另一有利的设计方案中,相应的焊料区域或相应的焊料预制件是无助焊剂的。
在此,助焊剂是在焊接时添加的物质,该物质引起通过焊料更好地润湿工件。通过化学反应,特别是借助于还原去除表面处存在的氧化物。相同的内容适用于在焊接过程期间由于空气中的氧气而形成的氧化物。助焊剂还能够降低边界面张力。根据具体要求或情况,助焊剂能够是含酸的或含溶剂的,或者具有活化剂,例如氯化锌、氯化铵或有机盐。
无助焊剂特别是指焊料预制件的焊料没有或几乎没有助焊剂。例如,如果焊料预制件的焊料仅具有或几乎仅具有不同金属的混合物或合金,则其是无助焊剂的。在此,如果焊料中所含的助焊剂量仅最多在工件润湿、去除待焊接工件上的氧化物和/或降低边界面张力方面具有可忽略的影响,则假定焊料“几乎”不含助焊剂。如果焊料仅具有微不足道或不期望的助焊剂污染,则假定焊料“几乎”不具有助焊剂。尽管在焊接时经常使用助焊剂,但是借助于无助焊剂的焊料预制件或焊料区域成功构成相应的焊料层和将相应的功率构件与基板连接,因为在所提出的功率模块中将相应的功率构件经由中间层的借助烧结制成的接合区域借助于烧结固定在基板上。对应地,相应的功率构件和基板在朝向另一工件的相应的表面或中间层的支承面处具有贵金属表面,例如金或银。由于该贵金属表面不会或实际上不会氧化,因此不需要对于焊接通常所需的助焊剂。
在本发明的另一有利的设计方案中,借助烧结制成的接合区域和相应的焊料区域彼此并排地设置在基板和相应的功率构件之间并且基本上具有相同的层厚度。
中间层通常平坦地构成,其中,相应的功率构件设置在该中间层的平坦的上侧上,并且基板设置在其平坦的下侧上。在中间层内,烧结的接合区域以及相应的焊料区域尤其彼此并排地设置,使得烧结的接合区域或焊料区域从中间层的平坦上侧连续地延伸到相对置的平台的中间层下侧。此外,烧结的接合区域优选地占据中间层的最大区域,使得相应的焊料区域相对较小。
烧结的接合区域的层厚度在此基本上对应于相应的焊料区域的相应的层厚度,使得中间层具有基本上恒定的层厚度。在此,较小的偏差是能够容忍的,例如只要在烧结的接合区域和/或相应的焊料区域内不形成或仅形成可忽略的空腔或气穴,例如通过烧结的接合区域或相应的焊料区域不具有恒定的层厚度所产生。此外,如果只存在可忽略的尖峰形成,则较小的偏差仍然是可容忍的。
例如,中间层或烧结的接合区域和相应的焊料区域可具有10μm至300μm、优选50μm至150μm或90μm至110μm的厚度,即大约100μm的层厚度。根据功率模块的设计方案,中间层或烧结的接合区域和/或相应的焊料区域的层厚度公差为±20%,特别是±10%或仅±5%还是能够接受的。
在此,结合该有利的设计方案提到的层厚度特别涉及制成的功率模块,即涉及在将相应的功率构件与基板通过加热中间层连接之后的状态。
在本发明的另一有利的设计方案中,相应的焊料区域具有最多约9mm2、特别是最多约4mm2的横截面。
在此,相应的焊料区域——在平行于基板的平坦上侧的平面中——能够具有环形的或圆形的或者矩形的或正方形的横截面。在正方形横截面的情况下,尺寸例如能够是3mm×3mm或2mm×2mm。也能够考虑更小的尺寸,例如1.6mm×1.6mm或小于2mm2或小于1mm2,即例如0.5mm×1mm。在此,在已经建立相应的功率构件与基板的连接之后,所说明的横截面能够特别地对应于相应的焊料区域的横截面。
在本发明的另一有利的设计方案中,基板包括直接接合铜(DCB)基板、绝缘金属基板(IMS)、活性金属钎焊(AMB)基板或电路板,其中,基板在其朝向中间层的一侧具有贵金属表面。
DCB基板和IMS尤其是载体结构,电印制导线和可能一个或多个半导体芯片、功率构件或其他构件能够施加到所述载体结构上或是可施加到所述载体结构上的。
贵金属表面例如能够具有金或银,其中,基板例如被相应地覆层。
所提出的、具有至少一个这种功率模块的设备尤其能够设计为整流器、逆变器或更一般地设计为变换器或变流器,或者能够包括这样的装置。特别地,所提出的功率模块或对应的设备能够在工业应用中、在电气或混合动力车辆中,即例如在火车、汽车、船、艇或飞机中使用。
如上所述,根据所提出的方法,能够提供并适当地设置所提出的功率模块的各个部件。能够将中间层加热至或略高于焊料的熔化温度,或者加热至或略高于烧结温度,以制造所提出的功率模块。为此,特别地,将整个装置加热至或略高于对应的温度。此外,特别根据烧结材料,能够将压力施加到中间层或整个装置上。例如,烧结材料和相应的焊料预制件能够设置在基板上:使得在加热之前,烧结材料和相应的焊料预制件之间的空腔仍然保留在基板上。
在本发明的另一有利的设计方案中,如果焊料的熔化温度高于烧结温度,则将中间层加热至焊料的熔化温度,或者如果烧结温度高于焊料的熔化温度,则将中间层加热至烧结温度。
在此,能够考虑在下文解释的变型形式。
根据第一变型形式,能够首先焊接并且然后烧结。为此,特别地,能够使用低熔点焊料,该焊料具有小于烧结温度的熔化温度。在所提出的功率模块的制造工艺期间,中间层或装置首先被加热到焊料的熔化温度,由此构成焊料连接。然后,通过进一步升高温度将中间层或装置加热至烧结温度,并且必要时将压力施加到中间层或装置上,由此创建烧结连接。在此,焊料优选地保持熔融态。在此,烧结连接的创建能够与焊料连接的创建一起在一个工艺步骤中执行,或者在尤其分开的工艺步骤中执行。
根据第二变体形式,能够首先烧结并且然后焊接。为此,特别地,能够使用高熔点焊料,其具有高于烧结温度的熔化温度。在所提出的功率模块的制造工艺期间,首先将中间层或装置加热至烧结温度,并且必要时将压力施加到中间层或装置上,由此创建烧结连接。然后,通过进一步升高温度将中间层或装置加热至焊料的熔化温度,由此创建焊料连接。由于焊料在熔化时因表面张力而倾向于形成球,因此在这种变型形式中尤其可抑制在烧结后仍会存在的空腔。在此,焊料连接的创建能够与烧结连接的创建一起在一个工艺步骤中执行,或者在单独的工艺步骤中执行。
在此,在本发明的另一有利的设计方案中,如果烧结温度小于或大于焊料的熔化温度,则用于借助烧结制成的接合区域的烧结材料的层厚度大于或小于用于相应的焊料区域的层厚度。
根据第一变型形式,其中,能够首先进行焊接并且然后进行烧结,烧结材料的层厚度因此小于焊料的层厚度。并且根据第二变型形式,其中,能够首先进行烧结并且然后进行焊接,烧结材料的层厚度因此大于焊料的层厚度。由于焊料在熔化时由于表面张力而倾向于形成球,所以在该变型形式中尤其能够抑制在烧结后仍会存在的空腔。烧结材料或焊料的所提到的层厚度在此涉及在通过加热和必要时施加压力创建两个连接之前的装置的状态。
在此,较厚的层优选比较薄的层厚10%至40%,优选15%至25%。在此,在一些实例中,较厚的层比较薄的层厚约10μm至40μm,优选15μm至25μm。
在本发明的一个替代的有利的设计方案中,焊料的熔化温度基本上等于烧结温度。
根据该另一变型形式,焊接和烧结实际上能够同时进行。为此能够使用焊料和烧结材料,其中,焊料的熔化温度基本上对应于烧结温度。在此,彼此相差小于10K、特别是小于5K的温度被认为是基本相同的。在此,烧结温度必要时能够与施加到中间层或装置上的压力相关。特别地,根据焊接和烧结方法,在烧结和焊接工艺中的温度能够非常相似,例如大约240°以熔化焊料和以进行烧结。因此,为了烧结目的,中间层或装置的加热足以确保焊料的熔化和焊接部位的可靠构成。特别地,因此不需要专门适配烧结工艺。在该变型形式中的优点是:能够尤其容易地在一个工作步骤中制造焊料连接和烧结连接。
在一些实例中,焊料预制件的层厚度能够选择为比烧结材料的层厚度稍厚,即例如厚5%至15%或大约5μm至15μm。烧结材料或焊料的所提到的层厚度在此涉及装置在通过加热和必要时施加压力创建两个连接之前的状态。
在此,在本发明的另一有利的设计方案中,借助烧结制成的接合区域的烧结材料的层厚度基本上等于用于相应的焊料区域的焊料的层厚度。
在通过加热和必要时施加压力创建两个连接之前,焊料预制件的厚度优选地基本上对应于烧结材料的厚度。特别地,除了小于±10μm或±10%、优选地小于±5μm或±5%,焊料预制件的厚度等于烧结材料的厚度。烧结材料或焊料的所提到的层厚度在此涉及装置在通过加热和必要时施加压力创建两个连接之前的状态。
用于制造所提出的功率模块的上面解释的、所提出的方法能够特别地包括结合所解释的有利的功率模块设计方案所解释的方法步骤。这尤其涉及用于制造中间层或相应焊料区域和(必要时)借助烧结制成的接合区域的所解释的方法步骤。
附图说明
下面根据附图所示的实施例更详细地描述和解释本发明。附图示出:
图1-图2示出所提出的功率模块的第一实施例和第二实施例,
图3-图6示出所提出的方法的第一实施例至第四实施例的流程图,
图7示出所提出的功率模块的第三实施例的制造中的第一中间状态,
图8-图9示出所提出的功率模块的第四实施例的制造中的第一中间状态和第二中间状态,
图10-图11示出所提出的功率模块的第五实施例的横截面图,和
图12示出所提出的电气设备的一个实施例。
具体实施方式
图1示出所提出的功率模块1的第一实施例,其中,示出贯穿功率模块1的横截面。
功率模块1具有基板2,在该基板上设置导电的中间层3。中间层3具有借助烧结制成的接合区域4。此外,功率模块1具有功率构件5,该功率构件设置在中间层3上并且该功率构件具有一个或多个与中间层3连接的连接部位6。此外,中间层3在连接部位6的区域中具有焊料区域7,该焊料区域与连接部位6连接并且该焊料区域借助于焊料预制件制造。
连接部位6尤其能够用作功率构件5的控制端子。此外,功率构件5能够附加地具有另一连接部位,该另一连接部位朝向借助烧结制成的接合区域4并且能够用作功率构件5的负载连接。原则上,也能够考虑多个这种另外的连接部位,该连接部位能够分别用作相应的功率构件5的负载连接。
在此,优选地,用于接触中间层3的连接结构已经存在于功率构件5中和基板2上。因此,特别地,基板2能够以结构化的方式构成,其中,所提到的结构在图1中没有更详细地示出。例如,能够通过以下方式实现结构化:基板2具有朝向中间层3的导电的表面,其中,该表面具有不导电的留空部或空隙,由此该表面的两个或多个区域彼此电绝缘。因此,特别地,还能够创建焊料区域7与借助烧结制成的接合区域4的电绝缘。例如,基板2也能够多层地设计。
烧结的接合区域4例如能够借助于烧结预制件来制造。替代地或附加地,烧结的接合区域4能够借助于3D打印、借助于覆层方法或借助于丝网/模板印刷来构成。
特别地,相应的焊料区域7或相应的焊料预制件能够没有助焊剂。
如图1所示,烧结的接合区域4和焊料区域7能够彼此并排地设置在基板2和功率构件5之间并且基本上具有相同的层厚度9。
相应的焊料区域7优选地具有至多大约9mm2、特别地至多4mm2的横截面,其中,考虑平行于基板2的平坦上侧的平面。
例如,基板2能够包括直接接合铜(DCB)基板、绝缘金属基板(IMS)、活性金属钎焊(AMB)基板或印刷电路板。
图2示出所提出的功率模块1的第二实施例,其中,又示出贯穿功率模块1的横截面。在此,与图1中相同的附图标记表示相同的对象。
基板2在其朝向中间层3的一侧具有贵金属表面8,例如具有金或银。在此,基板2包括直接接合铜(DCB)基板、绝缘金属基板(IMS)、活性金属钎焊(AMB)基板或印刷电路板。
在此,优选地,用于接触中间层3的连接结构特别地相对于贵金属表面8已经存在于功率构件5中和基板2上。因此,特别地,贵金属表面8能够被结构化地构成,其中,在图2没有详细示出所提到的结构。例如,能够通过以下方式实现结构化:即贵金属表面8形成导电表面,其中,该表面具有不导电的留空部或空隙,由此该表面的两个或多个区域彼此电绝缘。因此,特别地,还能够创建焊料区域7与借助烧结制成的接合区域4的电绝缘。例如,基板2也能够多层地设计。
此外,功率模块1具有两个连接部位6并且中间层具有两个焊料区域7。在此,相应的焊料区域7设置在相应的连接部位6的区域中并且与相应的连接部位6连接。相应的焊料区域7在此借助于焊料预制件制造。
两个连接部位6尤其用作功率构件5的控制连接。功率构件5能够附加地具有一个或多个另外的连接部位,该另外的连接部位朝向借助烧结制成的接合区域4并且能够用作功率构件5的一个或多个负载连接。
图3示出所提出的方法的第一实施例的流程图300。该流程始于步骤302并至少包括以下步骤。在步骤304中,提供基板。在步骤306中,在基板上提供用于烧结的接合区域的烧结材料和用于相应的焊料区域的焊料以形成中间层,其中,用于相应的焊料区域的焊料在相应的功率构件的相应的连接部位的区域中提供并且作为焊料预制件提供。在步骤308中,将相应的功率构件设置在借助烧结制成的接合区域和相应的焊料区域上或中间层上。在步骤310中,将中间层加热至焊料的熔化温度或烧结温度。该流程以步骤312结束。
在该方法的有利的设计方案中,流程图还能够包括在上文和下文进一步解释的另外的步骤。
图4示出所提出的方法的第二实施例的流程图。提供并适当地设置基板2、用于烧结的接合区域4的烧结材料、用于焊料区域7的焊料预制件以及功率构件5。在此,仅为了清楚起见,在图4中未详细示出相应的连接部位6。
在该实施例中,首先进行焊接,并且然后进行烧结。为此,特别地,能够使用低熔点焊料,该低熔点焊料具有小于烧结温度的熔化温度。在所提出的功率模块1的制造工艺期间,中间层3或装置首先被加热到焊料的熔化温度,由此创建焊料连接。在此,焊料优选地保持熔融状态。然后通过进一步升高温度将中间层3或装置加热至烧结温度,并且必要时将压力施加到中间层3或装置上,由此创建烧结连接。在此,烧结连接的创建能够与焊料连接的创建一起在一个工艺步骤中执行,或者在一个与其分开的工艺步骤中执行。
在此,焊料预制件优选比烧结材料厚10%至40%,优选15%至25%。在此,在一些实例中,焊料预制件比烧结材料厚约10μm至40μm,优选15μm至25μm。在此,在通过加热和必要时施加压力创建两个连接之前,所提到的烧结材料或焊料的层厚度涉及装置的状态。
图5示出所提出的方法的第三实施例的流程图。又提供并适当地设置基板2、用于接合区域4的烧结材料、用于焊料区域7的焊料预制件和功率构件5。在此,同样仅为了清楚起见,相应的连接部位6在图5中未详细示出。
根据该实施例,实际上同时进行焊接和烧结。为此能够使用焊料和烧结材料,其中,焊料的熔化温度基本上对应于烧结温度。特别地,根据焊接和烧结方法,在烧结和焊接工艺中的温度能够非常相似,例如为大约240°以用于熔化焊料和用于烧结。因此,为了烧结目的而加热中间层3或装置足以确保焊料的熔化和可靠地形成焊接部位。特别地,因此不需要特别适配烧结工艺。该变型方案的优点是:在一个工作步骤中能够特别容易地制造焊料连接和烧结连接。
在通过加热和必要时施加压力来创建两个连接之前,焊料预制件的厚度优选地基本上对应于烧结材料的厚度。特别地,焊料预制件的厚度降至小于±10μm或±10%,优选地小于±5μm或±5%,等于烧结材料的厚度。
在一些实例中,焊料预制件的层厚度9能够选择为比烧结材料的层厚度9稍厚,即例如厚5%至15%或大约5μm至15μm。在此,在通过加热和必要时施加压力创建两个连接之前,烧结材料或焊料的所提到的层厚度涉及装置的状态。
图6示出所提出的方法的第四实施例的流程图。又提供并适当地设置基板2、用于接合区域4的烧结材料、用于焊料区域7的焊料预制件以及功率构件5。在此,又仅为了清楚起见,在图6中未详细地示出相应的连接部位6。
根据该实施例,首先进行烧结,并且然后进行焊接。为此,特别地,能够使用高熔点焊料,该高熔点焊料具有高于烧结温度的熔化温度。在所提出的功率模块1的制造工艺期间,首先将中间层3或装置加热至烧结温度,并且必要时将压力施加到中间层或装置上,由此创建烧结连接。然后,通过进一步升高温度将中间层3或装置加热至焊料的熔化温度,由此创建焊料连接。在此,焊料连接的创建能够与烧结连接的创建一起在一个工艺步骤中执行,或者在一个与其分开的工艺步骤中执行。
在此,烧结材料优选比焊料预制件厚10%至40%,优选15%至25%。在此,在一些实例中,烧结材料比焊料预制件厚约10μm至40μm,优选15μm至25μm。在此,在通过加热和必要时施加压力创建两个连接之前,所提到的烧结材料或焊料的层厚度涉及装置的状态。
图7示出在所提出的功率模块1的第三实施例的制造中的第一中间阶段。在此示出了基板2的俯视图,在该第三实施例中,在该基板上施加用于接合区域4的烧结膏。此外,用于焊料区域7的焊料预制件施加到基板2上,其中,焊料区域7与接合区域4间隔开地设置。
图8和图9示出在所提出的功率模块1的第四实施例的制造中的第一中间阶段和第二中间阶段。与在图7中所示的第三实施例那样,又示出基板2的俯视图。如图8中所示,用于烧结的接合区域4的烧结预制件和用于焊料区域7的焊料预制件施加在基板2上,其中,焊料区域7又与烧结的接合区域4间隔开地设置。如在图9中所示,功率构件5与烧结的接合区域4和焊料区域7连接,并且现在起在所示出的俯视图中覆盖它们。
图10和图11示出贯穿所提出的功率模块1的第五实施例的横截面。
在此,图10示出贯穿功率模块1的烧结的接合区域4的横截面。对于该烧结的接合区域4,使用烧结预制件,该烧结预制件在烧结后具有硬的烧结芯4”。烧结的接合区域4还包括两个部分地在烧结期间形成的边缘区域4',其中,一个边缘区域设置在烧结芯4”与基板2之间并且另一边缘区域设置在烧结芯4”与功率构件5之间。例如,烧结的接合区域4能够具有构成为实心材料的烧结芯4”,该烧结芯在两侧上、即朝向功率构件5和朝向基板2分别具有烧结材料。附加地,还能够考虑分层的、烧结的接合区域4,其中,烧结材料和实心材料以层的方式交替,例如烧结材料-实心材料-烧结材料-实心材料-烧结材料。
在此,图11示出贯穿功率模块1的焊料区域7的横截面。将焊料预制件用于该焊料区域7。此外,示出连接部位6,该连接部位设置在其余的功率构件5和焊料区域7之间。在此,焊料区域7设置在连接部位6和基板7之间。
图12示出所提出的电气设备10的一个实施例。电气设备10具有所提出的功率模块1。例如,电气设备10设计为转换器。
Claims (13)
1.一种功率模块(1),包括:
-基板(2),
-导电的中间层(3),所述中间层设置在所述基板(2)上并且所述中间层具有借助烧结制成的接合区域(4),和
-至少一个功率构件(5),所述功率构件分别设置在所述中间层(3)上并且所述功率构件分别具有至少一个与所述中间层(3)连接的连接部位(6),
其特征在于,
-所述中间层(3)在相应的所述连接部位(6)的区域中具有借助焊料预制件制成的焊料区域(7),所述焊料区域与相应的所述连接部位(6)连接。
2.根据权利要求1所述的功率模块(1),其中,借助于烧结预制件制造借助烧结制成的所述接合区域(4)。
3.根据权利要求1所述的功率模块(1),其中,借助于3D打印、借助于覆层方法或借助于丝网/模板印刷构造借助烧结制成的所述接合区域(4)。
4.根据前述权利要求中至少一项所述的功率模块(1),其中,相应的所述焊料区域(7)或相应的所述焊料预制件是无助焊剂的。
5.根据前述权利要求中至少一项所述的功率模块(1),其中,借助烧结制成的所述接合区域(4)和相应的所述焊料区域(7)彼此并排地设置在所述基板(2)与相应的所述功率构件(5)之间,并且所述接合区域和所述焊料区域基本上具有相同的层厚度(9)。
6.根据前述权利要求中至少一项所述的功率模块(1),其中,相应的所述焊料区域(7)具有最多约9mm2、尤其最多约4mm2的横截面。
7.根据前述权利要求中至少一项所述的功率模块(1),其中,所述基板(2)包括直接接合铜(DCB)基板、绝缘金属基板(IMS)、活性金属钎焊(AMB)基板或者印刷电路板,并且
其中,所述基板(2)在所述基板的朝向所述中间层(3)的一侧具有贵金属表面(8)。
8.一种电气设备(10),特别是转换器,具有至少一个根据前述权利要求中至少一项所述的功率模块(1)。
9.一种用于制造根据权利要求1至6中任一项所述的功率模块(1)的方法,所述方法包括以下方法步骤:
-提供所述基板(2),
-将用于待烧结的所述接合区域(4)的烧结材料和用于相应的所述焊料区域(7)的焊料设置在所述基板(2)上以形成所述中间层(3),
其中,将用于相应的所述焊料区域(7)的所述焊料作为焊料预制件提供至相应的所述功率构件(5)的相应的所述连接部位(6)的区域中,
-将相应的所述功率构件(5)设置在所述接合区域(4)和相应的所述焊料区域(7)上或设置在所述中间层(3)上,并且
-将所述中间层(3)加热到所述焊料的熔化温度或加热到烧结温度。
10.根据权利要求9所述的方法,其中,如果所述焊料的熔化温度高于所述烧结温度,则将所述中间层(3)加热到所述焊料的熔化温度,或者如果所述烧结温度高于所述焊料的熔化温度,则将所述中间层加热到所述烧结温度。
11.根据权利要求9或10中任一项所述的方法,其中,如果所述烧结温度小于或大于所述焊料的熔化温度,则用于借助烧结制成的所述接合区域(4)的所述烧结材料的层厚度(9)大于或小于用于相应的所述焊料区域(7)的所述焊料的层厚度(9)。
12.根据权利要求9所述的方法,其中,所述焊料的熔化温度基本上等于所述烧结温度。
13.根据权利要求9或12中任一项所述的方法,其中,用于借助烧结制成的所述接合区域(4)的所述烧结材料的层厚度(9)基本上等于用于相应的所述焊料区域(7)的所述焊料的层厚度(9)。
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EP21157873.7A EP4047648A1 (de) | 2021-02-18 | 2021-02-18 | Leistungsmodul mit einem mittels sintern und löten mit einem substrat verbundenen leistungs-bauelement und entsprechendes herstellungsverfahren |
EP21157873.7 | 2021-02-18 | ||
PCT/EP2021/085263 WO2022174955A1 (de) | 2021-02-18 | 2021-12-10 | Leistungsmodul, elektrisches gerät und verfahren zur herstellung eines leistungsmoduls |
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JP4877046B2 (ja) * | 2007-04-25 | 2012-02-15 | 富士電機株式会社 | 半導体装置およびその製造方法 |
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US8555491B2 (en) * | 2007-07-19 | 2013-10-15 | Alpha Metals, Inc. | Methods of attaching a die to a substrate |
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DE102015200987A1 (de) * | 2015-01-22 | 2016-07-28 | Robert Bosch Gmbh | Verfahren zum Herstellen einer Lötverbindung und Schaltungsbauteil |
DE112015006049T5 (de) * | 2015-01-26 | 2017-10-12 | Mitsubishi Electric Corporation | Halbleiterbauteil und verfahren zum herstellen eines halbleiterbauteils |
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