CN110637366B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN110637366B
CN110637366B CN201880032261.8A CN201880032261A CN110637366B CN 110637366 B CN110637366 B CN 110637366B CN 201880032261 A CN201880032261 A CN 201880032261A CN 110637366 B CN110637366 B CN 110637366B
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insulating substrate
layer
semiconductor switching
switching element
semiconductor device
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CN110637366A (zh
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谷江尚史
岛津浩美
伊藤博之
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Proterial Ltd
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Hitachi Metals Ltd
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Abstract

本发明的目的在于，提供一种在陶瓷层中形成有配线层的半导体器件，其能够使半导体开关元件的栅极端子与配线层之间可靠地导通。本发明的半导体器件在形成于绝缘层上的陶瓷层的内部具有配线层，并且具有与半导体开关元件的栅极端子以外的端子连接的金属层，所述半导体开关元件的栅极端子与所述配线层经由用导电材料形成的连接部电连接，与所述金属层相比，所述连接部更加向所述半导体开关元件突出(参照图1)。

Description

半导体器件及其制造方法
技术领域
本发明涉及功率系半导体器件及其制造方法。
背景技术
近年来，多种多样的设备的电驱动不断进展，在对由成为其动力的数kV的电压及数百A的电流构成的大功率的交流直流的整流及AC电动机的转速进行控制的功率模块中，不断寻求小型化、高性能化、高可靠性。由于在功率模块动作时，搭载于内部的半导体芯片会发热，因此，为了实现小型化，需要高散热化。另外，因为半导体芯片在数kV的高电压下进行动作，所以需要确保与外部的绝缘性。另外，为了有效地控制半导体芯片，需要具备设计或制造工艺的自由度高的控制电路。
下述专利文献1中公开有涉及上述问题的技术。该文献中，在烧结的陶瓷基片上层叠低温烧成陶瓷(LTCC：Low Temperature Co－fired Ceramics)的未烧结的生片，并将其烧成而形成复合陶瓷基片，通过在复合陶瓷基片上安装电容器或IC芯片等电子部件而构成模块。
现有技术文献
专利文献
专利文献1：日本特开2012-033664号公报。
发明内容
发明要解决的技术问题
使用具有由配线和陶瓷构成的控制信号电路层和由金属构成的电路层的陶瓷基片，使控制信号电路层的配线层构成栅极电路，电路用厚金属层形成发射极电路或集电极电路，由此能够构成功率模块。为了使这种功率模块高可靠性地动作，需要可靠地得到搭载的半导体芯片与功率模块的电路的电导通。即，需要确保半导体芯片的栅极端子与控制信号电路的配线层的导通，并且确保发射极端子或集电极端子与由金属构成的电路层的导通。此时半导体芯片的栅极端子，因为其面积比发射极端子或集电极端子小，所以从定位或接合后的耐热变形的观点考虑，比发射极端子或集电极端子更难以确保导通。另外，由陶瓷构成的控制信号电路层的热传导率比由金属构成的电路层小。
本发明是鉴于上述问题而开发的，其目的在于，提供一种在陶瓷层中形成配线层的半导体器件，该半导体器件能够确保半导体开关元件的栅极端子与配线层之间的导通，并且确保散热性，从而能够同时实现高散热和高可靠性。
用于解决问题的技术方案
本发明的半导体器件在形成于绝缘层上的陶瓷层的内部具有配线层，并且具有与半导体开关元件的栅极端子以外的端子连接的金属层，所述半导体开关元件的栅极端子与所述配线层经由用导电材料形成的连接部电连接，与所述金属层相比，所述连接部更加向所述半导体开关元件突出。
发明效果
根据本发明的半导体器件，能够确保半导体开关元件的栅极端子与配线层之间的导通，并且确保散热性，从而能够同时实现高散热和高可靠性。
附图说明
图1是实施方式1的半导体器件1的结构图。
图2是第一绝缘基片13的结构图。
图3是第二绝缘基片14的结构图。
图4是半导体芯片的结构图。
图5是说明半导体器件1的部件展开的图。
图6是半导体器件1的剖视图。
图7是说明制造半导体器件1的方法的图。
图8是实施方式2的半导体器件1的剖视图。
图9是实施方式3的半导体器件1的剖视图。
图10是实施方式4的半导体器件1的剖视图。
图11是实施方式5的半导体器件1的整体结构图。
具体实施方式
＜实施方式1＞
图1是本发明实施方式1的半导体器件1的结构图。半导体器件1在内部搭载有IGBT(Insulated Gate Bipolar Transistor)芯片11和二极管芯片12。通过外部引出用的栅极端子15、外部引出用的发射极端子16、外部引出用的集电极端子17引出到半导体器件1的外部，半导体器件1能够作为倒相电路的一部分起作用。在此，表示了在半导体器件1的内部配置了两个IGBT芯片11和一个二极管芯片12的例子。
在半导体器件1的一个面配置有发射极端子及栅极端子用的第二绝缘基片14，在另一个面配置有集电极端子用的第一绝缘基片13。半导体芯片动作时产生的热能够从半导体器件1的两面进行散热。IGBT芯片11、二极管芯片12、第二绝缘基片14、第一绝缘基片13通过模制树脂18进行模制。由此，确保绝缘性及可靠性。在本实施例中，将高耐热的环氧类的树脂用于模制树脂18。
图2是第一绝缘基片13的结构图。集电极端子用的第一绝缘基片13具有绝缘层21。在绝缘层21的一个面配置有作为金属层的电路层22，在另一个面配置有散热层23。外部引出用的集电极端子17与电路层22连接，外部设备与半导体器件1经由集电极端子17电导通。在本实施方式1中，使用由氮化硅构成的陶瓷作为绝缘层21。因为相同的材料的绝缘性及热传导性优异并且具有高强度，所以从散热性和可靠性的观点考虑选择相同的材料。根据半导体器件1的用途及使用环境，还能够使用氧化铝或氮化铝等其它陶瓷。使用铜作为电路层22、散热层23及外部引出用的集电极端子17。这是因为电传导性及热传导性优异。根据半导体器件1的用途及使用环境还能够使用铝等其它金属材料。在本实施方式中，将散热层23的表面设为平滑的形状。这是为了在使用本半导体器件1时容易连接散热翅片等。另外，也能够在散热层23的表面设置翅片，使用散热层23本身来作为散热翅片。此时，虽然需要设置翅片，但不会增加由散热层23与散热翅片之间的连接部件等引起的热阻，能够进一步提高散热性。
图3是第二绝缘基片14的结构图。栅极端子用的第二绝缘基片14具有绝缘层31。在绝缘层31的一个主面配置有散热层34。在绝缘层31的另一个主面配置有作为金属层的电路层32和作为栅极端子用的配线层的绝缘配线33。
在本实施方式1中，使用由氮化硅构成的陶瓷作为绝缘层31。原因与绝缘层21相同。通过使用与第一绝缘基片13的绝缘层21相同的材料，能够得到半导体器件1整体的热变形平衡。根据半导体器件1的用途及使用环境，还能够使用氧化铝或氮化铝等其它陶瓷。使用铜作为电路层32、散热层34及外部引出用的发射极端子16。这是因为电传导性及热传导性优异。根据半导体器件1的用途及使用环境还能够使用铝等其它金属材料。
在电路层32的与半导体芯片接合的部位设置有作为连接部的突起35。突起35用于在将半导体芯片和电路层32接合时使电路层32与半导体芯片周边部之间隔开距离而确保耐压性。配置于与IGBT芯片11相对的部位的突起35形成为コ字型，以避开IGBT芯片11的栅极端子。因为二极管芯片12不具有栅极端子，所以配置于与二极管芯片12相对的位置的突起35不是コ字型而形成为矩形。另外，将散热层34的表面设为平滑的形状。这是为了在使用半导体器件1时容易连接散热翅片等。另外，也能够在散热层34的表面设置翅片，使用散热层34本身作为散热翅片。此时，虽然需要设置翅片，但不会增加由散热层34与散热翅片之间的连接部件等引起的热阻，能够进一步提高散热性。
在IGBT芯片11的与栅极端子相对的部位配置有与栅极端子导通的栅极端子用的绝缘配线33。使用低温烧结陶瓷作为绝缘配线33。通过层叠由烧结前的陶瓷材料和金属浆料构成的片材，并在1000℃程度以下的低温下将陶瓷和金属同时进行烧结，能够形成将金属配线层配置于内部的陶瓷绝缘体。此外，在本实施方式1中，作为低温烧结陶瓷，使用混合了以镁、铝、硅为主成分的三种以上的氧化物的材料。如果为将它们在1000℃下烧结的多结晶烧结体等，则通过印刷等形成并层叠金属浆料，而容易自由设计内部配线层，故而优选。另外，形成由内部具有金属配线层的陶瓷构成的绝缘配线33，其中，该金属配线层将用于与栅极端子连接的突起36和外部引出用的栅极端子15电连接。将低温烧结陶瓷烧结之后，设置于在陶瓷内部配置的配线表面。在本实施方式1中，通过扩散接合而将预先准备的栅极端子连接用的突起36与配线表面接合。除此以外，还能够在使用接合材进行的接合中设置突起、或通过在配线表面实施镀敷而设置突起。此时，突起36构成为面积比突起35小，但高度比突起35大，比突起35更向IGBT芯片11的栅极端子突出。
图4是半导体芯片的结构图。在IGBT芯片11的表面配置有栅极端子41和发射极端子42，栅极端子41的面积比发射极端子42小。在IGBT芯片11的背面配置有集电极端子43。二极管芯片12不具有栅极端子。其中，在IGBT芯片11的表面配置有芯片表面的栅极端子41和芯片表面的发射极端子42，芯片表面的栅极端子41的面积比芯片表面的发射极端子42小。在IGBT芯片11的背面具有集电极端子43。另一方面，二极管芯片12不具有栅极端子，而在表面具有阴极端子，在背面具有阳极端子。在本实施方式中，在半导体器件1的内部具有两个IGBT芯片11和一个二极管芯片12，但也能够变更IGBT芯片11或二极管芯片12的数量。另外，也能够使用MOS－FET芯片等代替IGBT芯片11。只要它们根据半导体器件1所要求的的容量及特性进行选择即可。
图5是说明半导体器件1的部件展开的图。在此示出除模制树脂18以外的部件。在半导体器件1中，通过将第二绝缘基片14和第一绝缘基片13上下配置，并在这些基片之间配置IGBT芯片11和二极管芯片12，构成电路。IGBT芯片11的发射极端子42和二极管芯片12的发射极端子通过接合材51与第二绝缘基片14连接。栅极端子41通过接合材52与第二绝缘基片14连接。IGBT芯片11的集电极端子43和二极管芯片12的集电极端子通过接合材53与第一绝缘基片13连接。该接合方式因为不需要接合线等，所以能够提供容易控制电路长及电阻，且电特性优异的电路。
在半导体器件1的上下表面分别配置有第二绝缘基片14的散热层34和第一绝缘基片13的散热层23。由此，能够从半导体器件1的两面有效地散热，所以能够提供在动作时从半导体芯片产生的热的散热特性优异的半导体器件1。
在将半导体器件1的各部件投影到主面上时，IGBT芯片11/二极管芯片12/绝缘配线33重叠的区域仅在IGBT芯片11的栅极端子41附近，IGBT芯片11的其它区域没有与绝缘配线33重叠。二极管芯片12在全区域内没有与绝缘配线33重叠。
构成电路层32的铜与构成绝缘配线33的低温烧结陶瓷比较，热传导率大。因此，通过将配置于各半导体芯片与散热层34之间的区域的绝缘配线33的面积最小化，且尽可能增加电路层32的面积，能够提高散热性。在本实施方式1中，因为仅在栅极端子周边形成绝缘配线33，所以能够大幅确保电路层32的面积并提高散热性。为了提高散热性，使由半导体芯片产生的热沿厚度方向消散，并且沿水平方向快速地扩散是有效的。在本实施方式中，构成电路层32的铜的一方的热传导率比构成配置于半导体芯片上下的绝缘基片的绝缘层的氮化硅高，通过将电路层32的厚度设为绝缘层厚度以上，能够进一步促进热向水平方向的扩散。
图6是半导体器件1的剖视图。在此示出IGBT芯片11附近的剖面放大图。如使用图3所说明的那样，从栅极端子用的绝缘配线33向半导体芯片突出的栅极端子连接用的突起36的高度比发射极电路层的连接用的突起35大。即，相对于发射极端子及栅极端子用绝缘基片的绝缘层31的主面，栅极端子连接用的突起36比发射极电路层的连接用的突起35的前端更突出。换言之，突起36的IGBT11侧的端部与IGBT芯片11之间的距离比突起35的IGBT芯片11侧的端部与IGBT芯片11之间的距离小。在各突起(突起35、突起36)和IGBT芯片11之间配置接合材51、52。如通过后述的制造方法所说明的那样，涂覆的接合材51、52的厚度相同，但因为因栅极端子连接用的突起36突出而在制造工序中进一步按压接合材52，所以完成后的接合材52比接合材51薄。这样，因为通过进一步按压接合材52进行制造，能够更可靠地确保栅极端子的导通，所以能够提高连接可靠性。
图7是说明制造半导体器件1的方法的图。首先，将对IGBT芯片11和二极管芯片12没有实施任何加工的状态设为初期状态(图7(a))。
图7(b)是涂覆接合材的工序。在本实施方式1中，首先在IGBT芯片11、二极管芯片12的表面涂覆接合材。在接合材中将Sn设为主成分的焊锡材料中，使用将熔点高的Sn和Cu设为主成分的材料作为接合材51及52，使用掩模将包含挥发成分的助焊剂状的焊锡涂覆到各半导体芯片的表面。此时，以IGBT芯片11的栅极端子41和发射极端子42不会电短路的方式，配置接合材51和52。在使用掩模涂覆接合材时，为了涂覆厚度不同的接合材，需要准备复杂的掩模实施多次涂覆工序。因此，在本实施方式1中，将涂覆的接合材的厚度设为相同，通过每一个半导体芯片使用一个掩模的一次的涂覆工序，涂覆接合材。
图7(c)是使用接合材51和52将半导体芯片与第二绝缘基片14接合的工序。第二绝缘基片14及半导体芯片的定位使用碳夹具实施。通过使用回流装置在将接合材51和52溶融后凝固，将各部件接合。碳夹具使用上下分割的夹具，在下夹具的上表面设置用于与上夹具定位的销和用于定位发射极端子及栅极端子用的绝缘基片14的凹部。在上夹具设置供下夹具的销通过的孔和用于定位各半导体芯片的贯通上下表面的孔。在制造时，以散热层34向下的方式在下夹具的凹部配置发射极端子及栅极端子用的绝缘基片14，接着，使用下夹具的销和上夹具的孔来定位下夹具和上夹具，接着，以从用于定位上夹具的各半导体芯片的孔涂覆的接合材51、52向下的方式配置各半导体芯片。在该状态下，通过使用回流装置进行接合，将各半导体芯片与发射极端子及栅极端子用的绝缘基片14接合。因为突起36的高度比突起35的高度大，所以当接合材51和52为相同的厚度时，容许接合时的半导体芯片的斜率及各部件的尺寸公差而进一步按压接合材52，由此，能够可靠地连接栅极端子。因此，能够提高可靠性高的半导体器件1。
图7(d)是表示第一绝缘基片13的电路层22侧的面。图7(e)是在电路层22的表面涂覆接合材53的工序。作为接合材53使用以Sn为主成分的焊锡材料，利用掩模涂覆膏状的焊锡材料。作为接合材53，使用将比接合材51和52熔点低的Sn、Ag、Cu为主成分的焊锡材料。
图7(f)是将第一绝缘基片13(已接合半导体芯片)和第二绝缘基片14接合的工序。第一绝缘基片13和第二绝缘基片14的定位使用碳夹具实施。通过使用回流装置溶融接合材53后使其凝固，接合各基片。因为接合材53的熔点比接合材51和52的熔点低，所以能够在回流工序中防止接合材51和52再溶融。此外，在本实施方式中，利用Ag的含量差异来将熔点设为不同，但也可以使用Bi及In等添加剂来控制熔点。
图7(g)是通过模制树脂18密封装置整体的工序。通过本工序完成半导体器件1。即，形成如下半导体器件的制造方法：首先，在半导体芯片的栅极端子及发射极端子涂覆接合材，接着使用该接合材将半导体芯片和发射极端子及栅极端子用的绝缘基片同时接合，接着将半导体芯片和集电极端子用的绝缘基片接合。该制造方法能够获得如下效果：首先通过连接栅极端子而可靠地确保小面积的栅极端子的导通，并且通过将发射极端子及栅极端子同时接合而能够简化制造工艺。
＜实施方式1：汇总＞
在本实施方式1的半导体器件1中，与突起35相比，突起36从由陶瓷材料和配线层构成的绝缘配线33更加向IGBT芯片11突出。由此，能够使面积小的栅极端子与配线层可靠地导通。
在本实施方式1的半导体器件1中，热传导率小的绝缘配线33仅配置于栅极端子周边，以确保更多的热传导率大的电路层32的面积。由此，能够确保充分的散热性。
＜实施方式2＞
图8是本发明的实施方式2的半导体器件1的剖视图。在本实施方式2中，突起36为越靠近前端(靠近IGBT芯片11侧的端部)越细的前端变细的形状。其他结构与实施方式1相同。在本实施方式2中，因为突起36为前端变细的形状，所以在回流工序中接合材52软化时突起36陷入接合材52的内部，能够更可靠地连接栅极端子。此外，在本实施方式中，通过扩散接合而将预先准备的栅极端子连接用的突起36与配线表面接合。除此以外，还能够在使用接合材的接合中设置突起，或通过在配线表面实施镀敷而设置突起。
＜实施方式3＞
图9是本发明实施方式3的半导体器件1的剖视图。在本实施方式3中，突起36具有弯曲结构，且高度方向的刚性比实施方式1小。其他结构与实施方式1同样。将突起36与栅极端子连接时，通过突起36强烈地按压IGBT芯片11的表面时，有可能会使IGBT芯片11表面的电极及内部的半导体元件破损。通过减小突起36的高度方向的刚性，能够可靠地防止将IGBT芯片11表面的电极及内部的半导体元件极端强烈按压，能够提供可靠性更高的半导体器件。
在本实施方式3中，还能够代替弯曲结构或与其并用地通过弹簧形状或锯齿形状等其他结构来降低高度方向的刚性。或者，通过将纵弾性系数小的材料用于突起36，也能够降低高度方向的刚性。能够根据突起36的制造方法及制造工艺选择采用它们中的任一种。
＜实施方式4＞
图10是本发明的实施方式4的半导体器件1的剖视图。在本实施方式4中，在接合材52的内部配置大致球形状的芯部件101代替突起36。其他结构与实施方式1同样。作为芯部件101，使用在铜球的表面进行镀镍进而在其上实施镀Sn的铜芯球。在本实施方式4中，将芯部件101的至少一部分配置于比突起35更靠近IGBT芯片11的位置。由此，能够将栅极端子41与配线层更可靠地连接。
在制造工艺中，通过回流装置使接合材52溶融、凝固时，芯部件101表面的镀Sn溶融、凝固而可靠地与栅极端子41导通，另一方面，因为构成芯部件101的铜及镍不溶融，所以能够确保绝缘配线33和IGBT芯片11之间的距离地将它们连接。
本实施方式4中，使用大致球形状的芯部件101，但如果为能够得到上述功能的形状，则还能够使用例如粉碎成多边形状或颗粒状的状态下的形状等的其他形状。另外，作为芯部件101，只要为经受回流工艺的高温的材料，则能够使用聚酰亚胺制的球材料等其他材料。这些可以根据芯部件101的制造方法及制造工艺来选择。
＜实施方式5＞
图11是本发明的实施方式5的半导体器件1的整体结构图。在实施方式1中，绝缘配线33为大致长方形，与此相对，在本实施方式5中，绝缘配线33具有向各突起36(即各栅极端子)分支的形状。
在本实施方式5中，在将半导体器件1的各部件投影到主面上时，绝缘配线33和IGBT芯片11仅在栅极端子41附近重叠。由此，能够将发射极端子42的正面与突起35连接。与构成绝缘配线33的低温烧结陶瓷比较，构成突起35的铜的热传导率大。因此，如本实施方式5，通过进一步增大IGBT芯片11与突起35接合的面积，能够有效地冷却半导体器件1。此外，在本实施方式中，IGBT用于开关元件，但在使用MOS－FET的情况下，栅极端子用的绝缘配线33仅在MOS－FET芯片和栅极端子附近重叠。
在本实施方式5中，因为绝缘配线33具有分支的复杂的形状，所以在将多个栅极端子用的绝缘配线33一块制造后需要通过切割加工等切断绝缘配线33，且制造难度变高。但是，也能够如在烧结陶瓷前的生片的状态下切断后进行烧结那样，通过与实施方式1不同的制造方法制造绝缘配线33。可以根据这些加工方法及半导体器件1中所要求的冷却性能等来选择适当的实施方式。
＜本发明的变形例＞
本发明不限定于上述实施方式，而包含各种各样的变形例。例如，上述的实施方式是为了容易理解本发明而进行详细说明的内容，未必限定于具有说明的全部的结构的内容。另外，能够将某实施方式的结构的一部分替换成其他实施方式的结构，另外，还能够在某实施方式的结构中添加其他实施方式的结构。另外，关于各实施方式的结构的一部分能够进行其他结构的追加、删除、替换。
在以上的实施方式中，对在半导体器件1的内部具有两个IGBT芯片11和一个二极管芯片12的例字进行了说明，但也能够变更IGBT芯片11及二极管芯片12的数量。也可以使用MOS-FET(Metal-Oxide-Semiconductor Field-Effect Transistor)芯片等代替IGBT芯片11。这些可根据半导体器件1中要求的容量及特性来选择。
符号说明
1：半导体器件
11：IGBT芯片
12：二极管芯片
13：第一绝缘基片
14：第二绝缘基片
15：栅极端子
16：发射极端子
17：集电极端子
18：模制树脂
21：第一绝缘基片的绝缘层
22：第一绝缘基片的电路层
23：第一绝缘基片的散热层
31：第二绝缘基片的绝缘层
32：第二绝缘基片的电路层
33：绝缘配线
34：第二绝缘基片的散热层
35：突起
36：突起
41：栅极端子
42：发射极端子
43：集电极端子
51：接合材
52：接合材
53：接合材
101：芯部件。

Claims (13)

1.一种包括半导体开关元件的半导体器件，其特征在于，包括：
第一绝缘基片，其安装有所述半导体开关元件；和
第二绝缘基片，其具有绝缘层，在所述绝缘层的一个表面具有配线层和金属层，
所述绝缘层的所述一个表面和所述第一绝缘基片的安装有所述半导体开关元件的表面彼此相对地配置，
所述配线层形成在陶瓷层的内部，该陶瓷层形成在所述绝缘层的所述一个表面，
所述半导体开关元件的栅极端子与所述配线层经由用导电材料形成的连接部和第一接合材电连接，
所述半导体开关元件的除所述栅极端子以外的端子与所述金属层经由第二接合材电连接，
从所述绝缘层的所述一个表面到所述连接部的所述第一绝缘基片侧的端部的距离，大于从所述绝缘层的所述一个表面到所述金属层的所述第一绝缘基片侧的表面的距离。
2.根据权利要求1所述的半导体器件，其特征在于：
所述连接部形成为从所述配线层向所述栅极端子突出的突起。
3.根据权利要求2所述的半导体器件，其特征在于：
所述连接部具有从所述绝缘层向所述栅极端子去前端变细的形状。
4.根据权利要求2所述的半导体器件，其特征在于：
所述连接部具有弹簧结构。
5.根据权利要求1所述的半导体器件，其特征在于：
所述连接部形成为配置在所述第一接合材的内部的芯部件。
6.根据权利要求1所述的半导体器件，其特征在于：
所述第一绝缘基片还安装有二极管芯片，
所述陶瓷层形成于以下位置，即：在将所述第一绝缘基片和所述第二绝缘基片投影到相对面上时，与所述半导体开关元件重叠且与所述二极管芯片不重叠的位置。
7.根据权利要求1所述的半导体器件，其特征在于：
所述半导体开关元件为IGBT或MOSFET，
所述陶瓷层形成于以下位置，即：在将所述第一绝缘基片和所述第二绝缘基片投影到相对面上时，与所述半导体开关元件的栅极端子重叠的位置，
所述金属层配置于以下位置，即：在将所述第一绝缘基片和所述第二绝缘基片投影到相对面上时，与所述陶瓷层不重叠且与所述半导体开关元件的发射极端子重叠的位置。
8.根据权利要求1所述的半导体器件，其特征在于：
所述第一绝缘基片在没有安装所述半导体开关元件的表面具有散热层，
所述第二绝缘基片在不具有所述配线层和所述金属层的另一个表面具有散热层。
9.根据权利要求1所述的半导体器件，其特征在于：
所述半导体开关元件为IGBT或MOSFET，
所述第一绝缘基片在安装有所述半导体开关元件的表面上具有金属层，所述第一绝缘基片的金属层与所述半导体开关元件的集电极端子电连接。
10.根据权利要求1所述的半导体器件，其特征在于：
所述第一绝缘基片安装有多个所述半导体开关元件，
所述配线层具有矩形的平板形状，
所述配线层形成于以下位置，即：在将所述第一绝缘基片和所述第二绝缘基片投影到相对面上时，与各所述半导体开关元件的栅极端子重叠的位置。
11.根据权利要求1所述的半导体器件，其特征在于：
所述第一绝缘基片安装有多个所述半导体开关元件，
所述配线层具有向各所述半导体开关元件的栅极端子分支的形状。
12.一种制造方法，其制造权利要求1所述的半导体器件，其特征在于：
所述半导体开关元件为IGBT或MOSFET，
所述方法具有：
在所述半导体开关元件的栅极端子和发射极端子涂覆所述第一接合材 的步骤；
使用所述第一接合材，将所述半导体开关元件与所述第二绝缘基片同时接合的步骤，
将所述半导体开关元件与所述第一绝缘基片接合的步骤。
13.根据权利要求12所述的制造方法，其特征在于：
所述方法还具有通过将陶瓷材料在1000℃以下进行烧结而形成所述陶瓷层的步骤。
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