CN102119435B - Soi芯片的制造方法 - Google Patents

Soi芯片的制造方法 Download PDF

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Publication number
CN102119435B
CN102119435B CN200980131333.5A CN200980131333A CN102119435B CN 102119435 B CN102119435 B CN 102119435B CN 200980131333 A CN200980131333 A CN 200980131333A CN 102119435 B CN102119435 B CN 102119435B
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China
Prior art keywords
soi
chip
layer
thickness
epitaxial growth
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Chinese (zh)
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CN102119435A (zh
Inventor
冈哲史
桑原登
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Shin Etsu Handotai Co Ltd
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Shin Etsu Handotai Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium

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  • Recrystallisation Techniques (AREA)
CN200980131333.5A 2008-08-28 2009-07-29 Soi芯片的制造方法 Active CN102119435B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008219981A JP4666189B2 (ja) 2008-08-28 2008-08-28 Ｓｏｉウェーハの製造方法
JP2008-219981 2008-08-28
PCT/JP2009/003573 WO2010023816A1 (ja) 2008-08-28 2009-07-29 Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ

Publications (2)

Publication Number Publication Date
CN102119435A CN102119435A (zh) 2011-07-06
CN102119435B true CN102119435B (zh) 2014-06-18

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CN200980131333.5A Active CN102119435B (zh) 2008-08-28 2009-07-29 Soi芯片的制造方法

Country Status (7)

Country Link
US (1) US8497187B2 (enExample)
EP (1) EP2320450B1 (enExample)
JP (1) JP4666189B2 (enExample)
KR (1) KR101573812B1 (enExample)
CN (1) CN102119435B (enExample)
TW (1) TWI453819B (enExample)
WO (1) WO2010023816A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5447111B2 (ja) * 2010-04-07 2014-03-19 信越半導体株式会社 Ｓｏｉウェーハの熱処理温度を求める方法及びランプ加熱型の気相成長装置における反応炉の温度管理方法
WO2011125305A1 (ja) * 2010-04-08 2011-10-13 信越半導体株式会社 シリコンエピタキシャルウエーハ、シリコンエピタキシャルウエーハの製造方法、及び半導体素子又は集積回路の製造方法
JP6086031B2 (ja) * 2013-05-29 2017-03-01 信越半導体株式会社 貼り合わせウェーハの製造方法
KR102361057B1 (ko) * 2016-06-14 2022-02-08 큐로미스, 인크 전력 및 rf 애플리케이션을 위한 가공된 기판 구조체
JP6824115B2 (ja) * 2017-06-19 2021-02-03 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN107265399A (zh) * 2017-07-03 2017-10-20 上海先进半导体制造股份有限公司 硅片密封腔体的制作方法
TWI751570B (zh) * 2020-06-02 2022-01-01 合晶科技股份有限公司 半導體基板及其形成方法
CN113764433B (zh) * 2020-06-02 2025-02-07 合晶科技股份有限公司 半导体基板及其形成方法
FR3119849B1 (fr) * 2021-02-12 2024-01-12 Soitec Silicon On Insulator Méthode de configuration pour ajuster les conditions de température d’un procédé d’épitaxie

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1269599A (zh) * 1999-03-26 2000-10-11 佳能株式会社 制造半导体部件的方法
WO2007083587A1 (ja) * 2006-01-23 2007-07-26 Shin-Etsu Handotai Co., Ltd. Ｓｏｉウエーハの製造方法およびｓｏｉウエーハ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP2004247610A (ja) 2003-02-14 2004-09-02 Canon Inc 基板の製造方法
JP4251054B2 (ja) * 2003-10-01 2009-04-08 株式会社デンソー 半導体装置の製造方法
EP1806769B1 (en) * 2004-09-13 2013-11-06 Shin-Etsu Handotai Co., Ltd. Soi wafer manufacturing method
JP4587034B2 (ja) * 2005-03-16 2010-11-24 信越半導体株式会社 Ｓｏｉウェーハの設計方法
JP5082299B2 (ja) * 2006-05-25 2012-11-28 株式会社Ｓｕｍｃｏ 半導体基板の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1269599A (zh) * 1999-03-26 2000-10-11 佳能株式会社 制造半导体部件的方法
WO2007083587A1 (ja) * 2006-01-23 2007-07-26 Shin-Etsu Handotai Co., Ltd. Ｓｏｉウエーハの製造方法およびｓｏｉウエーハ

Also Published As

Publication number Publication date
CN102119435A (zh) 2011-07-06
EP2320450A4 (en) 2011-09-28
WO2010023816A1 (ja) 2010-03-04
US8497187B2 (en) 2013-07-30
KR101573812B1 (ko) 2015-12-02
EP2320450B1 (en) 2013-08-28
US20110117727A1 (en) 2011-05-19
KR20110047201A (ko) 2011-05-06
JP2010056311A (ja) 2010-03-11
TWI453819B (zh) 2014-09-21
EP2320450A1 (en) 2011-05-11
JP4666189B2 (ja) 2011-04-06
TW201025444A (en) 2010-07-01

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