JP6824115B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 description 69
- 239000010703 silicon Substances 0.000 description 69
- 229920002120 photoresistant polymer Polymers 0.000 description 48
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 40
- 229910052814 silicon oxide Inorganic materials 0.000 description 40
- 229910052581 Si3N4 Inorganic materials 0.000 description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 27
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- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 229910021332 silicide Inorganic materials 0.000 description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
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- 230000003647 oxidation Effects 0.000 description 6
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
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- 229910052735 hafnium Inorganic materials 0.000 description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
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- 125000001475 halogen functional group Chemical group 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
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Description
ここでは、一つのメモリセルが一つのメモリトランジスタと一つの選択トランジスタとによって構成され、そのメモリセルがバルク領域に形成された半導体装置の一例について説明する。
ここでは、一つのメモリセルが一つのメモリトランジスタと一つの選択トランジスタとによって構成され、そのメモリセルがSOI領域に形成された半導体装置の一例について説明する。
実施の形態1、2では、一つのメモリセルが一つのメモリトランジスタと一つの選択トランジスタとによって構成される半導体装置について説明した。ここでは、一つのメモリセルが一つのメモリトランジスタによって構成され、そのメモリセルがバルク領域に形成された半導体装置について説明する。
ここでは、一つのメモリセルが一つのメモリトランジスタによって構成され、そのメモリセルがSOI領域に形成された半導体装置について説明する。
Claims (6)
- 半導体支持基板の上に絶縁膜を介在させて半導体層が形成された半導体基板を用意する工程と、
前記半導体基板に対して、第1領域および第2領域を規定し、前記第1領域に位置する前記半導体層および前記絶縁膜を除去して前記第1領域に位置する前記半導体支持基板を露出するとともに、前記第2領域に位置する前記半導体層および前記絶縁膜を残す工程と、
前記半導体基板に分離領域を形成することによって、前記第1領域に第1素子領域および第2素子領域を規定し、かつ、前記第2領域に第3素子領域を規定する工程を含む、素子領域を規定する工程と、
前記第1素子領域にメモリトランジスタを形成し、前記第2素子領域に第1トランジスタを形成し、前記第3素子領域に第2トランジスタを形成する工程を含む、半導体素子を形成する工程と
を有し、
前記メモリトランジスタを形成する工程は、
前記第1素子領域に、第1導電型のウェル領域を形成する工程と、
前記ウェル領域の上に、電荷蓄積層を含むゲート絶縁膜を介在させてメモリゲート電極を形成する工程と、
前記メモリゲート電極を注入マスクとして第2導電型の第1不純物を導入することにより、前記ウェル領域に第1不純物濃度を有する第1不純物領域を形成する工程と、
エピタキシャル成長法によって前記ウェル領域の表面にせり上げ部を形成する工程と、
前記メモリゲート電極の側壁面に、側壁絶縁膜を形成する工程と、
前記メモリゲート電極および前記側壁絶縁膜を注入マスクとして第2導電型の第2不純物を注入することにより、前記せり上げ部に、前記第1不純物濃度よりも高い第2不純物濃度を有する第2不純物領域を形成する工程と
を備え、
前記第1トランジスタを形成する工程は、前記せり上げ部を形成する前に、前記第2素子領域を覆うように、エピタキシャル成長を阻止するエピタキシャル成長阻止膜を形成する工程を含み、
前記せり上げ部を形成する工程は、前記第2素子領域が前記エピタキシャル成長阻止膜によって覆われた状態で行われる、半導体装置の製造方法。 - 前記半導体素子を形成する工程は、前記せり上げ部を形成する前に、露出している前記ウェル領域の表面を含む前記半導体基板の表面に水素アニール処理を行う工程を含む、請求項1記載の半導体装置の製造方法。
- 前記半導体素子を形成する工程は、前記ウェル領域に、前記メモリトランジスタと電気的に直列に接続される選択トランジスタを形成する工程を含む、請求項1記載の半導体装置の製造方法。
- 半導体支持基板の上に絶縁膜を介在させて半導体層が形成された半導体基板を用意する工程と、
前記半導体基板に対して、第1領域および第2領域を規定し、前記第1領域に位置する前記半導体層および前記絶縁膜を残すとともに、前記第2領域に位置する前記半導体層および前記絶縁膜を除去して前記第2領域に位置する前記半導体支持基板を露出する工程と、
前記半導体基板に分離領域を形成することによって、前記第1領域に第1素子領域および第2素子領域を規定し、かつ、前記第2領域に第3素子領域を規定する工程を含む、素子領域を規定する工程と、
前記第1素子領域にメモリトランジスタを形成し、前記第2素子領域に第1トランジスタを形成し、前記第3素子領域に第2トランジスタを形成する工程を含む、半導体素子を形成する工程と、
を有し、
前記メモリトランジスタを形成する工程は、
前記第1素子領域に位置する前記半導体層の上に、電荷蓄積層を含むゲート絶縁膜を介在させてメモリゲート電極を形成する工程と、
前記メモリゲート電極を注入マスクとして第2導電型の第1不純物を導入することにより、前記半導体層に第1不純物濃度を有する第1不純物領域を形成する工程と、
エピタキシャル成長法によって前記半導体層の表面にせり上げ部を形成する工程と、
前記メモリゲート電極の側壁面に、側壁絶縁膜を形成する工程と、
前記メモリゲート電極および前記側壁絶縁膜を注入マスクとして第2導電型の第2不純物を注入することにより、前記せり上げ部に、前記第1不純物濃度よりも高い第2不純物濃度を有する第2不純物領域を形成する工程と
を備え、
前記第2トランジスタを形成する工程は、前記せり上げ部を形成する前に、前記第3素子領域を覆うように、エピタキシャル成長を阻止するエピタキシャル成長阻止膜を形成する工程を含み、
前記せり上げ部を形成する工程は、前記第3素子領域が前記エピタキシャル成長阻止膜によって覆われた状態で行われる、半導体装置の製造方法。 - 前記半導体素子を形成する工程は、前記せり上げ部を形成する前に、露出している前記半導体支持基板の表面を含む前記半導体基板の表面に水素アニール処理を行う工程を含む、請求項4記載の半導体装置の製造方法。
- 前記半導体素子を形成する工程は、 前記第1素子領域に位置する前記半導体層に、前記メモリトランジスタと電気的に直列に接続される選択トランジスタを形成する工程を含む、請求項4記載の半導体装置の製造方法。
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