TWI237412B - Method for manufacturing semiconductor wafer - Google Patents

Method for manufacturing semiconductor wafer Download PDF

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Publication number
TWI237412B
TWI237412B TW90129214A TW90129214A TWI237412B TW I237412 B TWI237412 B TW I237412B TW 90129214 A TW90129214 A TW 90129214A TW 90129214 A TW90129214 A TW 90129214A TW I237412 B TWI237412 B TW I237412B
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Taiwan
Prior art keywords
wafer
layer
manufacturing
single crystal
silicon
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TW90129214A
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Chinese (zh)
Inventor
Wei-Feig Qu
Masanori Kimura
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Shinetsu Handotai Kk
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for manufacturing a semiconductor wafer wherein a semiconductor wafer having a sufficient lattice strain to enhance electron mobility and having an Si layer of less crystal defect despite of a relatively simple laminate structure is manufactured by a simple process. This manufacturing method comprises the step of epitaxial growth of an SiGe layer on the surface of a first silicon single crystal wafer, the step of coupling the surface of the SiGe layer with the surface of a second wafer with an oxide film in between, and the step of thinning off the first silicon single crystal wafer coupled with the second wafer to expose the Si layer with involved lattice strain.

Description

1237412 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（彳） 【技術範圍】 本發明係有關内藏砂層晶格扭曲之半導體晶圓的製造 方法。 【.先前的技術】 爲了使矽單晶半導體元件性能更好，提高矽單晶的電 子遷移率是一種有效的方法。因此目前正討論在具有普通 晶格常數（約5 _ 4 3 A)的矽單晶内藏有拉扯形變的扭 曲矽層、應用於例如N通道Μ ◦ S電晶體之活性層、可提 高其載體的遷移率，實現可快速動作之元件的可行性。 具有該扭曲矽層之半導體晶圓的製造方法在例如日本 特開平9 一 1 8 0 9 9 9號公報、日本特開平 1 1 - 2 3 3 4 4 0號公報上均有記載。該類技術都是用 來解決在晶格常數大於矽（S i )的矽化鍺（S i G e ) 層上作矽（S i )磊晶成長形成扭曲矽（s i )層，利用 晶格十分緩和的矽化鍺（S i G e )層使其産生扭曲矽（ S i )層，以及使矽化鍺（S i Ge)層不發生差排、當 扭曲矽（S i )層成長時也不使差排散播開來等上述之兩 課題。 但是上述兩種方法都至少要做兩次成膜製程（磊晶成 長或濺鍍法等）不能稱爲簡便的方法。關於該點詳述於下 〇 首先是記載於日本特開平9 一 1 8 0 9 9 9號公報， 半導體晶圓由表面開始的順序爲扭曲矽（S 1 )層/矽化 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公慶） (請先閱讀背面之注意事項再填寫本頁)1237412 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (彳) [Technical Scope] The present invention relates to a method for manufacturing a semiconductor wafer with a sand crystal lattice distortion. [. Previous technology] In order to make silicon single crystal semiconductor devices perform better, improving the electron mobility of silicon single crystal is an effective method. Therefore, a silicon single crystal with a common lattice constant (approximately 5 _ 4 3 A) is currently being discussed, which has a twisted silicon layer that is deformed by pulling, and is applied to, for example, an N-channel M ◦ S-transistor active layer to improve its carrier. The feasibility of realizing fast-moving components. A method for manufacturing a semiconductor wafer having such a twisted silicon layer is described in, for example, Japanese Patent Application Laid-Open No. 9-10899, and Japanese Patent Application Laid-Open No. 1-2-33440. This type of technology is used to solve the problem of forming a silicon (Si) epitaxial growth on a silicon silicide (SiGe) layer with a lattice constant greater than silicon (Si) to form a twisted silicon (si) layer. The tempered germanium silicide (S i Ge) layer causes it to produce a twisted silicon (S i) layer, so that the germanium silicide (S i Ge) layer does not have a differential row, and does not cause the twisted silicon (S i) layer to grow. Dispersion spreads out to wait for the above two topics. However, the above two methods need to be performed at least twice for the film formation process (epitaxial growth or sputtering method, etc.) cannot be called a simple method. This point is described in detail below. Firstly, it is described in Japanese Patent Application Laid-Open No. 9-1 8 0 99. The order of the semiconductor wafer from the surface is twisted silicon (S 1) layer / silicified. This paper is applicable to China. Standard (CNS) A4 specification (210X297 public holidays) (Please read the precautions on the back before filling this page)

-4- 1237412 A7 B7 五、發明説明（2 ) 鍺（s 1 Ge)層/鍺（Ge )層/矽（s i )層/二氧 化砂（S i〇2 )矽（s i )基板等構造，該製程如第三圖 所不、製作絕緣層上有砂S〇I ( S i 1 i c ο η〇η I n s u 1 a t 〇 r)的 晶圓（歩驟1 Ο Ο )—磊晶成長矽層（歩驟1 〇 2 )—成 長鍺（G e )層（歩驟1 〇 4)—成長矽（S i G e )層 (歩驟1 0 6 )—晶格緩和熱處理（歩驟1 〇 8 )-成長 扭曲矽（S i )層（歩驟；l ]_ 〇 )、共作了四次的磊晶成 長。 . 另外日本特開平1 1 — 2 3 3 4 4 〇號公報上記載的 半導體晶圓由表面開始的順序爲扭曲矽（S i )層/氟化 鈣（C a F 2 )層/矽化鍺（S i G e )層/矽（S i ) 層等構造，該製程如第四圖所示、準備矽晶圓（歩驟 2〇0 )-用濺鍍法堆積氟化鈣（c a F 2 )層（歩驟 202) —成長矽化鍺（SiGe)層（歩驟204) — 成長扭曲矽（S i )層（歩驟2 0 6 )，在此至少也做了 兩次薄膜成長、另外也做了氟化鈣（C a F 2 )層之特殊 層。 以往像這樣的方法因爲伴隨著太多的製程及複雜的層 疊構造其成本過高也欠缺普遍性。 【發明的揭示】 本發明的目的係提供爲了解決上述問題提供一種半導 體晶圓的製造方法，即使在比較單純的層疊構造、提高電 子的遷移率可得充分的晶格扭曲、而且製程簡單可製造出 本紙張尺度適用中國國家標準( CNS ) A4規格（210X297公釐） " — -5- (請先閲讀背面之注意事項再填寫本頁) 衣· 訂 經濟部智慧財產局員工消費合作社印說 1237412 A7 ___ B7 五、發明説明（3 ) 矽層結晶缺陷少的半導體晶圓。 (請先閲讀背面之注意事項再填寫本頁) 爲了達成上述的目的，本發明之半導體晶圓製造方法 的第一型態爲具有在第一砂單晶晶圓表面上作砂化鍺（ S i G e )的磊晶成長製程、和該砍化鍺（s i G e )層 表面與第二晶圓表面藉由氧化膜作結合的製程、和薄膜化 與該第二晶圓結合的該第一矽單晶晶圓且使其露出内藏晶 格扭曲矽層的製程等特徴。 本發明半導體晶圓製造方法第二型態具有在第一矽單 晶晶圓表面上作矽化鍺（S i G e ).的磊晶成長製程、和 在該矽化鍺（S 1 G e )層或第二晶圓表面至少形成一層 氧化膜的製程、和透過該矽化鍺（S i G e )層於第一矽 單晶晶圓上至少注入氫離子或稀有氣體離子形成微小氣泡 層的製程、和藉由前記之氧化膜結合該第一矽單晶晶圓與 第二晶圓之後、利用該微小氣泡層將第一矽單晶晶圓剥離 的製程等特徴。 經濟部智慧財產局員工消费合作fi印製 關於上述第二型態，依據上記剥離製程所剝離，硏磨 或熱處理移動至第二晶圓的上記第一矽單晶晶圓薄膜的剥 離面、或設置硏磨和熱處理搭配作平坦化製程則更佳。上 記的微小氣泡層可形成在第一個矽單晶晶圓的晶格扭曲區 域上。 關於上記第一及第二型態，上記氧化膜以熱氧化形成 於上記矽化鍺（S i G e )層表面爲佳。上記第二晶圓以 使用矽單晶圓爲佳。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -6- 1237412 A7 B7五、發明説明（4 ) 【圖面之簡單説明】 第一圖係顯示本發明之第一實施型態之流程圖。 第二圖係顯示本發明之第二實施型態之流程圖。 第三圖係顯示以往半導體晶圓的製造方法例之流程圖 第四圖係顯示以往半導體晶圓的製造方法其他例之流 程圖。 圖號說明 W 1-4- 1237412 A7 B7 V. Description of the invention (2) Germanium (s1Ge) layer / germanium (Ge) layer / silicon (si) layer / sand dioxide (Sio2) silicon (si) substrate and other structures, This process is as shown in the third figure, and a wafer (step 1 〇 〇) with sand S〇I (S i 1 ic ο η〇η I nsu 1 at 〇r) on the insulating layer is produced—epitaxial growth silicon layer (Step 1 〇2) —grown germanium (G e) layer (step 1 〇04) —grown silicon (S i Ge) layer (step 10 6) —lattice relaxation heat treatment (step 1 〇 8 )-Growth of a twisted silicon (S i) layer (step; l] _ 〇), epitaxial growth was performed four times in total. In addition, the order in which the semiconductor wafers described in Japanese Patent Application Laid-Open No. 1 1-2 3 3 4 4 0 start from the surface is a twisted silicon (S i) layer / calcium fluoride (C a F 2) layer / germanium silicide ( S i Ge) layer / silicon (S i) layer structure, this process is shown in the fourth figure, a silicon wafer is prepared (step 200)-calcium fluoride (ca F 2) is deposited by sputtering. Layer (step 202) — growing a germanium silicide (SiGe) layer (step 204) — growing a twisted silicon (S i) layer (step 2 0), at least two thin film growths were also done here, and another A special layer of calcium fluoride (C a F 2) layer. In the past, methods like this have been too costly due to too many processes and complicated laminated structures. [Disclosure of the Invention] An object of the present invention is to provide a method for manufacturing a semiconductor wafer in order to solve the above-mentioned problems. Even in a relatively simple laminated structure and improved electron mobility, sufficient lattice distortion can be obtained, and the process can be manufactured easily. The paper size used in this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) " — -5- (Please read the precautions on the back before filling this page) 1237412 A7 ___ B7 V. Description of the invention (3) Semiconductor wafer with less silicon layer crystal defects. (Please read the precautions on the back before filling this page.) In order to achieve the above-mentioned object, the first type of semiconductor wafer manufacturing method of the present invention has i G e) epitaxial growth process, a process in which the surface of the germanium (si Ge) layer and the second wafer surface are combined by an oxide film, and the first thin film is combined with the second wafer The process of a silicon single crystal wafer and exposing it to a built-in lattice-distorted silicon layer is unique. The second type of the semiconductor wafer manufacturing method of the present invention includes an epitaxial growth process of forming a silicon silicide (S i Ge) on the surface of the first silicon single crystal wafer, and a layer of the germanium silicide (S 1 Ge). Or a process of forming at least one oxide film on the surface of the second wafer, and a process of implanting at least hydrogen ions or rare gas ions on the first silicon single crystal wafer through the germanium silicide (S i Ge) layer to form a microbubble layer, After the first silicon single crystal wafer and the second wafer are combined with the foregoing oxide film, a process of peeling the first silicon single crystal wafer by using the micro-bubble layer is performed. Consumers ’cooperation with the Intellectual Property Bureau of the Ministry of Economic Affairs prints the above-mentioned second type, which is peeled off according to the above-mentioned stripping process, honing or heat-treating and moving to the peeling surface of the first silicon single crystal wafer film on the second wafer, or It is better to set honing and heat treatment for the flattening process. The microbubble layer described above can be formed on the lattice twisted area of the first silicon single crystal wafer. Regarding the first and second types of the above, the above-mentioned oxide film is preferably formed on the surface of the above-mentioned germanium silicide (SiGe) layer by thermal oxidation. The second wafer mentioned above is preferably a silicon single wafer. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -6- 1237412 A7 B7 V. Description of the invention (4) [Simplified description of the drawing] The first diagram shows the first embodiment of the present invention The flowchart. The second figure is a flowchart showing a second embodiment of the present invention. The third diagram is a flowchart showing an example of a conventional semiconductor wafer manufacturing method. The fourth diagram is a flowchart showing another example of a conventional semiconductor wafer manufacturing method. Drawing number description W 1

W 〇 4 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 1〇4 10 6 1〇8 1 1〇 2 0 0 2 0 2 第一矽（S i )晶圓 第二矽（S 1 )晶圓 石夕化鍺（S i G e )層 氧化膜 晶格扭曲矽層 氫離子 微小氣泡層 製作長於絕緣膜上的矽（S〇I )晶圓 矽層磊晶成長 鍺（G e )層成長 矽化鍺（S i G e )層成長 晶格緩和熱處理 晶格扭曲矽層成長 準備矽晶圓 用濺鍍法堆積C a F 2層 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 7 - 1237412 A7 B7 五、發明説明（5 ) 2 0 4 矽化鍺（SiGe)層成長 2 0 6 晶格扭曲矽層成長 (請先閱讀背面之注意事項再填寫本頁) 【實施本發明之最佳型態】 以下利用附圖説明本發明的實施型態，當然限於不脫 離本發明的技術思考下仍會有許多異於圖示的例子。 (第一實施型態） 第一圖係顯示本發明之第一實施型態製造半導體晶圓 的流程圖。第一圖所示的流程基本上是將兩片砂晶圓接合 、製作絕緣層上有石夕S〇I ( Silicon On Insulator )的晶圓 時只是在一般的製造流程裡加進成長矽化鍺（S i G e ) 層的製程（b )。 經濟部智慧財產局員工消費合作社印製 首先準備最後將成爲扭曲矽層材料的第一及第二的矽 晶圓W 1 、W 2 〔第一圖（a )〕。該矽晶圓W 1只要是 單結晶矽的話即可、可使用拉晶法C Z ( Czochralski )法或 浮動區熔法F Z ( F1 〇 a t i n g Ζ ο n e )法所製成的砂晶圓。但是 爲了提高形成元件的扭曲矽層品質、至少使用表面附近結 晶缺陷較少的晶圓爲佳。具體而言藉著熱處理而在晶圓表 面附近形成D Z層的晶圓、或藉著調整拉晶法（C Z法） 的拉晶條件來減低（或消滅）單結晶中所謂的Grown-in缺 陷的晶圓、或F Z晶圓等等爲佳。 其次是在前記第一矽晶圓W 1表面用磊晶成長法形成 矽化鍺（S i G e )層1 〇 〔第一圖（b )〕。形成矽化 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -8- 1237412 A7 B7 五、發明説明（6 ) 鍺（S i G e )層1 〇可使用例如分子線嘉晶成長裝置或 超高真空化學氣相沉積裝置（HV - CVD)等等。 (請先閱讀背面之注意事項再填寫本頁) 最好形成的矽化鍺（S i Ge )層1 〇其鍺（Ge ) 的成分爲1 0〜4 0%左右。未滿1 〇%的話無法形成充 分拉扯變形的扭曲矽層，超過4 0 %的話會因砂晶圓w 1 和矽化鍺（S i G e )層晶格常數不同使矽化鍺（ S i G e )層1 〇容易發生錯位差排的關係，對最後所形 成的扭曲矽層之結晶性産生壞影響。另外矽化鍺（ S i Ge )層1 〇的厚度最好是1 〇nm〜1 左右。未 滿1 0 n m的話無法形成充分拉扯變形的扭曲砂層、超過 1 的話則會因爲寄生容量增加使形成在扭曲矽層上的元 件特性變壞。根據上述製程，即使在第一矽晶圓W 1上形 .成晶格常數不同的矽化鍺（S i Ge)層1 0、也會因爲 第一矽晶圓W 1厚度的關係、不至於使第一個矽晶圓w 1 面發生差排。 經濟部智慧財產局員工消費合作社印製 其次是形成砂化鍺（S i G e )層1 〇表面的氧化膜 1 2 〔第一圖（C )〕。形成氧化膜可採用一般的熱氧化 法、也可用C V D法堆積。若採用熱氧化法的話，在矽化 鍺（S i G e )層1 〇表面會形成化學性安定的s i〇2層 1 2、多餘的鍺（G e )原子則從矽化鍺（S i G e )層 1 0被析出、使矽化鍺（S i G e )層1 0中的鍺（ G e )濃度變高。因此爲了抑制錯位差排的發生，作磊晶 成長時即使鍺（G e )成分較低也可因爲矽化鍺（ S 1 G e )層1 〇表面的熱氧化而提高最後所形成的扭曲 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -9 - 1237412 A7 B7 五、發明説明（7 ) 矽層的拉扯扭曲程度。另外，因爲可以得到充分的拉扯扭 曲、熱氧化及去除氧化膜的歩驟可重複進行。 其次是密合形成在矽化鍺（S i G e )層1 〇表面的 氧化膜1 2和弟一砂晶圓W 2表面、依照後段薄膜化製程 所可承受的結合強度來實行熱處理。〔結合熱處理第一圖 (d )〕。該熱處理的條件只要是可以承受後段薄膜化製 程條件的話，並不需特別限定、薄膜化若是進行切削、硏 磨的話，以8〇〇〜1 2 0 〇 t、0 · 5〜5小時左右爲 佳。 最後是薄膜化第一矽晶圓W 1，讓扭曲矽層1 4顯露 在外〔第一圖（e)〕。扭曲矽層14的厚度在1〜 1 ◦ 0 nm左右爲佳。超過1 〇 〇 nm的話，可能會因爲 矽化鍺（S i G e )層1 〇所成拉扯扭曲無法内藏之虞， 若未滿1 n m的話則無法獲得良好的元件特性，加工也困 難。 薄膜化矽層1 4的方法除了有切削、硏磨之外、用酸 或鹼水溶液的濕蝕刻、利用電漿的氣相乾蝕刻、磨光或是 將其切.片爲二之後加以硏磨等等。藉著這些薄膜化方法可 省略薄膜化前的結合熱處理、也可使用黏著劑結合。 (第二實施型態） 第二圖係顯示本發明之第二實施型態製造半導體晶圓 的流程圖。第二圖所示的流程基本上是將兩片矽晶圓以離 f植入法（氫離子剝離法也稱smart cut〔註冊商標〕）、 本紙張尺度適用中.國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 -10- 1237412 A7 B7 五、發明説明（8 ) (請先閱讀背面之注意事項再填寫本頁) 在製作絕緣層上有石夕S〇I (Silicon〇n Insulator)的晶圓 時的流程裡只加進成長矽化鍺（S i G e )層的製程（b )。還有關於第二圖到氧化矽化鍺（S i G e )層表面的 製程爲止〔第二圖（a)〜第二圖（c)〕和第一圖（a ).〜第一圖（c )製程相同省略重複説明。 形成於矽化鍺（S i G e )層之上氧化膜1 2的表面 開始、透過氧化膜1 2及矽化鍺（S i G e )層注入至少 氫離子或稀有氣體離子其中一種（第二圖（d )則爲氫離 子1 6 )、在第一矽晶圓W 1 .中因此.形成微小氣泡層1 8 〔第二圖（d )〕。 經濟部智慧財產局員工消费合作社印製 微小氣泡層1 8所形成的位置（深度）是由注入的氫 離子1 6的能量而定、以該微小氣泡層1 8作爲邊界後作 剥離熱處理、爲了要產生剥離，注入線量必須超過 1 X 1 〇 1 6 / c m2 (例如 5 X 1 〇 1 6 / c m2 )。爲 了確切 作到在剥離後所形成多層構造晶圓最外層的矽（S i )層 具有晶格扭曲（拉扯變形）、上述微小氣泡層1 8以形成 在第一矽晶圓W 1的晶格扭曲領域上（從第一矽晶圓W 1 表面1 0 0 n m以下領域）爲佳。其次是密合形成在矽化 鍺（S i G e )層1 〇表面的氧化膜1 2與第二矽晶圓 W 2表面〔第二圖（e )〕、加上5 0 0 °C以上的熱處理 (剥離熱處理）使上述微小氣泡層1 8產生剥離〔第二圖 (f ))。其後視需要而定、亦可施以高温結合熱處理以 提高結合強度。另外最近有一種離子注入剥離法、激起注 入的氫離子使其成電漿状態而不作剥離熱處理、也開發室 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -11 - 1237412 A7 B7 五、發明説明（9 ) '温下剥離的方法、採用該方法可省略剥離熱處理。 (請先閲讀背面之注意事項再填寫本頁) 剥離後的扭曲矽（s i )層1 4表面爲鏡面略爲粗糙 '施以硏磨費極少的硏磨法稱之爲觸碰式抛光（touch polish )加以平坦化〔第二圖（g )〕。在氬氣（a r )或 氫氣氣氛中熱處理使其平坦化以代替觸碰式抛光、也可搭 配這些方法來作平坦化。 至於熱處理條件，使用通常阻抗加熱式熱處理爐時 1 1 〇 0〜1 3〇〇°C、0 . 5〜5小時左右最適合、使 用快速加熱退火處理RT A ( Rapid Thermal Anneling)時 1 1 〇 〇〜1 3 5 0艺、1〜1 2 0秒左右最適合。而且 可搭配二者施行熱處理。 經濟部智慧財產局員工消費合作社印製 還有第一圖及第二圖所示的實施型態，如第一矽晶圓 w 1的矽化鍺（S i G e )層1 〇表面形成氧化膜1 2之 例，也可用於第二矽晶圓W 2上之氧化膜形成、也可用於 第一矽晶圓及第二矽晶圓雙方之氧化膜形成。還有第二矽 晶圓W 2若使用電阻率1 〇 〇 0 Ω · c m以上的高電阻率 晶圓、高周波特性優良可應用於行動體通信用的半導體。 再者第二矽晶圓W2也可用矽基板、藍寶石基板、S i C 、氮化鋁基板等絕緣性基板。 【實施例】 以下列舉實施例進一歩説明本發明，當然這些實施例 不是被特定加以解釋的。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -12 - 1237412 A7 B7 五、發明説明（10) (第一實施例：對應第一實施型態） 依照第一圖所示第一實施型態的順序用下記條件製造 具有充分晶格扭曲的半導體晶圓。 1 .使用晶圓（準備第一及第二晶圓）〔第一圖（a ).〕，直徑2〇〇m m、p型、結晶方位〈1 〇 〇〉、 1 Ο Ω · cm 2 ·在第一矽晶圓表面作矽化鍺（s i G e )層成長 (:U Η V — C V D 裝置）〔第一圖（b )〕W 〇4 (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1104 10 6 1〇8 1 1〇2 0 0 2 0 2 First Silicon (S i) Wafer Second Silicon (S 1) Wafer Stone Germanium (S i Ge) Layer Oxide Film Lattice Distorted Silicon Layer Hydrogen Ion Microbubble Layer Fabricate Silicon Layer on Silicon (SOI) Wafer Epitaxial growth germanium (G e) layer growth germanium silicide (S i Ge) layer growth lattice relaxation heat treatment lattice distortion distortion silicon layer growth preparation silicon wafer stacked by sputtering C a F 2 layers This paper is applicable to China Standard (CNS) A4 specification (210X297 mm) 7-1237412 A7 B7 V. Description of the invention (5) 2 0 4 Growth of germanium silicide (SiGe) layer 2 0 6 Growth of lattice twisted silicon layer (please read the precautions on the back first) (Fill in this page again) [The best mode for implementing the present invention] The following describes the implementation mode of the present invention using the drawings. Of course, there are still many examples that are different from the illustration without departing from the technical thinking of the present invention. (First Embodiment Mode) The first diagram is a flowchart showing a method for manufacturing a semiconductor wafer according to the first embodiment mode of the present invention. The process shown in the first figure is basically the joining of two sand wafers and the production of a wafer with a silicon on insulator (Si On Insulator) on the insulating layer is only added to the growth of germanium silicide ( S i G e) layer manufacturing process (b). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. First, prepare the first and second silicon wafers W 1 and W 2 which will eventually become distorted silicon layer materials [first image (a)]. This silicon wafer W 1 is only required to be monocrystalline silicon, and a sand wafer made by a pulling method C Z (Czochralski) method or a floating zone melting method F Z (F 1 0 a t i n g Z ο n e) method may be used. However, in order to improve the quality of the twisted silicon layer forming the device, it is better to use at least a wafer with fewer crystal defects near the surface. Specifically, a wafer in which a DZ layer is formed near the surface of the wafer by heat treatment, or by adjusting the crystal pulling conditions of the crystal pulling method (CZ method) to reduce (or eliminate) so-called Grown-in defects in a single crystal. Wafers, or FZ wafers are preferred. Secondly, a germanium silicide (SiGe) layer 10 is formed on the surface of the first silicon wafer W1 by epitaxial growth method [first image (b)]. Form silicified paper. Applicable to China National Standard (CNS) A4 specification (210X297 mm) -8-1237412 A7 B7 V. Description of the invention (6) Germanium (S i Ge) layer 1 can be grown using molecular wire Jiajing Equipment or ultra-high vacuum chemical vapor deposition equipment (HV-CVD) and so on. (Please read the precautions on the back before filling in this page) The best germanium silicide (SiGe) layer 10 has a germanium (Ge) composition of about 10% to 40%. If it is less than 10%, a twisted silicon layer with sufficient pull deformation cannot be formed, and if it exceeds 40%, the silicon wafer (SiGe) will be caused by the difference in lattice constant between the sand wafer w1 and the germanium silicide (SiGe) layer. The layer 10 is prone to misalignment, which has a bad effect on the crystallinity of the twisted silicon layer formed at the end. In addition, the thickness of the germanium silicide (SiGe) layer 10 is preferably about 10 nm to about 1. If it is less than 10 nm, a twisted sand layer that cannot be fully pulled and deformed will be formed. If it exceeds 1, the parasitic capacity will increase and the characteristics of the element formed on the twisted silicon layer will be deteriorated. According to the above process, even if a germanium silicide (SiGe) layer 10 having a different lattice constant is formed on the first silicon wafer W1, the thickness of the first silicon wafer W1 will not affect the thickness of the first silicon wafer W1. The first silicon wafer w 1 has a differential row. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Secondly, an oxide film 1 2 on the surface of the sanded germanium (S i Ge) layer 10 is formed [first image (C)]. The oxide film can be formed by a general thermal oxidation method or by a CVD method. If the thermal oxidation method is used, a chemically stable SiO2 layer 1 will be formed on the surface of the germanium silicide (S i Ge) layer 10. The excess germanium (Ge) atoms will be converted from the germanium silicide (SiGe). ) Layer 10 is precipitated to increase the germanium (G e) concentration in the germanium silicide (S i G e) layer 10. Therefore, in order to suppress the occurrence of misalignment, even if the germanium (G e) composition is low during epitaxial growth, the resulting warped paper can be improved due to the thermal oxidation of the surface of the germanium silicide (S 1 Ge) layer 10. The dimensions are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -9-1237412 A7 B7 V. Description of the invention (7) The degree of pulling distortion of the silicon layer. In addition, the steps of sufficient pulling and twisting, thermal oxidation, and removal of the oxide film can be repeated. The second step is to perform heat treatment by closely forming the oxide film 12 formed on the surface of the germanium silicide (S i Ge) layer 10 and the surface of the Si-Is wafer W 2 in accordance with the bonding strength that can be endured by the subsequent thin film formation process. [Combined heat treatment first figure (d)]. The conditions of the heat treatment are not particularly limited as long as they can withstand the later-stage thin film forming process. If the thin film is subjected to cutting and honing, the time is about 800-1200 t, and about 0.5-5 hours. good. Finally, the first silicon wafer W 1 is thinned to expose the twisted silicon layer 14 [first image (e)]. The thickness of the twisted silicon layer 14 is preferably about 1 to 1 ◦ 0 nm. If it exceeds 1000 nm, the pulling distortion caused by the germanium silicide (SiGe) layer 10 may not be built in. If it is less than 1 nm, good device characteristics cannot be obtained, and processing is difficult. The methods for thinning the silicon layer 14 include cutting, honing, wet etching with an acid or alkali aqueous solution, vapor-phase dry etching using a plasma, polishing, or cutting it. and many more. According to these thin-film formation methods, the bonding heat treatment before thin-film formation can be omitted, or bonding can be performed using an adhesive. (Second Embodiment Mode) The second diagram is a flowchart showing a method of manufacturing a semiconductor wafer according to a second embodiment mode of the present invention. The process shown in the second figure is basically the implantation of two silicon wafers by the ion implantation method (hydrogen ion stripping method is also called smart cut [registered trademark]), and the standard of this paper is applicable. National Standard (CNS) A4 Specifications (210X297 mm) (Please read the precautions on the back before filling out this page) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives -10- 1237412 A7 B7 V. Invention Description (8) (Please read the notes on the back first (Please fill in this page for more details.) In the process of making wafers with a silicon on silicon insulator (Silicon On Insulator), only the process (b) of growing a germanium silicide (SiGe) layer is added to the process flow. There is also the process from the second image to the surface of the germanium silicide (S i Ge) layer [second image (a) to second image (c)] and first image (a). ~ First image (c ) The manufacturing process is the same and repeated description is omitted. Beginning on the surface of the oxide film 12 formed on the germanium silicide (S i Ge) layer, at least one of hydrogen ions or rare gas ions is implanted through the oxide film 12 and the germanium silicide (Si Ge) layer (second image (D) is hydrogen ion 16), and thus a micro-bubble layer 1 8 is formed in the first silicon wafer W1 [second image (d)]. The position (depth) of the microbubble layer 18 printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is determined by the energy of the injected hydrogen ions 16 and the microbubble layer 18 is used as a boundary for stripping heat treatment. To produce peeling, the amount of injection line must exceed 1 X 106 / cm2 (e.g. 5 X 106 / cm2). In order to precisely make the silicon (S i) layer on the outermost layer of the multilayer structure wafer formed after the peeling has lattice distortion (pulling deformation), the above-mentioned micro-bubble layer 18 is formed to form a crystal lattice on the first silicon wafer W 1. Twisted areas (areas below 100 nm from the first silicon wafer W 1 surface) are preferred. Secondly, the oxide film 12 formed on the surface of the germanium silicide (S i Ge) layer 10 is closely adhered to the surface of the second silicon wafer W 2 [second image (e)], plus 50 ° C or more The heat treatment (peeling heat treatment) peels the microbubble layer 18 (second image (f)). Afterwards, depending on the need, a high-temperature bonding heat treatment may be applied to increase the bonding strength. In addition, recently, there is an ion implantation stripping method, which stimulates the implanted hydrogen ions to make the plasma state without stripping heat treatment. The paper size of the paper is also applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -11-1237412 A7 B7 V. Description of the invention (9) 'A method of peeling at a temperature, by which the peeling heat treatment can be omitted. (Please read the precautions on the back before filling in this page.) The peeled twisted silicon (Si) layer 1 4 has a slightly rough mirror surface. The honing method with minimal honing is called touch polishing. polish) to be flattened [second image (g)]. Heat treatment in an argon (ar) or hydrogen atmosphere to flatten it instead of touch polishing. These methods can also be used for flattening. As for the heat treatment conditions, 1 1 0 to 1 300 ° C and 0.5 to 5 hours are most suitable when a general resistance heating type heat treatment furnace is used, and 1 1 0 is used for rapid thermal annealing RT A (Rapid Thermal Anneling). 〇 ~ 1,350, and about 1 ~ 120 seconds are most suitable. In addition, heat treatment can be performed with both. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and the implementation patterns shown in the first and second figures, such as the germanium silicide (S i G e) layer 1 on the first silicon wafer w 1, an oxide film is formed on the surface. The example 12 can also be used for the formation of an oxide film on the second silicon wafer W 2, and also for the formation of an oxide film on both the first silicon wafer and the second silicon wafer. If the second silicon wafer W 2 uses a high-resistivity wafer with a resistivity of 1000 Ω · cm or more, it can be applied to semiconductors for mobile communications. In addition, the second silicon wafer W2 may be an insulating substrate such as a silicon substrate, a sapphire substrate, a SiC, or an aluminum nitride substrate. [Examples] The following examples further illustrate the present invention, and of course, these examples are not specifically explained. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -12-1237412 A7 B7 V. Description of the invention (10) (First embodiment: corresponding to the first embodiment) A sequence of one implementation mode produces a semiconductor wafer having sufficient lattice distortion using the following conditions. 1. Use wafers (preparing first and second wafers) [first image (a).], Diameter 2000mm, p-type, crystal orientation <100%>, 10 Ω · cm 2 · in The first silicon wafer was grown on the surface of germanium silicide (si G e) layer (: U Η V — CVD device) [first image (b)]

原料氣體：GeH4.、S i 2H6 .成長温度：7 Ο 〇 °CSource gas: GeH4., Si 2H6. Growth temperature: 7 〇 ° C

SiGe 成分：Si 0.7 G e 0 . 3 成長層厚度：150nm 3 ·矽化鍺（S i G e )表面氧化〔第一圖（c )〕 氧化條件：8 Ο 0 °C、高溫氧化 氧化膜厚：lOOnm 4·結合工程〔第一圖（d)〕 室温下將兩片晶圓密合後作1 〇 〇 〇 t、二小時的熱 處理（氧化性氣氛） 5 ·薄膜化〔第一圖（e )〕 平面切削：硏削第一矽晶圓到厚度約2 0 。 鏡面硏磨：硏磨第一矽晶圓到厚度約4 。 用 P A C E ( Plasma Assisted Chemical Etching)法作 氣相蝕刻，薄膜化第一矽晶圓厚度至約1 0 0 n m。（ P A C E法係記載於日本第2 5 6 5 6 1 7號專利之技術 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 、11 經濟部智慧財產局員工消費合作钍印災 -13- 1237412 A7 B7 經濟部智慧財產局員工消費合作社印製SiGe composition: Si 0.7 G e 0.3 Thickness of growth layer: 150nm 3 · Surface oxidation of germanium silicide (Si Ge) [first picture (c)] Oxidation conditions: 8 0 ° C, high temperature oxidation oxide film thickness: lOOnm 4 · Combination process [first image (d)] After the two wafers are tightly adhered at room temperature, a heat treatment (oxidizing atmosphere) of 1,000 t and two hours is performed. 5 · Thin film [first image (e) 〕 Plane cutting: The first silicon wafer is cut to a thickness of about 20. Mirror honing: Honing the first silicon wafer to a thickness of about 4. The first silicon wafer was thinned to a thickness of about 100 nm using a P A C E (Plasma Assisted Chemical Etching) method for vapor phase etching. (The PACE method is described in the Japanese Patent No. 2 5 6 5 6 17 patent technology. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling out this page).) 11 Consumption Cooperation of Employees in the Intellectual Property Bureau of the Ministry of Economic Affairs-13- 1237412 A7 B7 Printed by Employees' Cooperatives in the Intellectual Property Bureau of the Ministry of Economic Affairs

五、發明説明（H (第二實施例：對應第二實施型態） 依照第二圖所示第二實施型態的順序用下記條件製姐 具有充分晶格扭曲的半導體晶圓。 1 .使用晶_(準備第一及第二晶圓）〔第二圖（a )〕，直徑2 0〇m m、p型、結晶方位〈1 〇〇〉、 1 Ο Ω · cm 2 ·在第一矽晶圓表面作矽化鍺（S i G e )層成長 (UHV— CVD 裝置）〔第二圖（b)〕V. Description of the Invention (H (Second Embodiment: Corresponding to the Second Embodiment Mode) A semiconductor wafer having sufficient lattice distortion is manufactured using the following conditions in the order of the second embodiment mode shown in the second figure. 1. Use Crystal_ (preparation of first and second wafers) [second image (a)], diameter 200mm, p-type, crystal orientation <100%>, 10 Ω · cm 2 · on the first silicon crystal Round surface as germanium silicide (S i Ge) layer growth (UHV-CVD device) [second image (b)]

原料氣體：GeH4、Si2H6 成長温度·· 7 0 〇 °CSource gas: GeH4, Si2H6 Growth temperature · 7 0 ° C

SiGe成分：Si 0.85 Ge 〇.15 成長層厚度：120nm 3 .矽化鍺（SiGe)表面氧化〔第二圖（c)〕 氧化條件：8 0 0 °C、高溫氧化 氧化膜厚：1 0 0 n m 4 ·注入氫離子〔第二圖（d)〕 H+離子注入條件：35KeV、8x l〇l6/cm 5 ·剥離工程〔第二圖（e )及（f )] 室温下將兩片晶圓密合後作5 0 〇 °C、三十分鐘的熱 處理（氮氣氣氛）後剥離。剥離處理完後的多層晶圓之最 表層的矽層厚度爲1 3 0 nm 6 .結合熱處理 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公复） (請先閱讀背面之注意事項再填寫本頁) 訂 -14- 1237412 A7 _— B7 五、發明説明（12 ) 8〇0 °C、二小時、氮氣氣氛 7 ·觸碰式抛光〔第二圖（g)〕 硏磨約3 0 n m 【·應用於産業上之可能性】 正如以上所述，根據本發明可達成，即使是比較單純 的層積構造、提高電子遷移率可充分發生晶格扭曲、且可 簡單製作結晶缺陷少的矽層半導.體晶圓之製程等之效果。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -15«SiGe composition: Si 0.85 Ge 0.15 Growth layer thickness: 120nm 3. Surface oxidation of germanium silicide (SiGe) [second picture (c)] Oxidation conditions: 80 ° C, high temperature oxidation Oxidation film thickness: 100nm 4 · Hydrogen implantation [second image (d)] H + ion implantation conditions: 35KeV, 8x1016 / cm 5 · Stripping process [second image (e) and (f)] Two wafers are densely packed at room temperature After bonding, heat treatment (nitrogen atmosphere) was performed at 500 ° C for 30 minutes, and then peeled. The thickness of the outermost silicon layer of the multi-layer wafer after stripping is 130 nm 6. Combined with the heat treatment, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public copy) (Please read the note on the back first Please fill in this page again) Order -14- 1237412 A7 _ — B7 V. Description of the invention (12) 8000 ° C, two hours, nitrogen atmosphere 7 · Touch polishing [second image (g)] Honing about 3 0 nm [Possibility of application to the industry] As described above, according to the present invention, even a relatively simple laminated structure, improved electron mobility, sufficient lattice distortion, and simple crystal defects can be produced. The effect of less silicon layer semiconductor and bulk wafer process. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -15 «

Claims (1)

1237412 A8 B8 C8 D8 六、申請專利範圍i 1 •一種半導體晶圓的製造方法，其特徴具有 (請先閱讀背面之注意事項再填寫本頁) 將矽化鍺層（S i G e )磊晶成長於第一矽單晶晶圓 表面之製程、 和該矽化鍺層（S i G e )表面藉著氧化膜與第二晶 圓表面結合之製程、 和薄膜化與該第二晶圓結合後的該第一矽單晶晶圓、 使其露出内藏於矽層的晶格扭曲等製程。 2 · —種半導體晶圓的製造方法，其特徴具有 將矽化鍺層（S i G e )磊晶成長於第一矽單晶晶圓 表面之製程、 和該矽化鍺層（S i G e )表面或第二晶圓表面至少 有一方具有氧化膜之製程、 和藉由該矽化鍺（S i G e )層在第一矽單晶晶圓上 至少注入氫離子或稀有氣體離子其中一種形成微小氣泡層 之製程、 和藉由該氧化膜第一矽單晶晶圓與.第二晶圓結合後以 該微小氣泡層將該第一矽單晶晶圓剥離之製程。 經濟部智慧財產局員工消費合作社印製 3 ·如申請專利範圍第2項所記載之半導體晶圓的製 造方法，其中經由前述剥離製程所剝離硏磨或熱處理移動 至第二晶圓的上記第一矽單晶晶圓薄膜的剥離面、或將其 組合作平坦化之製程。 4 ·如申請專利範圍第2項所記載之半導體晶圓的製 造方法，其中前述微小氣泡層形成在前記第一矽單晶晶圓 的晶格扭曲領域上。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1237412 A8 B8 C8 D8 六、申請專利範圍2 (請先閱讀背面之注意事項再填寫本頁) 5 ·如申請專利範圍第3項所記載之半導體晶圓的製 造方法，其中前述微小氣泡層形成在前記第一矽單晶晶圓 的晶格扭曲領域上。 6 ·如申請專利範圍第1項所記載之半導體晶圓的製 造方法，其中前述氧化膜因熱氧化形成於前述矽化鍺層（ S i G e )的表面。 7 .如申請專利範圍第2項所記載之半導體晶圓的製 造方法，其中前述氧化膜因熱氧化形成於前述矽化鍺層（ S i G e )的表面。 8 ·如申請專利範圍第3項所記載之半導體晶圓的製 造方法，其中前述氧化膜因熱氧化形成於前述矽化鍺層（ s i G e )的表面。 9 ·如申請專利範圍第4項所記載之半導體晶圓的製 造方法，其中前述氧化膜因熱氧化形成於前述矽化鍺層（ s i G e )的表面。 經濟部智慧財產局員工消費合作社印製 1 0 ·如申請專利範圍第5項所記載之半.導體晶圓的 製造方法，其中前述氧化膜因熱氧化形成於前述矽化鍺層 (S i Ge)的表面。 1 1 ·如申請專利範圍第1項至第1 〇項之任一項所 FI己載之半導體晶圓的製造方法，其中前述第二晶圓採用石夕 單晶晶圓。 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐）1237412 A8 B8 C8 D8 6. Scope of patent application i 1 • A method for manufacturing semiconductor wafers, which has the following features (please read the precautions on the back before filling out this page) and epitaxially grow a germanium silicide layer (S i G e) The process of forming on the surface of the first silicon single crystal wafer, the process of combining the surface of the germanium silicide layer (S i Ge) with the surface of the second wafer through the oxide film, and the process of combining the thin film with the second wafer The first silicon single crystal wafer is exposed to a process such as lattice distortion that is embedded in the silicon layer. 2. A method for manufacturing a semiconductor wafer, which has a process of epitaxially growing a germanium silicide layer (S i Ge) on the surface of a first silicon single crystal wafer, and the germanium silicide layer (S i Ge) At least one of the surface or the surface of the second wafer has a process of forming an oxide film, and at least one of hydrogen ions or rare gas ions is implanted on the first silicon single crystal wafer through the germanium silicide (S i Ge) layer to form minute A process of forming a bubble layer, and a process of peeling off the first silicon single crystal wafer with the micro bubble layer after the first silicon single crystal wafer and the second wafer are combined by the oxide film. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs3. The method for manufacturing a semiconductor wafer as described in item 2 of the scope of patent application, wherein it is moved to the second wafer above the first through the honing or heat treatment removed by the aforementioned stripping process A process for flattening a peeling surface of a silicon single crystal wafer film, or flattening a group thereof. 4. The method for manufacturing a semiconductor wafer according to item 2 of the scope of the patent application, wherein the microbubble layer is formed on a lattice distortion field of the first silicon single crystal wafer described above. This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 1237412 A8 B8 C8 D8 6. Scope of patent application 2 (Please read the precautions on the back before filling this page) 5 · If the scope of patent application is the third item In the method of manufacturing a semiconductor wafer, the microbubble layer is formed on a lattice distortion region of the first silicon single crystal wafer described in the foregoing. 6. The method for manufacturing a semiconductor wafer according to item 1 of the scope of the patent application, wherein the oxide film is formed on the surface of the germanium silicide layer (SiGe) by thermal oxidation. 7. The method for manufacturing a semiconductor wafer according to item 2 of the scope of the patent application, wherein the oxide film is formed on the surface of the germanium silicide layer (SiGe) by thermal oxidation. 8. The method for manufacturing a semiconductor wafer according to item 3 of the scope of the patent application, wherein the oxide film is formed on the surface of the germanium silicide layer (s i G e) by thermal oxidation. 9. The method for manufacturing a semiconductor wafer according to item 4 of the scope of the patent application, wherein the oxide film is formed on the surface of the germanium silicide layer (s i G e) by thermal oxidation. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 10 · As described in Item 5 of the scope of patent application. Manufacturing method of conductor wafer, wherein the aforementioned oxide film is formed on the aforementioned germanium silicide layer (S i Ge) due to thermal oxidation s surface. 1 1 · The method for manufacturing a semiconductor wafer carried by FI as described in any one of the items 1 to 10 of the scope of patent application, wherein the aforementioned second wafer is a Shi Xi single crystal wafer. This paper size applies to China National Standard (CNS) A4 (210X297 mm)
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