CN102113115A - 晶片通孔及其制造方法 - Google Patents

晶片通孔及其制造方法 Download PDF

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Publication number
CN102113115A
CN102113115A CN2009801301910A CN200980130191A CN102113115A CN 102113115 A CN102113115 A CN 102113115A CN 2009801301910 A CN2009801301910 A CN 2009801301910A CN 200980130191 A CN200980130191 A CN 200980130191A CN 102113115 A CN102113115 A CN 102113115A
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conductive
substrate
hole
basal surface
wafer via
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丁汉屹
A·约瑟夫
A·斯塔珀
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International Business Machines Corp
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International Business Machines Corp
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Publication of CN102113115A publication Critical patent/CN102113115A/zh
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Abstract

一种晶片通孔结构，所述结构包括：半导体衬底(100)，其具有顶表面(105)和相反的底表面(320)；以及晶片通孔阵列，其包括至少一个导电晶片通孔(130)和至少一个非导电晶片通孔(125)，所述晶片通孔阵列的每一个晶片通孔从所述衬底(100)的所述顶表面(105)延伸到大于至所述衬底(100)的所述底表面(320)的中途与直到所述衬底(100)的所述底表面(320)之间。还公开了制造所述晶片通孔结构的方法。

Description

晶片通孔及其制造方法
技术领域
本发明涉及集成电路芯片的领域，更具体地，涉及在集成电路芯片中使用的晶片通孔及制造该晶片通孔的方法。
背景技术
为增加使用集成电路芯片的器件的密度，需要向集成电路芯片的顶表面和底表面均能提供互连。这需要形成适于承载高频和DC信号的从集成电路芯片的顶表面到底表面的晶片通孔。许多现有的通孔方案不是与现有的集成电路制程在整合上有困难，就是会造成在集成电路芯片的正表面和底表面之间的令人无法接受的信号传播劣化。因此，在本技术领域中，需要克服上述缺点和限制。
发明内容
本发明的第一方面为一种结构，包括：半导体衬底，其具有顶表面和相反的底表面；以及晶片通孔阵列，其包括至少一个导电晶片通孔和至少一个非导电晶片通孔，所述晶片通孔阵列的每个晶片通孔从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间。
本发明的第二方面为一种方法，包括：通过具有顶表面和相反的底表面的半导体衬底形成晶片通孔阵列，其中所述晶片通孔阵列包括至少一个导电晶片通孔和至少一个非导电晶片通孔，所述晶片通孔阵列的每一个晶片通孔从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途(halfway)与直到所述衬底的所述底表面之间。
本发明的第三方面为一种方法，包括：(a)在半导体衬底中形成第一沟槽和第二沟槽，所述第一和所述第二沟槽独立地从所述衬底的顶表面朝所述衬底的相反的底表面延伸小于所述衬底的厚度的距离；(b)同时地用介电材料完全填充所述第一沟槽并在所述第二沟槽的侧壁上形成所述介电材料的衬里；(c)用导电材料填充所述第二沟槽中的剩余空间；以及(d)从所述衬底的所述底表面减薄所述衬底以形成所述衬底的新底表面，所述第一沟槽的所述介电材料以及所述第二沟槽的所述衬里和导电材料在衬底的所述新底表面中暴露。
本发明的第四方面为穿过半导体衬底的信号传输线，所述衬底具有顶表面和相反的底表面，包括：导电晶片通孔，其从所述衬底的所述顶表面延伸至所述衬底的所述底表面，所述导电通孔的侧壁与所述衬底电绝缘；以及非导电通孔，其从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间，所述非导电通孔靠近所述导电晶片通孔并通过所述衬底的区域与所述导电晶片通孔分开。
附图说明
本发明的特征如随附的权利要求所述。然而，要完全了解本发明本身，请在连同附图一起阅读时，参考示意性实施例的详细说明，在附图中：
图1A至1O为示例了制造根据本发明的实施例的晶片通孔阵列的初始步骤的截面图；
图2A至2J为示例了完成制造根据本发明的实施例的晶片通孔阵列和使用根据本发明的实施例的晶片通孔阵列制造三维器件的截面图；
图3A至3D为根据本发明的实施例的晶片通孔的平面图；
图4A至4D为使用根据本发明的实施例的晶片通孔的波导模式的平面图；
图5为示例了图1B所示结构的备选结构的截面图；以及
图6为示例了图2I所示结构的备选结构的截面图。
具体实施方式
术语“晶片通孔”定义了封装的集成电路或芯片中自衬底的顶表面延伸穿过衬底到达衬底的相反的底表面的结构。根据本发明的实施例的晶片通孔可为导电或非导电的。虽然在下文的描述中，将导电和非导电(即，绝缘)的通孔说明并示例为从芯片顶表面延伸到底表面，但可将本发明实施于以下情况：导电通孔完全延伸穿过芯片，而非导电通孔仅部分地延伸通过芯片，因为非导电通孔的一个目的是隔离而非在芯片顶表面与底表面之间传递电信号。导电通孔包括至少一个导电元件并可以包括非导电元件。非导电通孔包括至少一个非导电元件并可包括完全被非导电元件包围的导电元件。晶片通孔的“晶片”源于以下事实：过孔在从称为晶片的半导体衬底分割出集成电路之前形成。术语“三维器件”定义的器件为：包括二个或更多个因层叠在彼此之上而电连接并物理接触的单个衬底。
图1A至1O为示例了制造根据本发明的实施例的晶片通孔阵列的初始步骤的截面图。在图1A中，半导体衬底100具有顶表面105。在顶表面105上形成的是第一介电层110。在第一介电层110的顶表面115上形成的是第二介电层120。第一和第二介电层110及120仅是举例说明，且形成在衬底100的顶表面105之上的可以只有一个介电层或多于两个介电层。在一个范例中，衬底100为体硅衬底。在一个范例中，第一介电层110是二氧化硅以及第二介电层120是氮化硅。
在图1B中，将沟槽125及130蚀刻穿过第一及第二介电层110及120并进入衬底100中。沟槽125及130可使用光刻/蚀刻制程来形成。示范性光刻/蚀刻制程包括：(1)在第二介电层120上形成光致抗蚀剂层；(2)通过构图的光掩模使光致抗蚀剂层暴露到光化辐射并显影光致抗蚀剂的曝光或未曝光区域，而在光致抗蚀剂层中形成开口；(4)使用例如反应性离子蚀刻(RIE)制程，蚀刻穿过第一及第二介电层；(5)去除构图的光致抗蚀剂层，以及(6)使用第一和第二介电层中的图形作为构图的硬掩模，使用例如RIE制程蚀刻衬底100。虽然在图1B中显示沟槽125及130被蚀刻到相同深度，但沟槽125及130可被蚀刻到不同深度。例如，一般称为“波希(Bosch)”硅蚀刻制程的蚀刻制程将蚀刻具有宽(W2)开口的沟槽比具有窄开口(W1)的沟槽深。参见图5。较深地蚀刻沟槽130将造成图6的结构。由此，沟槽125和130可独立地从105延伸到大于至衬底100的底表面的中途(halfway)与直到衬底100的底表面之间。
然而，如果衬底100是绝缘体上硅(SOI)衬底(即，具有掩埋氧化物层或BOX层的硅衬底)且掩埋氧化物层的顶表面与衬底100的顶表面105距离D1，则就算使用“波希”蚀刻制程，沟槽125及130仍将被蚀刻至相同的深度，因为BOX层将当作蚀刻停止层。在一个范例中，BOX层包括二氧化硅。
沟槽125及130从衬底的顶表面以距离D1延伸至衬底100中。沟槽125具有宽度W1及沟槽130具有宽度W2。W2大于W1。在一范例中，W1约1微米至约3微米。在一范例中，W2约3微米至10微米。在一范例中，D1约50微米至约200微米。在一范例中，W1约2微米、W2约5微米及D1约150微米。由于沟槽125及130可在附图平面中延长并延长到平面外(即，从上方观察时为矩形)，W1和W2量度了沟槽125及130的最小宽度(即，矩形的短边)。
在图1C中，多晶硅层135被沉积在第二介电层120的顶表面140、沟槽125及130的侧壁145及底部150上。在一范例中，多晶硅层135包括N型或P型掺杂的多晶硅。在一范例中，多晶硅层135包括掺杂硼的多晶硅。多晶硅层135具有厚度T1。在一范例中，T1约0.8微米至约2.4微米。
在图1D中，执行氧化，将多晶硅层135(见图1C)转换成二氧化硅层155。二氧化硅层155具有厚度T2。二氧化硅层155完全填充沟槽125，但未完全填充沟槽130，因为沟槽130的宽度W2大于二氧化硅层155的厚度T2的两倍。二氧化硅层保形地覆盖沟槽130的侧壁及底部。在一范例中，T2约等于W1的一半。在一范例中，氧化多晶硅层135(见图1C)以形成二氧化硅层155通过使用高压氧化(HIPOX)制程来实施。
由于掺杂硼的多晶硅的高氧化速率和HIPOX在深沟槽中形成均匀氧化物厚度的能力，掺杂硼的多晶硅(即，图1C的层135)的HIPOX是优选的。
可选地，图1D所示结构可用以下方式形成：氧化(如，在熔炉中)图1B中沟槽125及130的侧壁及底部，或在沟槽125及130的侧壁及底部上沉积(如，利用化学气相沉积(CVD)或原子层沉积(ALD))氧化物。可选地，任何合适的电介质，诸如氮化硅、氧化铝，或多个电介质的组合均是适宜的。
在图1E中，多晶硅层170被形成在二氧化硅层155的顶表面175上且完全填充沟槽130中的剩余空间。在一范例中，多晶硅层170包括本征(即，未掺杂的)多晶硅。在第二范例中，用任何已知掺杂剂，诸如磷、砷、或硼，对多晶硅进行原位掺杂。
在图1F中，执行CMP以从二氧化硅层155上方去除多晶硅层170，因此二氧化硅层155的顶表面175与沟槽130中多晶硅层170的顶表面共面。可选地，如本领域所公知的可采用CMP或光刻构图回蚀制程的任何组合以使晶片平坦化。
在图1G中，执行多晶硅凹陷制程，自介电层155的顶表面175及沟槽130的上方区域去除所有多晶硅层170。多晶硅层170在凹陷制程之后保留在沟槽130中的顶表面低于衬底100的顶表面105。多晶硅凹陷制程可使用RIE、湿法蚀刻、或RIE蚀刻及湿法蚀刻的组合来执行。在较佳实施例中，此凹陷延伸到介电层110下方，以有助于用层185盖帽沟槽，如图1I所示。
在图1H中，将介电层185形成在二氧化硅层155的顶表面175上及沟槽130中。介电层185完全填充沟槽130中因图1F的多晶硅凹陷蚀刻所造成的空间。可选地，介电层185填充沟槽130中形成的空间，致使空隙在图1I所示的平坦化之后不会延伸至表面105。在一范例中，介电层185包括TEOS氧化物(即，使用四乙氧基硅烷前驱物以CVD形成的氧化物)、硅烷氧化物(即，使用硅烷前驱物以CVD形成的氧化物)、或任何使用LPCVD(即，低压CVD)或HDPCVD(即，高密度等离子体CVD)或任何其它已知方法沉积的电介质。
在图1I中，执行CMP及/或其它蚀刻以自衬底100的顶表面105上方去除介电层185、二氧化硅层155、第二介电层120，在沟槽130中留下介电层185的帽盖(cap)。二氧化硅层155亦可留在沟槽125中。在CMP之后，沟槽125中二氧化硅层155的顶表面、沟槽130中二氧化硅层155的边缘、沟槽中介电层185的顶表面、及衬底100的顶表面105全部共面或大体上共面。虽然显示完全去除衬底100之上的所有层，但亦可执行局部去除或选择性局部去除。
在图1J中，新的第一介电层190及新的第二介电层195被形成在衬底100的顶表面105上。二氧化硅层155保留在沟槽125中，以及二氧化硅层155、多晶硅层170、及介电层185保留在被介电层190及195所保护的沟槽130中。介电层190及195的用途是为了有助于形成集成电路结构，诸如浅沟槽隔离(STI)、深沟槽电容器、MOSFET晶体管、双极结型晶体管、二极管、变容二极管、薄膜电阻器、MOS电容器等，如本领域中所公知。可选地，可采用任何已知的方法和结构来形成集成电路结构。
在图1K中，在衬底100中，通过结合新的第一及第二介电层190及195(见图1H)利用光刻/蚀刻制程形成STI 200，类似于上文所述，后续为TEOS CVD，其后为CMP。
接下来，执行附加的光刻/蚀刻制程/沉积制程，以形成FET 205及沟槽电容器210。FET 205及沟槽电容器为可在制造中的此时形成的集成电路器件范例。其它可在此时形成的器件包括双极晶体管、BiCMOS SiGe晶体管、二极管、MOS电容器、及电阻器。FET 205包括源极/漏极215、栅极电介质220、栅极电极225、及硅化物接触230。沟槽电容器210包括内板235及介电层238。在形成栅极介电层220之前，去除新的第一及第二介电层190及195；以及在形成硅化物层230之后，在衬底100的顶表面105上方形成层间介电层240。举例而言，层间介电层240包括下介电层245及上介电层250。层间介电层240可为单层或可包括多于两层。在一范例中，下介电层245包括氮化硅，以及上介电层250包括硼磷硅酸盐玻璃(BPSG)。
在图1K及后续的图1L至1O中，为清楚起见，显示下介电层245未覆盖FET 205的栅极225。实际上，下介电层245也覆盖FET 205的栅极225。
在图1L中，使用上文所述光刻/蚀刻制程，在FET 205的硅化物层230上方，形成穿过下和上介电层245及250的开口255。
在图1M中，在开口255中形成硅化物层230的导电柱(stud)接触265，以及在接触265和上介电层250上形成保护层270。例如利用在上介电层250上方形成完全填充沟槽255的导电层(如，利用蒸发、溅射或沉积)，其后再利用CMP，即可形成接触265。然后形成保护层270。接触265可单独包括用于晶片通孔芯275(见图1O)和晶片通孔接触280(见图1O)的下述任何材料组合。在一范例中，保护层270为介电层。在一范例中，保护层270包括氮化硅。
应理解，许多其它柱接触265在此时被形成到衬底100中的其它器件。应理解，还存有许多形成和金属化柱接触265的其它方法。应理解，有许多方法和结构可用来形成集成电路器件的柱接触，如本领域中所公知。
在图1N中，使用上文所述的光刻/蚀刻制程，在沟槽130上方，形成穿过保护层270及上和下介电层245及250的开口132。然后，执行RIE以自沟槽130去除介电层185(见图1L)。接下来，使用RIE蚀刻、湿法蚀刻或湿法和RIE的组合，自沟槽130去除多晶硅层170(见图1L)。注意，在这些多晶硅层170蚀刻期间，介电层155保护衬底100(当衬底100是硅时)不受蚀刻。为避免蚀刻衬底100，在沟槽130上方的开口132不得落到介电层155之外，以及在一优选实施例中，开口132被对准致使开口132落在层155内(即，当层270、250及240被蚀刻时，开口完全落在层185上，见图1M)，致使当多晶硅层170在层185被蚀刻之后而在开口132中暴露时，介电层155在多晶硅层170被蚀刻的情况下不在开口中暴露。
在图1O中，晶片通孔芯275被形成在沟槽130中，以及(与晶片通孔芯275)一体形成的晶片通孔接触280形成在沟槽130之上的保护层270(参见图1N)和层间介电层240中的开口中。例如，利用在上介电层250上方形成完全填充沟槽130及保护层270(参见图1N)和层间介电层240中的开口的导电层(如，利用蒸发、溅射或沉积)，及其后利用CMP，可形成晶片通孔芯275及晶片通孔接触280。在图1O中，CMP已完全去除所有保护层270(参见图1N)。可选地，在CMP之后保留保护层270的薄层。晶片通孔接触280和柱接触265的顶表面与上介电层250的顶表面共面。
在一范例中，晶片通孔芯275和晶片通孔接触280包括金属。在一范例中，晶片通孔芯275及晶片通孔接触280包括钨(W)或钨和氮化钛(TiN)。在一范例中，晶片通孔芯275和晶片通孔接触280包括第一沉积的氮化钛保形层及第二沉积的钨层。在一范例中，晶片通孔芯275及晶片通孔接触280包括第一沉积的氮化钛保形层、第二沉积的保形钛(Ti)层及第三沉积的钨层。可使用CVD来沉积钛、氮化钛和钨。
在一范例中，晶片通孔芯275及晶片通孔接触280包括钨或钨及氮化钽(TaN)。在一范例中，晶片通孔芯275及晶片通孔接触280包括第一沉积的氮化钽保形层及第二沉积的钨层。在一范例中，晶片通孔芯275及晶片通孔接触280包括第一沉积的氮化钽保形层、第二沉积的保形钽(Ta)层及第三沉积的钨层。可使用CVD来沉积钽及氮化钽及钨。
其它可用于晶片通孔芯275及晶片通孔接触280的冶金组合包括铜(Cu)、钌(Ru)、Ta及TaN的组合。这些组合包括以下组合，每一组合按形成顺序为：Ta/Cu、TaN/Cu、Ru/Cu、TaN/Ta/Cu/、TaN/Ru/Cu、Ta/Ru/Cu、Ru/Ta/Cu、Ru/TaN/Cu、TaN/Ta/Ru/Cu。
应理解，柱接触265可由与形成晶片通孔芯275及晶片通孔接触280的相同或不同材料形成。同样地，柱接触可由上文针对晶片通孔芯275及晶片通孔接触280所列的任何材料组合形成。应理解，许多晶片通孔芯275及晶片通孔接触280可在此时形成。应理解，还存有许多形成及金属化晶片通孔芯275及晶片通孔接触280的其它方法。例如，可使用电镀的铜代替钨，及可使用钽或氮化钽代替氮化钛。亦应理解，如图2A至2J所图解及如上文所述，藉由从底部减薄衬底100，可形成晶片通孔。晶片通孔芯275与衬底100被二氧化硅层155所电隔离。晶片通孔芯275及二氧化硅层155在沟槽130的侧壁上的部分将成为导电晶片通孔(晶片通孔芯275为导电部分及二氧化硅层为非导电部分)。在沟槽125中的二氧化硅层155将成为非导电晶片通孔。
图2A至2J为示例了完成制造根据本发明的实施例的晶片通孔阵列及使用根据本发明的实施例的晶片通孔阵列制造三维器件的截面图。
在图2A(未按比例绘制)中，形成于一组层间介电层300中的是对应的布线及过孔305。可选的端子衬垫310被形成在该组层间介电层300的顶表面315上且与该组层间介电层300的最上方层间介电层中的最上方布线305电接触。该组层间介电层的最下方层间介电层中的布线与柱接触265及集成接触区域280物理及电接触。在图2A中未图解该组层间介电层300的个别层间介电层。将操作(handle)衬底325附接在该组层间介电层300的顶表面315。使用粘合剂层(未示出)来附接操作晶片325。在一范例中，操作衬底325为石英晶片。
在图2B中，衬底100自底部减薄(例如，利用研磨)，以形成离沟槽125及130距离D2的新底表面320。在一范例中，D2约5微米至约50微米。在一范例中，D2约20微米。在减薄之后，衬底100的厚度为D3。在一范例中，D3约50微米至约200微米。在一范例中，D3约170微米。
在图2C中，执行对硅有选择性的RIE或湿法蚀刻，使衬底100的底表面320(见图2B)凹陷，因此沟槽125及130的填充材料突出于新顶表面320A之上。
在图2D中，执行CMP以去除突出于顶表面320A(见图2C)之上的填充材料，以形成晶片通孔阵列330。在图2D的范例中，每一晶片通孔阵列330包括两个非导电晶片通孔125A及一个导电通孔130A。在CMP之后，导电晶片通孔芯275及二氧化硅层155参(见图2C)在衬底100的底表面320处暴露。
在图2E中，在二氧化硅上方执行选择性优先蚀刻硅的RIE或湿法蚀刻，以使顶表面320A(参见图2D)凹陷低于晶片通孔阵列330的底部，并形成衬底100的新底表面335。
在图2F中，在衬底底表面335及晶片通孔阵列330之上形成介电层340。在一范例中，介电层340为等离子体增强化学气相沉积(PECVD)氧化硅。
在图2G中，执行CMP以自晶片通孔阵列330的底表面去除介电层340。介电层340保留在介电层340的底表面335上，且介电层340填充在晶片通孔阵列330间在每一晶片通孔阵列的各晶片通孔125A及130A间的任何空间。晶片通孔125A及130A的底表面为与介电层340的顶表面350共面或大体上共面。
可选地，可继续在图2B中图解及上文所述的背面研磨制程，直到图2D的非导电晶片通孔125A及导电晶片通孔130A被直接形成(跳过图2C的制程)，或在研磨及去除晶片通孔及表面320A(参见图2D)的任何研磨损坏的“清除”CMP之后形成。在沟槽125被显著地比沟槽130更深地蚀刻至衬底100中时(见图2A)时，可以有利地应用该备选方案。如果沟槽130被蚀刻得明显比沟槽125深(见图5)，则研磨将暴露导电通孔130A而非非导电通孔125A，如图6所示。
注意，晶片通孔125A包括仅填充有绝缘体的第一沟槽，以及晶片通孔130A包括具有仅由包围导电芯的介电衬里组成的填料(filling)的第二沟槽。
在图2H中，导电衬垫345被形成在晶片通孔阵列330上的介电层340的顶表面350上，以及导电焊料凸块355形成在衬垫345上。在一范例中，通过构图的光致抗蚀剂层的电镀敷或通过金属掩模的蒸发而形成衬垫345及焊料凸块355。如果衬垫345为通过镀敷形成，首先沉积薄的电晶种(seed)层，其在去除光致抗蚀剂层之后利用RIE或湿法蚀刻去除。
在图2I中，在芯片切割之前或之后，去除操作晶片325(见图2G)。去除操作晶片325的示范方法为使粘合剂暴露到紫外线辐射，如本领域中所所熟知的。在一优选实施例中，在切割之后去除操作晶片325，使造成减薄的晶片破裂的可能性降到最低。
图2J为在焊料回流步骤之前的分解图。在图2J中，使含有电部件的上衬底360以导电焊料凸块365对准端子衬垫310，及衬底100以焊料凸块355对准具有导电衬垫375及含有电部件(未示出)的下衬底370。此配置允许在熔化焊料凸块的退火之前自对准这三个部件，将衬底100、360及370电布线到一起，并完成制程。电部件的范例包括但不限于：晶体管、二极管、电阻器、电容器、电感器及布线。
虽然在图2J中示例了衬垫至焊料凸块的连接，但(i)在衬底360与衬底100之间、(ii)在衬底100与衬底370之间、或(iii)在衬底360与衬底100之间以及在衬底100与衬底370之间，也可以使用其它类型的连接，诸如衬垫至衬垫的连接。虽然在衬底360上显示焊料凸块及在衬底100上显示衬垫，但衬垫可形成在衬底360上以及焊料凸块可形成在衬底100上。虽然在衬底100上显示焊料凸块以及在衬底370上显示衬垫，但衬垫可形成在衬底100上以及焊料凸块可形成于衬底370上。衬底360可以由布线或拉片接合(tab bond)取代。如果交换衬底100的焊料凸块和衬垫，则衬底370可以由布线或拉片接合取代。
图3A至3D为根据本发明的实施例的晶片通孔的示范平面图。在图3A中，单一晶片通孔阵列330A由以下组成：以二氧化硅层155填充的非导电晶片通孔125A，以及由插入在导电通孔区域275与衬底100之间的二氧化硅层155构成的单一导电晶片通孔130A。
在图3B中，晶片通孔阵列330B由以下组成：两个以二氧化硅层155填充的非导电晶片通孔125A，其在由插入在导电通孔区域275与衬底100之间的二氧化硅层155构成的导电晶片通孔130A的对侧上。
在图3C中，晶片通孔阵列330C包括：四个以二氧化硅层155填充的非导电晶片通孔125A，其在由插入在导电通孔区域275与衬底100之间的二氧化硅层155构成的导电晶片通孔130A的四侧中的每一侧的对侧上。
在图3D中，晶片通孔阵列330D由以下组成：七个以二氧化硅层155填充的非导电晶片通孔125A，以及由插入在导电通孔区域275与衬底100之间的二氧化硅层155构成的两个导电晶片通孔130A。晶片通孔125A中的三个位于两个晶片通孔130A之间。晶片通孔125A中的四个与前三个晶片通孔125A和两个晶片通孔130的组合所形成的四侧中的每一侧相对。晶片通孔阵列330B、330C及330D用作共面波导。
在图3A、3B、3C及3D的每一个附图中，每个晶片通孔125A及130A为衬底100的区域所包围。本发明本实施例的晶片通孔包括：至少一个导电元件，其从衬底顶表面延伸穿过衬底到达衬底的底表面；及至少一个非导电(即，电介质或绝缘体)元件，也是从衬底顶表面延伸穿过衬底到达衬底的底表面。
应理解，具有不同数量和配置的晶片通孔125A及130A的许多其它晶片通孔阵列也是可行的，且不限于在图3A、3B、3C及3D中所示的数量及组态。
图4A至4D为使用根据本发明的实施例的晶片通孔的波导模式的平面图。在图4A、4B、4C及4D中，G代表未与衬底绝缘且连接至接地的电导体填充沟槽；S代表未与衬底绝缘且连接至信号源的电导体填充沟槽；I代表电绝缘体填充沟槽；IG代表连接至接地且与衬底绝缘的电导体填充沟槽；及IS代表连接至信号源且与衬底绝缘的电导体填充沟槽。在G、S、I、IG及IS结构之间的空间是衬底。
对于特征阻抗、传播损耗及有效介电常数(Er)，图4A、4B、4C及4D的结构被模型化为信号波导。低传播损耗及小的有效介电常数是优选的。此模型基于：相对介电常数11.9及导电率7.41Siemens/米的硅衬底；针对G、IG、S及IS结构的电导体，导电率1.82E7Siemens/米的钨；及针对I、IG及IS结构的绝缘体，相对介电常数4.1的二氧化硅。
顶视图中G及S结构的尺寸为50×3微米。顶视图中IG及IS结构的尺寸为52×5微米(具包围绝缘体1微米厚的G及S结构)。顶视图中I结构的尺寸为52×5微米。在Ansoft HFSS-3D全波EM仿真软件上执行仿真。表I给出图4A、4B、4C及4D中每一结构的仿真结果。
表I
Figure BDA0000046312900000141
根据模拟可以得到以下结论。对于共面波导，绝缘晶片通孔具有较低特征阻抗、较少传播损耗、较低有效介电常数，以及对于具有较少潜在不合意耦合的信号传播是较佳的。原因是，硅是有损耗的，但二氧化硅不是。硅的较高介电常数造成比较低介电常数二氧化硅的寄生电容高的寄生电容。
因此，接地结构可使用如在本发明实施例中的直接接触衬底的晶片通孔(G结构)，只要跨晶片通孔的电压够低，致使几乎没有或没有任何电流传导通过衬底。对于信号结构，为降低通过衬底的信号传导，诸如本发明第二和第三实施例中的绝缘导体(IS结构)为较佳。
图5为示例了图1B所示结构的备选结构的截面图。在图5中，沟槽130B从顶表面105以距离D3延伸至衬底100中，而沟槽125从顶表面105以距离D2延伸至衬底100，如上文参考图1B所述。D3大于D2，而D2等于D1(见图1B)。
图6为示例图2I所示结构的备选结构的截面图。如果图1B的结构以图5的结构取代，则产生图6的结构。在图6中，导电通孔130B接触衬垫345，而非导电通孔125B(在此情况中为误称，其为局部通孔)未接触衬垫345。衬底100和介电层340的区域插入在非导电通孔与衬垫345之间。
因此，本发明实施例提供将晶片通孔整合至现有集成电路制程的结构及方法，其在集成电路芯片正面与底表面之间具有良好的信号传播。
上述本发明实施例的说明是用于了解本发明。应理解，本发明不限于本文所述的特定实施例，而是在不脱离本发明范畴下，能够进行各种修改、重新配置及替换，正如本领域的技术人员所理解的。因此，以下申请专利范围是用来涵盖所有此类在本发明精神及范畴之内的修改及变更。

Claims (30)

1.一种结构，其包括：
半导体衬底，其具有顶表面和相反的底表面；以及
晶片通孔阵列，其包括至少一个导电晶片通孔和至少一个非导电晶片通孔，所述晶片通孔阵列的每一个晶片通孔独立地从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间。
2.根据权利要求1的结构，其中所述至少一个非导电通孔包括仅填充有绝缘体的第一沟槽，以及所述至少一个导电通孔包括具有仅由包围导电芯的介电衬里构成的填料的第二沟槽。
3.根据权利要求2的结构，其中所述芯包括(i)钨、(ii)铜、(iii)组合钛、氮化钛或钛和氮化钛的钨、(iv)组合钽和氮化钽的钨、(v)组合钛、氮化钛和钌中的一种或多种的铜、或(vi)组合钽、氮化钽和钌中的一种或多种的铜。
4.根据权利要求2的结构，还包括：
导电柱接触，在所述衬底的所述顶表面处到所述至少一个导电晶片通孔；以及
导电背面衬垫，物理且电接触所述至少一个导电晶片通孔，所述背面衬垫靠近所述衬底的所述底表面。
5.根据权利要求4的结构，其中所述背面衬垫与所述至少一个非导电晶片通孔物理接触。
6.根据权利要求4的结构，还包括：在所述衬底的所述底表面上的绝缘层、延伸穿过所述绝缘层的所述至少一个导电晶片通孔和所述至少一个非导电晶片通孔、在所述绝缘层上的所述背面衬垫。
7.根据权利要求4的结构，其中，所述柱接触与所述导电芯一体形成。
8.根据权利要求4的结构，还包括：
布线层组，形成在所述衬底的所述顶表面之上；
导电正面衬垫，在所述布线层的顶表面上，所述正面衬垫通过所述布线层组中的布线而电连接至所述柱接触。
9.根据权利要求8的结构，还包括：
(i)在所述背面衬垫上的焊料凸块，(ii)在所述正面衬垫上的焊料凸块，或(iii)在所述背面衬垫上的第一焊料凸块和在所述正面衬垫上的第二焊料凸块。
10.根据权利要求1的结构，还包括：
一个或多个器件，至少部分地形成在所述衬底中；
所述一个或多个器件选自：场效晶体管、双极晶体管、BiCMOS SiGe晶体管、二极管、电阻器以及电容器。
11.一种方法，其包括：
通过具有顶表面和相反的底表面的半导体衬底形成晶片通孔阵列，其中所述晶片通孔阵列包括至少一个导电晶片通孔和至少一个非导电晶片通孔，所述晶片通孔阵列的每一个晶片通孔独立地从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间。
12.根据权利要求11的方法，其中所述至少一个非导电通孔包括仅填充有绝缘体的沟槽，以及所述至少一个导电通孔包括具有仅由包围导电芯的介电衬里构成的填料的沟槽。
13.根据权利要求12的方法，还包括：
形成至所述芯的导电柱接触；
在所述衬底的所述底表面上形成绝缘层；以及
在所述绝缘层上形成导电背面衬垫，所述至少一个导电晶片通孔和所述至少一个非导电晶片通孔延伸穿过所述绝缘层，所述背面衬垫物理并电接触所述芯且物理接触所述介电衬里和所述绝缘体。
14.一种方法，其包括：
(a)在半导体衬底中形成第一沟槽和第二沟槽，所述第一和所述第二沟槽独立地从所述衬底的顶表面朝所述衬底的相反的底表面延伸小于所述衬底的厚度的距离；
(b)同时地用介电材料完全填充所述第一沟槽并在所述第二沟槽的侧壁上形成所述介电材料的衬里；
(c)用导电材料填充所述第二沟槽中的剩余空间；以及
(d)从所述衬底的所述底表面减薄所述衬底以形成所述衬底的新底表面，所述第一沟槽的所述介电材料以及所述第二沟槽的所述衬里和导电材料在衬底的所述新底表面中暴露。
15.根据权利要求14的方法，其中(b)包括：
在所述第一沟槽的侧壁上以及在所述第二沟槽的所述侧壁上形成多晶硅层；以及
氧化所述多晶硅层以在所述第一沟槽中形成所述介电材料并在所述第二沟槽的所述侧壁上形成所述介电材料的所述衬里。
16.根据权利要求14的方法，其中用硼掺杂所述多晶硅。
17.根据权利要求14的方法，在(b)与(c)之间还包括：
(i)用多晶硅填充所述第二沟槽中的剩余空间；
(ii)使所述多晶硅凹陷低于所述衬底的所述顶表面；
(iii)用附加的介电材料填充在所述多晶硅上方的所述沟槽；以及
(iv)从所述第二沟槽去除所述多晶硅和所述附加的介电材料。
18.根据权利要求17的方法，在(iii)与(iv)之间还包括：
至少部分地在所述衬底中形成一个或多个器件；
在所述衬底的所述顶表面上形成层间介电层；
穿过所述层间介电层形成到达所述附加的介电材料的第一开口以及穿过所述层间介电层形成到达所述一个或多个器件中的至少一个器件的第二开口；以及
其中(c)同时填充所述第二沟槽、所述第一开口及第二开口。
19.根据权利要求18的方法，其中所述一个或多个器件选自：场效晶体管、双极晶体管、BiCMOS SiGe晶体管、二极管、电阻器以及电容器。
20.根据权利要求14的方法，在(c)与(d)之间还包括：
在所述衬底的所述顶表面之上形成布线层组；以及
在所述布线层的顶表面上形成导电正面衬垫，所述正面衬垫通过所述布线层组中的布线而电连接至所述柱接触。
21.根据权利要求20的方法，还包括：
(e)形成导电背面衬垫，所述导电背面衬垫物理并电接触所述第二沟槽的所述导电材料，所述背面衬垫靠近所述衬底的所述底表面。
22.根据权利要求21的方法，其中所述背面衬垫物理接触所述第一沟槽的所述介电材料。
23.根据权利要求21的方法，在(d)与(e)之间还包括：
在所述衬底的所述底表面上形成绝缘层，所述第一沟槽的所述介电材料延伸穿过所述绝缘层以及所述第二沟槽的所述衬里和所述导电材料延伸穿过所述绝缘层，所述背面衬垫形成在所述绝缘层上。
24.根据权利要求21的方法，还包括：
(i)在背面衬垫上形成焊料凸块，(ii)在所述正面衬垫上形成焊料凸块，或(iii)在背面衬垫上形成第一焊料凸块并在所述正面衬垫上形成第二焊料凸块。
25.根据权利要求14的方法，其中(d)包括：
研磨所述衬底的所述底表面以形成所述衬底的新底表面；
化学蚀刻所述衬底的所述新底表面以暴露所述第一沟槽的所述介电材料和所述第二沟槽的所述衬里；以及
化学机械抛光以暴露所述第二沟槽的所述导电材料。
26.一种穿过半导体衬底的信号传输线，所述衬底具有顶表面和相反的底表面，包括：
导电晶片通孔，其从所述衬底的所述顶表面延伸至所述衬底的所述底表面，所述导电通孔的侧壁与所述衬底电绝缘；以及
非导电通孔，其从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间，所述非导电通孔靠近所述导电晶片通孔并通过所述衬底的区域与所述导电晶片通孔分开。
27.根据权利要求26的信号传输线，还包括：
附加的非导电通孔，其从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间，所述附加的非导电通孔被设置在所述导电通孔的与所述非导电通孔相反的侧上，所述附加的非导电通孔靠近所述导电晶片通孔并通过所述衬底的附加的区域与所述导电晶片通孔分开。
28.根据权利要求26的信号传输线，还包括：
第一、第二以及第三附加的非导电通孔，其从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间，所述非导电通孔和所述第一、第二以及第三附加的非导电通孔被设置在所述导电通孔的各第一、第二、第三以及第四侧上，所述第一侧与所述第二侧对置，所述第三侧与所述第四侧对置；所述第一、第二以及第三附加的非导电通孔与所述导电通孔通过所述衬底的各第一、第二以及第三附加的区域分开。
29.根据权利要求26的信号传输线，还包括：
附加的导电晶片通孔，其从所述衬底的所述顶表面延伸至所述衬底的所述底表面，所述附加的导电通孔的侧壁与所述衬底电绝缘；
一个或多个内部非导电通孔，其从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间，所述一个或多个内部非导电通孔插入在所述导电通孔与所述附加的导电通孔之间，所述一个或多个内部非导电通孔在所述导电通孔的与所述非导电通孔相反的侧上；
附加的非导电通孔，其从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间，所述附加的非导电通孔被设置在所述附加的导电通孔的与所述一个或多个内部非导电通孔相反的侧上；以及
第一和第二外部非导电通孔，其从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间，所述第一和第二外部非导电通孔被设置在由所述导电通孔、所述一或多个内部非导电通孔以及所述附加的导电通孔所构成的芯群组的不同侧上。
30.根据权利要求26的信号传输线，还包括：
第一和第二附加的导电晶片通孔，其从所述衬底的所述顶表面延伸至所述衬底的所述底表面，所述附加的导电通孔的侧壁与所述衬底电绝缘；
第一一个或多个内部非导电通孔，其从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间，所述第一一个或多个非导电通孔插入在所述导电通孔与所述第一附加的导电通孔之间，所述第一一个或多个内部非导电通孔在所述导电通孔的与所述附加的非导电通孔相反的侧上；
第二一个或多个内部非导电通孔，其从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间，所述第二一个或多个非导电通孔插入在所述第一附加的导电通孔与所述第二附加的导电通孔之间，所述第二一个或多个内部非导电通孔在所述导电通孔的与所述非导电通孔相反的侧上；
附加的非导电通孔，其从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间，所述附加的非导电通孔被设置在所述第二附加的导电通孔的与所述第二一个或多个内部非导电通孔相反的侧上；以及
第一和第二外部非导电通孔，其从所述衬底的所述顶表面延伸到大于至所述衬底的所述底表面的中途与直到所述衬底的所述底表面之间，所述第一和第二外部非导电通孔被设置在由所述导电通孔、所述第一一个或多个内部非导电通孔、所述第一附加的导电通孔、所述第一一个或多个内部非导电通孔、以及所述附加的导电通孔构成的芯群组的不同侧上。
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TWI479554B (zh) 2015-04-01
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