WO2022217785A1 - 存储器的制作方法及存储器 - Google Patents

存储器的制作方法及存储器 Download PDF

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Publication number
WO2022217785A1
WO2022217785A1 PCT/CN2021/109361 CN2021109361W WO2022217785A1 WO 2022217785 A1 WO2022217785 A1 WO 2022217785A1 CN 2021109361 W CN2021109361 W CN 2021109361W WO 2022217785 A1 WO2022217785 A1 WO 2022217785A1
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WIPO (PCT)
Prior art keywords
layer
hole structure
electrode plate
contact pad
capacitive contact
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PCT/CN2021/109361
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English (en)
French (fr)
Inventor
白卫平
朱丽
应战
Original Assignee
长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/500,245 priority Critical patent/US20220336462A1/en
Publication of WO2022217785A1 publication Critical patent/WO2022217785A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present application relates to the technical field of storage devices, and in particular, to a method for manufacturing a memory and a memory.
  • DRAM Dynamic Random Access Memory
  • a dynamic random access memory is generally composed of a plurality of memory cells, and each memory cell usually includes a transistor (Transistor) structure and a capacitor (Capacitor) device.
  • the capacitor stores data information, and the transistor structure controls the reading and writing of the data information in the capacitor.
  • capacitors are usually arranged on the substrate and are electrically connected to the capacitive contact pads in the substrate.
  • the contact area between the capacitor and the capacitive contact pad becomes smaller and the contact resistance becomes larger. , which affects the storage speed and storage efficiency of the memory.
  • an embodiment of the present application provides a method for fabricating a memory, which includes: providing a substrate, and the substrate is provided with a plurality of capacitor contact pads arranged at intervals; and on the first surface of each of the capacitor contact pads forming a first groove; forming a conductive column in the first groove, the upper end surface of the conductive column is flush with the first surface of the capacitive contact pad; forming a plurality of capacitors on the substrate, a plurality of The capacitors are in one-to-one correspondence with a plurality of the capacitor contact pads and are electrically connected; the first electrode plate of each capacitor covers the conductive column in the corresponding capacitor contact pad, and the first electrode plate
  • the material is the same as the material of the conductive column.
  • a substrate is provided first, and a plurality of capacitor contact pads arranged at intervals are provided in the substrate; a first groove is formed on the first surface of each capacitor contact pad; A conductive column is formed in the groove, and the upper end surface of the conductive column is flush with the first surface of the capacitive contact pad; a plurality of capacitors are formed on the substrate, and the plurality of capacitors are in one-to-one correspondence with the plurality of capacitive contact pads and are electrically connected;
  • the first electrode plate covers the conductive column in the corresponding capacitor contact pad, and the material of the first electrode plate is the same as that of the conductive column.
  • the contact area between the conductive column and the first electrode plate as a whole with the capacitor contact pad is increased, and the contact between the capacitor and the capacitor is reduced. Contact resistance between pads, thereby improving storage efficiency and storage speed.
  • an embodiment of the present application further provides a memory, which includes: a substrate and a capacitor disposed on the substrate, the substrate is provided with a plurality of capacitor contact pads arranged at intervals, each of the capacitor contact pads There is a conductive column inside; the capacitor includes: a second electrode plate, a plurality of first hole structures are arranged in the second electrode plate, and a plurality of the first hole structures are connected with a plurality of the capacitor contact pads.
  • the material of the plates is the same.
  • the memory provided by the embodiment of the present application includes a substrate and a capacitor disposed on the substrate.
  • the substrate is provided with a plurality of capacitive contact pads arranged at intervals, and each capacitive contact pad is provided with a conductive column.
  • the capacitor includes a second electrode plate, a dielectric layer and a first electrode plate, wherein a plurality of first hole structures are arranged in the second electrode plate, and the plurality of first hole structures correspond to the plurality of capacitive contact pads one-to-one; the dielectric The layer is arranged on the hole wall of the first hole structure, and the dielectric layer located in the first hole structure is surrounded by a second hole structure; the first electrode plate is arranged in the second hole structure, and the first electrode plate is electrically connected to the capacitor contact pad.
  • the material of the conductive pillars is the same as that of the first electrode plate.
  • FIG. 1 is a flowchart of a method for manufacturing a memory in an embodiment of the present application
  • FIG. 2 is a top view of a substrate in an embodiment of the application
  • FIG. 3 is a schematic structural diagram of a substrate in an embodiment of the present application.
  • FIG. 4 is a top view after forming a photoresist layer in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram after forming a photoresist layer in an embodiment of the present application.
  • FIG. 6 is a top view after forming the first groove in an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram after forming a first groove in an embodiment of the present application.
  • FIG. 8 is a top view after forming a first conductive layer in an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram after forming the first conductive layer in an embodiment of the present application.
  • FIG. 10 is a top view after forming the conductive pillars in the embodiment of the present application.
  • FIG. 11 is a schematic structural diagram after forming a conductive column in an embodiment of the present application.
  • FIG. 13 is a top view after forming a barrier layer in an embodiment of the application.
  • FIG. 14 is a schematic structural diagram after forming a barrier layer in an embodiment of the present application.
  • FIG. 15 is a top view after forming the first electrode layer in the embodiment of the application.
  • FIG. 16 is a schematic structural diagram after forming the first electrode layer in an embodiment of the present application.
  • 17 is a top view after forming a preset mask layer in an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram after forming a preset mask layer in an embodiment of the present application.
  • 19 is a top view after forming a hard mask layer in an embodiment of the application.
  • FIG. 20 is a schematic structural diagram after forming a hard mask layer in an embodiment of the present application.
  • 21 is a top view after forming the first hole structure in the embodiment of the present application.
  • FIG. 22 is a schematic structural diagram after forming the first hole structure in an embodiment of the present application.
  • FIG. 23 is a schematic structural diagram after forming a dielectric layer in an embodiment of the present application.
  • FIG. 24 is a top view after forming a protective layer in an embodiment of the present application.
  • 25 is a schematic structural diagram after forming a protective layer in an embodiment of the present application.
  • 26 is a top view after exposing the barrier layer in an embodiment of the application.
  • FIG. 27 is a schematic structural diagram of the exposed barrier layer in an embodiment of the present application.
  • FIG. 28 is a top view after removing part of the barrier layer in an embodiment of the present application.
  • FIG. 29 is a schematic structural diagram of the embodiment of the present application after removing part of the barrier layer
  • FIG. 30 is a top view after forming the second electrode layer in the embodiment of the application.
  • FIG. 31 is a schematic structural diagram after forming the second electrode layer in an embodiment of the application.
  • 35 is a schematic structural diagram after forming an insulating layer in an embodiment of the application.
  • 36 is a top view after removing part of the insulating layer in an embodiment of the present application.
  • FIG. 37 is a schematic structural diagram of an embodiment of the present application after removing part of the insulating layer
  • FIG. 39 is a schematic structural diagram after forming the second conductive layer in an embodiment of the present application.
  • FIG. 40 is a schematic structural diagram of a lower plate of a capacitor in an embodiment of the present application.
  • FIG. 41 is a schematic diagram of the structure after forming the M1 metal layer in an embodiment of the present application.
  • the first electrode plate of the capacitor is electrically connected to the capacitor contact pad, and the first electrode plate is usually arranged above the capacitor contact pad, and the lower end surface of the first electrode plate is in contact with the upper end surface of the capacitor contact pad.
  • the contact area between the first electrode plate and the capacitor contact pad becomes smaller, and the contact resistance between the first electrode plate and the capacitor contact pad increases, resulting in lower storage speed and storage efficiency of the memory.
  • an embodiment of the present application provides a method for fabricating a memory.
  • a capacitor is formed,
  • the first electrode plate of the capacitor covers the corresponding conductive column, and the material of the first electrode plate is the same as that of the conductive column, thereby increasing the contact area between the conductive column and the first electrode plate as a whole and the contact pad of the capacitor, reducing the Contact resistance of capacitors to capacitive contact pads, thereby increasing storage efficiency and storage speed.
  • an embodiment of the present application provides a method for manufacturing a memory, and the method for manufacturing comprises the following steps:
  • Step S101 providing a substrate, and the substrate is provided with a plurality of capacitor contact pads arranged at intervals.
  • the substrate 100 serves as a supporting member of the memory for supporting other components provided thereon.
  • a plurality of capacitive contact pads 110 may be provided in the substrate 100 , the plurality of capacitive contact pads 110 are arranged at intervals, and the plurality of capacitive contact pads 110 are arranged in a honeycomb shape in the substrate 100 .
  • one capacitive contact pad 110 is located in the center, six capacitive contact pads 110 are arranged around the capacitive contact pad 110 , and the center of the six capacitive contact pads 110 is The connecting lines form a regular hexagon.
  • the material of the capacitor contact pad 110 includes tungsten (W) to facilitate subsequent electrical connection with the capacitor.
  • the material of the substrate 100 includes silicon oxide (SiO 2 ), so as to electrically isolate each capacitor contact pad 110 in the substrate 100 and prevent electrical connection between adjacent capacitor contact pads 110 .
  • the material of the capacitive contact pad 110 and the material of the substrate 100 are not limited, for example, the material of the capacitive contact pad 110 may also be one or more of titanium nitride, titanium tungsten, aluminum or copper.
  • Step S102 forming a first groove on the first surface of each capacitor contact pad.
  • the first surface of the capacitive contact pad 110 is the surface of the capacitive contact pad 110 exposed to the substrate 100 , that is, the upper surface of the capacitive contact pad 110 shown in FIGS. 4 to 11 .
  • a first groove 111 is formed on the upper surface of each capacitive contact pad 110 .
  • the first groove 111 can be formed by a patterning process, that is, a desired pattern is formed on the capacitive contact pad 110 by processes such as gluing, exposing, developing, etching, and degumming.
  • the step of forming a first groove on the first surface of each capacitive contact pad includes:
  • a photoresist layer 200 is formed on the substrate, and the photoresist layer 200 has a first pattern. As shown in FIG. 4 and FIG. 5 , the photoresist layer 200 has a fourth hole structure penetrating the layer, and the fourth hole structure exposes the capacitive contact pad 110 .
  • the circle shown by the dotted line represents the edge of the first surface of the capacitive contact pad 110
  • the hole area of the fourth hole structure is smaller than the area of the corresponding first surface of the capacitive contact pad 110 , so that the capacitance The central area of the contact pad 110 is exposed, and the edge area of the capacitive contact pad 110 is not exposed. That is, the photoresist layer 200 covers the edge region of the first surface of the capacitive contact pad 110 and the substrate 100 , so as to form the first groove 111 on the first surface of the capacitive contact pad 110 .
  • the capacitor contact pad 110 is etched along a first pattern, and a first groove 111 is formed on the first surface of the capacitor contact pad 110 . As shown in FIG. 6 and FIG. 7 , part of the capacitor contact pad 110 is removed by etching to form the first groove 111 .
  • the opening area of the first groove 111 may be 1/3-1/2 of the area of the first surface of the capacitive contact pad 110 , wherein the opening area of the first groove 111 refers to the first groove 111 . , that is, the opening area of the upper end of the first groove 111 shown in FIGS. 6 and 7 .
  • the depth of the first groove 111 may be 1/3-2/3 of the thickness of the capacitive contact pad 110 .
  • the depth of the first groove 111 refers to the distance between the bottom of the first groove 111 and the open end of the first groove 111
  • the thickness of the capacitive contact pad 110 refers to the distance between the first surface of the capacitive contact pad 110 and the first surface of the capacitive contact pad 110 .
  • the distance between the second surface opposite the surface That is, the depth of the first groove 111 and the thickness of the capacitive contact pad 110 both refer to the dimension in the vertical direction (Y direction) shown in FIG. 7 .
  • the photoresist layer 200 is removed.
  • the photoresist layer 200 may be removed by an ashing process or the like. After the photoresist layer 200 is removed, the substrate 100 is exposed.
  • Step S103 forming a conductive column in the first groove, and the upper end surface of the conductive column is flush with the first surface of the capacitive contact pad.
  • conductive pillars 120 are deposited and formed in the first grooves 111 , the conductive pillars 120 are filled in the first grooves 111 , and the upper end surfaces of the conductive pillars 120 are flush with the first surface of the capacitive contact pad 110 to Flatten the top surface of the structure shown in Figure 11.
  • a conductive column is formed in the first groove, and the step of the upper end surface of the conductive column being flush with the first surface of the capacitive contact pad includes:
  • a conductive material is deposited in the first groove 111 and on the substrate 100 to form a first conductive layer 130 .
  • the first conductive layer 130 is filled in the first groove 111 and covers the substrate 100 .
  • the circle shown by the dotted line on the outside is the edge of the first surface of the capacitive contact pad 110
  • the dotted line on the inside is the edge of the first surface of the capacitive contact pad 110 .
  • the circle is the edge of the first groove 111 .
  • the first conductive layer 130 is formed, the first conductive layer 130 located on the substrate 100 is removed, and the remaining first conductive layer 130 forms a plurality of conductive pillars 120 .
  • each capacitive contact pad 110 has a conductive post 120 formed therein.
  • the first conductive layer 130 on the substrate 100 may be removed by chemical mechanical polishing (Chemical-Mechanical Polishing, CMP for short).
  • Step S104 forming a plurality of capacitors on the substrate, and the plurality of capacitors are in one-to-one correspondence with the plurality of capacitive contact pads and are electrically connected; the first electrode plate of each capacitor covers the conductive column in the corresponding capacitive contact pad, and the first electrode The material of the plate is the same as that of the conductive column.
  • a plurality of capacitors are formed on the substrate 100, and the plurality of capacitors are in one-to-one correspondence with the plurality of capacitive contact pads 110 and are electrically connected. It can be understood that the number of capacitors is equal to that of the capacitive contact pads 110 , and each capacitive contact pad 110 is connected to one capacitor.
  • the first electrode plate of each capacitor covers the conductive column 120 in the corresponding capacitor contact pad 110 , and the material of the first electrode plate is the same as that of the conductive column 120 .
  • the area of the lower end surface of the first electrode plate may be 1.5-3 times the area of the upper end surface of the corresponding conductive column 120 .
  • the first electrode plate and the conductive column 120 form a whole to form the lower electrode plate of the capacitor together.
  • the contact area of the contact pad increases, that is, the contact area between the lower plate of the capacitor and the first contact pad increases, thereby reducing the contact resistance between the capacitor and the first contact pad and improving the storage speed and storage efficiency of the memory.
  • a substrate 100 is provided, and a plurality of capacitor contact pads 110 arranged at intervals are provided in the substrate 100; a first groove 111 is formed on the first surface of each capacitor contact pad 110; A conductive column 120 is formed in the first groove 111, and the upper end surface of the conductive column 120 is flush with the first surface of the capacitive contact pad 110; a plurality of capacitors are formed on the substrate 100, and the plurality of capacitors are one with the plurality of capacitive contact pads 110.
  • a corresponding and electrically connected; the first electrode plate of each capacitor covers the conductive column 120 in the corresponding capacitor contact pad 110 , and the material of the first electrode plate is the same as that of the conductive column 120 .
  • the conductive post 120 in the capacitive contact pad 110 By arranging the conductive post 120 in the capacitive contact pad 110, and the conductive post 120 and the first electrode plate are made of the same material, the contact area between the conductive post 120 and the first electrode plate as a whole with the capacitive contact pad 110 is increased, and the contact area with the capacitive contact pad 110 is reduced. The contact resistance between the capacitor and the capacitor contact pad 110 is improved, thereby improving storage efficiency and storage speed.
  • a plurality of capacitors are formed on the substrate, and the steps of the plurality of capacitors and the plurality of capacitive contact pads corresponding to each other and electrically connected may include:
  • Step S1041 forming a barrier layer on the substrate, and the barrier layer covers the substrate, the capacitive contact pad and the conductive column.
  • the barrier layer 300 may be formed on the substrate 100 through a deposition process.
  • the barrier layer 300 is formed on the substrate by a chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) process, a physical vapor deposition (Physical Vapor Deposition, referred to as PVD) process, or an atomic layer deposition (Atomic Layer Deposition, referred to as ALD) process, etc. 100 on.
  • CVD chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • ALD atomic layer deposition
  • the material of the barrier layer 300 includes SiBN, and the layer can be used as an etching barrier layer to reduce or prevent damage to the substrate 100 in the subsequent fabrication process.
  • the barrier layer 300 has relatively excellent high temperature performance, lower dielectric constant and dielectric loss, and better insulation performance, so as to improve the performance of the memory.
  • FIG. 13 is a top view after forming the barrier layer 300 in the embodiment of the present application.
  • the barrier layer 300 covers the substrate 100 , the capacitive contact pads 110 and the conductive pillars 120 , so the capacitive contact pads 110 and the conductive pillars 120 is the circle shown by the dotted line in FIG. 13 , the circle located on the outer side is the edge of the first surface of the capacitive contact pad 110 , and the circle located on the inner side is the edge of the conductive column 120 , that is, the conductive column 120 is located on the capacitive contact pad 110 .
  • the circle located on the outer side is the edge of the first surface of the capacitive contact pad 110
  • the circle located on the inner side is the edge of the conductive column 120 , that is, the conductive column 120 is located on the capacitive contact pad 110 .
  • Step S1042 forming a second electrode plate on the barrier layer, the second electrode plate is formed with a plurality of first hole structures, and the plurality of first hole structures are in one-to-one correspondence with the plurality of capacitor contact pads.
  • the second electrode plate 420 is formed with a plurality of first hole structures 410 , the plurality of first hole structures 410 penetrate through the second electrode plate 420 , and the first hole structures 410 can be formed by photolithography and etching processes . It can be understood that the second electrode plate 420 is the upper electrode plate of the capacitor.
  • the plurality of first hole structures 410 correspond to the plurality of capacitive contact pads 110 one-to-one. It can be understood that the number of the first hole structures 410 and the capacitive contact pads 110 are the same, and one first hole structure 410 corresponds to one capacitive contact pad 110 For example, the first hole structures 410 are located just above the corresponding capacitive contact pads 110 .
  • the size of the first hole structure 410 may be larger than the size of the first surface of the capacitive contact pad 110 .
  • the orthographic projection of the first hole structure 410 on the substrate 100 covers the first surface of the capacitive contact pad 110 , which is convenient for subsequent operations in the first hole.
  • a dielectric layer 600 and a second electrode plate 420 are formed within the structure 410 .
  • a second electrode plate is formed on the barrier layer, the second electrode plate is formed with a plurality of first hole structures, and the step of one-to-one correspondence between the plurality of first hole structures and the plurality of capacitive contact pads may include:
  • the first electrode layer 400 is formed on the barrier layer 300 . 15 and FIG. 16 , the first electrode layer 400 may be formed on the barrier layer 300 through a deposition process, that is, the first electrode layer 400 covers the barrier layer 300 , and the material of the first electrode layer 400 may include titanium nitride (TiN).
  • TiN titanium nitride
  • a hard mask layer 520 is formed on the first electrode layer 100 .
  • the hard mask layer 520 is formed with a plurality of etching holes 510 , a plurality of etching holes 510 and a plurality of capacitor contact pads 110 One-to-one correspondence.
  • a plurality of etching holes 510 are formed in the hard mask layer 520 , the etching holes 510 penetrate through the hard mask layer 520 , and the plurality of etching holes 510 correspond to the plurality of capacitor contact pads 110 one-to-one .
  • a preset mask layer 500 is first deposited on the first electrode layer 400 ; and then referring to FIGS. 19 and 20 , the preset mask layer 500 is etched to form The etching hole 510 , the preset mask layer 500 having the etching hole 510 is the hard mask layer 520 .
  • the etching hole 510 may be formed by a Self-aligned Double Patterning (SADP) process, a Self-aligned Quadruple Patterning (Self-aligned Quadruple Patterning) process or an EUV (Extreme Ultraviolet) photolithography process.
  • SADP Self-aligned Double Patterning
  • Self-aligned Quadruple Patterning Self-aligned Quadruple Patterning
  • EUV Extreme Ultraviolet
  • the hard mask layer 520 is formed, and the first electrode layer 400 is etched along the etching hole 510 to form the first hole structure 410 .
  • the first electrode layer 400 is etched by using the hard mask layer 520 as a mask to form a first hole structure 410 in the first electrode layer 400 .
  • the pattern on the hard mask layer 520 is transferred to the first electrode layer 400 to form the second electrode plate 420 having the first hole structure 410 .
  • the second electrode plate 420 can be formed by one etching, and each capacitor is interconnected through the second electrode plate 420 .
  • the second electrode plate 420 supports the dielectric layer 600 and the first electrode plate 810 formed later, and the supporting area is large, which facilitates the formation of a capacitor with a large aspect ratio, that is, the stability of the capacitor.
  • the yield of the memory is improved.
  • the hard mask layer 520 is removed. As shown in FIGS. 21 and 22 , the hard mask has been removed, and the second electrode plate 420 is exposed, so as to form a dielectric layer 600 on the upper surface and the side surface of the second electrode plate 420 .
  • Step S1043 forming a dielectric layer on the hole wall of the first hole structure, the dielectric layer is surrounded by a second hole structure, and the second hole structure extends to the capacitor contact pad.
  • a dielectric layer 600 is formed on the hole wall of the first hole structure 410 , and the dielectric layer 600 may be a high dielectric constant layer, so that the layer has better insulating properties.
  • the dielectric layer 600 in the first hole structure 410 is surrounded by a second hole structure 610 , and the second hole structure 610 extends to the capacitor contact pad 110 . That is, the second hole structure 610 also penetrates the barrier layer 300 to expose the capacitive contact pad 110 and the conductive pillar 120 in the second hole structure 610 .
  • the step of forming a dielectric layer on the hole walls of the first hole structure may include:
  • a dielectric layer 600 is deposited on the hole walls and bottom of the first hole structure 410 and on the second electrode plate 420 , and the dielectric layer 600 in the first hole structure 410 surrounds the second hole structure 610 .
  • the second electrode plate 420 supports the dielectric layer 600 , and the supporting area is large, which is beneficial to increase the deposition area of the dielectric layer 600 and improve the deposition quality of the dielectric layer 600 .
  • the dielectric layer 600 located on the hole wall of the first hole structure 410 is retained, the remaining dielectric layer 600 is removed, and the second hole structure 610 exposes the barrier layer 300 . It can be understood that the dielectric layer 600 located on the surface of the second electrode plate 420 facing away from the substrate 100 and the dielectric layer 600 located at the bottom of the hole of the second hole structure 610 are removed, leaving the hole wall located in the first hole structure 410 the dielectric layer 600 .
  • the dielectric layer 600 on the hole wall of the first hole structure 410 is retained, and after the remaining dielectric layer 600 is removed, part of the barrier layer 300 is removed to expose the capacitive contact pad 110 and the conductive pillar 120 in the second hole structure 610 .
  • the barrier layer 300 is etched along the second hole structure 610 , so that the second hole structure 610 penetrates the barrier layer 300 and extends to the capacitor contact pad 110 .
  • the step of forming the dielectric layer 600 on the hole wall of the first hole structure 410 may include:
  • a dielectric layer 600 is deposited on the hole walls and the bottom of the first hole structure 410 and the second electrode plate 420 , and the dielectric layer 600 in the first hole structure 410 is surrounded by the first hole structure 410 .
  • Two hole structures 610 As shown in FIGS. 24 and 25 , the dielectric layer 600 covers the second electrode plate 420 .
  • a protective layer 700 is deposited on the dielectric layer 600 to form a third hole structure 710 surrounded by the protective layer 700 in the second hole structure 610 .
  • the protective layer 700 covers the dielectric layer 600
  • the material of the protective layer 700 can be a conductive material.
  • the material of the protective layer 700 can be the same as the material of the first electrode plate 810 to be formed subsequently. , that is, the protective layer 700 and the first electrode plate 810 together form the lower electrode plate of the capacitor.
  • the circle shown by the outermost dotted line is the edge of the second pole plate 420
  • the circle shown by the outermost dotted line is the edge of the second pole plate 420
  • the circle indicated by the dotted line is the edge of the dielectric layer 600
  • the circle indicated by the innermost dotted line is the edge of the conductive pillar 120
  • the circle indicated by the dotted line at the second inner side is the edge of the first surface of the capacitive contact pad 110
  • the third hole structure 710 is not marked in the top view.
  • the bottom of the hole on the third hole structure 710 , the protective layer 700 and the dielectric layer 600 on the second electrode plate 420 are removed, and the third hole structure 710 exposes the barrier Layer 300.
  • the protective layer 700 and the dielectric layer 600 are etched along the third hole structure 710 , so that the barrier layer 300 is exposed in the third hole structure 710 . While etching the protective layer 700 and the dielectric layer 600 at the bottom of the third hole structure 710, the protective layer 700 and the dielectric layer 600 on the surface of the second electrode plate 420 away from the substrate 100 are also etched to expose the first plate 420. Diode plate 420 .
  • the second pole plate 420 is exposed, the circle shown by the solid line on the outermost side is the edge of the second pole plate 420 , and the circle shown by the solid line on the outermost side is the edge of the second pole plate 420 .
  • the circle shown by the innermost solid line is the edge of the protective layer 700 . That is, the dielectric layer 600 is between the circle shown by the outermost solid line and the circle shown by the solid line at the outer side of the order, and the circle shown by the solid line at the second outer side and the solid line at the inner side are between the dielectric layer 600 .
  • the protective layer 700 covers the capacitive contact pads 110 and the conductive pillars 120 between the circles shown, that is, the capacitive contact pads 110 and the conductive pillars 120 are circles shown in dotted lines in FIG. 26 and are not exposed.
  • part of the barrier layer 300 is removed to expose the capacitive contact pads 110 and the conductive pillars 120 in the third hole structure 710 .
  • the barrier layer 300 is etched along the third hole structure 710 to expose the capacitive contact pads 110 and the conductive pillars 120 . That is, the third hole structure 710 penetrates through the barrier layer 300 and extends to the capacitor contact pad 110 .
  • Step S1044 forming a first electrode plate in the second hole structure, and the first electrode plate is electrically connected to the capacitor contact pad and covers the conductive column.
  • the first electrode plate 810 is made of conductive material and is in contact with the capacitor contact pad 110 to realize electrical connection between the first electrode plate 810 and the capacitor contact pad 110 .
  • the first electrode plate 810 is formed in the second hole structure 610 , and the first electrode plate 810 has no requirement for supporting strength, and a material with good compatibility with the dielectric layer 600 and a high work function can be selected.
  • the material of the first electrode plate 810 may include titanium nitride (TiN) or a mixture of titanium nitride and tungsten.
  • the first electrode plate 810 covers the conductive pillars 120 .
  • the area of the lower end surface of the first electrode plate 810 is 1.5-3 times the area of the corresponding upper end surface of the conductive pillar 120 .
  • the material of the first electrode plate 810 is the same as that of the conductive column 120 .
  • the first electrode plate 810 and the conductive column 120 are integrated together to form the lower electrode plate of the capacitor.
  • the step of forming the first electrode plate 810 in the second hole structure 610 may specifically include:
  • a second electrode layer 800 is formed in the third hole structure 710 , on the protective layer 700 , on the dielectric layer 600 and on the second electrode plate 420 , and the second electrode layer 800 is in phase with the capacitive contact pad 110 touch.
  • the second electrode layer 800 is filled in the third hole structure 710 and covers the first electrode plate 810 , the protective layer 700 and the dielectric layer 600 .
  • the second electrode layer 800 located on the dielectric layer 600 and the second electrode plate 420 is removed, and the remaining second electrode layer 800 forms the first electrode plate 810 .
  • the second electrode layer 800 located in the third hole structure 710 is retained, and the retained second electrode layer 800 forms the first electrode plate 810 , and the number of the first electrode plate 810 is multiple, A first electrode plate 810 is formed in each of the third hole structures 710 .
  • the second electrode layer 800 may be removed by an etching process, that is, by depositing the second electrode layer 800 and etch back to form a plurality of separate first electrode plates 810 .
  • the steps further include:
  • an insulating layer 910 is formed on the second electrode plate 420 , the dielectric layer 600 and the first electrode plate 810 .
  • the insulating layer 910 covers the first electrode plate 810 , the dielectric layer 600 and the second electrode plate 420 .
  • the first electrode plate 810 , the dielectric layer 600 and the second electrode plate 420 are shown by dotted lines in FIG. 34 and are not exposed.
  • the material of the insulating layer 910 may include silicon dioxide.
  • part of the insulating layer 910 is removed to expose part of the second electrode plate 420 , and the remaining insulating layer 910 covers the first electrode plate 810 .
  • part of the insulating layer 910 above the edge of the second electrode plate 420 is removed to expose part of the second electrode plate 420 , thereby electrically connecting the second electrode plate 420 to other structures.
  • the remaining insulating layer 910 covers the first electrode plates 810 to electrically isolate each of the first electrode plates 810 .
  • the first electrode plate 810 and the dielectric layer 600 are dotted lines in the top view shown in FIG. 34 and are not exposed.
  • a second conductive layer 920 is formed on the second electrode plate 420 and the insulating layer 910 .
  • a second conductive layer 920 is deposited on the first electrode plate 810 and the insulating layer 910.
  • the material of the second conductive layer 920 may include tungsten, silicon germanium (SiGe), or tungsten and germanium A mixture of silicon.
  • the first electrode plate 810 , the dielectric layer 600 , the second electrode plate 420 and the insulating layer 910 are dotted lines in the top view shown in FIG. 38 and are not exposed.
  • the second electrode plate 420 is electrically connected to other structures through the second conductive layer 920 .
  • the M1 metal layer 930 is electrically connected to the second electrode plate 420 through the second conductive layer 920 .
  • the first electrode plate 810 and the conductive column 120 are made of the same material, forming the lower electrode plate 820 as shown in FIG. 40 , the contact area between the lower electrode plate 820 and the capacitive contact pad 110 is increased, and Plate area has also increased.
  • the substrate 100 includes a core area and a peripheral area, a capacitor is formed on the core area of the substrate 100 , and a peripheral circuit is formed on the peripheral area of the substrate 100 .
  • the second conductive layer 920 covers the second electrode plate 420 and the insulating layer 910.
  • the second conductive layer 920 also covers the peripheral region of the substrate 100. Part of the second conductive layer 920 is removed by an etching process, so that the core region and The second conductive layer 920 on the peripheral area of the substrate 100 is disconnected, and peripheral circuits are formed on the peripheral area of the substrate 100 .
  • the second conductive layer 920 may be electrically connected to the M1 metal layer 930 .
  • the memory in the embodiment of the present application includes a substrate 100 and capacitors disposed on the substrate 100 , and the substrate 100 is provided with a plurality of capacitor contact pads 110 arranged at intervals.
  • the capacitive contact pads 110 are exposed on the surface of the substrate 100 so as to be electrically connected with the subsequently formed capacitors.
  • the number of capacitive contact pads 110 can be set in multiples, and the multiple capacitive contact pads 110 are arranged at intervals, and each capacitive contact pad 110 is in contact with one of the multiple capacitors formed subsequently to control the capacitor to read data. or output.
  • the plurality of capacitive contact pads 110 are arranged in an array, for example, the plurality of capacitive contact pads 110 are arranged in a honeycomb shape in the substrate 100 .
  • Each capacitive contact pad 110 is provided with a conductive post 120 .
  • a first groove is formed on the first surface of the capacitive contact pad 110 , and the conductive post 120 is filled in the first groove, as shown in FIGS. 38 and 39 .
  • a first groove is formed on the upper surface of the capacitive contact pad 110 .
  • the upper end surface of the conductive column 120 may be flush with the first surface of the capacitive contact pad 110 , the area of the upper end surface of the conductive column 120 is 1/3-1/2 of the area of the first surface of the capacitive contact pad 110 , and the conductive column 120
  • the height of the capacitor contact pad 110 may be 1/3-2/5 of the height of the capacitive contact pad 110 .
  • a barrier layer 300 is also disposed on the substrate 100 .
  • the material of the barrier layer 300 includes SiBN.
  • the barrier layer 300 can reduce or prevent damage to the substrate 100 in the subsequent fabrication process; on the other hand, the barrier layer 300 has relatively excellent high temperature performance and lower dielectric constant and dielectric loss , the insulation performance is better.
  • the capacitor includes a first plate 810, a second plate 420, and a dielectric layer 600 disposed between the first plate 810 and the second plate 420.
  • the material of the second electrode plate 420 may include titanium nitride
  • the material of the first electrode plate 810 may be selected from a material with good compatibility with the dielectric layer 600 and a high work function.
  • the material of the first electrode plate 810 may include titanium nitride or A mixture of titanium nitride and tungsten.
  • the second electrode plate 420 is provided with a plurality of first hole structures.
  • the plurality of first hole structures correspond to the plurality of capacitive contact pads 110 one-to-one.
  • the orthographic projection of the first hole structures 410 on the substrate 100 covers the capacitive contact pads 110 the first surface, so that there is enough space in the first hole structure 410 for forming the dielectric layer 600 and the first electrode plate 810 .
  • the dielectric layer 600 is disposed on the hole wall of the first hole structure 410 , and the dielectric layer 600 is surrounded by the second hole structure 610 . As shown in FIG. 38 and FIG. 39 , the dielectric layer 600 covers the hole walls of the first hole structure 410 , and the dielectric layer 600 may be a high dielectric constant (High-K) layer, so that the layer has better insulating properties .
  • High-K high dielectric constant
  • the capacitor further includes a protective layer 700 , the protective layer 700 is disposed on the hole wall of the second hole structure 610 , and the protective layer 700 is located in the second hole structure 610 A third hole structure 710 is formed around it.
  • the protective layer 700 may be a conductive material.
  • the material of the protective layer 700 may be the same as the material of the first electrode plate 810 .
  • the third hole structure extends to the substrate 100 to expose the capacitive contact pad 110 . That is, the third hole structure penetrates through the barrier layer 300 , so that the capacitor contact pad 110 is exposed in the third hole structure, so that the first electrode plate 810 in the third hole is in contact with the capacitor contact pad 110 .
  • the first electrode plate 810 is disposed in the second hole structure 610 , and the first electrode plate 810 is electrically connected to the capacitive contact pad 110 , so as to make electrical connection between the capacitor and the capacitive contact pad 110 .
  • the first electrode plates 810 cover the corresponding conductive pillars 120 .
  • the area of the lower end surface of the first electrode plate 810 is 1.5-3 times the area of the corresponding upper end surface of the conductive column 120 .
  • the material of the first electrode plate 810 is the same as that of the conductive column 120 .
  • the first electrode plate 810 and the conductive column 120 are integrated, and as shown in FIG. 40 , the lower electrode plate 820 of the capacitor is formed together.
  • the conductive column 120 in the capacitor contact pad 110 the contact area between the lower plate 820 of the capacitor and the capacitor contact pad 110 is increased, the contact resistance between the capacitor and the capacitor contact pad 110 is reduced, and the storage efficiency is improved and storage speed.
  • this arrangement also increases the plate area of the lower plate 820 of the capacitor.
  • the protective layer 700 surrounds the third hole structure, and the first electrode plate 810 is filled in the third hole structure, that is, the protective layer 700 is disposed between the dielectric layer 600 and the first electrode plate 810 .
  • the number of the first electrode plates 810 is multiple, and each first electrode plate 810 is arranged in a third hole structure, so as to electrically isolate the first electrode plates 810, and each capacitor is interconnected through the second electrode plate 420 .
  • the second electrode plate 420 supports the dielectric layer 600 and the first electrode plate 810 formed later, and the supporting area is large, which facilitates the formation of a capacitor with a large aspect ratio, that is, the stability of the capacitor.
  • the yield of the memory is improved.
  • the capacitor is also provided with an insulating layer 910, the insulating layer 910 covers the first pole plate 810 to ensure insulation between the first pole plates 810, the insulating layer 910 covers part of the second pole plate 420, For example, the insulating layer 910 exposes edge regions of the second electrode plate 420 to electrically connect the second electrode plate 420 with other structures.
  • the insulating layer 910 and the second pole plate 420 are provided with a second conductive layer 920, and the second conductive layer 920 is electrically connected with the second pole plate 420, so as to realize the electrical connection between the second pole plate 420 and other structures, such as with M1
  • the metal layer 930 is electrically connected.
  • the substrate 100 includes a core area and a peripheral area, a capacitor is formed on the core area of the substrate 100 , and a peripheral circuit is formed on the peripheral area of the substrate 100 .
  • the second conductive layer 920 covers the second electrode plate 420 and the insulating layer 910 , the second conductive layer 920 also covers the peripheral area of the substrate 100 , and the second conductive layer 920 forms a peripheral circuit by etching.
  • the memory provided by this embodiment of the present application includes a substrate 100 and a capacitor disposed on the substrate 100 .
  • the substrate 100 is provided with a plurality of capacitive contact pads 110 arranged at intervals, and each capacitive contact pad 110 is provided with a conductive column 120 .
  • the capacitor includes a second electrode plate 420 , a dielectric layer 600 and a first electrode plate 810 , wherein the second electrode plate 420 is provided with a plurality of first hole structures, and the plurality of first hole structures are connected with the plurality of capacitor contact pads 110 .
  • the dielectric layer 600 is arranged on the hole wall of the first hole structure, and the dielectric layer 600 located in the first hole structure is surrounded by a second hole structure; the first electrode plate 810 is arranged in the second hole structure, the first An electrode plate 810 is electrically connected to the capacitor contact pad 110 and covers the corresponding conductive column 120 .
  • the material of the conductive column 120 is the same as that of the first electrode plate 810 .
  • references to the terms “one embodiment,” “some embodiments,” “illustrative embodiments,” “examples,” “specific examples,” or “some examples” and the like are meant to incorporate embodiments A particular feature, structure, material, or characteristic described or exemplified is included in at least one embodiment or example of the present application.
  • schematic representations of the above terms do not necessarily refer to the same embodiment or example.
  • the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

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Abstract

本申请提供一种存储器的制作方法及存储器，涉及存储设备技术领域，用于解决存储速度和存储效率较低的技术问题，该制作方法包括：提供基底，基底内设有多个间隔设置的电容接触垫；在每个电容接触垫的第一表面上形成第一凹槽；在第一凹槽内形成导电柱，导电柱的上端面与电容接触垫的第一表面齐平；在基底上形成多个电容器，多个电容器与多个电容接触垫一一对应且电连接；每个电容器的第一极板覆盖对应的导电柱，且第一极板的材质与导电柱的材质相同。通过在电容接触垫内设置导电柱，且导电柱和第一极板材质相同，增加了导电柱和第一极板作为一个整体与电容接触垫的接触面积，减少电容器与电容接触垫的接触电阻，从而提高存储效率和存储速度。

Description

存储器的制作方法及存储器
本申请要求于2021年04月15日提交中国专利局、申请号为202110406663.3、申请名称为“存储器的制作方法及存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储设备技术领域，尤其涉及一种存储器的制作方法及存储器。
背景技术
随着半导体技术和存储技术不断发展，电子设备不断向小型化、集成化方向发展，动态随机存储器(Dynamic Random Access Memory，简称DRAM)因其具有较高的存储密度以及较快的读写速度被广泛地应用在各种电子设备中。动态随机存储器一般由多个存储单元组成，每个存储单元通常包括晶体管(Transistor)结构和电容(Capacitor)器。电容器存储数据信息，晶体管结构控制电容器中的数据信息的读写。
在动态随机存储器中，电容器通常设置在基底上，且与基底中的电容接触垫电连接，然而，随着尺寸微缩，电容器与电容接触垫之间的接触面积越来越小，接触电阻变大，影响存储器的存储速度和存储效率。
发明内容
第一方面，本申请实施例提供一种存储器的制作方法，其包括：提供基底，所述基底内设有多个间隔设置的电容接触垫；在每个所述电容接触垫的第一表面上形成第一凹槽；在所述第一凹槽内形成导电柱，所述导电柱的上端面与所述电容接触垫的第一表面齐平；在所述基底上形成多个电容器，多个所述电容器与多个所述电容接触垫一一对应且电连接；每个所述电容器的第一极板覆盖对应的所述电容接触垫内的所述导电柱，且所述第一极板的材质与所述导电柱的材质相同。
本申请实施例提供的存储器的制作方法具有如下优点：
本申请实施例提供的存储器的制作方法中，先提供基底，基底内设有多个间隔设置的电容接触垫；在每个电容接触垫的第一表面上形成第一凹槽；在第一凹槽内形成导电柱，导电柱的上端面与电容接触垫的第一表面齐平；在基底上形成多个电容器，多个电容器与多个电容接触垫一一对应且电连接；每个电容器的第一极板覆盖对应的电容接触垫内的导电柱，且第一极板的材质与导电柱的材质相同。通过在电容接触垫内设置导电柱，且导电柱和第一极板的材质相同，从而增加了导电柱和第一极板作为一个整体时与电容接触垫的接触面积，减少了电容器与电容接触垫之间的接触电阻，从而提高存储效率和存储速度。
第二方面，本申请实施例还提供一种存储器，其包括：基底和设置在所述基底上的电容器，所述基底内设有多个间隔设置的电容接触垫，每个所述电容接触垫内设有一个导电柱；所述电容器包括：第二极板，所述第二极板中设置有多个第一孔洞结构，多个所述第一孔洞结构与多个所述电容接触垫一一对应；介电层，所述介电层设在所述第一孔洞结构的孔壁，位于所述第一孔洞结构内的所述介电层围设成第二孔洞结构；第一极板，所述第一极板设置在所述第二孔洞结构中，所述第一极板与所述电容接触垫电连接，且覆盖对应的导电柱，所述导电柱的材质与所述第一极板的材质相同。
本申请实施例提供的存储器具有如下优点：
本申请实施例提供的存储器包括基底和设置在基底上的电容器，基底内设有多个间隔设置的电容接触垫，每个电容接触垫内设有一个导电柱。电容器包括第二极板、介电层和第一极板，其中，第二极板中设置有多个第一孔洞结构，多个第一孔洞结构与多个电容接触垫一一对应；介电层设在第一孔洞结构的孔壁，位于第一孔洞结构内的介电层围设成第二孔洞结构；第一极板设置在第二孔洞结构中，第一极板与电容接触垫电连接，且覆盖对应的导电柱，导电柱的材质与第一极板的材质相同。通过在电容接触垫内设置导电柱，且导电柱和第一极板的材质相同，从而增加了导电柱和第一极板作为一个整体时与电容接触垫的接触面积，减少了电容器与电容接触垫之间的接触电阻，从而提高存储效率和存储速度。
附图说明
图1为本申请实施例中的存储器的制作方法的流程图；
图2为本申请实施例中的基底的俯视图；
图3为本申请实施例中的基底的结构示意图；
图4为本申请实施例中的形成光刻胶层后的俯视图；
图5为本申请实施例中的形成光刻胶层后的结构示意图；
图6为本申请实施例中的形成第一凹槽后的俯视图；
图7为本申请实施例中的形成第一凹槽后的结构示意图；
图8为本申请实施例中的形成第一导电层后的俯视图；
图9为本申请实施例中的形成第一导电层后的结构示意图；
图10为本申请实施例中的形成导电柱后的俯视图；
图11为本申请实施例中的形成导电柱后的结构示意图；
图12为本申请实施例中的形成多个电容器的流程图；
图13为本申请实施例中的形成阻挡层后的俯视图；
图14为本申请实施例中的形成阻挡层后的结构示意图；
图15为本申请实施例中的形成第一电极层后的俯视图；
图16为本申请实施例中的形成第一电极层后的结构示意图；
图17为本申请实施例中的形成预设掩膜板层后的俯视图；
图18为本申请实施例中的形成预设掩膜板层后的结构示意图；
图19为本申请实施例中的形成硬掩膜板层后的俯视图；
图20为本申请实施例中的形成硬掩膜板层后的结构示意图；
图21为本申请实施例中的形成第一孔洞结构后的俯视图；
图22为本申请实施例中的形成第一孔洞结构后的结构示意图；
图23为本申请实施例中的形成介电层后的结构示意图；
图24为本申请实施例中的形成保护层后的俯视图；
图25为本申请实施例中的形成保护层后的结构示意图；
图26为本申请实施例中的暴露阻挡层后的俯视图；
图27为本申请实施例中的暴露阻挡层后的结构示意图；
图28为本申请实施例中的去除部分阻挡层后的俯视图；
图29为本申请实施例中的去除部分阻挡层后的结构示意图；
图30为本申请实施例中的形成第二电极层后的俯视图；
图31为本申请实施例中的形成第二电极层后的结构示意图；
图32为本申请实施例中的形成第一极板后的俯视图；
图33为本申请实施例中的形成第一极板后的结构示意图；
图34为本申请实施例中的形成绝缘层后的俯视图；
图35为本申请实施例中的形成绝缘层后的结构示意图；
图36为本申请实施例中的去除部分绝缘层后的俯视图；
图37为本申请实施例中的去除部分绝缘层后的结构示意图；
图38为本申请实施例中的形成第二导电层后的俯视图；
图39为本申请实施例中的形成第二导电层后的结构示意图；
图40为本申请实施例中的电容器的下极板的结构示意图；
图41为本申请实施例中的形成M1金属层后的结构示意图。
具体实施方式
相关技术中，电容器的第一极板与电容接触垫电连接，通常将第一极板设置在电容接触垫的上方，且第一极板的下端面与电容接触垫的上端面相接触。然而，随着尺寸微缩，第一极板与电容接触垫的接触面积变小，第一极板与电容接触垫的接触电阻变大，导致存储器的存储速度和存储效率较低。
为了提高存储速度和存储效率，本申请实施例提供一种存储器的制作方法，通过在电容接触垫内形成导电柱，且导电柱的上端面与电容接触垫的上端面齐平，再形成电容器，电容器的第一极板覆盖对应的导电柱，且第一极板的材质与导电柱的材质相同，从而增加了导电柱和第一极板作为一个整体时与电容接触垫的接触面积，减少了电容器与电容接触垫的接触电阻，从而提高存储效率和存储速度。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
参照图1，本申请实施例提供一种存储器的制作方法，该制作方法包 括以下步骤：
步骤S101、提供基底，基底内设有多个间隔设置的电容接触垫。
参照图2和图3，基底100作为存储器的支撑部件，用于支撑设在其上的其他部件。基底100内可以设有多个电容接触垫110，多个电容接触垫110间隔设置，多个电容接触垫110在基底100内呈蜂巢状排布。示例性的，如图2所示，多个电容接触垫110中，一个电容接触垫110位于中心，六个电容接触垫110环绕该电容接触垫110设置，且这六个电容接触垫110的中心连线形成正六边形。
电容接触垫110的材质包括钨(W)，以便于后续与电容器电连接。基底100的材质包括氧化硅(SiO2)，以使基底100内的各电容接触垫110之间电气隔离，防止相邻的电容接触垫110之间电连接。当然，电容接触垫110的材质和基底100的材质并不是限定的，例如，电容接触垫110的材质还可以为氮化钛、钨化钛、铝或铜中的一种或者多种。
步骤S102、在每个电容接触垫的第一表面上形成第一凹槽。
参照图4至图11，电容接触垫110的第一表面为电容接触垫110暴露于基底100的表面，即如图4至图11所示的电容接触垫110的上表面。每个电容接触垫110的上表面形成有一个第一凹槽111。示例性的，第一凹槽111可以通过图形化工艺形成，即通过涂胶、曝光、显影、刻蚀、去胶等过程在电容接触垫110上形成所需图形。
在一些可能的示例中，在每个电容接触垫的第一表面上形成第一凹槽的步骤包括：
参照图4和图5，在基底上形成光刻胶层200，光刻胶层200具有第一图案。如图4和图5所示，光刻胶层200具有贯穿该层第四孔洞结构，第四孔洞结构暴露出电容接触垫110。
如图4所示的俯视图中，虚线所示的圆形表示电容接触垫110的第一表面的边缘，第四孔洞结构的孔洞面积小于对应的电容接触垫110的第一表面的面积，使得电容接触垫110的中心区域暴露出来，电容接触垫110的边缘区域未暴露出来。即光刻胶层200覆盖电容接触垫110的第一表面的边缘区域和基底100，以便于在电容接触垫110的第一表面上形成第一凹槽111。
参照图6和图7，形成光刻胶层200后，沿第一图案刻蚀电容接触垫 110，在电容接触垫110的第一表面上形成第一凹槽111。如图6和图7所示，刻蚀去除部分电容接触垫110，以形成第一凹槽111。示例性的，第一凹槽111的开口面积可以为电容接触垫110的第一表面的面积的1/3-1/2，其中，第一凹槽111的开口面积是指第一凹槽111的开口端的面积，即图6和图7所示的第一凹槽111的上端的开口面积。
第一凹槽111的深度可以为电容接触垫110的厚度的1/3-2/3。其中，第一凹槽111的深度是指第一凹槽111的槽底与第一凹槽111的开口端的距离，电容接触垫110的厚度是指电容接触垫110的第一表面和与第一表面相对的第二表面之间的距离。即第一凹槽111的深度和电容接触垫110的厚度均指图7所示的竖直方向(Y方向)的尺寸。
在电容接触垫110的第一表面上形成第一凹槽111之后，去除光刻胶层200。示例性的，光刻胶层200可以通过灰化(Ashing)工艺等去除，去除光刻胶层200后，基底100暴露出来。
步骤S103、在第一凹槽内形成导电柱，导电柱的上端面与电容接触垫的第一表面齐平。
参照图8至图11，在第一凹槽111内沉积形成导电柱120，导电柱120填充于第一凹槽111，导电柱120的上端面与电容接触垫110的第一表面齐平，以使图11所示的结构上表面平整。
在一些可能的示例中，在第一凹槽内形成导电柱，导电柱的上端面与电容接触垫的第一表面齐平的步骤包括：
在第一凹槽111内和基底100上沉积导电材料，形成第一导电层130。参照图8和图9，第一导电层130填充于第一凹槽111内且覆盖在基底100上。如图8所示的俯视图中，电容接触垫110和第一凹槽111未显露，位于外侧的虚线所示的圆形为电容接触垫110的第一表面的边缘，位于内侧的虚线所示的圆形为第一凹槽111的边缘。
参照图10和图11，形成第一导电层130，去除位于基底100上的第一导电层130，保留的第一导电层130形成多个导电柱120。如图10和图11所示，每个电容接触垫110内形成有一个导电柱120。示例性的，位于基底100上的第一导电层130可以通过化学机械研磨(Chemical-Mechanical Polishing，简称CMP)去除。
步骤S104、在基底上形成多个电容器，多个电容器与多个电容接触垫 一一对应且电连接；每个电容器的第一极板覆盖对应的电容接触垫内的导电柱，且第一极板的材质与导电柱的材质相同。
在基底100上形成多个电容器，多个电容器与多个电容接触垫110一一对应且电连接。可以理解的是，电容器与电容接触垫110的数量相等，每个电容接触垫110连接一个电容器。每个电容器的第一极板覆盖相对应的电容接触垫110内导电柱120，且第一极板的材质与导电柱120的材质相同。第一极板的下端面的面积可以为对应的导电柱120的上端面的面积的1.5-3倍。
如此设置，第一极板与导电柱120形成一个整体，共同形成电容器的下极板，导电柱120设置在第一接触垫内，第一极板810与导电柱120所形成的整体与第一接触垫的接触面积增大，即电容器的下极板与第一接触垫的接触面积增大，从而减少了电容器与第一接触垫的接触电阻，提高存储器的存储速度和存储效率。
本申请实施例提供的存储器的制作方法中，提供基底100，基底100内设有多个间隔设置的电容接触垫110；在每个电容接触垫110的第一表面上形成第一凹槽111；在第一凹槽111内形成导电柱120，导电柱120的上端面与电容接触垫110的第一表面齐平；在基底100上形成多个电容器，多个电容器与多个电容接触垫110一一对应且电连接；每个电容器的第一极板覆盖对应的电容接触垫110内的导电柱120，且第一极板的材质与导电柱120的材质相同。通过在电容接触垫110内设置导电柱120，且导电柱120和第一极板的材质相同，从而增加了导电柱120和第一极板作为一个整体时与电容接触垫110的接触面积，减少了电容器与电容接触垫110的接触电阻，从而提高存储效率和存储速度。
参照图12至图33，本申请实施例中，在基底上形成多个电容器，多个电容器与多个电容接触垫一一对应且电连接的步骤可以包括：
步骤S1041、在基底上形成阻挡层，阻挡层覆盖基底、电容接触垫和导电柱。
参照图13和图14，阻挡层300可以通过沉积工艺形成在基底100上。示例性的，阻挡层300通过化学气相沉积(Chemical Vapor Deposition，简称CVD)工艺、物理气相沉积(Physical Vapor Deposition，简称PVD)工艺或者原子层沉积(Atomic Layer Deposition，简称ALD)工艺等形成在 基底100上。
阻挡层300的材质包括SiBN，该层可以用作刻蚀阻挡层，以减少或者防止后续制作过程中损伤基底100。此外，阻挡层300具有较为优异的高温性能和较低的介电常数及介电损耗，绝缘性能较好，以提高存储器的性能。
需要说明的是，参照图13，图13为本申请实施例中的形成阻挡层300后的俯视图，阻挡层300覆盖基底100、电容接触垫110和导电柱120，因此电容接触垫110和导电柱120为图13中虚线所示的圆形，位于外侧的圆形为电容接触垫110的第一表面的边缘，位于内侧的圆形为导电柱120的边缘，即导电柱120位于电容接触垫110内。
步骤S1042、在阻挡层上形成第二极板，第二极板形成有多个第一孔洞结构，多个第一孔洞结构与多个电容接触垫一一对应。
参照图15至图22，第二极板420形成有多个第一孔洞结构410，多个第一孔洞结构410贯穿第二极板420，第一孔洞结构410可以通过光刻及刻蚀工艺形成。可以理解的是，第二极板420为电容器的上极板。
多个第一孔洞结构410与多个电容接触垫110一一对应，可以理解的是，第一孔洞结构410与电容接触垫110的数量相同，且一个第一孔洞结构410对应一个电容接触垫110，例如，第一孔洞结构410位于相对应的电容接触垫110的正上方。
第一孔洞结构410的尺寸可以大于电容接触垫110的第一表面的尺寸，例如，第一孔洞结构410在基底100上的正投影覆盖电容接触垫110的第一表面，便于后续在第一孔洞结构410内形成介电层600和第二极板420。
在一些可能的示例中，在阻挡层上形成第二极板，第二极板形成有多个第一孔洞结构，多个第一孔洞结构与多个电容接触垫一一对应的步骤可以包括：
在阻挡层300上形成第一电极层400。参照15和图16，第一电极层400可以通过沉积工艺形成在阻挡层300上，即第一电极层400覆盖阻挡层300，第一电极层400的材质可以包括氮化钛(TiN)。
形成第一电极层100之后，在第一电极层100上形成硬掩模板层520，硬掩模板层520中形成有多个刻蚀孔510，多个刻蚀孔510与多个电容接触垫110一一对应。参照图17至图20，硬掩模板层520中形成有多个刻 蚀孔510，刻蚀孔510贯穿硬掩模板层520，且多个刻蚀孔510与多个电容接触垫110一一对应。
示例性的，参照图17和图18，先在第一电极层400上沉积预设掩膜板层500；再参照图19和图20，对预设掩膜板层500进行刻蚀，以形成刻蚀孔510，具有刻蚀孔510的预设掩膜板层500即为硬掩模板层520。
刻蚀孔510可以通过自对准双图形(Self-aligned Double Patterning，简称SADP)工艺、自对准四重图案(Self-aligned Quadruple Patterning)工艺或者EUV(Extreme Ultraviolet)光刻工艺形成。如图19所示的俯视图中，第一电极层400暴露在刻蚀孔510内，电容接触垫110和导电柱120仍如图19中虚线所示，并未显露。
形成硬掩模板层520，沿刻蚀孔510刻蚀第一电极层400，以形成第一孔洞结构410。参照图21和图22，以硬掩模板层520为掩膜，对第一电极层400进行刻蚀，以在第一电极层400中形成第一孔洞结构410。
通过刻蚀工艺，将硬掩模板层520上的图形传递到第一电极层400，形成具有第一孔洞结构410的第二极板420。如图21所示的俯视图中，部分阻挡层300显露，电容接触垫110和导电柱120仍如图21中虚线所示，并未显露。如此设置，第二极板420可以一次刻蚀形成，各电容器通过第二极板420互连。通过先形成第二极板420，第二极板420对后续形成的介电层600和第一极板810进行支撑，支撑面积较大，便于形成深宽比较大的电容器，即电容器的稳定性较好，提高存储器的良率。
形成第一孔洞结构410之后，去除硬掩模板层520。如图21图22所示，硬掩模板已经去除，第二极板420暴露，以便于在第二极板420的上表面和侧表面形成介电层600。
步骤S1043、在第一孔洞结构的孔壁上形成介电层，介电层围设成第二孔洞结构，且第二孔洞结构延伸至电容接触垫。
参照图23至图29，第一孔洞结构410的孔壁上形成有介电层600，介电层600可以为高介电常数层，以使该层具有较好的绝缘性能。位于第一孔洞结构410内的介电层600围设成第二孔洞结构610，且第二孔洞结构610延伸至电容接触垫110。即第二孔洞结构610还贯穿阻挡层300，以在第二孔洞结构610内暴露电容接触垫110和导电柱120。
在一些可能的示例中，参照图23，在第一孔洞结构的孔壁上形成介电 层的步骤可以包括：
在第一孔洞结构410的孔壁和孔底、以及第二极板420上沉积形成介电层600，位于第一孔洞结构410内的介电层600围设成第二孔洞结构610。在介电层600的形成过程中，第二极板420对介电层600进行支撑，支撑面积较大，有利于增大介电层600的沉积面积和提高介电层600的沉积质量。
形成介电层600后，保留位于第一孔洞结构410的孔壁的介电层600，去除其余的介电层600，第二孔洞结构610暴露出阻挡层300。可以理解的是，去除位于第二极板420背离基底100的表面上的介电层600，以及位于第二孔洞结构610的孔底的介电层600，保留位于第一孔洞结构410的孔壁的介电层600。
保留位于第一孔洞结构410的孔壁的介电层600，去除其余的介电层600之后，去除部分阻挡层300，以在第二孔洞结构610暴露出电容接触垫110和导电柱120。示例性的，沿第二孔洞结构610刻蚀阻挡层300，以使第二孔洞结构610贯穿阻挡层300，延伸至电容接触垫110。
在另一些可能的示例中，参照图24至图29，在第一孔洞结构410的孔壁上形成介电层600的步骤可以包括：
参照图24和图25，在第一孔洞结构410的孔壁和孔底、以及第二极板420上沉积形成介电层600，位于第一孔洞结构410内的介电层600围设成第二孔洞结构610。如图24和图25所示，介电层600覆盖第二极板420。
继续参照图24和图25，形成介电层600之后，在介电层600上沉积形成保护层700，位于第二孔洞结构610内的保护层700围设成第三孔洞结构710。如图24和图25所示，保护层700覆盖介电层600，保护层700的材质可以为导电材料，示例性的，保护层700的材质可以与后续形成的第一极板810的材质相同，即保护层700和第一极板810共同形成电容器的下极板。
需要说明的是，参照图24所示的形成保护层700后的俯视图，四个依次套设的圆形中，最外侧的虚线所示的圆形为第二极板420的边缘，次外侧的虚线所示的圆形为介电层600的边缘，最内侧的虚线所示的圆形为导电柱120的边缘，次内侧的虚线所示的圆形为电容接触垫110的第一表面 的边缘，第三孔洞结构710未在该俯视图中标出。
参照图26和图27，形成保护层700后，去除位于第三孔洞结构710的孔底，以及位于第二极板420上的保护层700和介电层600，第三孔洞结构710暴露出阻挡层300。如图26和图27所示，沿第三孔洞结构710刻蚀保护层700和介电层600，以使第三孔洞结构710中暴露阻挡层300。刻蚀第三孔洞结构710的孔底的保护层700和介电层600的同时，还刻蚀位于第二极板420背离基底100的表面上的保护层700和介电层600，以暴露第二极板420。
需要说明的是，参照图26所示的俯视图，第二极板420显露，位于最外侧的实线所示的圆形为第二极板420的边缘，次外侧的实线所示的圆形为介电层600的边缘，最内侧的实线所示的圆形为保护层700的边缘。即位于最外侧的实线所示的圆形和位次外侧的实线所示的圆形之间为介电层600，位于次外侧的实线所示的圆形和位于内侧的实线所示的圆形之间为保护层700，保护层700覆盖电容接触垫110和导电柱120，即电容接触垫110和导电柱120如图26中虚线所示的圆形，并未显露。
参照图28和图29，暴露出阻挡层300之后，去除部分阻挡层300，以在第三孔洞结构710暴露出电容接触垫110和导电柱120。如图28和图29所示，沿第三孔洞结构710刻蚀阻挡层300，以暴露电容接触垫110和导电柱120。即第三孔洞结构710贯穿阻挡层300且延伸至电容接触垫110。
步骤S1044、在第二孔洞结构中形成第一极板，第一极板与电容接触垫电连接，且覆盖导电柱。
参照图30至图33，第一极板810为导电材质且与电容接触垫110相接触，以实现第一极板810与电容接触垫110之间的电连接。第一极板810形成在第二孔洞结构610中，第一极板810无支撑强度的要求，可以选用与介电层600兼容性好、功函数高的材料。示例性的，第一极板810的材质可以包括氮化钛(TiN)或者氮化钛与钨的混合物。
第一极板810覆盖导电柱120，示例性的，第一极板810的下端面的面积为对应的导电柱120的上端面的面积的1.5-3倍。第一极板810材质与导电柱120的材质相同，形成第一极板810后，第一极板810和导电柱120为一个整体，共同形成电容器的下极板。通过将导电柱120形成在电容接触垫110内，增加了电容器的下极板与电容接触垫110的接触面积， 减小了电容器与电容接触垫110之间的接触电阻，从而提高了存储效率和存储速度。此外，如此设置也增大了电容器的下极板的极板面积。
当介电层600上形成有保护层700时，在第二孔洞结构610中形成第一极板810的步骤可以具体包括：
参照图30和图31，在第三孔洞结构710中、保护层700上、介电层600上和第二极板420上形成第二电极层800，第二电极层800与电容接触垫110相接触。如图30和图31所示，第二电极层800填充于第三孔洞结构710中且覆盖第一极板810、保护层700和介电层600。
参照图32和图33，形成第二电极层800后，去除位于介电层600上和第二极板420上的第二电极层800，保留的第二电极层800形成第一极板810。
如图32和图33所示，保留位于第三孔洞结构710中的第二电极层800，保留下来的第二电极层800形成第一极板810，第一极板810的数量为多个，每个第三孔洞结构710内形成有一个第一极板810。示例性的，第二电极层800可以通过刻蚀工艺去除，即通过沉积第二电极层800并回刻以形成多个分离的第一极板810。
需要说明的是，参照图34至图40，在基底100上形成多个电容器，多个电容器与多个电容接触垫110一一对应且电连接的步骤之后，还包括：
参照图34和图35，在第二极板420、介电层600和第一极板810上形成绝缘层910。绝缘层910覆盖第一极板810、介电层600和第二极板420，第一极板810、介电层600和第二极板420为图34中虚线所示，并未显露。绝缘层910的材质可以包括二氧化硅。
参照图36和图37，形成绝缘层910后，去除部分绝缘层910，以暴露部分第二极板420，保留的绝缘层910覆盖第一极板810。如图36和图37所示，去除第二极板420边缘上方的部分绝缘层910，以暴露部分第二极板420，从而将第二极板420与其他结构电连接。保留的绝缘层910覆盖第一极板810，以使各第一极板810之间电隔离。第一极板810和介电层600为图34所示的俯视图的虚线，并未显露。
参照图38和图39，去除部分绝缘层910后，在第二极板420和绝缘层910上形成第二导电层920。如图38和图39所示，在第一极板810和绝缘层910上沉积形成第二导电层920，第二导电层920的材质可以包括 钨、锗化硅(SiGe)或者钨和锗化硅的混合物。第一极板810、介电层600、第二极板420和绝缘层910为图38所示的俯视图的虚线，并未显露。通过第二导电层920将第二极板420与其他结构电连接，例如，如图41所示，通过第二导电层920实现M1金属层930与第二极板420电连接。
参照图40，第一极板810与导电柱120的材质相同，其形成如图40所示的下极板820，下极板820与电容接触垫110的接触面积增加，且下极板820的极板面积也有所增加。
需要说明的是，参照图41，基底100包括核心区和外围区，基底100的核心区上形成有电容器，基底100的外围区上形成有外围电路。第二导电层920覆盖第二极板420和绝缘层910，第二导电层920还覆盖基底100的外围区，通过刻蚀工艺去除部分第二导电层920，以将位于基底100的核心区和基底100的外围区上的第二导电层920断开，并在基底100的外围区上形成外围电路。第二导电层920可以电连接M1金属层930。
参照图38至图41，本申请实施例中的存储器包括基底100和设置在基底100上的电容器，基底100内设有多个间隔设置的电容接触垫110。电容接触垫110暴露于基底100表面，以便与后续形成的电容器电连接。
电容接触垫110的数量可以设置有多个，多个电容接触垫110间隔设置，每个电容接触垫110与后续形成的多个电容器中的一个电容器相接触，以控制该电容器进行数据的读入或者输出。多个电容接触垫110呈阵列排布，例如，多个电容接触垫110在基底100内呈蜂巢状排布。
每个电容接触垫110内设有一个导电柱120，示例性的，电容接触垫110的第一表面形成有第一凹槽，导电柱120填充于第一凹槽中，如图38和图39所示，电容接触垫110的上表面上形成有第一凹槽。导电柱120的上端面可以与电容接触垫110的第一表面齐平，导电柱120的上端面的面积为电容接触垫110的第一表面的面积的1/3-1/2，导电柱120的高度可以为电容接触垫110的高度的1/3-2/5。
基底100上还设置有阻挡层300。阻挡层300的材质包括SiBN，一方面，阻挡层300可以减少或者防止后续制作过程中损伤基底100；另一方面，阻挡层300具有较为优异的高温性能和较低的介电常数及介电损耗，绝缘性能较好。
继续参照图38和图39，电容器包括第一极板810、第二极板420，以 及设置在第一极板810和第二极板420之间的介电层600。第二极板420的材质可以包括氮化钛，第一极板810可以选用与介电层600兼容性好、功函数高的材料，例如，第一极板810的材质可以包括氮化钛或者氮化钛和钨的混合物。
第二极板420中设置有多个第一孔洞结构，多个第一孔洞结构与多个电容接触垫110一一对应，第一孔洞结构410在基底100上的正投影覆盖电容接触垫110的第一表面，以使第一孔洞结构410中有足够的空间用于形成介电层600和第一极板810。
介电层600设置在第一孔洞结构410的孔壁，介电层600围设成第二孔洞结构610。如图38和图39所示，介电层600覆盖第一孔洞结构410的孔壁，介电层600可以为高介电常数(High-K)层，以使该层具有较好的绝缘性能。
在一种可能的示例中，如图38和图39所示，电容器还包括保护层700，保护层700设置在第二孔洞结构610的孔壁，且位于第二孔洞结构610内的保护层700围设成第三孔洞结构710。保护层700可以为导电材料，示例性的，保护层700的材质可以与第一极板810的材质相同。
第三孔洞结构延伸至基底100，以暴露电容接触垫110。即第三孔洞结构贯穿阻挡层300，从而使得电容接触垫110暴露在第三孔洞结构中，以使第三孔洞内的第一极板810与电容接触垫110接触。
第一极板810设置在第二孔洞结构610中，第一极板810与电容接触垫110电连接，以使电容器与电容接触垫110之间的电连接。第一极板810覆盖对应的导电柱120。
示例性的，第一极板810的下端面的面积为对应的导电柱120的上端面的面积的1.5-3倍。第一极板810材质与导电柱120的材质相同，形成第一极板810后，第一极板810和导电柱120为一个整体，如图40所示共同形成电容器的下极板820。通过将导电柱120形成在电容接触垫110内，增加了电容器的下极板820与电容接触垫110的接触面积，减小了电容器与电容接触垫110之间的接触电阻，从而提高了存储效率和存储速度。此外，如此设置也增大了电容器的下极板820的极板面积。
当电容器包括保护层700时，保护层700围设层第三孔洞结构，第一极板810填充在第三孔洞结构中，即保护层700设置在介电层600和第一 极板810之间。
第一极板810的数量为多个，每个第一极板810设置在一个第三孔洞结构中，以使各第一极板810之间电隔离，各个电容器通过第二极板420互连。通过先形成第二极板420，第二极板420对后续形成的介电层600和第一极板810进行支撑，支撑面积较大，便于形成深宽比较大的电容器，即电容器的稳定性较好，提高存储器的良率。
如图38和图39所示，电容器上还设置有绝缘层910，绝缘层910覆盖第一极板810，以保证第一极板810之间绝缘，绝缘层910覆盖部分第二极板420，例如，绝缘层910暴露第二极板420的边缘区域，以使第二极板420与其他结构电连接。
绝缘层910和第二极板420上设置有第二导电层920，第二导电层920与第二极板420之间电连接，以实现第二极板420与其他结构电连接，例如与M1金属层930电连接。
需要说明的是，参照图41，基底100包括核心区和外围区，基底100的核心区上形成有电容器，基底100的外围区上形成有外围电路。第二导电层920覆盖第二极板420和绝缘层910，第二导电层920还覆盖基底100的外围区，第二导电层920通过刻蚀形成外围电路。
本申请实施例提供的存储器包括基底100和设置在基底100上的电容器，基底100内设有多个间隔设置的电容接触垫110，每个电容接触垫110内设有一个导电柱120。电容器包括第二极板420、介电层600和第一极板810，其中，第二极板420中设置有多个第一孔洞结构，多个第一孔洞结构与多个电容接触垫110一一对应；介电层600设在第一孔洞结构的孔壁，位于第一孔洞结构内的介电层600围设成第二孔洞结构；第一极板810设置在第二孔洞结构中，第一极板810与电容接触垫110电连接，且覆盖对应的导电柱120，导电柱120的材质与第一极板810的材质相同。通过在电容接触垫110内设置导电柱120，且导电柱120和第一极板810的材质相同，从而增加了导电柱120和第一极板810作为一个整体时与电容接触垫110的接触面积，即增加了电容器的下极板820与电容接触垫110的接触面积，减少了电容器与电容接触垫110之间的接触电阻，从而提高存储效率和存储速度。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点 说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (17)

  1. 一种存储器的制作方法，其中，包括：
    提供基底，所述基底内设有多个间隔设置的电容接触垫；
    在每个所述电容接触垫的第一表面上形成第一凹槽；
    在所述第一凹槽内形成导电柱，所述导电柱的上端面与所述电容接触垫的第一表面齐平；
    在所述基底上形成多个电容器，多个所述电容器与多个所述电容接触垫一一对应且电连接；每个所述电容器的第一极板覆盖对应的所述电容接触垫内的所述导电柱，且所述第一极板的材质与所述导电柱的材质相同。
  2. 根据权利要求1所述的存储器的制作方法，其中，所述第一凹槽的开口面积为所述电容接触垫的第一表面的面积的1/3-1/2。
  3. 根据权利要求1所述的存储器的制作方法，其中，所述第一凹槽的深度为所述电容接触垫的厚度的1/3-2/5。
  4. 根据权利要求1所述的存储器的制作方法，其中，所述第一极板的下端面的面积为对应的所述导电柱的上端面的面积的1.5-3倍。
  5. 根据权利要求1所述的存储器的制作方法，其中，在所述第一凹槽内形成导电柱的步骤包括：
    在所述第一凹槽内和所述基底上沉积导电材料，形成第一导电层；
    去除位于所述基底上的所述第一导电层，保留的所述第一导电层形成多个所述导电柱。
  6. 根据权利要求5所述的存储器的制作方法，其中，通过化学机械研磨去除位于所述基底上的所述第一导电层。
  7. 根据权利要求1所述的存储器的制作方法，其中，在每个所述电容接触垫的第一表面上形成第一凹槽的步骤包括：
    在所述基底上形成光刻胶层，所述光刻胶层具有第一图案；
    沿所述第一图案刻蚀所述电容接触垫，在所述电容接触垫的第一表面上形成所述第一凹槽；
    去除所述光刻胶层。
  8. 根据权利要求1所述的存储器的制作方法，其中，在所述基底上形成多个电容器，多个所述电容器与多个所述电容接触垫一一对应且电连接 的步骤包括：
    在所述基底上形成阻挡层，所述阻挡层覆盖所述基底、所述电容接触垫和所述导电柱；
    在所述阻挡层上形成第二极板，所述第二极板形成有多个第一孔洞结构，多个所述第一孔洞结构与多个所述电容接触垫一一对应；
    在所述第一孔洞结构的孔壁上形成介电层，所述介电层围设成第二孔洞结构，且所述第二孔洞结构延伸至所述电容接触垫；
    在所述第二孔洞结构中形成第一极板，所述第一极板与所述电容接触垫电连接，且覆盖所述导电柱。
  9. 根据权利要求8所述的存储器的制作方法，其中，在所述阻挡层上形成第二极板，所述第二极板形成有多个第一孔洞结构，多个所述第一孔洞结构与多个所述电容接触垫一一对应的步骤包括：
    在所述阻挡层上形成第一电极层；
    在所述第一电极层上形成硬掩模板层，所述硬掩模板层中形成有多个刻蚀孔，多个所述刻蚀孔与多个所述电容接触垫一一对应；
    沿所述刻蚀孔刻蚀所述第一电极层，以形成所述第一孔洞结构；
    去除所述硬掩模板层。
  10. 根据权利要求8所述的存储器的制作方法，其中，在所述第一孔洞结构的孔壁上形成介电层，所述介电层围设成第二孔洞结构，且所述第二孔洞结构延伸至所述电容接触垫的步骤包括：
    在所述第一孔洞结构的孔壁和孔底、以及所述第二极板上沉积所述介电层，位于所述第一孔洞结构内的所述介电层围设成所述第二孔洞结构；
    保留位于所述第一孔洞结构的孔壁的所述介电层，去除其余的所述介电层，所述第二孔洞结构暴露出所述阻挡层；
    去除部分所述阻挡层，以在所述第二孔洞结构中暴露出所述电容接触垫和所述导电柱。
  11. 根据权利要求8所述的存储器的制作方法，其中，在所述第一孔洞结构的孔壁上形成介电层，所述介电层围设成第二孔洞结构，且所述第二孔洞结构延伸至所述电容接触垫的步骤包括：
    在所述第一孔洞结构的孔壁和孔底、以及所述第二极板上沉积所述介电层，位于所述第一孔洞结构内的所述介电层围设成所述第二孔洞结构；
    在所述介电层上沉积保护层，位于所述第二孔洞结构内的所述保护层围设成第三孔洞结构；
    去除位于所述第三孔洞结构孔底的所述保护层和所述介电层，并去除位于所述第二极板上的所述保护层和所述介电层，以使所述第三孔洞结构暴露出所述阻挡层；
    去除部分所述阻挡层，以在所述第三孔洞结构中暴露出所述电容接触垫和所述导电柱。
  12. 根据权利要求11所述的存储器的制作方法，其中，在所述第二孔洞结构中形成第一极板，所述第一极板与所述电容接触垫电连接，且覆盖所述导电柱的步骤包括：
    在所述第三孔洞结构中、所述保护层上、所述介电层上和所述第二极板上形成第二电极层，所述第二电极层与所述电容接触垫相接触；
    去除位于所述介电层上和所述第二极板上的所述第二电极层，保留的所述第二电极层形成所述第一极板。
  13. 根据权利要求8所述的存储器的制作方法，其中，在所述基底上形成多个电容器，多个所述电容器与多个所述电容接触垫一一对应且电连接的步骤之后，还包括：
    在所述第二极板、所述介电层和所述第一极板上形成绝缘层；
    去除部分所述绝缘层，以暴露部分所述第二极板，保留的所述绝缘层覆盖所述第一极板；
    在所述第二极板和所述绝缘层上形成第二导电层。
  14. 一种存储器，其中，所述存储器包括基底和设置在所述基底上的电容器，所述基底内设有多个间隔设置的电容接触垫，每个所述电容接触垫内设有一个导电柱；
    所述电容器包括：第二极板，所述第二极板中设置有多个第一孔洞结构，多个所述第一孔洞结构与多个所述电容接触垫一一对应；
    介电层，所述介电层设在所述第一孔洞结构的孔壁，位于所述第一孔洞结构内的所述介电层围设成第二孔洞结构；
    第一极板，所述第一极板设置在所述第二孔洞结构中，所述第一极板与所述电容接触垫电连接，且覆盖对应的导电柱，所述导电柱的材质与所述第一极板的材质相同。
  15. 根据权利要求14所述的存储器，其中，所述电容器还包括保护层，所述保护层设置在所述介电层和所述第一极板之间。
  16. 根据权利要求14所述的存储器，其中，所述第一极板的下端面的面积为对应的所述导电柱的上端面的面积的1.5-3倍。
  17. 根据权利要求14所述的存储器，其中，所述导电柱的上端面的面积为所述电容接触垫的第一表面的面积的1/3-1/2。
PCT/CN2021/109361 2021-04-15 2021-07-29 存储器的制作方法及存储器 WO2022217785A1 (zh)

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