WO2022037038A1 - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
WO2022037038A1
WO2022037038A1 PCT/CN2021/079626 CN2021079626W WO2022037038A1 WO 2022037038 A1 WO2022037038 A1 WO 2022037038A1 CN 2021079626 W CN2021079626 W CN 2021079626W WO 2022037038 A1 WO2022037038 A1 WO 2022037038A1
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Prior art keywords
interlayer insulating
insulating layer
layer
contact structure
contact
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PCT/CN2021/079626
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English (en)
French (fr)
Inventor
赵亮
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长鑫存储技术有限公司
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Priority to EP21773267.6A priority Critical patent/EP3985723A4/en
Priority to US17/386,017 priority patent/US12114477B2/en
Publication of WO2022037038A1 publication Critical patent/WO2022037038A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Definitions

  • the present invention relates to a semiconductor device and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • the substrate includes a cell region and a peripheral region;
  • a first interlayer insulating layer and a second interlayer insulating layer are formed on the substrate of the cell region and the peripheral region, and the first interlayer insulating layer and the second interlayer insulating layer are along the spaced apart in a direction perpendicular to the substrate;
  • a columnar capacitor array comprising columnar capacitors arranged at intervals, the columnar capacitors being formed in the first interlayer insulating layer and the second interlayer insulating layer in the cell region;
  • a contact structure is formed in the first interlayer insulating layer and the second interlayer insulating layer in the peripheral region.
  • a method of forming a semiconductor device comprising:
  • a substrate including a cell region and a peripheral region
  • a first interlayer insulating layer and a second interlayer insulating layer are formed on the substrate, and the first interlayer insulating layer and the second interlayer insulating layer are arranged at intervals along a direction perpendicular to the substrate ;
  • a columnar capacitor array is formed in the first interlayer insulating layer and the second interlayer insulating layer in the unit region, and the columnar capacitor array includes columnar capacitors arranged at intervals.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment
  • FIG. 2 is a schematic top view of a first electrode layer and a peripheral structure according to an embodiment
  • FIG. 3 is a schematic cross-sectional view of a semiconductor device according to another embodiment
  • FIG. 4 is a flowchart of a method for forming a semiconductor device according to an embodiment
  • FIG. 5 is a flowchart of a method for forming a semiconductor device according to another embodiment
  • FIG. 6 is a schematic cross-sectional view of the semiconductor device after step S310;
  • step S320 is a schematic cross-sectional view of the semiconductor device after step S320;
  • step S330 is a schematic cross-sectional view of the semiconductor device after the contact metal layer is formed in step S330;
  • step S330 is a schematic cross-sectional view of the semiconductor device after step S330;
  • step S340 is a schematic cross-sectional view of the semiconductor device after step S340;
  • step S350 is a schematic cross-sectional view of the semiconductor device after step S350;
  • step S370 is a schematic cross-sectional view of the semiconductor device after step S370;
  • step S511 is a schematic cross-sectional view of the semiconductor device after step S511;
  • step S512 is a schematic cross-sectional view of the semiconductor device after step S512;
  • step S400 is a schematic cross-sectional view of the semiconductor device after step S400;
  • step S500 is a schematic cross-sectional view of the semiconductor device after step S500;
  • step S420 is a schematic cross-sectional view of the semiconductor device after step S420;
  • FIG. 19 is a schematic top view of a cell region of the semiconductor device of FIG. 18;
  • FIG. 20 is a schematic cross-sectional view of the semiconductor device after step S610.
  • the size of the columnar capacitors in the dynamic random access memory is also constantly shrinking. Therefore, the current device structure and wiring density are low, which can no longer meet the increasing integration requirements.
  • the semiconductor device includes a substrate (not shown), a first interlayer insulating layer 741 , a second interlayer insulating layer 742 , Columnar capacitor array 200 and contact structure 700 .
  • the substrate includes a cell region 100A and a peripheral region 100B, and the material of the substrate may be monocrystalline silicon, polycrystalline silicon, silicon-on-insulator (SOI), etc., or other materials known to those skilled in the art.
  • the cell region 100A and the peripheral region 100B may be isolated by a shallow trench isolation structure (not shown) in the substrate to prevent leakage current and other phenomena, thereby improving the reliability of the semiconductor device.
  • the first interlayer insulating layer 741 and the second interlayer insulating layer 742 are formed on the substrates of the cell region 100A and the peripheral region 100B, and the first interlayer insulating layer 741 and the second interlayer insulating layer 742 are formed along a direction parallel to the substrate. Orientation spaced.
  • the materials of the first interlayer insulating layer 741 and the second interlayer insulating layer 742 may be low-K dielectrics, and the low-K dielectrics refer to dielectric materials with a dielectric constant or equal to 4, such as silicon oxide or the like.
  • a support layer 750 may also be formed on the surface of the first interlayer insulating layer 741 and/or the surface of the second interlayer insulating layer 742, and the extension direction of the support layer 750 is parallel to the direction of the surface of the substrate, so as to be the first An interlayer insulating layer 741 and a second interlayer insulating layer 742 provide support.
  • the thicknesses of the first interlayer insulating layer 741 and the second interlayer insulating layer 742 define the height of the support layer 750 to be formed subsequently. Therefore, the thicknesses of the first interlayer insulating layer 741 and the second interlayer insulating layer 742 can be determined according to The height position of the supporting layer 750 to be formed is adjusted.
  • the columnar capacitor array 200 includes the columnar capacitors arranged at intervals, and the columnar capacitors are formed in the first interlayer insulating layer 741 and the second interlayer insulating layer 742 in the cell region 100A.
  • the columnar capacitor array 200 is used for storing data, so as to realize the data storage function of the memory.
  • the contact structure 700 is formed in the first interlayer insulating layer 741 and the second interlayer insulating layer 742 in the peripheral region 100B.
  • the first interlayer insulating layer 741 and the second interlayer insulating layer 742 extend to cover the entire surface of the peripheral region 100B, thereby completely covering the contact structure 700 .
  • the connection path of the contact structure 700 can be effectively shortened, thereby effectively utilizing the space of the columnar capacitor array 200, Further, the arrangement density of each structure in the semiconductor device is increased, and the integration degree of the semiconductor device is improved.
  • the contact structure 700 includes a first contact structure 720 and a second contact structure 730 which are interconnected, and the first contact structure 720 or the second contact structure 730 penetrates through the first interlayer insulating layer 741 or the second layer
  • the inter-insulating layer 742 realizes interconnection.
  • the materials of the first contact structure 720 and the second contact structure 730 may be conductive metal materials such as tungsten, and the materials of the first contact structure 720 and the second contact structure 730 may be the same or different.
  • an intermediate metal layer 710 is formed on the side of the first interlayer insulating layer 741 away from the substrate, and the surface of the intermediate metal layer 710 is flush with the surface of the first interlayer insulating layer 741 .
  • the intermediate metal layers 710 and the contact structures 700 are alternately arranged in the direction perpendicular to the substrate, that is, the first contact structure 720, an intermediate metal layer 710, the second contact structure 730 and the Another intermediate metal layer 710 .
  • the first contact structure 720 and the second contact structure 730 are interconnected through the intermediate metal layer 710 , the first contact structure 720 penetrates the first interlayer insulating layer 741 to be connected upward to the intermediate metal layer 710 , and the second contact structure 730 penetrates the second The interlayer insulating layer 742 and the support layer 750 are connected downward to the same intermediate metal layer 710 , thereby realizing the interconnection of the first contact structure 720 and the second contact structure 730 .
  • the intermediate metal layer 710 by disposing the intermediate metal layer 710, not only can the lengths of the first contact structure 720 and the second contact structure 730 in the contact structure 700 be effectively shortened to reduce the overall resistance of the contact structure 700, but also
  • the contact structure 700 has a certain length in a plane parallel to the substrate, thereby shortening the length of the connection path between the cell region 100A and the peripheral region 100B in the horizontal plane.
  • three or more interlayer insulating layers may also be provided, and a support layer 750 is formed between every two adjacent interlayer insulating layers to adapt to the depth and width
  • the relatively high columnar capacitor structure improves the stronger support capacity, thereby preventing the structural damage of the columnar capacitor and further improving the structural stability of the semiconductor device.
  • the multiple support layers 750 can be arranged at equal distances in the vertical direction, so as to ensure that the first electrode layer 210 is uniformly stressed.
  • the thicknesses of the plurality of support layers 750 may be different.
  • the support layers 750 at the top and the bottom may be thicker, and the support layer 750 at the middle may be thinner.
  • the material of each support layer 750 may be the same, for example, all of them are silicon oxide or silicon nitride; the material of each support layer 750 may also be different, for example, one of the support layers 750 is made of silicon oxide, and the other support layers 750 are made of silicon oxide.
  • the material is silicon nitride.
  • the first contact structure 720 and the second contact structure 730 are vertically interconnected or offset interconnected.
  • the vertical interconnection means that the center of the projection of the first contact structure 720 on the substrate coincides with the center of the projection of the second vertical structure on the substrate, and the dislocation interconnection means that the first contact structure 720 is located on the substrate.
  • the center of the projection on the substrate does not coincide with the center of the projection of the second vertical structure on the substrate, as shown in FIG.
  • the columnar capacitor array 200 includes a first electrode layer 210 , a capacitor dielectric layer 220 and a second electrode layer 230 , wherein the first electrode layer 210 , the capacitor dielectric layer 220 and the second electrode layer 230 are all disposed on the Cell area 100A.
  • the first electrode layer 210 is disposed on the substrate, and the first electrode layer 210 includes a plurality of columnar structures arranged in an array. Further, the columnar structure of the first electrode layer 210 in this embodiment has a cavity passing through in a direction perpendicular to the substrate. Exemplarily, the cavity can be but not limited to a cylindrical hole, an inverted trapezoidal hole, a rectangular hole, etc. . Exemplarily, the inner wall of the columnar structure of the first electrode layer 210 may have an irregular shape, such as an arc shape or a wave shape. This embodiment does not specifically limit the shape of the columnar structure of the first electrode layer 210 .
  • the material of the first electrode layer 210 may be polysilicon or metal, may also be a stacked structure of metal and titanium nitride, or may be zero-doped and/or doped polysilicon.
  • the support layer 750 of the semiconductor device is connected to the outer walls of the plurality of columnar structures of the first electrode layer 210 to maintain the structural stability of the first electrode layer 210 .
  • the semiconductor device includes two supporting layers 750 , wherein one supporting layer 750 is provided on top of the plurality of columnar structures of the first electrode layer 210 , and the other supporting layer 750 is located on the first electrode layer 210 the middle of the multiple columnar structures.
  • the capacitor dielectric layer 220 covers the inner surface and the outer surface of the first electrode layer 210 .
  • the material of the capacitor dielectric layer 220 is a high-K dielectric layer with a dielectric constant greater than 7.
  • the material of the capacitor dielectric layer 220 may be a metal oxide.
  • the capacitor dielectric layer 220 may also be a laminated structure, such as a two-layer structure of hafnium oxide and zirconium oxide, so as to further improve the performance of the memory capacitor.
  • the second electrode layer 230 covers the surface of the capacitive dielectric layer 220 .
  • the second electrode layer 230 is disposed on the inner surface and the outer surface of the capacitor dielectric layer 220 , that is, the second electrode can be both inside the first electrode layer 210 of the columnar structure of the first electrode layer 210 and the capacitor dielectric layer 220
  • a columnar capacitor may also be formed together with the capacitive dielectric layer 220 outside the first electrode layer 210 of the columnar structure of the first electrode layer 210 .
  • the second electrode layer 230 may be a single layer or a laminated structure.
  • the material of the second electrode layer 230 may be polysilicon or metal.
  • the second electrode layer 230 is a laminated structure
  • the second electrode layer 230 may be composed of metal and titanium nitride.
  • the first electrode layer 210 , the capacitor dielectric layer 220 and the second electrode layer 230 can form a double-sided column capacitor at the column structure of each first electrode layer 210 , and further constitute a column capacitor array.
  • the first electrode layer 210 , the capacitor dielectric layer 220 and the second electrode layer 230 are jointly used to form the columnar capacitor array 200 , that is, to form a double-sided columnar capacitor structure with larger storage capacity.
  • the semiconductor device further includes an electrode filling layer 600 .
  • the electrode filling layer 600 covers the surface of the second electrode layer 230 and fills the gap formed by the second electrode layer 230 .
  • the electrode filling layer 600 covers the surface of the second electrode layer 230 and fills the gaps between the second electrode layers 230 , that is, the electrode filling layer 600 fills up between the columnar structures of the adjacent first electrode layers 210 .
  • the material of the electrode filling layer 600 may be undoped polysilicon or doped polysilicon, and the doped polysilicon may be, for example, boron-doped polysilicon.
  • the electrode filling layer 600 can prevent the second electrode layer 230 from contacting the external environment to prevent oxidation or corrosion of the second electrode layer 230 , thereby improving the stability of the second electrode layer 230 and improving the reliability of the semiconductor device.
  • a plurality of contact nodes 110 are further formed in the substrate, and the bottom of the columnar structure of the first electrode layer 210 is connected to the contact nodes 110 in the unit region 100A in a one-to-one correspondence.
  • the contact structure 720 is connected to the contact node 110 in the peripheral region 100B.
  • a plurality of contact nodes 110 arranged in an array are formed in the substrate of the unit region 100A, and the projection of the contact nodes 110 on the substrate and the plurality of columnar structures in the first electrode layer 210 are on the substrate
  • the projections of the first electrode layers 210 are overlapped, so that the bottoms of the columnar structures of the first electrode layers 210 are electrically connected to the contact nodes 110 in the unit region 100A, so that the contact nodes 110 and the first electrode layers 210 are electrically connected.
  • a conductive structure is also formed in the substrate of the peripheral region 100B, and the first contact structure 720 in the first interlayer insulating layer 741 and the second interlayer insulating layer 742 is electrically connected to the contact node 110 in the peripheral region 100B, so as to Control signals are obtained from the contact node 110 .
  • the semiconductor device further includes a peripheral structure 500 located at the edge of the columnar capacitor array 200 , and the peripheral structure 500 is formed in the first interlayer insulating layer 741 and the second interlayer insulating layer 742 .
  • the top of the peripheral structure 500 is flush with the top of the first electrode layer 210 .
  • the relationship between the peripheral structure 500 and the first electrode layer 210 can be improved.
  • the supporting force of the top prevents the top from collapsing when the semiconductor device is fabricated.
  • the bottom of the peripheral structure 500 can extend down to the surface of the substrate, so that the height of the peripheral structure 500 is the same as that of the columnar capacitor array, wherein the height refers to the dimension of the device structure along the direction perpendicular to the substrate.
  • the height of the peripheral structure 500 may be higher than the height of the columnar capacitor structure, or the height of the peripheral structure 500 may be 1/2, 2/3, etc. of the height of the columnar capacitor structure, but the heights are set at the same height
  • the peripheral structure 500 and the columnar capacitor array can obtain a better support effect on the premise of occupying a smaller internal volume of the device, thereby effectively improving the reliability of the columnar capacitor structure.
  • the peripheral structure 500 can provide stable protection for the preparation and use of the columnar capacitor, thereby effectively improving the stability and reliability during the preparation of the columnar capacitor, thereby improving the preparation yield and service life of the semiconductor device.
  • the ring width of the annular peripheral structure 500 is greater than or equal to twice the inner diameter of the columnar structure of the first electrode layer 210 .
  • the top of the columnar structure of the first electrode layer 210 is also in an open state, that is, when the peripheral structure 500 is filled, the first electrode is also filled.
  • the cavities in the columnar structure of the layer 210 are filled, however, the cavities in the columnar structure of the first electrode layer 210 need to be used to form columnar capacitors. The fillings in the cavities in the structure are cleaned to prevent the impact on the performance of the columnar capacitors.
  • the above cleaning steps will cause complicated process steps, and there is also a risk of affecting the performance of the device. Therefore, it should be avoided as far as possible to prevent the filler from entering the cavity.
  • the ring width of the peripheral structure 500 to be greater than or equal to twice the inner diameter of the columnar structure of the first electrode layer 210 , the opening at the top of the columnar structure of the first electrode layer 210 can be filled during the filling process. Fast closing, so that the filler cannot continue to enter the cavity, thereby reducing the content of the filler in the cavity and improving the complexity of the process steps.
  • FIG. 2 is a schematic top view of the first electrode layer 210 and the peripheral structure 500 according to an embodiment. For convenience of description, only the first electrode layer 210 and the peripheral structure 500 are shown in FIG. 2 . Referring to FIG. The diameter d1 of the columnar structure of the first electrode layer 210 was set to 40 nm, and the ring width d2 of the peripheral structure 500 was set to be 80 nm. With the arrangement of this embodiment, the peripheral structure 500 can achieve the required protection effect with a smaller structure volume.
  • the ring width of the peripheral structure 500 needs to be made larger to ensure its supporting effect.
  • the ring width of the peripheral structure 500 should be equal to 3 times or 4 times the inner diameter of the columnar structure of the first electrode layer 210 .
  • the peripheral structure 500 is a circumferentially closed or discontinuous structure.
  • the circumferential closure means that the peripheral structure 500 is cut in a direction parallel to the substrate, and the cross-section of the peripheral structure 500 is a closed ring.
  • the semiconductor device can be supported by uniform force in all directions, thereby avoiding damage to the columnar capacitor on one side.
  • the discontinuous structure refers to that the peripheral structures 500 are arranged discontinuously in the extending direction of the ring shape. For example, if the arrangement density in the columnar capacitor array changes gradually, the arrangement of the columnar capacitors may be sparser.
  • the peripheral structure 500 is not provided on one side of the capacitor, and the peripheral structure 500 is only provided on the side where the columnar capacitors are densely arranged to form a U-shaped peripheral structure 500, thereby reducing the volume of the peripheral structure 500 and providing a higher level of integration. high semiconductor devices.
  • FIG. 3 is a schematic cross-sectional view of a semiconductor device according to another embodiment.
  • the semiconductor device further includes a third contact structure 800 and a fourth contact structure 900 .
  • the bottom of the third contact structure 800 is connected to the second electrode layer 230
  • the bottom of the fourth contact structure 900 is connected to the contact structure 700 ; the top of the fourth contact structure 900 is flush with the top of the third contact structure 800 .
  • the fourth contact structure 900 is electrically connected to the column capacitor through the second electrode layer 230
  • the third contact structure 800 is electrically connected to the contact node 110 of the peripheral region 100B through the contact structure 700 .
  • the fourth contact structure 900 is electrically connected to the column capacitor through the electrode filling layer 600 and the second electrode layer 230 .
  • FIG. 4 is a flowchart of a method for forming a semiconductor device according to an embodiment.
  • the method for forming a semiconductor device includes steps S100 to S400 .
  • S100 Provide a substrate, where the substrate includes a cell region 100A and a peripheral region 100B.
  • the material of the substrate may be monocrystalline silicon, polycrystalline silicon, silicon-on-insulator (SOI), etc., or other materials known to those skilled in the art.
  • the substrate is divided into a unit area 100A and a peripheral area 100B, contact nodes 110 are formed in both the unit area 100A and the peripheral area 100B of the substrate, and a plurality of contact nodes 110 in the substrate of the unit area 100A are arranged in an array .
  • the contact structure 700 is formed in the first interlayer insulating layer 741 and the second interlayer insulating layer 742 in the peripheral region 100B.
  • the first interlayer insulating layer 741 and the second interlayer insulating layer 742 may be formed on the surface of the substrate by chemical vapor deposition, spin coating, or the like.
  • a support layer 750 may be formed on the surface of the first interlayer insulating layer 741 and/or the surface of the second interlayer insulating layer 742 to further improve the support force. That is, the first interlayer insulating layer 741 , one supporting layer 750 , the second interlayer insulating layer 742 , and the other supporting layer 750 may be formed alternately and sequentially on the substrate.
  • the support layer 750 can be used to support the first electrode layer 210 formed later on the one hand, and can also be used to isolate elements in the substrate and elements such as column capacitors to be formed.
  • a thermal oxidation process can be used to form the support layer 750, the material of the support layer 750 includes but not limited to silicon nitride, and the materials of the first interlayer insulating layer 741 and the second interlayer insulating layer 742 include but not limited to silicon oxide.
  • the thicknesses of the first interlayer insulating layer 741 and the second interlayer insulating layer 742 define the height of the support layer 750 to be formed subsequently. Therefore, the thicknesses of the first interlayer insulating layer 741 and the second interlayer insulating layer 742 can be determined according to The height position of the supporting layer 750 to be formed is adjusted.
  • three or four support layers 750 may be provided. After the semiconductor device is finally formed, all of the first interlayer insulating layer 741 and the second interlayer insulating layer 742 of the cell region 100A are removed, and the first interlayer insulating layer 741 and the second interlayer insulating layer 742 of the peripheral region 100B remain .
  • the step S300 in the method for forming a semiconductor device includes: forming the interconnected first contact structure 720 and the second interlayer insulating layer 742 in the peripheral region 100B. Two contact structures 730 ; wherein, the first contact structure 720 or the second contact structure 730 is interconnected by passing through the first interlayer insulating layer 741 or the second interlayer insulating layer 742 .
  • the step of forming the interconnected first contact structure 720 and the second contact structure 730 in the first interlayer insulating layer 741 and the second interlayer insulating layer 742 in the peripheral region 100B includes: the first layer in the peripheral region 100B In the interlayer insulating layer 741 and the second interlayer insulating layer 742, a first contact structure 720 and a second contact structure 730 of vertical interconnection or dislocation interconnection are formed.
  • the first interlayer insulating layer 741 and the second interlayer insulating layer 742 may be formed on the substrate first, and then the first interlayer insulating layer 741 and the second interlayer insulating layer 742 in the peripheral region 100B may be formed A contact structure 700 is formed in .
  • FIG. 5 is a flowchart of a method for forming a semiconductor device according to another embodiment.
  • step S200 and step S300 may be performed alternately, for example, the first interlayer insulating layer 741 is formed first, and then the first interlayer insulating layer 741 is formed first. Part of the contact structure 700 is formed in the first interlayer insulating layer 741, then the second interlayer insulating layer 742 is formed, and the rest of the contact structure 700 is formed in the first interlayer insulating layer 741, which is easier to form by using the method of cross execution Contact structure 700 with more structural levels and better electrical performance.
  • step S200 and step S300 include steps S310 to S370 in total.
  • step S310 forming a patterned first mask layer 120 on the surface of the first interlayer insulating layer 741 .
  • 6 is a schematic cross-sectional view of the semiconductor device after step S310. Referring to FIG. 6, after step S310, an opening is formed in the first mask layer 120, the opening exposes part of the first interlayer insulating layer 741, and the opening is perpendicular to the substrate. The projection in the direction coincides with the contact node 110 in the peripheral region 100B, and the first mask layer 120 is used to form the first contact structure trench 721 .
  • the first mask layer 120 may be a photoresist mask layer or a hard mask layer.
  • the embodiments of the present application do not specifically limit the material of the first mask layer 120, and the mask layer formed in other steps
  • the material of the film layer and the first mask layer 120 in this step may be the same or different, which is not specifically limited in the embodiment of the present application, and will not be repeated in other steps.
  • FIG. 7 is a schematic cross-sectional view of the semiconductor device after step S320 .
  • a first contact structure trench 721 penetrating vertically is formed in the first interlayer insulating layer 741 , and the first contact
  • the dimension of the structural trench 721 in the horizontal plane is smaller than the dimension of the contact node 110 .
  • the first contact structure 720 is a schematic cross-sectional view of the semiconductor device after forming the contact metal layer 722 in step S330, and FIG. 9 is a schematic cross-sectional view of the semiconductor device after step S330. Referring to FIGS. 8 to 9, after step S330, the first contact structure trench is formed. The first contact structure 720 is completely filled in 721 , thereby realizing the signal extraction to the contact node 110 .
  • the material of the first contact structure 720 may be, but not limited to, tungsten.
  • step S340 forming a patterned second mask layer 130 on the surface of the first interlayer insulating layer 741 .
  • 10 is a schematic cross-sectional view of the semiconductor device after step S340. Referring to FIG. 10, after step S340, an opening is formed in the second mask layer 130, and the opening exposes the top of the first contact structure 720 and a part of the first interlayer insulating layer 741, and the size of the opening in the second mask layer 130 in the horizontal plane is larger than the size of the contact node 110 and the size of the first contact structure 720, by forming a larger opening, a larger size can be formed in the subsequent steps. electrode layer, thereby improving the contact reliability of the contact structure 700 and reducing the contact resistance.
  • step S350 Etch the first interlayer insulating layer 741 and the first contact structure 720 to a set depth through the patterned second mask layer 130 , and remove the remaining second mask layer 130 .
  • 11 is a schematic cross-sectional view of the semiconductor device after step S350 . Referring to FIG. 11 , after step S350 , a trench is formed in the first interlayer insulating layer 741 with the size and thickness of the intermediate metal layer 710 to be formed.
  • the contact structure 700 including the first contact structure 720, the second contact structure 730 and the two intermediate metal layers 710 as shown in FIG. 12 can be formed, and the method for forming the contact structure 700 in this embodiment is used. , not only can effectively shorten the length of the contact structure 700 in the contact structure 700 to reduce the overall resistance of the contact structure 700, but also can make the contact structure 700 have a certain length in the plane parallel to the substrate, thereby shortening the cell area 100A and the length of the connection path in the horizontal plane with the peripheral region 100B.
  • step S500 is further included before step S400 : forming a peripheral structure 500 in the first interlayer insulating layer 741 and the second interlayer insulating layer 742 , and the peripheral structure 500 is located at the edge of the columnar capacitor array 200 .
  • step S500 includes steps S510 to S520.
  • S510 forming a first trench 510 and a plurality of second trenches 211 in the first interlayer insulating layer 741 and the second interlayer insulating layer 742 , the plurality of second trenches 211 are arranged in an array, and the first trenches
  • the grooves 510 are annularly arranged around the overall outer contour of the plurality of first grooves 510 .
  • the first trench 510 is used to form the peripheral structure 500, and the plurality of second trenches 211 are used to form the columnar capacitor array 200.
  • the peripheral structure 500, the trenches and the columnar capacitor array are simultaneously formed in one step.
  • 200 grooves can simplify the preparation steps, thereby achieving higher preparation efficiency.
  • the semiconductor device includes the first and second interlayer insulating layers 741 and 742 and the support layer 750
  • a first trench is formed in the first and second interlayer insulating layers 741 and 742 and the support layer 750
  • the grooves 510 and the plurality of second grooves 211 are arranged in an array, and the first grooves 510 are annularly arranged around the overall outer contour of the plurality of first grooves 510 .
  • step S510 may include steps S511 to S512.
  • FIG. 13 is a schematic cross-sectional view of the semiconductor device after step S511 . Referring to FIG. 13 , after step S511 , a part of the support layer 750 is exposed from the third mask layer 140 .
  • S512 Etch the first interlayer insulating layer 741, the second interlayer insulating layer 742 and the support layer 750 to the surface of the substrate through the patterned third mask layer 140 to form the first trench 510 and a plurality of second trenches Slot 211.
  • the plurality of second grooves 211 are arranged in an array, and the first grooves 510 are annularly arranged around the overall outer contour of the plurality of first grooves 510 .
  • the plurality of support layers 750, the first interlayer insulating layer 741 and the second interlayer insulating layer 742 are etched to remove part of the cell region 100A
  • the support layer 750, a part of the first interlayer insulating layer 741 and a part of the second interlayer insulating layer 742, and a plurality of second trenches 211 are formed in the cell region 100A, and then the patterned third mask layer 140 is removed.
  • FIG. 14 is a schematic cross-sectional view of the semiconductor device after step S512 .
  • multiple layers are formed in the first interlayer insulating layer 741 , the second interlayer insulating layer 742 and the supporting layer 750 on the cell region 100A.
  • a second groove 211 .
  • all the second trenches 211 are arranged in a hexagonal close-packed arrangement.
  • the second groove 211 may be an inverted trapezoidal hole, a rectangular hole, or the like, and the inner wall thereof may be, for example, an arc shape, which is not specifically limited in this embodiment.
  • the supporting layer 750 , the first interlayer insulating layer 741 and the second interlayer insulating layer 742 are still left on the peripheral region 100B, so as to protect the lining of the peripheral region 100B in the subsequent process steps of forming the columnar capacitor. end.
  • the second trench 211 needs to be formed in the alternately stacked support layer 750 , the first interlayer insulating layer 741 and the second interlayer insulating layer 742 , the bottom of the second trench 211 can be formed in the subsequent
  • the first electrode layer 210 with a plurality of columnar structures is formed on the wall and the inner wall. Therefore, the thickness of the first interlayer insulating layer 741 and/or the second interlayer insulating layer 742 can be increased to increase the subsequent formation of the columnar structure.
  • the height of the first electrode layer 210 of the capacitor increases the surface area of the first electrode layer 210 of the columnar capacitor, thereby increasing the capacitance value of the formed columnar capacitor.
  • FIG. 16 is a schematic cross-sectional view of the semiconductor device after step S500 .
  • the peripheral structure 500 may be formed by a deposition process combined with a planarization process. For example, first, a material layer of the peripheral structure 500 is formed in the first trench 510 by a process such as physical vapor deposition or chemical vapor deposition; then, a planarization process is performed to remove the material layer of the peripheral structure 500 on the top of the device to form a flat periphery Structure 500 material layers.
  • the material of the peripheral structure 500 may be at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. It can be understood that the material of the peripheral structure 500 has high strength , therefore, by setting the peripheral structure 500 , the overall strength of the semiconductor device in use can be improved, and device failure can be avoided. Further, the peripheral structure 500 can also protect the device structure during the manufacturing process, so as to prevent the failure of the columnar capacitor, so as to improve the stability and reliability during the preparation of the columnar capacitor, thereby improving the manufacturing yield of the semiconductor device.
  • step S400 includes steps S410 to S450 to form the columnar capacitor array 200 .
  • a first electrode layer 210 is formed in the first trench 510 and the second trench 211, where the first electrode layer 210 includes a plurality of columnar structures.
  • FIG. 15 is a schematic cross-sectional view of the semiconductor device after step S400 .
  • a first electrode layer 210 is formed on the inner walls and bottom walls of the first trench 510 and the second trench 211 .
  • the topography of the portion of the first electrode layer 210 formed in the second trench 211 is the same as that of the second trench 211 , thereby forming a plurality of columnar structures in the first electrode layer 210 .
  • step S410 is set before step S520.
  • the first electrode layer 210 may be formed on the basis of the deposition process combined with the planarization process. For example, first, an electrode material layer is formed on the surface of the support layer 750 and in the first trench 510 and the second trench 211 by a process such as physical vapor deposition or chemical vapor deposition; then, a planarization process is performed to remove the electrode material Therefore, only the electrode material layers in the first trenches 510 and the second trenches 211 are retained to form the first electrode layer 210 having a plurality of columnar structures.
  • the contact node 110 of the cell region 100A is exposed through the second trench 211 , so that the bottom of the columnar structure of the first electrode layer 210 of the formed first electrode layer 210 can be electrically connected to the contact node 110 .
  • the material of the first electrode layer 210 may be polysilicon or metal. When the material of the first electrode layer 210 is metal, a stacked structure of titanium nitride and Ti can also be used; when the first electrode layer 210 is polysilicon, it can be zero-doped and/or doped polysilicon.
  • FIG. 17 is a schematic cross-sectional view of the semiconductor device after step S420. Referring to FIG. 17, after step S420, a plurality of openings are formed in the fourth mask layer 150, and the projection of each opening on the substrate is the same as that of the plurality of openings.
  • the projections of the columnar structures on the substrate are all partially overlapped, so as to remove the respective first interlayer insulating layers 741 and the second interlayer insulating layers 742 and retain the respective supporting layers 750 and the plurality of openings in the fourth mask layer 150 It is used to form a plurality of capacitor opening holes in a subsequent step to remove the remaining first interlayer insulating layer 741 and the second interlayer insulating layer 742 in the cell region 100A.
  • the peripheral structure 500 is a material layer, and the remaining peripheral structure 500 material layers are used as the peripheral structure 500 .
  • FIG. 18 is a schematic cross-sectional view of the semiconductor device after step S430
  • FIG. 19 is a schematic top view of the unit area 100A of the semiconductor device of FIG. 18.
  • a capacitor opening is formed in the unit area 100A, referring to FIG. 19.
  • each capacitor opening hole is used to open three columnar capacitor holes, and the capacitor opening hole exposes part of the substrate.
  • each capacitor opening hole can also be used to open four or more capacitor holes.
  • the entire first interlayer insulating layer 741 , the entire second interlayer insulating layer 742 and part of the support layer 750 of the cell region 100A can be removed through the capacitor opening holes, so that the capacitor dielectric layer 220 and the second The electrode layer 230 is used to form double-sided columnar capacitors and increase the capacitance of the columnar capacitors.
  • the remaining support layers 750 are laterally connected to the outer walls of the plurality of columnar structures of the first electrode layer 210 to support the first electrode layer 210 .
  • the top supporting layer 750 is located at the top periphery of the plurality of columnar structures of the first electrode layer 210
  • the middle supporting layer 750 is located in the middle of the plurality of columnar structures of the first electrode layer 210 , so as to support the first electrode layer 210 Provide effective support.
  • the capacitor dielectric layer 220 covers the inner and outer surfaces of the columnar structure of the first electrode layer 210 of the first electrode layer 210 to make full use of the inner and outer surfaces of the first electrode layer 210 to form a larger electrode surface area.
  • the material of the capacitor dielectric layer 220 may be a high-K dielectric material such as metal oxide.
  • the capacitor dielectric layer 220 may be a laminated structure, such as a double structure of hafnium oxide-zirconia.
  • the second electrode layer 230 can form a columnar capacitor with the capacitor dielectric layer 220 and the first electrode layer 210 both inside the columnar structure of the first electrode layer 210 and outside the columnar structure of the first electrode layer 210 .
  • a chemical vapor deposition process or an atomic layer deposition process can be used to form the capacitor dielectric layer 220 on the inner and outer surfaces of the first electrode layer 210 and the exposed surfaces of the respective support layers 750; and on the inner surface of the capacitor dielectric layer 220 and the outer surface to form a second electrode layer 230 .
  • the capacitor dielectric layer 220 and the second electrode layer 230 are further extended to cover the surface of the supporting layer 750 remaining on the peripheral region 100B in sequence.
  • the method for forming a semiconductor device further includes step S600.
  • FIG. 1 is a schematic cross-sectional view of the semiconductor device after step S600 .
  • the electrode filling layer 600 may be formed on the surface of the second electrode layer 230 by using a chemical vapor deposition process, so that the electrode filling layer 600 fills the gap between the second electrode layers 230 . Further, the material of the electrode filling layer 600 may be undoped or boron-doped polysilicon.
  • the method for forming a semiconductor device further includes step S700.
  • step S610 is further included: removing the electrode filling layer 600 in the peripheral region 100B.
  • FIG. 20 is a schematic cross-sectional view of the semiconductor device after step S610 . Further, referring to FIG. 3, FIG. 3 is a schematic cross-sectional view of the semiconductor device after step S700.
  • a third interlayer insulating layer 760 may be formed on top of the electrode filling layer 600, the peripheral structure 500 and the supporting layer 750 first, and the A patterned fifth mask layer is formed on the surface of the third interlayer insulating layer 760, a plurality of openings are formed in the fifth mask layer, the openings expose part of the third interlayer insulating layer 760, and some of the openings are vertically aligned with those located at
  • the top middle metal layer 710 is partially overlapped, and another part of the opening is partially overlapped with the electrode filling layer 600 in the vertical direction; after that, the first interlayer insulating layer 741 and the second interlayer insulating layer are etched through the patterned fifth mask layer 742, to form contact trenches; then, each contact trench can be filled with metal conductive material by an electroplating or sputtering process, and the excess metal conductive material is further removed by a chemical mechanical planarization process, thereby forming a fourth contact structure 900 and the third contact structure 800 .
  • steps in the flowcharts of FIG. 4 to FIG. 5 are shown in sequence according to the arrows, these steps are not necessarily executed in the sequence shown by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIG. 4 to FIG. 5 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. These sub-steps or stages may be executed at different times. The order of execution of the stages is also not necessarily sequential, but may be performed alternately or alternately with other steps or sub-steps of other steps or at least a portion of a stage.

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Abstract

本发明涉及一种半导体器件及其形成方法，半导体器件包括：衬底，衬底包括单元区域和外围区域；形成在单元区域和外围区域的衬底上的第一层间绝缘层和第二层间绝缘层，第一层间绝缘层和第二层间绝缘层沿垂直于衬底的方向间隔排布；柱状电容阵列，柱状电容阵列包括间隔排布的柱状电容，柱状电容形成在单元区域的第一层间绝缘层和第二层间绝缘层中；接触结构，接触结构形成在外围区域的第一层间绝缘层和第二层间绝缘层中。

Description

半导体器件及其形成方法
相关申请交叉引用
本申请要求2020年08月21日递交的、标题为“半导体器件及其形成方法”、申请号为2020108480676的中国申请，其公开内容通过引用全部结合在本申请中。
技术领域
本发明涉及一种半导体器件及其形成方法。
背景技术
随着移动设备的不断发展，手机、平板电脑、可穿戴设备等带有电池供电的移动设备被越来越多地应用于生活中，存储器作为移动设备中必不可少的元件，人们对存储器的小体积、集成化提出了巨大的需求。
目前，动态随机存储器(Dynamic Random Access Memory，DRAM)以其快速的传输速度被广泛应用于移动设备中。
发明内容
本申请的实施例提供一种半导体器件，包括：
衬底，所述衬底包括单元区域和外围区域；
第一层间绝缘层和第二层间绝缘层，形成在所述单元区域和所述外围区域的所述衬底上，所述第一层间绝缘层和所述第二层间绝缘层沿垂直于所述衬底的方向间隔排布；
柱状电容阵列，所述柱状电容阵列包括间隔排布的柱状电容，所述柱状电容形成在所述单元区域的所述第一层间绝缘层和所述第二层间绝缘层中；以及
接触结构，所述接触结构形成在所述外围区域的所述第一层间绝缘层和所述第二层间绝缘层中。
一种半导体器件的形成方法，包括：
提供衬底，所述衬底包括单元区域和外围区域；
在所述衬底上形成第一层间绝缘层和第二层间绝缘层，所述第一层间绝缘层和所述第二层间绝缘层沿垂直于所述衬底的方向间隔排布；
在所述外围区域的所述第一层间绝缘层和所述第二层间绝缘层中形成接触结构；以及
在所述单元区域的所述第一层间绝缘层和所述第二层间绝缘层中形成柱状电容阵列，所述柱状电容阵列包括间隔排布的柱状电容。本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为一实施例的半导体器件的剖面示意图；
图2为一实施例的第一电极层和外围结构的俯视示意图；
图3为另一实施例的半导体器件的剖面示意图；
图4为一实施例的半导体器件的形成方法的流程图；
图5为另一实施例的半导体器件的形成方法的流程图；
图6为步骤S310后的半导体器件的剖面示意图；
图7为步骤S320后的半导体器件的剖面示意图；
图8为步骤S330中形成接触金属层后的半导体器件的剖面示意图；
图9为步骤S330后的半导体器件的剖面示意图；
图10为步骤S340后的半导体器件的剖面示意图；
图11为步骤S350后的半导体器件的剖面示意图；
图12为步骤S370后的半导体器件的剖面示意图；
图13为步骤S511后的半导体器件的剖面示意图；
图14为步骤S512后的半导体器件的剖面示意图；
图15为步骤S400后的半导体器件的剖面示意图；
图16为步骤S500后的半导体器件的剖面示意图；
图17为步骤S420后的半导体器件的剖面示意图；
图18为步骤S430后的半导体器件的剖面示意图；
图19为图18的半导体器件的单元区域的俯视示意图；
图20为步骤S610后的半导体器件的剖面示意图。
元件标号说明：
单元区域：100A；外围区域：100B；接触节点：110；第一掩膜层：120；第二掩膜层：130；第三掩膜层：140；第四掩膜层：150；柱状电容阵列：200；第一电极层：210；第二沟槽：211；电容介质层：220；第二电极层：230；外围结构：500；第一沟槽：510；电极填充层：600；接触结构：700；中间金属层：710；第一接触结构：720；第一接触结构沟槽：721；接触金属层：722；第二接触结构：730；第一层间绝缘层：741；第二层间绝缘层：742；支撑层：750；第三层间绝缘层：760；第三接触结构：800；第四接触结构：900。
具体实施方式
随着体积的不断微缩，动态随机存储器中的柱状电容的尺寸也在不断缩小，因此，现在的器件结构和布线方式的密度较低，已无法满足日益提高的集成度需求。
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体地实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本发明的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指 的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
图1为一实施例的半导体器件的剖面示意图，参考图1，在本实施例中，半导体器件包括衬底(未图示)、第一层间绝缘层741、第二层间绝缘层742、柱状电容阵列200和接触结构700。
具体地，衬底包括单元区域100A和外围区域100B，衬底的材料可以为单晶硅、多晶硅、绝缘体上硅(SOI)等，或者本领域技术人员已知的其他材料。进一步地，单元区域100A与外围区域100B可以通过衬底中的浅沟槽隔离结构(未图示)相隔离，以防止漏电流等现象，从而提高半导体器件的可靠性。
第一层间绝缘层741和第二层间绝缘层742形成在单元区域100A和外围区域100B的衬底上，第一层间绝缘层741和第二层间绝缘层742沿平行于衬底的方向间隔排布。具体地，第一层间绝缘层741和第二层间绝缘层742的材料可以为低K介质，低K介质是指介电常数或等于4的介质材料，例如可以为氧化硅等。
进一步地，第一层间绝缘层741的表面和/或第二层间绝缘层742的表面还可以形成有支撑层750，支撑层750的延伸方向与衬底表面的方向相平行，从而为第一层间绝缘层741和第二层间绝缘层742提供支撑。第一层间绝缘层741和第二层间绝缘层742的厚度界定出后续所形成的支撑层750的高度，因此，第一层间绝缘层741和第二层间绝缘层742的厚度可根据所需形成的支撑层750的高度位置进行调整。
柱状电容阵列200，柱状电容阵列200包括间隔排布的柱状电容，柱状电容形成在单元区域100A的第一层间绝缘层741和第二层间绝缘层742中。其中，柱状电容阵列200用于存储数据，以实现存储器的数据存储功能。
接触结构700，接触结构700形成在外围区域100B的第一层间绝缘层741和第二层间绝缘层742中。第一层间绝缘层741和第二层间绝缘层742延伸覆盖整个外围区域100B的表面，从而将接触结构700完全覆盖。
在本实施例中，通过在第一层间绝缘层741和第二层间绝缘层742中设置接触结构700，可以有效缩短接触结构700的连接路径，从而有效利用了柱状电容阵列200的空间，进而提高了半导体器件中各个结构的排布密度，改善了半导体器件的集成度。
在其中一个实施例中，接触结构700包括互连的第一接触结构720和第二接触结构730，第一接触结构720或第二接触结构730通过贯穿第一层间绝缘层741或第二层间绝缘层742实现互连。示例性地，第一接触结构720和第二接触结构730的材料可以为钨等导电金属材料，且第一接触结构720和第二接触结构730的材料可以相同，也可以不同。
进一步地，第一层间绝缘层741中远离衬底的一侧还形成有中间金属层710，中间金属层710的表面与第一层间绝缘层741的表面相齐平。中间金属层710和接触结构700在垂直于衬底的方向上依次交替设置，即，垂直于衬底的方向上依次排列有第一接触结构720、一中间金属层710、第二接触结构730及另一中间金属层710。第一接触结构720和第二接触结构730通过中间金属层710实现互连，第一接触结构720贯穿第一层间绝缘层741以向上连接至中间金属层710，第二接触结构730贯穿第二层间绝缘层742和支撑层750以向下连接至同一中间金属层710，从而实现第一接触结构720和第二接触结构730的互连。
在本实施例中，通过设置中间金属层710，不仅可以有效缩短接触结构700中的第一接触结构720和第二接触结构730的长度，以减小接触结构700的整体阻值，还可以使接触结构700在平行于衬底的平面内具有一定的长度，从而缩短单元区域100A和外围区域100B在水平面内的连接路径的长度。
需要说明的是，在其他实施例中，也可以设置三个或三个以上层间绝缘层，且每两个相邻的层间绝缘层之间均形成有支撑层750，以适配深宽比较高的柱状电容结构，提高更强的支撑能力，从而防止柱状电容的结构损伤，进一步提升半导体器件的结构稳定性。当设置多个支撑层750时，可以使多个支撑层750在垂直方向上等距设置，从而确保第一电极层210受力均匀。
再进一步地，多个支撑层750的厚度可以不同，示例性地，可以使位于顶部和底部的支撑层750较厚，且位于中部的支撑层750较薄。而且，各个支撑层750的材料可以相同，例如均为氧化硅或氮化硅；各个支撑层750的材料也可以不完全相同，例如其中一个支撑层750的材料为氧化硅，其余支撑层750的材料为氮化硅。
在其中一个实施例中，第一接触结构720和第二接触结构730垂直互连或错位互连。具体地，垂直互连是指第一接触结构720在衬底上的投影的中 心与第二垂直结构在衬底上的投影的中心相重合，错位互连是指第一接触结构720在衬底上的投影的中心与第二垂直结构在衬底上的投影的中心不相重合，如图1中所示的即为错位互连的第一接触结构720和第二接触结构730。
在其中一个实施例中，柱状电容阵列200包括第一电极层210、电容介质层220和第二电极层230，其中，第一电极层210、电容介质层220和第二电极层230均设置于单元区域100A。
第一电极层210，设置于衬底上，第一电极层210包括呈阵列式排布的多个柱状结构。进一步地，本实施例的第一电极层210的柱状结构具有垂直于衬底的方向上贯通的空腔，示例性地，空腔可以为但不限于圆柱形孔、倒梯形孔、矩形孔等。示例性地，第一电极层210的柱状结构的内壁可以为不规则形貌，如弧形或波浪形，本实施例不具体限制第一电极层210的柱状结构的形状。其中，第一电极层210的材料可以为多晶硅或金属，也可以为金属与氮化钛的层叠结构，还可以为零掺杂和/或掺杂的多晶硅。
进一步地，半导体器件的支撑层750连接至第一电极层210的多个柱状结构的外壁，以维持第一电极层210的结构稳定。在图1所示的实施例中，半导体器件包括两个支撑层750，其中一个支撑层750设于第一电极层210的多个柱状结构的顶部，另一个支撑层750位于第一电极层210的多个柱状结构的中部。
电容介质层220，覆盖第一电极层210的内表面和外表面。具体地，电容介质层220的材料为介电常数大于7的高K介质层，示例性地，电容介质层220的材料可以为金属氧化物。进一步地，电容介质层220也可以为叠层结构，例如为氧化铪和氧化锆的两层结构，以进一步提升存储器电容的性能。通过将电容介质层220设置在第一电极层210的内表面和外表面上，可以有效提升第一电极层210的表面的利用率，以形成更大电极面积的柱状电容。
第二电极层230，覆盖电容介质层220的表面。具体地，第二电极层230设置于电容介质层220的内表面和外表面，即，第二电极既可以在第一电极层210的柱状结构的第一电极层210的内部与电容介质层220共同构成柱状电容，还可以在第一电极层210的柱状结构的第一电极层210的外部与电容介质层220共同构成柱状电容。其中，第二电极层230可以为单层或叠层结构，当第二电极层230为单层结构时，第二电极层230的材料可以为多晶硅 或金属，当第二电极层230为叠层结构时，第二电极层230可以由金属和氮化钛共同构成。
因此，在本实施例中，第一电极层210、电容介质层220和第二电极层230可以在每个第一电极层210的柱状结构处形成一个双面的柱状电容，并进而构成柱状电容阵列。在本实施例中，第一电极层210、电容介质层220和第二电极层230共同用于形成柱状电容阵列200，即，形成了具有较大存储容量的双面柱状电容结构。
在其中一个实施例中，继续参考图1，半导体器件还包括电极填充层600，电极填充层600覆盖第二电极层230的表面，且充满第二电极层230构成的间隙。具体地，电极填充层600覆盖第二电极层230的表面上，并充满第二电极层230之间的间隙，即，电极填充层600填充满相邻的第一电极层210的柱状结构之间的间隙。进一步地，电极填充层600的材料可以为未掺杂多晶硅或者掺杂多晶硅，掺杂多晶硅例如可以为硼掺杂多晶硅。电极填充层600可以避免第二电极层230与外部环境接触，以防止第二电极层230的氧化或腐蚀现象，从而提高了第二电极层230的稳定性，进而改善了半导体器件的可靠性。
在其中一个实施例中，继续参考图1，衬底中还形成有多个接触节点110，第一电极层210的柱状结构的底部与单元区域100A中的接触节点110一一对应连接，第一接触结构720与外围区域100B中的接触节点110连接。具体地，在单元区域100A的衬底中形成有多个呈阵列式排布的接触节点110，接触节点110在衬底上的投影与第一电极层210中的多个柱状结构在衬底上的投影相重合，以使各个第一电极层210的柱状结构的底部与单元区域100A中的接触节点110电性连接，从而使接触节点110与第一电极层210电性连接。在外围区域100B的衬底中还形成有导电结构，第一层间绝缘层741和第二层间绝缘层742中的第一接触结构720与外围区域100B中的接触节点110电性连接，以从接触节点110获取控制信号。
在其中一个实施例中，继续参考图1，半导体器件还包括位于柱状电容阵列200边缘的外围结构500，外围结构500形成在第一层间绝缘层741和第二层间绝缘层742中。
进一步地，外围结构500的顶部与第一电极层210的顶部相齐平，通过 使外围结构500的顶部与第一电极层210的顶部相齐平，可以提升外围结构500对第一电极层210的顶部的支撑力，防止半导体器件制备时顶部坍塌。进一步地，外围结构500的底部可以向下延伸至衬底表面，以使外围结构500的高度与柱状电容阵列的高度相同，其中，高度是指器件结构沿垂直于衬底的方向上的尺寸。在其他实施例中，也可以使外围结构500的高度高于柱状电容结构的高度，或使外围结构500的高度为柱状电容结构的高度的1/2、2/3等，但等高设置的外围结构500和柱状电容阵列可以在较小占用器件内部体积的前提下，获得较好的支撑效果，从而有效提高柱状电容结构的可靠性。外围结构500可以为柱状电容的制备和使用过程提供稳定的保护，从而有效提升柱状电容制备过程中的稳定性和可靠性，从而提高半导体器件的制备良率和使用寿命。
在其中一个实施例中，环形的外围结构500的环宽大于或等于第一电极层210的柱状结构的内径的2倍。具体地，在本实施例的制备过程中，在对外围结构500进行填充时，第一电极层210的柱状结构的顶部也为开放状态，即，填充外围结构500的同时也会对第一电极层210的柱状结构中的空腔进行填充，但是，第一电极层210的柱状结构中的空腔需要用于形成柱状电容，因此，填充外围结构500后还需要对第一电极层210的柱状结构中的空腔中的填充物进行清理，以防止对柱状电容性能的影响。
可以理解的是，上述清理步骤会造成工艺步骤复杂，还存在影响器件性能的风险，因此，应当尽量避免填充物进入空腔中。在本实施例中，通过设置外围结构500的环宽大于或等于第一电极层210的柱状结构的内径的2倍，可以使第一电极层210的柱状结构的顶部的开口在填充过程中被快速封闭，从而使填充物无法继续进入空腔，进而降低了空腔中的填充物的含量，改善了工艺步骤的复杂度。
进一步地，可以使外围结构500的环宽等于第一电极层210的柱状结构的内径的2倍。示例性地，图2为一实施例的第一电极层210和外围结构500的俯视示意图，为了便于说明，图2中仅示出了第一电极层210和外围结构500，参考图2，可以使第一电极层210的柱状结构的直径d1为40nm，并使外围结构500的环宽d2为80nm。通过本实施例的设置方式，可以使外围结构500以较小的结构体积实现需要的保护效果。需要说明的是，若柱状电容 结构的尺寸进一步缩小，或柱状电容的深宽比进一步提高，需要使外围结构500的环宽更大，以确保其支撑效果，例如使外围结构500的环宽等于第一电极层210的柱状结构的内径的3倍或4倍。
在其中一个实施例中，外围结构500为周向闭合或断续结构。其中，继续参考图2，周向闭合是指，将外围结构500沿平行于衬底的方向剖开，外围结构500的剖面为一个闭合环形。在本实施例中，通过设置外围结构500为周向闭合结构，可以使半导体器件在各个方向上获得受力均匀的支撑，从而避免单侧的柱状电容损伤。在其他实施例中，断续结构是指外围结构500在其环形的延伸方向上间断式设置，例如，若柱状电容阵列中的排布密度为渐变式变化的，则可以在柱状电容排列较稀疏的一侧不设置外围结构500，而仅在柱状电容排列较密集的一侧设置外围结构500，以形成一U形结构的外围结构500，从而减小外围结构500的体积，提供一集成度更高的半导体器件。
图3为另一实施例的半导体器件的剖面示意图，参考图3，在本实施例中，半导体器件还包括第三接触结构800和第四接触结构900。第三接触结构800的底部与第二电极层230连接，第四接触结构900的底部与接触结构700连接；其中，第四接触结构900的顶部与第三接触结构800的顶部相齐平。在本实施例中，第四接触结构900通过第二电极层230电连接至柱状电容，第三接触结构800通过接触结构700电连接至外围区域100B的接触节点110。进一步地，若第二电极层230表面还填充有电极填充层600，则第四接触结构900通过电极填充层600和第二电极层230电连接至柱状电容。
图4为一实施例的半导体器件的形成方法的流程图，参考图4，在本实施例中，半导体器件的形成方法包括步骤S100至S400。
S100：提供衬底，衬底包括单元区域100A和外围区域100B。其中，衬底的材料可以为单晶硅、多晶硅、绝缘体上硅(SOI)等，或者本领域技术人员已知的其他材料。衬底划分为单元区域100A和外围区域100B，衬底的单元区域100A和外围区域100B中均形成有接触节点110，且在单元区域100A的衬底中的多个接触节点110呈阵列式排布。
S200：在衬底上形成第一层间绝缘层741和第二层间绝缘层742，第一层间绝缘层741和第二层间绝缘层742沿平行于衬底的方向间隔排布。
S300：在外围区域100B的第一层间绝缘层741和第二层间绝缘层742中形成接触结构700。
S400：在单元区域100A的第一层间绝缘层741和第二层间绝缘层742中形成柱状电容阵列200，柱状电容阵列200包括间隔排布的柱状电容。
在其中一个实施例中，步骤S200可以通过化学气相沉积、旋涂等工艺在衬底的表面上形成第一层间绝缘层741和第二层间绝缘层742。为了提升对柱状电容的支撑能力，可以在第一层间绝缘层741的表面和/或第二层间绝缘层742的表面形成支撑层750，以进一步提升支撑力。即，可以在衬底上交替层叠依次形成第一层间绝缘层741、一个支撑层750、第二层间绝缘层742和另一个支撑层750。其中，支撑层750一方面可以用于对后续形成的第一电极层210进行底部支撑，另一方面还可以用于隔离衬底中的元件和待形成的柱状电容等元件。
进一步地，可以采用热氧化工艺形成支撑层750，支撑层750的材料包含但不限于氮化硅，第一层间绝缘层741和第二层间绝缘层742的材料包含但不限于氧化硅。第一层间绝缘层741和第二层间绝缘层742的厚度界定出后续所形成的支撑层750的高度，因此，第一层间绝缘层741和第二层间绝缘层742的厚度可根据所需形成的支撑层750的高度位置进行调整。
在其他实施例中，为了对第一电极层210进行更好地支撑，可以设置三个或四个支撑层750。在最终形成半导体器件后，去除单元区域100A的全部第一层间绝缘层741和第二层间绝缘层742，并保留外围区域100B的第一层间绝缘层741和第二层间绝缘层742。
在其中一个实施例中，半导体器件的形成方法中的步骤S300包括：在外围区域100B的第一层间绝缘层741和第二层间绝缘层742中形成互连的第一接触结构720和第二接触结构730；其中，第一接触结构720或第二接触结构730通过贯穿第一层间绝缘层741或第二层间绝缘层742实现互连。进一步地，步骤在外围区域100B的第一层间绝缘层741和第二层间绝缘层742中形成互连的第一接触结构720和第二接触结构730包括：在外围区域100B的第一层间绝缘层741和第二层间绝缘层742中形成垂直互连或错位互连的第一接触结构720和第二接触结构730。
在一些实施例中，可以先在衬底上形成第一层间绝缘层741和第二层间 绝缘层742，再在外围区域100B的第一层间绝缘层741和第二层间绝缘层742中形成接触结构700。
图5为另一实施例的半导体器件的形成方法的流程图，参考图5，在另一些实施例中，步骤S200和步骤S300可以交叉执行，例如先形成第一层间绝缘层741，并在第一层间绝缘层741中形成部分接触结构700，之后在形成第二层间绝缘层742，并在第一层间绝缘层741中形成剩余的接触结构700，采用交叉执行的方法更便于形成结构层次较多、电学性能更好的接触结构700。参考图5，在本实施例中，步骤S200和步骤S300共包括步骤S310至S370。
S310：在第一层间绝缘层741的表面形成图形化的第一掩膜层120。图6为步骤S310后的半导体器件的剖面示意图，参考图6，在步骤S310后，第一掩膜层120形成有开口，开口暴露部分第一层间绝缘层741，且开口在垂直于衬底方向上的投影与外围区域100B中的接触节点110相重合，第一掩膜层120用于形成第一接触结构沟槽721。需要说明的是，第一掩膜层120可以为光阻掩膜层，也可以为硬掩模层，本申请实施例不具体限定第一掩膜层120的材料，在其他步骤中形成的掩膜层与本步骤的第一掩膜层120的材料可以相同，也可以不同，本申请实施例也不做具体限定，在其他步骤中将不再进行赘述。
S320：通过图形化的第一掩模层蚀刻第一层间绝缘层741至接触节点110的表面，并去除剩余的第一掩膜层120。图7为步骤S320后的半导体器件的剖面示意图，参考图7，在步骤S320后，第一层间绝缘层741中形成有沿竖直方向贯通的第一接触结构沟槽721，且第一接触结构沟槽721在水平面内的尺寸小于接触节点110的尺寸。
S330：在第一接触结构沟槽721中和第一层间绝缘层741的面形成接触金属层722，并去除第一层间绝缘层741表面的接触金属层722，剩余的接触金属层722作为第一接触结构720。图8为步骤S330中形成接触金属层722后的半导体器件的剖面示意图，图9为步骤S330后的半导体器件的剖面示意图，参考图8至图9，在步骤S330后，第一接触结构沟槽721中完全填充有第一接触结构720，从而实现了对接触节点110的信号引出。其中，第一接触结构720的材料可以是但不限于钨。
S340：在第一层间绝缘层741的表面形成图形化的第二掩膜层130。图10为步骤S340后的半导体器件的剖面示意图，参考图10，在步骤S340后，第二掩膜层130中形成有开口，开口暴露第一接触结构720的顶部和部分第一层间绝缘层741，且第二掩膜层130中的开口在水平面内的尺寸大于接触节点110的尺寸和第一接触结构720的尺寸，通过形成较大的开口，可以在后续步骤中形成较大尺寸的中间电极层，从而提高接触结构700的接触可靠性，并降低接触电阻。
S350：通过图形化的第二掩膜层130蚀刻第一层间绝缘层741和第一接触结构720至设定深度，并去除剩余的第二掩膜层130。图11为步骤S350后的半导体器件的剖面示意图，参考图11，在步骤S350后，第一层间绝缘层741中形成一与待形成的中间金属层710的尺寸和厚度相当的沟槽。
S360：在第一层间绝缘层741的沟槽中填充中间金属层710，并在第一层间绝缘层741的表面形成支撑层750和第二层间绝缘层742。
S370：重复前述步骤S310至S360，以在外围区域100B形成第二接触结构730和另一中间金属层710。
通过上述步骤S310至S370，可以形成如图12所示的包括第一接触结构720、第二接触结构730和两个中间金属层710的接触结构700，通过本实施例的接触结构700的形成方法，不仅可以有效缩短接触结构700中的接触结构700长度，以减小接触结构700的整体阻值，还可以使接触结构700在平行于衬底的平面内具有一定的长度，从而缩短单元区域100A和外围区域100B在水平面内的连接路径的长度。
在其中一个实施例中，步骤S400前还包括步骤S500：在第一层间绝缘层741和第二层间绝缘层742中形成外围结构500，外围结构500位于柱状电容阵列200边缘。具体地，在其中一个实施例中，步骤S500包括步骤S510至S520。
S510：在第一层间绝缘层741和第二层间绝缘层742中形成第一沟槽510和多个第二沟槽211，多个第二沟槽211呈阵列式排布，第一沟槽510围绕多个第一沟槽510的整体外轮廓环形设置。
具体地，第一沟槽510用于形成外围结构500，多个第二沟槽211用于形成柱状电容阵列200，在本实施例中，通过一个步骤同时形成外围结构500 沟槽和柱状电容阵列200的沟槽，可以简化制备步骤，从而实现更高的制备效率。当半导体器件包括第一层间绝缘层741和第二层间绝缘层742和支撑层750时，在第一层间绝缘层741和第二层间绝缘层742和支撑层750中形成第一沟槽510和多个第二沟槽211，多个第二沟槽211呈阵列式排布，第一沟槽510围绕多个第一沟槽510的整体外轮廓环形设置。
在其中一个实施例中，步骤S510可以包括步骤S511至S512。
S511：在支撑层750表面形成图形化的第三掩膜层140。图13为步骤S511后的半导体器件的剖面示意图，参考图13，在步骤S511后，第三掩膜层140暴露出部分支撑层750。
S512：通过图形化的第三掩膜层140蚀刻第一层间绝缘层741、第二层间绝缘层742和支撑层750至衬底表面，以形成第一沟槽510和多个第二沟槽211。其中，多个第二沟槽211呈阵列式排布，第一沟槽510围绕多个第一沟槽510的整体外轮廓环形设置。具体地,以图形化的第三掩膜层140为掩膜，对多个支撑层750、第一层间绝缘层741和第二层间绝缘层742进行刻蚀，以去除单元区域100A的部分支撑层750、部分第一层间绝缘层741和部分第二层间绝缘层742，并在单元区域100A中形成多个第二沟槽211，然后去除图形化的第三掩膜层140。
图14为步骤S512后的半导体器件的剖面示意图，参考图14，在步骤S512后，在单元区域100A上的第一层间绝缘层741、第二层间绝缘层742与支撑层750内形成多个第二沟槽211。进一步地，所有的第二沟槽211呈六方密堆积排布。再进一步地，第二沟槽211可以为倒梯形孔、矩形孔等，其内壁例如可以为弧形，在本实施例中不做具体限制。此外，本实施例中，外围区域100B上还保留有支撑层750、第一层间绝缘层741和第二层间绝缘层742，以在后续柱状电容形成的工艺步骤中保护外围区域100B的衬底。
可以理解的是，由于需要在交替层叠的支撑层750、第一层间绝缘层741和第二层间绝缘层742中形成第二沟槽211，进而在后续可在第二沟槽211的底璧和内壁上形成具有多个柱状结构的第一电极层210，因此，可以通过增加第一层间绝缘层741和/或第二层间绝缘层742的厚度，以增大后续所形成的柱状电容的第一电极层210的高度，从而增加柱状电容的第一电极层210的表面积，进而提高形成的柱状电容的电容值。
S520：在第一沟槽510中形成外围结构500。
具体地，图16为步骤S500后的半导体器件的剖面示意图，参考图16，在步骤S500后，外围结构500可在沉积工艺的基础上结合平坦化工艺形成。例如，首先，采用物理气相沉积或化学气相沉积等工艺形成外围结构500材料层于第一沟槽510中；然后，执行平坦化工艺以去除器件顶部的外围结构500材料层，以形成平坦的外围结构500材料层。
在本实施例中，外围结构500的材料可以为氧化硅、氮化硅、氮氧化硅、碳氮化硅中的至少一种，可以理解的是，上述外围结构500的材料具有较高的强度，因此，通过设置外围结构500可以提升半导体器件的使用时的整体强度，避免器件失效。进一步地，外围结构500还可以在制备过程中对器件结构进行保护，从而防止柱状电容的失效，以提升柱状电容制备过程中的稳定性和可靠性，进而提高半导体器件的制备良率。
在其中一个实施例中，步骤S400包括步骤S410至S450，以形成柱状电容阵列200。
S410：在第一沟槽510和第二沟槽211中形成第一电极层210，第一电极层210包括多个柱状结构。
具体地，图15为步骤S400后的半导体器件的剖面示意图，参考图15，在步骤S410后，在第一沟槽510和第二沟槽211的内壁和底璧上形成第一电极层210。第一电极层210形成于第二沟槽211中的部分的形貌与第二沟槽211的形貌相同，从而形成第一电极层210中的多个柱状结构。可以理解的是，先在沟槽中形成的第一电极层210可以隔离外围结构500与第一层间绝缘层741和第二层间绝缘层742之间的界面，防止去除多余的外围结构500的材料时对第一层间绝缘层741和第二层间绝缘层742造成损伤，从而提高半导体器件的可靠性，因此，在本实施例中，将步骤S410设置于步骤S520之前。
进一步地，第一电极层210可在沉积工艺的基础上结合平坦化工艺形成。例如，首先，采用物理气相沉积或化学气相沉积等工艺形成电极材料层于支撑层750的表面上、以及第一沟槽510和第二沟槽211中；然后，执行平坦化工艺以去除电极材料层中位于支撑层750上方的部分，从而只保留第一沟槽510和第二沟槽211中的电极材料层，以构成具有多个柱状结构的第一电 极层210。
在本实施例中，单元区域100A的接触节点110通过第二沟槽211暴露出来，从而使形成的第一电极层210的第一电极层210的柱状结构的底部能够与接触节点110电性连接。其中，第一电极层210的材料可以为多晶硅或金属。当第一电极层210的材料为金属时，还可以采用氮化钛和Ti层叠结构；当第一电极层210为多晶硅时，可以为零掺杂和/或掺杂的多晶硅。
S420：在外围结构500材料层的表面形成图形化的第四掩膜层150。具体地，图17为步骤S420后的半导体器件的剖面示意图，参考图17，在步骤S420后，第四掩膜层150中形成多个开口，且每个开口在衬底上的投影与多个柱状结构在衬底上的投影均部分重合，以去除各个的第一层间绝缘层741和第二层间绝缘层742并保留各个的支撑层750，第四掩膜层150中的多个开口用于在后续步骤中形成多个电容打开孔，以去除单元区域100A剩余的第一层间绝缘层741和第二层间绝缘层742。
S430：通过图形化的第四掩膜层150蚀刻去除单元区域100A的全部第一层间绝缘层741和第二层间绝缘层742和部分支撑层750，并去除高于第一电极层210的外围结构500材料层，剩余的外围结构500材料层作为外围结构500。
具体地，图18为步骤S430后的半导体器件的剖面示意图，图19为图18的半导体器件的单元区域100A的俯视示意图，在步骤S430后，在单元区域100A中形成了电容打开孔，参考图19，在本实施例中每个电容打开孔用于打开3个柱状结构的电容孔，且电容打开孔暴露部分衬底。在其他实施例中，每个电容打开孔也可以用于打开4个或4个以上的电容孔。
参考图18，通过电容打开孔可以去除单元区域100A的全部第一层间绝缘层741、全部第二层间绝缘层742和部分支撑层750，从而在后续步骤中沉积电容介质层220和第二电极层230，以形成双面的柱状电容，增大柱状电容的容值。剩余的支撑层750横向连接第一电极层210的多个柱状结构的外壁，以对第一电极层210进行支撑。具体地，顶部的支撑层750位于第一电极层210的多个柱状结构的顶部外围，中部的支撑层750位于第一电极层210的多个柱状结构的中间部位，以对第一电极层210进行有效的支撑。
S440：在第一电极层210的内表面和外表面形成电容介质层220。
S450：在电容介质层220的表面形成第二电极层230。
具体地，电容介质层220覆盖第一电极层210的第一电极层210的柱状结构的内表面和外表面，以充分利用第一电极层210的内表面和外表面，构成具有较大电极表面积的柱状电容。进一步地，电容介质层220的材料可以为金属氧化物等高K介质材料。进一步地，电容介质层220可以为叠层结构，例如氧化铪-氧化锆的双重结构。第二电极层230在对应第一电极层210的柱状结构的内部和第一电极层210的柱状结构的外部均能够与电容介质层220以及第一电极层210构成柱状电容。
进一步地，可以采用化学气相沉积工艺或原子层沉积工艺在第一电极层210的内表面和外表面以及各个支撑层750暴露出的表面形成电容介质层220；并在电容介质层220的内表面和外表面形成第二电极层230。本实施例中，电容介质层220和第二电极层230还依次延伸覆盖在外围区域100B上保留的支撑层750的表面上。
在其中一个实施例中，半导体器件的形成方法还包括步骤S600。
S600：在第二电极层230的表面形成电极填充层600，电极填充层600充满第二电极层230构成的间隙。
具体地，继续参考图1，图1即为步骤S600后的半导体器件的剖面示意图。可以采用化学气相沉积工艺在第二电极层230的表面形成电极填充层600，以使电极填充层600填满第二电极层230之间的间隙。进一步地，电极填充层600的材料可以为未掺杂或者硼掺杂的多晶硅。
在其中一个实施例中，半导体器件的形成方法还包括步骤S700。
S700：在第二电极层230上形成第二接触结构730，并在接触结构700上形成第三接触结构800，第二接触结构730和第三接触结构800同时形成。
具体地，在形成第三接触结构800前，还包括步骤S610：去除外围区域100B的电极填充层600，图20为步骤S610后的半导体器件的剖面示意图。进一步地，继续参考图3，图3即为步骤S700后的半导体器件的剖面示意图，可以先在电极填充层600、外围结构500和支撑层750的顶部形成第三层间绝缘层760，并在第三层间绝缘层760的表面形成图形化的第五掩膜层，第五掩膜层中形成有多个开口，开口暴露部分第三层间绝缘层760，部分开口在垂直方向上与位于顶部的中间金属层710部分重合，另一部分开口在垂直 方向上与电极填充层600部分重合；之后，通过图形化的第五掩膜层蚀刻第一层间绝缘层741和第二层间绝缘层742，以形成接触沟槽；然后，可以采用电镀或溅射工艺向各个接触沟槽中填充金属导电材料，并进一步通过化学机械平坦化工艺去除多余的金属导电材料，从而形成第四接触结构900和第三接触结构800。
应该理解的是，虽然图4至图5的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图4至图5中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种半导体器件，包括：
    衬底，所述衬底包括单元区域和外围区域；
    第一层间绝缘层和第二层间绝缘层，形成在所述单元区域和所述外围区域的所述衬底上，所述第一层间绝缘层和所述第二层间绝缘层沿垂直于所述衬底的方向间隔排布；
    柱状电容阵列，所述柱状电容阵列包括间隔排布的柱状电容，所述柱状电容形成在所述单元区域的所述第一层间绝缘层和所述第二层间绝缘层中；以及
    接触结构，所述接触结构形成在所述外围区域的所述第一层间绝缘层和所述第二层间绝缘层中。
  2. 根据权利要求1所述的半导体器件，其中所述接触结构包括互连的第一接触结构和第二接触结构，所述第一接触结构或所述第二接触结构通过贯穿所述第一层间绝缘层或所述第二层间绝缘层实现互连。
  3. 根据权利要求2所述的半导体器件，其中所述第一接触结构和所述第二接触结构垂直互连或错位互连。
  4. 根据权利要求1所述的半导体器件，其中还包括位于所述柱状电容阵列边缘的外围结构，所述外围结构形成在所述第一层间绝缘层和所述第二层间绝缘层中。
  5. 根据权利要求1所述的半导体器件，其中所述外围结构为周向闭合或断续结构。
  6. 根据权利要求2所述的半导体器件，其中所述第一层间绝缘层的表面和/或所述第二层间绝缘层的表面还形成有支撑层，所述支撑层的延伸方向与所述衬底表面的方向相平行，从而为所述第一层间绝缘层和所述第二层间绝缘层提供支撑；其中，所述第一层间绝缘层和所述第二层间绝缘层的厚度界定出后续所形成的所述支撑层的高度。
  7. 根据权利要求6所述的半导体器件，其中所述第一层间绝缘层中远离所述衬底的一侧还形成有：
    中间金属层，所述中间金属层的表面与所述第一层间绝缘层的表面相齐平；所述中间金属层和所述接触结构在垂直于所述衬底的方向上依次交替设 置，即，垂直于衬底的方向上依次排列有所述第一接触结构、所述中间金属层、所述第二接触结构及另一所述中间金属层；所述第一接触结构和所述第二接触结构通过所述中间金属层实现互连，所述第一接触结构贯穿所述第一层间绝缘层以向上连接至所述中间金属层，所述第二接触结构贯穿所述第二层间绝缘层和所述支撑层以向下连接至同一所述中间金属层，从而实现所述第一接触结构和所述第二接触结构的互连。
  8. 根据权利要求6所述的半导体器件，其中在所述第一层间绝缘层和所述第二层间绝缘层之外，至少还包括一个层间绝缘层，且每两个相邻的层间绝缘层之间均形成有所述支撑层，以适配所述柱状电容。
  9. 根据权利要求6所述的半导体器件，其中所述柱状电容阵列包括第一电极层、电容介质层和第二电极层，其中所述第一电极层、所述电容介质层和所述第二电极层均设置于所述单元区域：
    所述第一电极层包括呈阵列式排布的多个柱状结构；所述支撑层连接至所述第一电极层的所述多个柱状结构的外壁，以维持所述第一电极层的结构稳定；
    所述电容介质层覆盖所述第一电极层的内表面和外表面；并且
    所述第二电极层覆盖所述电容介质层的表面。
  10. 根据权利要求9所述的半导体器件，还包括：
    电极填充层，所述电极填充层覆盖所述第二电极层的表面，且充满所述第二电极层构成的间隙。
  11. 根据权利要求9所述的半导体器件，其中所述衬底中还形成有多个接触节点，所述第一电极层的所述多个柱状结构的底部与所述单元区域中的接触节点一一对应连接，所述第一接触结构与所述外围区域中的所述接触节点连接。
  12. 根据权利要求11所述的半导体器件，还包括第三接触结构和第四接触结构；所述第三接触结构的底部与所述第二电极层连接，所述第四接触结构的底部与所述接触结构连接；其中，所述第四接触结构的顶部与所述第三接触结构的顶部相齐平；所述第四接触结构通过所述第二电极层电连接至所述柱状电容，所述第三接触结构通过所述接触结构电连接至所述外围区域的所述接触节点。
  13. 一种半导体器件的形成方法，包括：
    提供衬底，所述衬底包括单元区域和外围区域；
    在所述衬底上形成第一层间绝缘层和第二层间绝缘层，所述第一层间绝缘层和所述第二层间绝缘层沿垂直于所述衬底的方向间隔排布；
    在所述外围区域的所述第一层间绝缘层和所述第二层间绝缘层中形成接触结构；
    在所述单元区域的所述第一层间绝缘层和所述第二层间绝缘层中形成柱状电容阵列，所述柱状电容阵列包括间隔排布的柱状电容。
  14. 根据权利要求13所述的形成方法，其中所述在所述外围区域的所述第一层间绝缘层和所述第二层间绝缘层中形成接触结构，包括：
    在所述外围区域的所述第一层间绝缘层和所述第二层间绝缘层中形成互连的第一接触结构和第二接触结构；
    其中，所述第一接触结构或所述第二接触结构通过贯穿所述第一层间绝缘层或所述第二层间绝缘层实现互连。
  15. 根据权利要求14所述的形成方法，其中所述在所述外围区域的所述第一层间绝缘层和所述第二层间绝缘层中形成互连的第一接触结构和第二接触结构，包括：
    在所述外围区域的所述第一层间绝缘层和所述第二层间绝缘层中形成垂直互连或错位互连的第一接触结构和第二接触结构。
  16. 根据权利要求13所述的形成方法，还包括：
    在所述第一层间绝缘层和所述第二层间绝缘层中形成外围结构，所述外围结构位于所述柱状电容阵列边缘。
  17. 根据权利要求16所述的形成方法，其中所述在所述第一层间绝缘层和所述第二层间绝缘层中形成外围结构，包括：
    在所述第一层间绝缘层和所述第二层间绝缘层中形成周向闭合或断续的外围结构。
  18. 根据权利要求13所述的形成方法，还包括：
    在所述第一层间绝缘层的表面和/或所述第二层间绝缘层的表面形成支撑层。
  19. 根据权利要求18所述的形成方法，所述衬底的所述单元区域和所述 外围区域中均形成有多个接触节点，且在所述单元区域中的所述多个接触节点呈阵列式排布。
  20. 根据权利要求19所述的形成方法，所述的在所述衬底上形成所述第一层间绝缘层和所述第二层间绝缘层；以及所述的在所述外围区域的所述第一层间绝缘层和所述第二层间绝缘层中形成所述接触结构包括：
    在所述第一层间绝缘层的表面形成图形化的第一掩膜层，用于形成第一接触结构沟槽；
    通过图形化的所述第一掩模层蚀刻所述第一层间绝缘层至所述接触节点的表面，并去除剩余的所述第一掩膜层；
    在所述第一接触结构沟槽中和所述第一层间绝缘层的面形成接触金属层，并去除所述第一层间绝缘层表面的所述接触金属层，剩余的所述接触金属层作为所述第一接触结构；
    在所述第一层间绝缘层的表面形成图形化的第二掩膜层，所述第二掩膜层中的开口在水平面内的尺寸大于所述接触节点的尺寸和所述第一接触结构的尺寸；
    通过图形化的所述第二掩膜层蚀刻所述第一层间绝缘层和所述第一接触结构至设定深度，并去除剩余的所述第二掩膜层；
    在所述第一层间绝缘层的沟槽中填充中间金属层，并在所述第一层间绝缘层的表面形成所述支撑层和所述第二层间绝缘层；以及
    重复前述步骤，以在所述外围区域形成所述第二接触结构和另一中间金属层。
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