WO2022052545A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2022052545A1
WO2022052545A1 PCT/CN2021/100413 CN2021100413W WO2022052545A1 WO 2022052545 A1 WO2022052545 A1 WO 2022052545A1 CN 2021100413 W CN2021100413 W CN 2021100413W WO 2022052545 A1 WO2022052545 A1 WO 2022052545A1
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Prior art keywords
layer
region
stack structure
substrate
manufacturing
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PCT/CN2021/100413
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English (en)
French (fr)
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刘欣然
孙玉乐
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长鑫存储技术有限公司
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Priority to US17/476,794 priority Critical patent/US20220085021A1/en
Publication of WO2022052545A1 publication Critical patent/WO2022052545A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same.
  • Dynamic Random Access Memory is widely used in mobile devices such as mobile phones and tablet computers due to its advantages of small size, high integration and fast transmission speed.
  • capacitor is mainly used to store electric charge.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies in the prior art, and to provide a semiconductor device and a manufacturing method thereof, which can prevent the failure of the capacitor and improve the stability of the capacitor.
  • a method for manufacturing a semiconductor device comprising:
  • the second region is patterned and etched, and the film stack structure in the second region is removed.
  • the etching of the film layer stack structure forms a first region including a through hole exposing the substrate and a first region including a hole segment not exposing the substrate Two areas, including:
  • the patterned etching of the second region to remove the film stack structure in the second region includes:
  • the photoresist layer is removed.
  • the etching of the film stack structure in the second region and the substrate facing the second region includes:
  • Dry etching is performed on the film layer stack structure in the second region by using an etching gas along a direction perpendicular to the film layer stack structure.
  • the etching gas includes at least one of carbon tetrafluoride gas or sulfur hexafluoride gas.
  • the first region is a central region of the film stack structure
  • the second region is an edge region of the film stack structure
  • the substrate facing the first region includes a plurality of storage node contact plugs, and each of the through holes can be in a one-to-one correspondence Each of the storage node contact plugs is exposed.
  • the manufacturing method further includes:
  • a capacitor array is formed in each of the through holes.
  • the film-layer stacking structure includes a support layer and a sacrificial layer that are overlapped in a direction perpendicular to the substrate, and the capacitor array is formed in each of the through holes, including :
  • a conductive layer covering the upper electrode layer is formed, and the conductive layer fills the gap between the through hole and two adjacent capacitors.
  • a semiconductor device prepared by the method for manufacturing a semiconductor device according to any one of the above.
  • the through holes in the first region are reserved, so that the capacitors formed subsequently can be contacted and connected to the substrate through the through holes, and the electricity of the capacitor can be stored in the substrate, so as to realize the capacitor storage;
  • the bottom of the capacitor is supported to prevent the capacitor from collapsing, which can improve the stability of the capacitor.
  • FIG. 1 is a flowchart of a method of fabricating a semiconductor device according to an embodiment of the disclosure.
  • FIG. 2 is a schematic diagram after completing step S110 of the manufacturing method of the present disclosure.
  • FIG. 3 is a schematic diagram after completing step S120 of the manufacturing method of the present disclosure.
  • FIG. 4 is a flowchart of step S120 in FIG. 1 .
  • FIG. 5 is a schematic diagram after step S1203 of the manufacturing method of the present disclosure is completed.
  • FIG. 6 is a schematic diagram after completing step S1204 of the manufacturing method of the present disclosure.
  • FIG. 7 is a schematic diagram after step S130 of the manufacturing method of the present disclosure is completed.
  • FIG. 8 is a flowchart of step S130 in FIG. 1 .
  • FIG. 9 is a schematic diagram after completing step S1301 of the manufacturing method of the present disclosure.
  • FIG. 10 is a schematic diagram after step S1303 of the manufacturing method of the present disclosure is completed.
  • FIG. 11 is a schematic diagram after completing step S140 of the manufacturing method of the present disclosure.
  • FIG. 12 is a flowchart of step S140 in FIG. 1 .
  • FIG. 13 is a schematic diagram after completing step S1401 of the manufacturing method of the present disclosure.
  • FIG. 14 is a schematic diagram after completing step S1402 of the manufacturing method of the present disclosure.
  • FIG. 15 is a schematic diagram after step S1404 of the manufacturing method of the present disclosure is completed.
  • Substrate 11. Storage node contact plug; 2. Membrane layer stacking structure; 211, Through hole; 221, Hole segment; 201, First sacrificial layer; 202, First support layer; 203, Second sacrificial layer; 204, second support layer; 3, mask material layer; 31, polymer layer; 32, oxide layer; 33, hard mask layer; 4, photoresist layer; 5, column capacitor; 51, lower electrode layer; 52, capacitor dielectric layer; 53, upper electrode layer; 6, bottom support layer; 7, conductive layer; A, first region; B, second region.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor device. As shown in FIG. 1 , the manufacturing method may include:
  • Step S110 providing a substrate, and forming a film stack structure on the substrate;
  • Step S120 etching the film stack structure to form a first region containing through holes exposing the substrate and a second region containing hole segments not exposing the substrate;
  • Step S130 the second region is patterned and etched, and the film stack structure in the second region is removed.
  • the hole segment in the second region is removed, no capacitor is formed in the hole segment, so after the sacrificial layer is removed, there is no dangling capacitor, which can prevent the capacitor from being suspended due to dangling
  • the failure also prevents the floating capacitor from collapsing due to no support at the bottom, and prevents short circuit between adjacent capacitors.
  • the through holes in the first region are reserved, so that the capacitors formed subsequently can be contacted and connected to the substrate through the through holes, and the electricity of the capacitor can be stored in the substrate, so as to realize the capacitor storage;
  • the bottom of the capacitor is supported to prevent the capacitor from collapsing, which can improve the stability of the capacitor.
  • step S110 a substrate is provided, and a film layer stack structure is formed on the substrate.
  • the substrate can have a flat plate structure, which can be rectangular, circular, oval, polygonal or irregular, and its material can be silicon or other semiconductor materials, and the shape and material of the substrate are not particularly limited herein.
  • the substrate may include a base 1 and a bottom support layer 6 formed on the surface of the base 1, a plurality of storage node contact plugs 11 distributed in an array are formed in the bottom support layer 6, and the storage node contact plugs 11 may be annular structures, and It can be made of conductor or semiconductor material, for example, the material can be tungsten, copper or polysilicon, etc.
  • the bottom support layer 6 may be provided with a plurality of via holes distributed in an array, each via hole may be a through hole, and the storage node contact plug 11 may be formed in the via hole, for example, by vacuum evaporation,
  • the storage node contact plugs 11 are formed in the via holes by means of magnetron sputtering or chemical vapor deposition.
  • the storage node contact plugs 11 may also be formed by other means, which will not be listed here.
  • a film stack structure 2 may be formed on the substrate, and the film stack structure 2 may include a single-layer film layer or a multi-layer film layer, which is not particularly limited herein.
  • the film layer stack structure 2 may include a plurality of film layers, for example, it may include a support layer and a sacrificial layer arranged in an overlapping manner, for example, it may include a first sacrificial layer 201, The first support layer 202 , the second sacrificial layer 203 and the second support layer 204 , wherein the first sacrificial layer 201 may be formed on the surface of the bottom support layer 6 .
  • the first sacrificial layer 201 , the first supporting layer 202 , the second sacrificial layer 203 and the second supporting layer 204 can be formed on the surface of the bottom supporting layer 6 by vacuum evaporation or magnetron sputtering.
  • the first sacrificial layer 201 , the first supporting layer 202 , the second sacrificial layer 203 and the second supporting layer 204 are formed in a stacked manner, which is not particularly limited here.
  • the first sacrificial layer 201 can be formed on the surface of the bottom support layer 6, and its material can be SiO2 ;
  • the first supporting layer 202 can be a thin film formed on the side of the first sacrificial layer 201 away from the substrate, and its material can be nitrogen Silicon carbide or SiCN;
  • the second sacrificial layer 203 can be formed on the side of the first support layer 202 away from the first sacrificial layer 201, and can be made of the same material as the first sacrificial layer 201, with the same thickness;
  • the second support layer 204 can be formed On the side of the second sacrificial layer 203 away from the first supporting layer 202, the material of the second sacrificial layer 203 can be the same as that of the first supporting layer 202, and the thicknesses of the first supporting layer 202 and the second supporting layer 204 can be the same or different. There is no special restriction on this.
  • step S120 the film stack structure is etched to form a first region including through holes exposing the substrate and a second region including hole segments not exposing the substrate.
  • the film stack structure 2 may have a first area A and a second area B distributed side by side, and the first area A and the second area B may be arranged adjacent to each other. There may be two second areas B, and the two second areas B may be located on both sides of the first area A, for example, the first area A may be the central area of the film stack structure 2, and the second area B may be is the edge region of the film stack structure 2 .
  • the film stack structure 2 can be etched to form a capacitor hole for depositing capacitors, the capacitor hole can extend in a direction perpendicular to the substrate, and its cross-sectional shape can be circular or rectangular, etc., or It is an irregular shape, and the shape of the capacitor hole is not specially limited here.
  • capacitor holes with different etching depths appear in different regions of the film stack structure 2, that is, the through holes 211 exposing the substrate can be formed in the first region A, and the through holes 211 can be formed in the first region A.
  • a hole segment 221 that does not expose the substrate is formed in the region B.
  • the structure after step S120 is completed is as shown in FIG. 3 .
  • the through holes 211 may be multiple, and the multiple through holes 211 may be distributed in an array.
  • the substrate facing the first area A may include a plurality of storage node contact plugs distributed in an array. 11. It should be noted that the number of the through holes 211 can be equal to the number of the storage node contact plugs 11, and each of the through holes 211 can expose the storage node contact plugs 11 in a one-to-one correspondence.
  • step S120 may include steps S1201-S1205, wherein:
  • Step S1201 forming a mask material layer on the side of the film stack structure away from the substrate.
  • a mask material layer can be formed on the side of the film stack structure 2 away from the substrate by chemical vapor deposition, vacuum evaporation, atomic layer deposition or other methods.
  • the mask material layer can have multiple layers or a single-layer structure.
  • the material may be at least one of polymer, SiO 2 , SiN, poly, and SiCN, and of course, other materials, which will not be listed here.
  • the mask material layer 3 can be a multi-layer, which can include a polymer layer 31, an oxide layer 32 and a hard mask layer, wherein the polymer layer 31 can be formed on the film layer.
  • the surface of the stack structure 2 facing away from the substrate, the oxide layer 32 may be located between the hard mask layer and the polymer layer 31 .
  • the polymer layer 31 can be formed on the surface of the film stack structure 2 away from the substrate by a chemical vapor deposition process, and an oxide layer 32 can be formed on the surface of the polymer layer 31 away from the film layer stack structure 2 by a vacuum evaporation process. The process forms a hard mask layer on the surface of oxide layer 32 facing away from polymer layer 31 .
  • Step S1202 forming a photoresist layer on the surface of the mask material layer away from the substrate.
  • the photoresist layer 4 can be formed on the surface of the mask material layer 3 away from the substrate by spin coating or other methods, and the material of the photoresist layer 4 can be positive photoresist or negative photoresist, which is not limited here. .
  • Step S1203 exposing and developing the photoresist layer to form a plurality of developing regions, each of which exposes the mask material layer.
  • the photoresist layer 4 can be exposed by using a mask, and the pattern of the mask can be matched with the pattern required by the layer stack structure 2 . Subsequently, the exposed photoresist layer 4 can be developed to form a plurality of developing areas, each developing area can expose the mask material layer 3 , and the pattern of the developing area can be the same as the pattern required by the film layer stack structure 2 Likewise, the width of the development area can be the same as the size of the desired capacitor hole.
  • the structure after step S1203 is completed is shown in FIG. 5 .
  • Step S1204 etching the mask material layer in the developing area to form a mask pattern.
  • the mask material layer 3 may be etched in the developing area by a plasma etching process, and the film stack structure 2 may be exposed in the etching area, thereby forming a desired mask pattern on the mask material layer 3 .
  • a mask pattern can be formed by one etching process, and when the mask material layer 3 is a multi-layer structure, each film layer can be etched in layers That is, one etching process can etch one layer, and multiple etching processes can be used to etch through the mask layer to form a mask pattern.
  • FIG. 6 shows the structure after completing step S1204 in the embodiment of the manufacturing method of the present disclosure.
  • Step S1205 perform anisotropic etching on the film stack structure according to the mask pattern, and use the substrate as an etching stop layer to form the film stack structure in the first region.
  • the through hole is formed, and the hole segment is formed in the film layer stack structure located in the second region.
  • the layer stack structure 2 can be etched anisotropically according to the mask pattern.
  • the layer stack structure 2 can be etched in the developing area of the mask pattern by a dry etching process, and the substrate can be etched.
  • As an etch stop layer a plurality of capacitor holes are formed in the film stack structure 2 .
  • the etching depths in different regions of the film stack structure 2 are different, so that a plurality of through holes 211 are formed in the film stack structure 2 located in the first region A, and a plurality of through holes 211 are formed in the film stack structure 2 located in the first region
  • One or more hole segments 221 are formed in the film layer stack structure 2 of the second region B, and the open end of each hole segment 221 facing away from the substrate can be flush with the open end of the through hole 211 facing away from the substrate, and it is close to the substrate.
  • the ends can be in either sacrificial layer. For example, its end near the substrate is located in the first sacrificial layer 201 .
  • each through hole 211 may be disposed in a one-to-one correspondence with each storage node contact plug 11 located in the first area A, and the open end of each through hole 211 near the substrate side may be corresponding to the storage node contact plug 11 corresponding thereto.
  • 3 shows the structure after step S1205 in the embodiment of the manufacturing method of the present disclosure is completed.
  • step S130 the second region is patterned and etched, and the film stack structure in the second region is removed.
  • the second region B can be patterned and etched by a photolithography process to remove the film stack structure 2 in the second region B, and only the film stack structure of the first region A is retained to prevent the formation of capacitors in the hole segment 221. , to avoid that the capacitor is in a suspended state after the sacrificial layer is removed, and the stored power cannot be stored to the storage node contact plug 11, resulting in failure of the capacitor;
  • the structure after step S130 is completed is shown in FIG. 7 .
  • step S130 may include steps S1301-S1303, wherein:
  • Step S1301 forming a photoresist layer on the surface of the first region.
  • a photoresist layer 4 can be formed on the surface of the hard mask layer 33 away from the substrate by spin coating, coating, chemical vapor deposition or other methods, and the photoresist layer 4 can be stacked with film layers.
  • the first area A of 2 is disposed directly opposite to prevent the first area A from being etched.
  • the material of the photoresist layer 4 may be positive photoresist or negative photoresist, which is not limited herein.
  • Step S1302 etch the film stack structure in the second region and the substrate facing the second region.
  • the film stack structure 2 and the substrate may be etched in the second region B by a plasma etching process to remove each hole segment 221 .
  • the film stack structure 2 and the substrate can be etched by an etching gas.
  • dry etching can be performed on the film stack structure 2 in the second region B along the direction perpendicular to the film layer stack structure 2, and the etching gas can chemically react with the material of the film layer stack structure 2, so as to remove the film layer stack structure 2 in the second region B.
  • the etching gas may be a single gas or a mixed gas of multiple gases, which is not particularly limited here.
  • the etching gas may include at least one of carbon tetrafluoride gas or sulfur hexafluoride gas, for example, it may be carbon tetrafluoride gas, sulfur hexafluoride gas, or tetrafluoride gas
  • the mixed gas of carbon dioxide gas and sulfur hexafluoride gas may also be other gases that can be used for etching the film stack structure 2 and the substrate, which will not be listed here.
  • Step S1303 removing the photoresist layer.
  • FIG. 10 shows the structure after completing step S1303 of the manufacturing method of the present disclosure.
  • the manufacturing method of the present disclosure may further include:
  • Step S140 forming a capacitor array in each of the through holes.
  • a capacitor array can be formed in each through hole 211 in the first region A by vacuum evaporation, magnetron sputtering, chemical vapor deposition or atomic layer deposition, etc.
  • the capacitor array can include a plurality of spaced arrangements
  • the columnar capacitors 5 and the conductor layer 7 covering the surface of each capacitor array, each columnar capacitor 5 can be contacted and connected to each storage node contact plug 11 respectively, when in use, a plurality of capacitors can be charged and discharged at the same time, thereby increasing the capacitance,
  • the conductive layer 7 can be in contact with the capacitor array in order to electrically extract the capacitors.
  • Each column capacitor 5 may include a lower electrode layer 51 , a capacitor dielectric layer 52 and an upper electrode layer 53 , wherein the lower electrode layer 51 is in the shape of a strip, which can be formed on the wall and bottom of the through hole 211 , and can be located in the storage
  • the side of the node contact plug 11 facing away from the substrate, the lower electrode layer 51 can be in contact with the storage node contact plug 11, and it can be directed to the side of the storage node contact plug 11 facing away from the substrate along the direction perpendicular to the storage node contact plug 11 extended so as to form the columnar capacitor 5 .
  • the capacitor dielectric layer 52 is located between the lower electrode layer 51 and the upper electrode layer 53, and can form a double-sided capacitor, so as to improve the capacitance.
  • Each support layer can be wrapped around the outer periphery of the lower electrode layer 51 , can support the lower electrode layer 51 laterally, increase the stability of the lower electrode layer 51 in the lateral direction, and prevent the lower electrode layer 51 from being deformed laterally
  • step S140 may include steps S1401-S1405, as shown in FIG. 12, wherein:
  • step S1401 a lower electrode layer is formed in each of the through holes, and the lower electrode layer is in contact and connected with the storage node contact plug.
  • the through hole 211 can be used as a capacitor hole, and the lower electrode layer 51 can be formed on the sidewall of the through hole 211 .
  • a lower electrode layer 51 that conforms to the bottom of the capacitor hole and the surface of the sidewall can be formed in the capacitor hole.
  • the lower electrode layer 51 can be formed in the capacitor hole and its top surface at the same time.
  • the bottom electrode layer 51 on the top surface of the capacitor hole is removed, and only the bottom electrode layer 51 on the bottom and sidewalls is left.
  • the final structure of the bottom electrode layer 51 is shown in FIG. 13 .
  • the lower electrode layer 51 may be in contact with the storage node contact plug 11 through a capacitor hole, so as to input the electricity stored in the lower electrode layer 51 to the storage dielectric contact plug, thereby realizing capacitor storage.
  • the chemical vapor deposition process can be used to form the lower electrode layer 51 in the capacitor hole.
  • the lower electrode layer 51 can also be formed by other processes.
  • the material of the lower electrode layer 51 can be titanium nitride, and of course, it can also be For other materials that can be used as electrodes, the material and forming process of the lower electrode layer 51 are not particularly limited here.
  • Step S1402 removing each of the sacrificial layers.
  • each sacrificial layer in the first region A can be removed, and each supporting layer can be retained, which can not only increase the storage density of the capacitor, but also support the lower electrode layer 51, so as to avoid the lower electrode layer 51.
  • the electrode layer 51 is deformed outward to reduce the risk of short circuit.
  • Step S1403 forming a capacitor dielectric layer on the surface of the structure formed by the lower electrode layer and the support layer.
  • a capacitor dielectric layer 52 may be formed on the lower electrode layer 51 in the capacitor hole in the first region A.
  • the capacitor dielectric layer 52 may be a thin film formed on the surface of the lower electrode layer 51 , which The capacitor dielectric layer 52 is formed by processes such as vacuum evaporation or magnetron sputtering. Of course, the capacitor dielectric layer 52 can also be formed by other processes, which will not be listed here.
  • the capacitor dielectric layer 52 may be a single-layer film structure composed of the same material, or may be a mixed film-layer structure composed of film layers of different materials.
  • it may include a material with a higher dielectric constant, for example, it may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, or mixtures thereof, of course, It can also be other materials, which will not be listed one by one here.
  • a material with a higher dielectric constant for example, it may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, or mixtures thereof, of course, It can also be other materials, which will not be listed one by one here.
  • Step S1404 forming an upper electrode layer on the surface of the capacitor dielectric layer facing away from the lower electrode layer.
  • the upper electrode layer 53 may be formed on the outer surface of the capacitor dielectric layer 52 by a chemical vapor deposition process. Of course, the upper electrode layer 53 may also be formed by other processes, which are not limited herein.
  • the material of the upper electrode layer 53 can be titanium nitride, of course, can also be other materials, which will not be listed one by one here. In the embodiment of the manufacturing method of the present disclosure, the structure after step S1404 is completed is shown in FIG. 15 .
  • Step S1405 forming a conductive layer covering the upper electrode layer, the conductive layer filling the capacitor hole and the gap between two adjacent capacitors.
  • the conductive layer 7 can be formed on the surface of the upper electrode layer 53 by a vacuum evaporation process, so that the electric charges can be fully contacted with the upper electrode layer 53 , which helps to improve the capacitor charging efficiency.
  • the conductive layer 7 can cover the surface of the upper electrode layer 53 and can fill the through hole 211 and the gap between two adjacent capacitors, which can not only lead the capacitors electrically, but also enhance the stability of each capacitor in the capacitor array.
  • the conductive layer 7 can be composed of silicon material, metal material or metal compound, for example, it can be silicon, silicon germanium, tungsten, titanium silicide, titanium oxide or tungsten oxide, etc., which are not limited herein.
  • Embodiments of the present disclosure also provide a semiconductor device, which can be fabricated by the method for manufacturing a semiconductor device in any of the foregoing embodiments.
  • the semiconductor device can be a memory chip, for example, a DRAM (Dynamic Random Access Memory, dynamic random access memory), of course, can also be other semiconductor devices, which will not be listed here.
  • DRAM Dynamic Random Access Memory, dynamic random access memory
  • the beneficial effects of the semiconductor device reference may be made to the aforementioned beneficial effects of the hard mask structure, which will not be repeated here.

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Abstract

一种半导体器件及其制造方法，涉及半导体技术领域。该制造方法包括：提供衬底（1），在所述衬底（1）上形成膜层堆叠结构（2）；刻蚀所述膜层堆叠结构（2），形成含有露出所述衬底（1）的通孔（221）的第一区域（A）及含有未露出所述衬底（1）的孔段的第二区域（B）；图形化刻蚀所述第二区域（B），去除所述第二区域（B）内的所述膜层堆叠结构（2）。该半导体器件的制造方法可防止电容失效，提高电容稳定性。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请要求于2020年09月14日递交的、名称为《半导体器件及其制造方法》的中国专利申请第202010962311.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种半导体器件及其制造方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)因具有体积小、集成化程度高及传输速度快等优点，被广泛应用于手机、平板电脑等移动设备中。电容器作为动态随机存储器的核心部件，主要用于存储电荷。
通常在制造电容器的过程中，需要在衬底上形成交叠设置的支撑层和牺牲层，刻蚀支撑层和牺牲层以形成用于容纳电容器的孔状结构，在形成电容器后再去除牺牲层。然而，受制备工艺限制，使得不同刻蚀区域的膜层刻蚀深度不一，去除牺牲层后，部分电容因悬空而失效。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术中的不足，提供一种半导体器件及其制造方法，可防止电容失效，提高电容稳定性。
根据本公开的一个方面，提供一种半导体器件的制造方法，包括：
提供衬底，在所述衬底上形成膜层堆叠结构；
刻蚀所述膜层堆叠结构，形成含有露出所述衬底的通孔的第一区域及含有未露出所述衬底的孔段的第二区域；
图形化刻蚀所述第二区域，去除所述第二区域内的所述膜层堆叠结构。
在本公开的一种示例性实施例中，所述刻蚀所述膜层堆叠结构，形成含有露出所述衬底的通孔的第一区域及含有未露出所述衬底的孔段的第二区域，包括：
在所述膜层堆叠结构背离所述衬底的一侧形成掩膜材料层；
在所述掩膜材料层背离所述衬底的表面形成光刻胶层；
对所述光刻胶层进行曝光并显影，形成多个显影区，各所述显影区露出所述掩膜材料层；
在所述显影区对所述掩膜材料层进行刻蚀，以形成掩膜图案；
根据所述掩膜图案对所述膜层堆叠结构进行非等向刻蚀，并以所述衬底为刻蚀停止层，在位于所述第一区域的膜层堆叠结构中形成所述通孔，在位于所述第二区域的膜层堆叠结构中形成所述孔段。
在本公开的一种示例性实施例中，所述图形化刻蚀所述第二区域，去除所述第二区域内的所述膜层堆叠结构，包括：
在所述第一区域的表面形成光刻胶层；
刻蚀所述第二区域的所述膜层堆叠结构及与所述第二区域正对的衬底；
去除所述光刻胶层。
在本公开的一种示例性实施例中，所述刻蚀所述第二区域的所述膜层堆叠结构及与所述第二区域正对的衬底，包括：
沿垂直于所述膜层堆叠结构的方向对所述第二区域的膜层堆叠结构采用刻蚀气体进行干法刻蚀。
在本公开的一种示例性实施例中，所述刻蚀气体包括四氟化碳气体或六氟化硫气体中至少一种。
在本公开的一种示例性实施例中，所述第一区域为所述膜层堆叠结构的中心区域，所述第二区域为所述膜层堆叠结构的边缘区域。
在本公开的一种示例性实施例中，所述通孔为多个，与所述第一区域正对的衬底包括多个存储节点接触塞，且各所述通孔能一一对应的露出各所述存储节点接触塞。
在本公开的一种示例性实施例中，所述制造方法还包括：
在各所述通孔中形成电容阵列。
在本公开的一种示例性实施例中，所述膜层堆叠结构包括沿垂直于衬底的方向交叠设置的支撑层和牺牲层，所述在各所述通孔中形成电容阵列，包括：
在各所述通孔中形成下电极层，所述下电极层与所述存储节点接触塞接触连接；
去除各所述牺牲层；
在所述下电极层和所述支撑层共同构成的结构的表面形成电容介质层；
在所述电容介质层背离所述下电极层的表面形成上电极层；
形成覆盖所述上电极层的导电层，所述导电层充满所述通孔及相邻两个电容之间的间隙。
根据本公开的一个方面，提供一种半导体器件，所述半导体器件由上述任一项所述的半导体器件的制造方法制备。
本公开的半导体器件及其制造方法，在去除第二区域中的孔段后，不会在孔段中形成电容，因而在去除牺牲层后，不会有悬空的电容存在，进而可防止电容因悬空而失效，也避免了悬空的电容因底部无支撑而倒塌，防止相邻电容间发生短路。此外，保留了第一区域中的通孔，使得后续形成的电容可通过通孔与衬底接触连接，可将电容的电量存储至衬底中，从而实现电容存储；同时，可通过衬底对电容底部进行支撑，防止电容倒塌，可提高电容稳定性。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施方式半导体器件的制造方法的流程图。
图2为完成本公开制造方法的步骤S110后的示意图。
图3为完成本公开制造方法的步骤S120后的示意图。
图4为图1中步骤S120的流程图。
图5为完成本公开制造方法的步骤S1203后的示意图。
图6为完成本公开制造方法的步骤S1204后的示意图。
图7为完成本公开制造方法的步骤S130后的示意图。
图8为图1中步骤S130的流程图。
图9为完成本公开制造方法的步骤S1301后的示意图。
图10为完成本公开制造方法的步骤S1303后的示意图。
图11为完成本公开制造方法的步骤S140后的示意图。
图12为图1中步骤S140的流程图。
图13为完成本公开制造方法的步骤S1401后的示意图。
图14为完成本公开制造方法的步骤S1402后的示意图。
图15为完成本公开制造方法的步骤S1404后的示意图。
图中：1、基底；11、存储节点接触塞；2、膜层堆叠结构；211、通孔；221、孔段；201、第一牺牲层；202、第一支撑层；203、第二牺牲层；204、第二支撑层；3、掩膜材料层；31、聚合物层；32、氧化层；33、硬掩模层；4、光刻胶层；5、柱状电容；51、下电极层；52、电容介质层；53、上电极层；6、底部支撑层；7、导电层；A、第一区域；B、第二区域。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本发明将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
上述所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中，如有可能，各实施例中所讨论的特征是可互换的。在上面的描述中，提供许多具体细节从而给出对本发明的实施方式的充 分理解。然而，本领域技术人员将意识到，可以实践本发明的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本发明的各方面。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”仅作为标记使用，不是对其对象的数量限制。
本公开实施方式提供了一种半导体器件的制造方法，如图1所示，该制造方法可以包括：
步骤S110，提供衬底，在所述衬底上形成膜层堆叠结构；
步骤S120，刻蚀所述膜层堆叠结构，形成含有露出所述衬底的通孔的第一区域及含有未露出所述衬底的孔段的第二区域；
步骤S130，图形化刻蚀所述第二区域，去除所述第二区域内的所述膜层堆叠结构。
本公开的半导体器件的制造方法，在去除第二区域中的孔段后，不会在孔段中形成电容，因而在去除牺牲层后，不会有悬空的电容存在，进而可防止电容因悬空而失效，也避免了悬空的电容因底部无支撑而倒塌，防止相邻电容间发生短路。此外，保留了第一区域中的通孔，使得后续形成的电容可通过通孔与衬底接触连接，可将电容的电量存储至衬底中，从而实现电容存储；同时，可通过衬底对电容底部进行支撑，防止电容倒塌，可提高电容稳定性。
下面对本公开实施方式半导体器件的制造方法的各步骤进行详细说明：
在步骤S110中，提供衬底，在所述衬底上形成膜层堆叠结构。
衬底可呈平板结构，其可为矩形、圆形、椭圆形、多边形或不规则图形，其材料可以是硅或其他半导体材料，在此不对衬底的形状及材料做特殊限定。
衬底可包括基底1和形成于基底1表面的底部支撑层6，该底部支撑层6内形成有多个呈阵列分布的存储节点接触塞11，该存储节点接触塞11可为环形结构，且可由导体或半导体材料构成，例如，其材料可以是钨、铜或聚硅等。
举例而言，底部支撑层6内可设有多个呈阵列分布的过孔，各过孔均可为通孔，可在过孔内形成存储节点接触塞11，例如，可通过真空蒸镀、磁控溅射或化学气相沉积等方式在过孔内形成存储节点接触塞11，当然，还可以通过其他方式形成存储节点接触塞11，在此不再一一列举。
如图2所示，可在衬底上形成膜层堆叠结构2，膜层堆叠结构2可以包括单层膜层，也可以包括多层膜层，在此不做特殊限定。在一实施方式中，膜层堆叠结构2可包括多层膜层，举例而言，其可包括交叠设置支撑层和牺牲层，例如，其可包括依次叠层设置的第一牺牲层201、第一支撑层202、第二牺牲层203和第二支撑层204，其中，第一牺牲层201可形成于底部支撑层6的表面。
可通过真空蒸镀或磁控溅射等方式在底部支撑层6的表面形成第一牺牲层201、第一支撑层202、第二牺牲层203和第二支撑层204，当然，也可通过其他方式形成叠层设置的第一牺牲层201、第一支撑层202、第二牺牲层203和第二支撑层204，在此不做特殊限定。
第一牺牲层201可形成于底部支撑层6的表面，其材料可以是SiO 2；第一支撑层202可以是形成于第一牺牲层201背离衬底的一侧的薄膜，其材料可以是氮化硅或SiCN；第二牺牲层203可形成于第一支撑层202背离第一牺牲层201的一侧，并可与第一牺牲层201的材料相同，厚度相等；第二支撑层204可形成于第二牺牲层203层背离第一支撑层202 的一侧，其可与第一支撑层202的材料相同，第一支撑层202与第二支撑层204的厚度可以相同，也可以不同，在此不做特殊限定。
在步骤S120中，刻蚀所述膜层堆叠结构，形成含有露出所述衬底的通孔的第一区域及含有未露出所述衬底的孔段的第二区域。
如图2所示，膜层堆叠结构2可具有并排分布的第一区域A和第二区域B，且第一区域A和第二区域B可相互邻接设置。第二区域B可以有两个，两个第二区域B可分别位于第一区域A的两侧，举例而言，第一区域A可为膜层堆叠结构2的中心区域，第二区域B可为膜层堆叠结构2的边缘区域。
可对膜层堆叠结构2进行刻蚀，以形成用于沉积电容的电容孔，该电容孔可沿垂直于衬底的方向延伸，且其横截面的形状可以是圆形或矩形等，还可以是不规则形状，在此不对电容孔的形状做特殊限定。
在刻蚀过程中，受刻蚀工艺限制，在膜层堆叠结构2的不同区域出现不同刻蚀深度的电容孔，即：可在第一区域A形成露出衬底的通孔211，在第二区域B形成未露出衬底的孔段221，在本公开制造方法的实施方式中，完成步骤S120后的结构如图3所示。
在一实施方式中，通孔211可为多个，多个通孔211可呈阵列分布，与此同时，与第一区域A正对的衬底可包括多个呈阵列分布的存储节点接触塞11，需要说明的是，通孔211的数量可与存储节点接触塞11的数量相等，且各通孔211能一一对应的露出各存储节点接触塞11。
在本公开的一种实施方式中，如图4所示，步骤S120可以包括步骤S1201-步骤S1205，其中：
步骤S1201，在所述膜层堆叠结构背离所述衬底的一侧形成掩膜材料层。
可通过化学气相沉积、真空蒸镀、原子层沉积或其它方式在膜层堆叠结构2背离衬底的一侧形成掩膜材料层，掩膜材料层可以有多层，也可以为单层结构，其材料可以是聚合物、SiO 2、SiN、poly和SiCN中至少一种，当然，也可以是其它材料，在此不再一一列举。
在一实施方式中，如图5所示，掩膜材料层3可为多层，其可以包括聚合物层31、氧化层32和硬掩膜层，其中，聚合物层31可形成于膜 层堆叠结构2背离衬底的表面，氧化层32可位于硬掩膜层和聚合物层31之间。可通过化学气相沉积工艺在膜层堆叠结构2背离衬底的表面形成聚合物层31，通过真空蒸镀工艺在聚合物层31背离膜层堆叠结构2的表面形成氧化层32，通过原子层沉积工艺在氧化层32背离聚合物层31的表面形成硬掩膜层。
步骤S1202，在所述掩膜材料层背离所述衬底的表面形成光刻胶层。
可通过旋涂或其它方式在掩膜材料层3背离衬底的表面形成光刻胶层4，光刻胶层4材料可以是正性光刻胶或负性光刻胶，在此不做特殊限定。
步骤S1203，对所述光刻胶层进行曝光并显影，形成多个显影区，各所述显影区露出所述掩膜材料层。
可采用掩膜版对光刻胶层4进行曝光，该掩膜版的图案可与膜层堆叠结构2所需的图案匹配。随后，可对曝光后的光刻胶层4进行显影，从而形成多个显影区，每个显影区可露出掩膜材料层3，且显影区的图案可与膜层堆叠结构2所需的图案相同，显影区的宽度可与所需的电容孔的尺寸相同。在本公开制造方法的实施方式中，完成步骤S1203后的结构如图5所示。
步骤S1204，在所述显影区对所述掩膜材料层进行刻蚀，以形成掩膜图案。
可通过等离子刻蚀工艺在显影区对掩膜材料层3进行刻蚀，刻蚀区域可露出膜层堆叠结构2，从而在掩膜材料层3上形成所需的掩膜图案。需要说明的是，当掩膜材料层3为单层结构时，可采用一次刻蚀工艺形成掩膜图案，当掩膜材料层3为多层结构时，可对各膜层进行分层刻蚀，即：一次刻蚀工艺可刻蚀一层，可采用多次刻蚀工艺将掩膜层刻透，以形成掩膜图案。
需要说明的是，在完成上述刻蚀工艺后，可通过清洗液清洗或通过灰化等工艺去除光刻胶层4，使掩膜材料层3不再被光刻胶层4覆盖，将形成的掩膜层暴露出来，得到硬掩膜结构。图6示出了完成本公开制造方法的实施方式中步骤S1204后的结构。
步骤S1205，根据所述掩膜图案对所述膜层堆叠结构进行非等向刻蚀，并以所述衬底为刻蚀停止层，在位于所述第一区域的膜层堆叠结构中形成所述通孔，在位于所述第二区域的膜层堆叠结构中形成所述孔段。
可根据掩膜图案对膜层堆叠结构2进行非等向刻蚀，举例而言，可通过干法刻蚀工艺在掩膜图案的显影区对膜层堆叠结构2进行刻蚀，并以衬底作为刻蚀停止层，在膜层堆叠结构2内形成多个电容孔。在此过程中，由于制作工艺限制，在膜层堆叠结构2的不同区域的刻蚀深度不一，从而在位于第一区域A的膜层堆叠结构2中形成多个通孔211，在位于第二区域B的膜层堆叠结构2中形成一个或多个孔段221，且各孔段221背离衬底的开放端可与通孔211背离衬底的开放端平齐，且其靠近衬底的端部可位于任一牺牲层中。例如，其靠近衬底的端部位于第一牺牲层201中。
当第一区域A为膜层堆叠结构2的中心区域，第二区域B为膜层堆叠结构2的边缘区域时，可在膜层堆叠结构2的边缘形成多个未露出衬底的孔段221，在膜层堆叠结构2的中心形成多个呈阵列分布的通孔211。举例而言，各通孔211可与位于第一区域A的各存储节点接触塞11一一对应设置，且各通孔211靠近衬底一侧的开放端可与与其对应的存储节点接触塞11的表面接触，以便于在通孔211中形成电容后，通过存储节点接触塞11对电容中的电荷进行存储，图3示出了完成本公开制造方法的实施方式中步骤S1205后的结构。
在步骤S130中，图形化刻蚀所述第二区域，去除所述第二区域内的所述膜层堆叠结构。
可采用光刻工艺对第二区域B进行图形化刻蚀，以去除第二区域B内的膜层堆叠结构2，只保留第一区域A的膜层堆叠结构，防止在孔段221中形成电容，避免在去除牺牲层后电容处于悬空状态，而无法将存储的电量存储至存储节点接触塞11，导致电容失效；同时，也避免了因电容悬空而倒塌，防止相邻电容间发生短路，在本公开制造方法的实施方式中，完成步骤S130后的结构如图7所示。
在本公开的一种实施方式中，如图8所示，步骤S130可以包括步骤 S1301-步骤S1303，其中：
步骤S1301，在所述第一区域的表面形成光刻胶层。
如图9所示，可通过旋涂、涂布、化学气相沉积或其它方式在硬掩模层33背离衬底的表面形成光刻胶层4，该光刻胶层4可与膜层堆叠结构2的第一区域A正对设置，防止第一区域A被刻蚀。光刻胶层4材料可以是正性光刻胶或负性光刻胶，在此不做特殊限定。
步骤S1302刻蚀所述第二区域的所述膜层堆叠结构及与所述第二区域正对的衬底。
可通过等离子刻蚀工艺在第二区域B对膜层堆叠结构2及衬底进行刻蚀，以去除各孔段221。例如，可通过刻蚀气体对膜层堆叠结构2及衬底进行刻蚀。例如，可沿垂直于膜层堆叠结构2的方向对第二区域B的膜层堆叠结构2进行干法刻蚀，通过刻蚀气体与膜层堆叠结构2的材料进行化学反应，从而去除位于第二区域B的膜层堆叠结构2。刻蚀气体可以是单一气体，也可以是多种气体的混合气体，在此不做特殊限定。
举例而言，刻蚀气体可以包括四氟化碳气体或六氟化硫气体中至少一种，例如，其可以是四氟化碳气体，也可以是六氟化硫气体，还可以是四氟化碳气体和六氟化硫气体的混合气体，当然，刻蚀气体还可以是其他能够用于刻蚀膜层堆叠结构2及衬底的气体，在此不再一一列举。
步骤S1303，去除所述光刻胶层。
在完成上述刻蚀工艺后，可通过清洗液清洗或通过灰化等工艺去除光刻胶层4，使第一区域A不再被光刻胶层4覆盖，同时去除硬掩模层33，将形成的膜层堆叠结构2暴露出来。图10示出了完成本公开制造方法的步骤S1303后的结构。
如图1所示，本公开的制造方法还可以包括：
步骤S140，在各所述通孔中形成电容阵列。
可通过真空蒸镀、磁控溅射、化学气相沉积或原子层沉积等方式在第一区域A的各通孔211中形成电容阵列，如图11所示，电容阵列可包括多个间隔排布的柱状电容5以及覆盖于各电容阵列表面的导电体层7，各柱状电容5可分别与各存储节点接触塞11接触连接，在使用时， 多个电容可同时充放电，从而提高电容量，导电层7可与电容阵列接触，以便将电容电学引出。
每个柱状电容5均可包括下电极层51、电容介质层52及上电极层53，其中，下电极层51呈条状，其可形成于通孔211的孔壁及底部，且可位于存储节点接触塞11背离衬底的一侧，下电极层51可与存储节点接触塞11接触连接，且其可沿垂直于存储节点接触塞11的方向向存储节点接触塞11背离衬底的一侧延伸，以便形成柱状电容5。电容介质层52位于下电极层51和上电极层53之间，可形成双面电容，以便于提高电容量。各支撑层可包覆于下电极层51的外周，可对下电极层51进行横向支撑，增加下电极层51在横向上的稳定性，防止下电极层51产生横向形变。
在本公开的一种实施方式中，在各所述通孔211中形成电容阵列，即：步骤S140可以包括步骤S1401-步骤S1405，如图12所示，其中：
步骤S1401，在各所述通孔中形成下电极层，所述下电极层与所述存储节点接触塞接触连接。
通孔211可作为电容孔，可在通孔211的侧壁形成下电极层51。具体而言，可在电容孔内形成随形贴合于电容孔底部及侧壁表面的下电极层51，为了工艺方便，可在电容孔内和其顶表面同时形成下电极层51，随后可去除电容孔顶表面的下电极层51，只保留其底部及侧壁上的下电极层51，最终形成的下电极层51的结构如图13所示。此外，下电极层51可通过电容孔与存储节点接触塞11接触连接，以将下电极层51存储的电量输入至存储介电接触塞，从而实现电容存储。
举例而言，可采用化学气相沉积工艺在电容孔中形成下电极层51，当然，还可通过其他工艺形成下电极层51，下电极层51的材料可以是氮化钛，当然，也可以是其他可以作为电极的材料，在此不对下电极层51的材料及形成工艺做特殊限定。
步骤S1402，去除各所述牺牲层。
如图14所示，在形成下电极层51后可去除第一区域A内各牺牲层，而保留各支撑层，既可增大电容存储密度，又可对下电极层51进行支撑，避免下电极层51向外发生形变，降低短路风险。
步骤S1403，在所述下电极层和所述支撑层共同构成的结构的表面形成电容介质层。
如图15所示，可在第一区域A的电容孔内的下电极层51上形成电容介质层52，举例而言，电容介质层52可以是形成于下电极层51表面上的薄膜，可通过真空蒸镀或磁控溅射等工艺形成电容介质层52，当然，还可以通过其他工艺形成电容介质层52，在此不再一一列举。电容介质层52可以是由同一种材料构成的单层膜结构，也可以是由不同材质的膜层构成的混合膜层结构。举例而言，其可包括具有较高介电常数的材料，例如，其可以是氧化铝、氧化铪、氧化镧、氧化钛、氧化锆、氧化钽、氧化铌、氧化锶或其混合物，当然，还可以是其他材料，在此不再一一列举。
步骤S1404，在所述电容介质层背离所述下电极层的表面形成上电极层。
可采用化学气相沉积工艺在电容介质层52的外表面形成上电极层53，当然，还可通过其他工艺形成上电极层53，在此不做特殊限定。上电极层53的材料可以是氮化钛，当然，还可以是其他材料，在此不再一一列举。在本公开制造方法的实施方式中，完成步骤S1404后的结构如图15所示。
步骤S1405，形成覆盖所述上电极层的导电层，所述导电层充满所述电容孔及相邻两个电容之间的间隙。
如图11所示，可通过真空蒸镀工艺在上电极层53的表面形成导电层7，以使电荷与上电极层53充分接触，有助于提高电容充电效率。该导电层7可覆盖于上电极层53的表面，且可充满通孔211及相邻两个电容之间的间隙，既可将电容电学引出，又可加强电容阵列中各电容的稳定性。导电层7可由硅材料、金属材料或金属化合物构成，举例而言，其可以是硅、锗硅、钨、硅化钛、氧化钛或氧化钨等，在此不做特殊限定。
本公开实施还提供一种半导体器件，该半导体器件可由上述任一实施方式的半导体器件的制造方法制备而成。
上述半导体器件中各部分的具体细节及制造工艺已经在对应的半导 体器件的制造方法中进行了详细描述，因此，此处不再赘述。该半导体器件可以是存储芯片，例如，DRAM(Dynamic Random Access Memory，动态随机存取存储器)，当然，还可以是其它半导体器件，在此不再一一列举。该半导体器件的有益效果可参考上述的硬掩膜结构的有益效果，在此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (10)

  1. 一种半导体器件的制造方法，其中，包括：
    提供衬底，在所述衬底上形成膜层堆叠结构；
    刻蚀所述膜层堆叠结构，形成含有露出所述衬底的通孔的第一区域及含有未露出所述衬底的孔段的第二区域；
    图形化刻蚀所述第二区域，去除所述第二区域内的所述膜层堆叠结构。
  2. 根据权利要求1所述的制造方法，其中，所述刻蚀所述膜层堆叠结构，形成含有露出所述衬底的通孔的第一区域及含有未露出所述衬底的孔段的第二区域，包括：
    在所述膜层堆叠结构背离所述衬底的一侧形成掩膜材料层；
    在所述掩膜材料层背离所述衬底的表面形成光刻胶层；
    对所述光刻胶层进行曝光并显影，形成多个显影区，各所述显影区露出所述掩膜材料层；
    在所述显影区对所述掩膜材料层进行刻蚀，以形成掩膜图案；
    根据所述掩膜图案对所述膜层堆叠结构进行非等向刻蚀，并以所述衬底为刻蚀停止层，在位于所述第一区域的膜层堆叠结构中形成所述通孔，在位于所述第二区域的膜层堆叠结构中形成所述孔段。
  3. 根据权利要求1所述的制造方法，其中，所述图形化刻蚀所述第二区域，去除所述第二区域内的所述膜层堆叠结构，包括：
    在所述第一区域的表面形成光刻胶层；
    刻蚀所述第二区域的所述膜层堆叠结构及与所述第二区域正对的衬底；
    去除所述光刻胶层。
  4. 根据权利要求3所述的制造方法，其中，所述刻蚀所述第二区域的所述膜层堆叠结构及与所述第二区域正对的衬底，包括：
    沿垂直于所述膜层堆叠结构的方向对所述第二区域的膜层堆叠结构采用刻蚀气体进行干法刻蚀。
  5. 根据权利要求4所述的制造方法，其中，所述刻蚀气体包括四氟化碳气体或六氟化硫气体中至少一种。
  6. 根据权利要求1所述的制造方法，其中，所述第一区域为所述膜层堆叠结构的中心区域，所述第二区域为所述膜层堆叠结构的边缘区域。
  7. 根据权利要求1所述的制造方法，其中，所述通孔为多个，与所述第一区域正对的衬底包括多个存储节点接触塞，且各所述通孔能一一对应的露出各所述存储节点接触塞。
  8. 根据权利要求7所述的制造方法，其中，所述制造方法还包括：
    在各所述通孔中形成电容阵列。
  9. 根据权利要求8所述的制造方法，其中，所述膜层堆叠结构包括沿垂直于衬底的方向交叠设置的支撑层和牺牲层，所述在各所述通孔中形成电容阵列，包括：
    在各所述通孔中形成下电极层，所述下电极层与所述存储节点接触塞接触连接；
    去除各所述牺牲层；
    在所述下电极层和所述支撑层共同构成的结构的表面形成电容介质层；
    在所述电容介质层背离所述下电极层的表面形成上电极层；
    形成覆盖所述上电极层的导电层，所述导电层充满所述通孔及相邻两个电容之间的间隙。
  10. 一种半导体器件，其中，所述半导体器件由权利要求1-9任一项所述的半导体器件的制造方法制备。
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