WO2022205659A1 - 半导体结构制作方法及半导体结构 - Google Patents

半导体结构制作方法及半导体结构 Download PDF

Info

Publication number
WO2022205659A1
WO2022205659A1 PCT/CN2021/104782 CN2021104782W WO2022205659A1 WO 2022205659 A1 WO2022205659 A1 WO 2022205659A1 CN 2021104782 W CN2021104782 W CN 2021104782W WO 2022205659 A1 WO2022205659 A1 WO 2022205659A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
conductive layer
bit line
substrate
pattern
Prior art date
Application number
PCT/CN2021/104782
Other languages
English (en)
French (fr)
Inventor
于业笑
刘忠明
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/468,920 priority Critical patent/US11942522B2/en
Publication of WO2022205659A1 publication Critical patent/WO2022205659A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular, to a method for fabricating a semiconductor structure and a semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the opening and closing of the transistor, so that the stored in the capacitor can be read through the bit line. data information in, or write data information into the capacitor.
  • An embodiment of the present application provides a method for fabricating a semiconductor structure, which includes: providing a substrate in which a plurality of active regions are arranged at intervals; and sequentially forming a first stacked structure and a first lithography on the substrate
  • the first photoresist layer is negatively developed using the first mask as a mask to form a first pattern; the first laminated structure is etched along the first pattern, and the first layer is etched along the first pattern.
  • a second pattern is formed in a stacked structure; using the first stacked structure with the second pattern as a mask, the substrate is etched to a predetermined depth to form a recess, and multiple layers are formed on the remaining substrate.
  • the protrusions are arranged at intervals, the recesses surround the protrusions, and the active regions are exposed between the protrusions.
  • the semiconductor structure fabrication method provided by the embodiment of the present application includes: providing a substrate provided with a plurality of spaced active regions; sequentially forming a first stacked structure and a first photoresist layer on the substrate; using a first mask The first photoresist layer is negatively developed for the mask to form a first pattern; the first laminated structure is etched along the first pattern to form a second pattern in the first laminated structure; A stacked layer structure is a mask, the substrate is etched to a predetermined depth to form recesses, and a plurality of spaced bosses are formed on the remaining substrate, the recesses surround the bosses, and the active regions are exposed between the bosses.
  • the embodiment of the present application uses the first photoresist layer once Negative development, and one-time etching of the first laminated structure to form a desired pattern, avoids the alignment problem of two development and etching, and improves the stability of the semiconductor structure and the performance of the semiconductor device.
  • the first stacked structure does not need to be backfilled, which reduces the manufacturing process and the number of layers of the first stacked structure, thereby reducing the complexity of the first stacked structure.
  • Embodiments of the present application further provide a semiconductor structure, which includes a bit line, and the bit line is formed by the above-mentioned method for fabricating a semiconductor structure.
  • the semiconductor structure provided by the embodiment of the present application includes a bit line, and the bit line is formed by the above-mentioned semiconductor structure manufacturing method, which reduces the possibility of bridging between the bumps connected to the bit line, thereby improving the stability of the semiconductor structure and the semiconductor device.
  • the bit line is formed by the above-mentioned semiconductor structure manufacturing method, which reduces the possibility of bridging between the bumps connected to the bit line, thereby improving the stability of the semiconductor structure and the semiconductor device.
  • 1 is a top view of the related art after forming a first photoresist layer
  • Fig. 2 is the sectional view at A-A place in Fig. 1;
  • FIG. 3 is a top view of an intermediate layer in the related art after a sixth pattern is formed
  • Fig. 4 is the sectional view at B-B place in Fig. 3;
  • FIG. 5 is a top view after forming a second photoresist layer in the related art
  • Fig. 6 is the sectional view at C-C place in Fig. 5;
  • Fig. 7 is the sectional view at D-D place among Fig. 5;
  • FIG. 8 is a top view of an intermediate layer in the related art after forming an eighth pattern
  • Figure 9 is a sectional view at E-E in Figure 8.
  • Figure 11 is a sectional view at F-F in Figure 10.
  • FIG. 13 is a top view of the related art after forming a bit line
  • Figure 14 is a sectional view at G-G in Figure 13;
  • 15 is a schematic diagram of forming a bit line damage boss in the related art
  • 16 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present application.
  • 17 is a top view after forming a first photoresist layer according to an embodiment of the present application.
  • Figure 18 is a sectional view at A 1 -A 1 in Figure 17;
  • FIG. 19 is a diagram of a first mask plate according to an embodiment of the application.
  • 20 is a top view of an embodiment of the present application after etching a substrate to a predetermined depth
  • Figure 21 is a sectional view at B 1 -B 1 in Figure 20;
  • 22 is a top view after removing the hard mask layer according to an embodiment of the present application.
  • Figure 23 is a sectional view at C 1 -C 1 in Figure 22;
  • Figure 25 is a sectional view at D 1 -D 1 in Figure 24;
  • 26 is a top view after removing the first conductive layer and part of the second conductive layer according to an embodiment of the present application;
  • Figure 27 is a sectional view at E 1 -E 1 in Figure 26;
  • FIG. 28 is a top view of an embodiment of the application after removing the insulating layer and part of the second conductive layer;
  • Figure 29 is a sectional view at F 1 -F 1 in Figure 28;
  • FIG. 30 is a top view after forming a bit line according to an embodiment of the present application.
  • Figure 31 is a cross-sectional view at G 1 -G 1 in Figure 30;
  • 32 is a top view after forming a second photoresist layer according to an embodiment of the present application.
  • FIG. 33 is a cross-sectional view at I 1 -I 1 in FIG. 32 .
  • the fabrication of a semiconductor structure includes the following steps: providing a substrate, as shown in FIG. 2 , the substrate 100 includes a plurality of active regions 110 arranged at intervals; A third laminated structure 700, an intermediate layer 800, a fourth laminated structure 900 and a first photoresist layer 300 are formed in sequence on the top, and the first photoresist layer 300 has a fifth pattern; A photoresist layer 300 is used as a mask, and the fourth stacked structure 900 and the intermediate layer 800 are etched to form a sixth pattern in the intermediate layer 800 ; referring to FIGS.
  • the fourth stacked layer is backfilled on the intermediate layer 800 structure 900, and a second photoresist layer 600 is formed on the fourth stacked structure 900, and the second photoresist layer 600 has a seventh pattern; referring to FIG. 8 and FIG. 9, the second photoresist layer 600 is used as a mask film, the fourth stacked structure 900 and the intermediate layer 800 are etched to form an eighth pattern, the eighth pattern and the sixth pattern do not overlap; referring to FIG. 10 and FIG. 11 , the third stack is etched using the intermediate layer 800 as a mask
  • the layer structure 700 and the substrate 100 form a bit line contact region on the substrate 100, and the active region 110 is exposed in the bit line contact region.
  • the eighth pattern and the sixth pattern are easily overlapped, resulting in the pattern on the intermediate layer 800 being bridged, and then the remaining third stacked structure 700 is bridged as shown by the dotted line in FIG. Structural stability and performance of semiconductor devices.
  • bit lines 400 are formed on the substrate 100 , and the bit lines 400 pass through the bosses and the active regions 110 .
  • Part of the bit line 400 is located on the boss reserved on the substrate 100, as shown in the L2 region in FIG. 13, this segment of the bit line 400 is through the bit line, and part of the bit line 400 is located on the active area 110 of the substrate 100, as shown in FIG. 13
  • this segment of bit line 400 is its own bit line.
  • the bumps near the bit line 400 such as the region shown by the dotted line in FIG. 15 , are easily damaged, which reduces the stability of the semiconductor structure and the performance of the semiconductor device.
  • an embodiment of the present application provides a method for fabricating a semiconductor structure, which sequentially forms a first stacked structure and a first photoresist layer on a substrate;
  • the first photoresist layer is negatively developed for the mask to form a first pattern;
  • the first laminated structure is etched along the first pattern to form a second pattern in the first laminated structure;
  • a stacked layer structure is a mask, the substrate is etched to a predetermined depth to form recesses, and a plurality of spaced bosses are formed on the remaining substrate, the recesses are arranged around the bosses, and the active regions are exposed between the bosses.
  • the method for fabricating a semiconductor structure in the embodiment of the present application may specifically include the following steps:
  • Step S101 providing a substrate in which a plurality of spaced active regions are arranged.
  • the active region 110 is provided in the substrate 100 . As shown in FIG. 18 , the active region 110 is not exposed on the surface of the substrate 100 .
  • the number of active regions 110 may be multiple, and the multiple active regions 110 are arranged at intervals.
  • a Shallow Trench Isolation (STI) structure is arranged between the plurality of active regions 110, and silicon oxide (SiO 2 ) is arranged in the shallow trench isolation structure 120, so that the plurality of active regions 110 are isolation.
  • the material of the active region 110 may include silicon (Si).
  • the substrate 100 may be a silicon (Si) substrate, and the substrate may also be a germanium (Ge) substrate, a silicon on insulator (SOI) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate ) substrate or gallium nitride (GaN) substrate, etc.
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • Step S102 forming a first stacked structure and a first photoresist layer on the substrate in sequence.
  • a first stacked structure 200 is formed on the substrate 100, and the first stacked structure 200 covers the active region 110 of the substrate 100; a first photoresist layer is formed on the first stacked structure 200 300 , the first photoresist layer 300 covers the first stacked structure 200 .
  • an insulating layer 210 , a first conductive layer 220 , a hard mask layer 230 , a first mask layer 240 and a first anti-reflection layer 250 are sequentially formed on the substrate 100 .
  • the insulating layer 210 is used for further isolating the active region 110 in the substrate 100 and protecting the active region 110, and its material includes one or more of silicon nitride, silicon oxide and silicon oxynitride.
  • the material of the first conductive layer 220 includes polysilicon
  • the material of the hard mask layer 230 includes one or more of silicon oxide, titanium nitride or silicon nitride
  • the material of the first mask layer 240 includes SOH
  • the reflective material includes silicon oxynitride.
  • a first photoresist layer 300 is formed on the first anti-reflection layer 250.
  • the first photoresist layer 300 can be a phenol-formaldehyde polymer, the chemical structure of the photoresist can be changed by light, and the exposed part of the photoresist or the unexposed part of the photoresist can be removed by a chemical solvent.
  • Step S103 performing negative development on the first photoresist layer by using the first mask plate as a mask to form a first pattern.
  • a first mask is formed on the first photoresist layer 300 (the first mask is not shown in the figure), and the first mask is used as a mask for the first photoresist
  • the resist layer 300 is negatively developed (the full English name is Negative Type Develop, NTD for short). Through negative development, the exposed portion of the first photoresist layer 300 is retained, and the unexposed portion of the first photoresist layer 300 is removed.
  • the exposure time may be 10-15s, the negative development time may be 50-80s, and the negative developer may be Tima90.
  • a first pattern is formed in the first photoresist layer 300 by one development, and the first pattern has relatively dense patterns. This arrangement, on the one hand, reduces the subsequent manufacturing process of the first stacked structure 200 and improves the manufacturing efficiency of the semiconductor structure, on the other hand, avoids the alignment problem of two development, and avoids the occurrence of bridging after the first stacked structure 200 is etched , thereby improving the stability of the semiconductor structure and the performance of the semiconductor device.
  • the pattern of the first mask may be a plurality of ellipses arranged at intervals. This arrangement reduces the area of the orthographic projection of the bosses on the substrate 100 , thereby increasing the area of the bit line contact region, thereby preventing the adjacent bosses from being etched during subsequent formation of the bit lines.
  • the subsequent etching of the first photoresist layer 300 , the first stacked structure 200 and the substrate 100 the first photoresist layer 300 forms an elliptical column
  • the first stacked structure 200 forms an elliptical column
  • an elliptical boss is formed on the substrate 100 .
  • Step S104 etching the first stacked structure along the first pattern to form a second pattern in the first stacked structure.
  • the first anti-reflection layer 250, the first mask layer 240, the hard mask layer 230, the insulating layer 210 and the first conductive layer are etched along the first pattern 220. It can be understood that, after the step of etching the first stacked structure 200 along the first pattern, the step of removing the first photoresist layer 300 is also included.
  • Step S105 using the first laminated structure with the second pattern as a mask, etching the substrate to a predetermined depth to form depressions, and forming a plurality of spaced bosses on the remaining substrate, the depressions surround the bosses, and the convexities are formed. Active regions are exposed between the stages.
  • the substrate 100 is etched by using the first stacked structure 200 having the second pattern as a mask to a predetermined depth, such as the position H shown in FIG. 21 .
  • a predetermined depth such as the position H shown in FIG. 21 .
  • the upper portion of the substrate 100 is etched to form a desired pattern, and the lower portion of the substrate 100 is not etched, ie, the lower portion of the substrate 100 remains.
  • the preset depth may be 1/5 ⁇ 1/3 of the thickness of the substrate 100 . That is, a depression 130 is formed in the substrate 100 , and the depth of the depression 130 is 1/5 ⁇ 1/3 of the thickness of the substrate 100 , and a plurality of spaced bosses are formed on the remaining substrate 100 .
  • the etched area forms a depression 130
  • the unetched substrate 100 forms a boss
  • the depression 130 is arranged around the boss, and there are exposed between the bosses.
  • the active region 110 that is, a part of the bottom of the recess 130 is the active region 110 ; further, the boss may be a bit line contact, and the bit line is connected to the transistor through the bit line contact.
  • the active regions 110 are exposed between adjacent bosses.
  • the bosses separate two adjacent active regions 110 , for example, the bosses cover part of the regions at both ends of the active regions 110 .
  • the semiconductor structure fabrication method provided by the embodiment of the present application includes: providing a substrate 100, and the substrate 100 is provided with a plurality of active regions arranged at intervals; and sequentially forming a first stacked structure 200 and a first photoresist layer 300 on the substrate 100;
  • the first photoresist layer 300 is negatively developed using the first mask as a mask to form a first pattern; the first laminated structure 200 is etched along the first pattern to form a second laminated structure 200 pattern; using the first stacked structure 200 with the second pattern as a mask, etching the substrate 100 to a predetermined depth to form recesses 130, and forming a plurality of spaced-apart bosses on the remaining substrate 100, the recesses 130 surrounding Bosses, and active regions 110 are exposed between the bosses.
  • the photoresist layer is formed twice, and the photoresist layer needs to be developed each time, and the intermediate layer 800 is etched twice to form the desired pattern.
  • the adhesive layer 300 is negatively developed once, and the first laminated structure 200 is etched once to form a desired pattern, which avoids the alignment problem of two development and etching, and improves the stability of the semiconductor structure and the performance of the semiconductor device.
  • the first stacked structure 200 does not need to be backfilled, which reduces the manufacturing process and also reduces the number of layers of the first stacked structure 200 , thereby reducing the complexity of the first stacked structure 200 . Transferring the desired pattern to the substrate 100 through the first stacked structure 200 reduces the possibility of bridging between the bosses, thereby further improving the stability of the semiconductor structure and the performance of the semiconductor device.
  • the steps further include:
  • the first anti-reflection layer 250 , the first mask layer 240 and the hard mask layer 230 are removed to expose the first conductive layer 220 .
  • an insulating layer 210 and a first conductive layer 220 are sequentially left on the substrate 100 , and the insulating layer 210 covers the bosses of the substrate 100 .
  • the second conductive layer 410 is filled in the recess 130, and the second conductive layer 410 covers the first Conductive layer 220 .
  • the second conductive layer 410 is formed by depositing a conductive material in the recess 130 and on the first conductive layer 220, that is, the second conductive layer 410 fills the recess 130, covers the substrate 100, and covers the first conductive layer 410.
  • a conductive layer 220 As shown in FIG. 25 , the upper surface of the second conductive layer 410 is flush.
  • the material of the second conductive layer 410 and the material of the first conductive layer 220 may be the same, for example, the second conductive layer 410 and the first conductive layer 220 are both polysilicon layers.
  • part of the second conductive layer 410 and all of the first conductive layer 220 on the insulating layer 210 are removed, so that the remaining second conductive layer 410 is flush with the insulating layer 210 .
  • part of the second conductive layer 410 and the entire first conductive layer 220 facing away from the substrate 100 are removed to expose the insulating layer 210 .
  • the upper surface of the insulating layer 210 is flush with the upper surface of the second conductive layer 410 , so that the upper surface of the semiconductor structure shown in FIG. 27 is flat so that other layers on the surface can be formed.
  • the second conductive layer 410 By removing part of the second conductive layer 410 and all of the first conductive layer 220, there is no second conductive layer 410 between the second bit line structure (passing through the bit line) in the subsequently formed bit line 400 and the substrate 100, that is, the second conductive layer 410 is removed. There is no second conductive layer 410 between the two bit line structure and the boss, and the thickness of the second conductive layer 410 between the first bit line structure (self bit line) in the subsequently formed bit line 400 and the substrate 100 is also reduced Small.
  • capacitive contacts are formed between the bit lines 400, and the capacitive contacts are usually conductive materials to electrically connect the capacitors.
  • An insulating layer is provided between the bit line 400 and the capacitor contact for electrical isolation. Therefore, the bit line 400, the insulating layer and the capacitor contact usually form parasitic capacitance.
  • the plate area of the parasitic capacitance is reduced, thereby reducing the parasitic capacitance, improving the signal stability of the bit line 400, so that the semiconductor structure has better electrical parameters .
  • a third conductive layer and a protective layer are sequentially formed on the insulating layer 210 and the remaining second conductive layer 410 .
  • the material of the third conductive layer may include one or more of tungsten, titanium, aluminum, nickel, titanium oxide or titanium nitride, and the material of the protective layer may include silicon nitride.
  • the height of the upper surface of the protective layer from the upper surface of the substrate 100 is reduced under the condition that the thicknesses of the third conductive layer and the protective layer remain unchanged, Therefore, the height of the bit line 400 formed subsequently is reduced, which is beneficial to improve the stability of the bit line 400 .
  • the insulating layer 210 and part of the insulating layer 210 are also removed.
  • the second conductive layer 410 so that the remaining second conductive layer 410 is flush with the substrate 100 .
  • the insulating layer 210 and part of the second conductive layer 410 may be further removed to expose the substrate 100.
  • the remaining second conductive layer 410 is flush with the substrate 100 .
  • a third conductive layer 420 and a protective layer 430 are sequentially formed on the substrate 100 and the second conductive layer 410 .
  • bit line 400 extends along the first direction and passes through the active region and the boss, and the plurality of bit lines 400 are arranged along the second direction; the first direction is perpendicular to the second direction.
  • each bit line 400 passes through the active region 110 and the bosses in the vertical direction (the Y direction as shown in FIG. 30 ).
  • Each bit line 400 extends along the first direction, and the plurality of bit lines 400 are arranged along the second direction. Referring to FIG. 30 , each bit line 400 extends in a vertical direction, as shown in the Y direction in FIG. 30 ; a plurality of bit lines 400 are arranged at intervals in the horizontal direction, as in the X direction as shown in FIG. 30 .
  • the bit line 400 may include a plurality of first bit line structures and a plurality of second bit line structures, and the first bit line structures and the second bit line structures are alternately arranged along the first direction.
  • the first bit line structure is located on the active region 110, as shown in FIG. 30, the first bit line structure is located at L1, the first bit line structure is its own bit line, which passes through the active region 110; the second bit line structure is located at On the boss, as shown in FIG. 30 , the second bit line structure is located at L2 , and the second bit line structure passes through the bit line and passes through the boss.
  • the height of the bit line 400 may be 90-100 nm. Compared with the related art, the height of the bit line 400 is 130-140 nm, the height of the bit line 400 in the embodiment of the present application is reduced, thereby improving the stability of the bit line 400 sex.
  • the steps of removing part of the protective layer 430, the third conductive layer 420 and the remaining second conductive layer 410 to form a plurality of spaced bit lines 400 may specifically include:
  • a second stacked structure 500 is formed on the protective layer 430 .
  • the step of forming the second stacked structure 500 on the protective layer 430 includes: sequentially forming a filling layer 510 , a second anti-reflection layer 520 , a second mask layer 530 and a second layer on the protective layer 430 Three anti-reflection layers 540 .
  • the material of the filling layer 510 includes amorphous carbon
  • the material of the second anti-reflection layer 520 and the third anti-reflection layer 540 includes silicon oxynitride
  • the material of the second mask layer 530 includes SOH (Spin on Hardmask). mask composition).
  • a second photoresist layer 600 is formed on the second stacked structure 500, and the second photoresist layer is formed by using the second mask as a mask 600 performs positive development to form a third pattern.
  • the pattern of the second mask is a plurality of rectangles arranged in parallel. The pattern of the second mask corresponds to the active region 110 and the bosses.
  • the second stacked structure 500 is etched along the third pattern, and a fourth pattern is formed in the second stacked structure 500 .
  • the pattern on the second mask is transferred to the second stacked structure 500 .
  • the protective layer 430 , the third conductive layer 420 and the second conductive layer 410 are etched using the second laminated structure 500 having the fourth pattern as a mask, and the remaining protective layer 430 and the third conductive layer are etched 420 and the second conductive layer 410 form the bit line 400 .
  • the height of the bit line 400 is lower, and the stability is better; It should be noted that, as shown in FIG. 30 and FIG. 31 , after the bit line 400 is formed, the remaining second stacked structure 500 is removed.
  • Embodiments of the present application further provide a semiconductor structure.
  • the semiconductor structure includes a bit line 400 .
  • the bit line 400 is formed by the semiconductor structure manufacturing method in the above-mentioned embodiment, and the formed bit line 400 passes through a substrate. With the bosses 100 and the active region 110, the possibility of bridging between the bosses is reduced, thereby improving the stability of the semiconductor structure and the performance of the semiconductor device.
  • the height of the formed bit line 400 is relatively low, for example, the height of the bit line 400 is 90-100 nm, and the stability of the bit line 400 is good.
  • there is no second conductive layer 410 between the second bit line structure and the substrate 100 in the subsequently formed bit line 400 that is, there is no second conductive layer 410 between the second bit line structure and the boss, and the subsequently formed bit line structure does not have the second conductive layer 410.
  • the thickness of the second conductive layer 410 between the first bit line structure in the line 400 and the substrate 100 is also reduced.
  • capacitive contacts are formed between the bit lines 400, and the capacitive contacts are made of conductive materials to electrically connect the capacitors.
  • An insulating layer is usually provided between the bit line 400 and the capacitor contact for electrical isolation. Therefore, the bit line 400, the insulating layer and the capacitor contact usually form parasitic capacitance.
  • the plate area of the parasitic capacitance is reduced, thereby reducing the parasitic capacitance, improving the signal stability of the bit line 400, so that the semiconductor structure has better electrical parameters .
  • references to the terms “one embodiment,” “some embodiments,” “illustrative embodiments,” “examples,” “specific examples,” or “some examples” and the like are meant to incorporate embodiments A particular feature, structure, material, or characteristic described or exemplified is included in at least one embodiment or example of the present application.
  • schematic representations of the above terms do not necessarily refer to the same embodiment or example.
  • the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Landscapes

  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本申请提供一种半导体结构制作方法及半导体结构，涉及半导体制造技术领域，用于解决半导体结构稳定性和半导体器件的性能较低的技术问题，包括：提供设有多个间隔设置的有源区的基底；在基底上依次形成第一叠层结构和第一光刻胶层；对第一光刻胶层负显影，形成第一图案；沿第一图案刻蚀第一叠层结构，在第一叠层结构中形成第二图案；以具有第二图案的第一叠层结构为掩膜，刻蚀基底至预设深度以形成凹陷，保留的基底上形成多个间隔设置的凸台，凹陷环绕凸台，凸台间暴露有源区。通过对第一光刻胶层一次负显影，且对第一叠层结构一次刻蚀，避免了两次显影、刻蚀的对准问题，降低了凸台间桥接可能性，提高半导体结构的稳定性和半导体器件的性能。

Description

半导体结构制作方法及半导体结构
本申请要求于2021年03月31日提交中国专利局、申请号为202110348268.4、申请名称为“半导体结构制作方法及半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体结构制作方法及半导体结构。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体结构，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启与关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
然而，随着尺寸微缩，现有的位线结构制造过程中易发生单点桥连作用，导致位线触点与位线触点发生短路，影响器件性能；另外圆形位线接触孔图案，占据了较大的位线空间，位线蚀刻过程中，易破环相邻位线触点的侧壁，导致位线结构不稳定。
发明内容
本申请实施例提供一种半导体结构制作方法，其包括：提供基底，所述基底中设置有多个间隔设置的有源区；在所述基底上依次形成第一叠层结构和第一光刻胶层；以第一掩膜板为掩膜对所述第一光刻胶层进行负显影，形成第一图案；沿所述第一图案刻蚀所述第一叠层结构，在所述第一叠层结构中形成第二图案；以具有所述第二图案的第一叠层结构为掩膜，刻蚀所述基底至预设深度以形成凹陷，并在保留的所述基底上形成多个间 隔设置的凸台，所述凹陷环绕所述凸台，所述凸台之间暴露有所述有源区。
本申请实施例提供的半导体结构制作方法具有如下优点：
本申请实施例提供的半导体结构制作方法包括：提供设置有多个间隔设置的有源区的基底；在基底上依次形成第一叠层结构和第一光刻胶层；以第一掩膜板为掩膜对第一光刻胶层进行负显影，形成第一图案；沿第一图案刻蚀第一叠层结构，在第一叠层结构中形成第二图案；以具有第二图案的第一叠层结构为掩膜，刻蚀基底至预设深度以形成凹陷，并在保留的基底上形成多个间隔设置的凸台，凹陷环绕凸台，凸台之间暴露有源区。相较于相关技术中形成两次光刻胶层，且每次光刻胶层进行显影，并对中间层两次刻蚀形成所需图案，本申请实施例通过对第一光刻胶层一次负显影，且对第一叠层结构一次刻蚀形成所需图案，避免了两次显影、刻蚀的对准问题，提高了半导体结构的稳定性和半导体器件的性能。此外，第一叠层结构无需回填，减少了制程，也减少了第一叠层结构的层数，从而降低第一叠层结构的复杂度。通过第一叠层结构向基底传递所需图案，降低了凸台之间的桥接的可能性，从而进一步提高半导体结构的稳定性和半导体器件的性能。
本申请实施例还提供一种半导体结构，其包括位线，所述位线通过如上所述的半导体结构制作方法形成。
本申请实施例提供的半导体结构包括位线，位线通过上述半导体结构制作方法形成，降低了与位线相连接的凸台之间的桥接的可能性，从而提高半导体结构的稳定性和半导体器件的性能，具体效果参照上文所述，在此不再赘述。
附图说明
图1为相关技术中的形成第一光刻胶层后的俯视图；
图2为图1中A-A处的剖视图；
图3为相关技术中的中间层形成第六图案后的俯视图；
图4为图3中B-B处的剖视图；
图5为相关技术中的形成第二光刻胶层后的俯视图；
图6为图5中C-C处的剖视图；
图7为图5中D-D处的剖视图；
图8为相关技术中的中间层形成第八图案后的俯视图；
图9为图8中E-E处的剖视图；
图10为相关技术中的形成位线接触区后的俯视图；
图11为图10中F-F处的剖视图；
图12为相关技术中的凸台桥接的示意图；
图13为相关技术中的形成位线后的俯视图；
图14为图13中G-G处的剖视图；
图15为相关技术中的形成位线损伤凸台的示意图；
图16为本申请实施例的半导体结构制作方法的流程图；
图17为本申请实施例的形成第一光刻胶层后的俯视图；
图18为图17中A 1-A 1处的剖视图；
图19为本申请实施例的第一掩膜板的图形；
图20为本申请实施例的刻蚀基底至预设深度后的俯视图；
图21为图20中B 1-B 1处的剖视图；
图22为本申请实施例的去除硬掩模层后的俯视图；
图23为图22中C 1-C 1处的剖视图；
图24为本申请实施例的形成第二导电层后的俯视图；
图25为图24中D 1-D 1处的剖视图；
图26为本申请实施例的去除第一导电层和部分第二导电层后的俯视图；
图27为图26中E 1-E 1处的剖视图；
图28为本申请实施例的去除绝缘层和部分第二导电层后的俯视图；
图29为图28中F 1-F 1处的剖视图；
图30为本申请实施例的形成位线后的俯视图；
图31为图30中G 1-G 1处的剖视图；
图32为本申请实施例的形成第二光刻胶层后的俯视图；
图33为图32中I 1-I 1处的剖视图。
具体实施方式
相关技术中，参照图1至图15，制作半导体结构包括以下步骤：提供基底，如图2所示，基底100包括多个间隔设置的有源区110；参照图1和图2，在基底100上依次形成第三叠层结构700、中间层800、第四叠层结构900和第一光刻胶层300，第一光刻胶层300具有第五图案；参照图3和图4，以第一光刻胶层300为掩膜，刻蚀第四叠层结构900和中间层800，在中间层800中形成第六图案；参照图5至图7，在中间层800上回填第四叠层结构900，并在第四叠层结构900上形成第二光刻胶层600，第二光刻胶层600具有第七图案；参照图8和图9，以第二光刻胶层600为掩膜，刻蚀第四叠层结构900和中间层800，形成第八图案，第八图案与第六图案不相重合；参照图10和图11，以中间层800为掩膜刻蚀第三叠层结构700和基底100，在基底100上形成位线接触区，位线接触区中暴露有源区110。
可以理解的是，基底100一部分被刻蚀显露出有源区110，基底100未刻蚀的区域被保留，形成多个间隔设置的凸台。然而，上述制作过程中，第八图案与第六图案易重合，导致中间层800上的图案产生桥接，进而使得保留的第三叠层结构700产生如图12虚线所示的桥接，降低了半导体结构的稳定性和半导体器件的性能。
参照图13和图14，在基底100上形成位线400，位线400经过凸台和有源区110。部分位线400位于基底100保留的凸台上，如图13所示的L2区域，该段位线400为穿过位线，部分位线400位于基底100的有源区110上，如图13所示的L1区域，该段位线400为自身位线。然而，形成位线400的过程中，易损伤位线400附近的凸台，如图15虚线所示的区域，降低了半导体结构的稳定性和半导体器件的性能。
为了提高半导体结构的稳定性和半导体器件的性能，本申请实施例提供一种半导体结构制作方法，其在基底上依次形成第一叠层结构和第一光刻胶层；以第一掩膜板为掩膜对第一光刻胶层进行负显影，形成第一图案；沿第一图案刻蚀第一叠层结构，在第一叠层结构中形成第二图案；以具有第二图案的第一叠层结构为掩膜，刻蚀基底至预设深度以形成凹陷，并在保留的基底上形成多个间隔设置的凸台，凹陷环绕凸台设置，凸台之间暴露有源区。通过对第一光刻胶层一次负显影，且对第一叠层结构一次刻蚀形成所需图案，避免了两次显影、刻蚀的对准问题，提高了半导体结构的 稳定性和半导体器件的性能。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
参照图16，本申请实施例中的半导体结构制作方法具体可以包括以下步骤：
步骤S101、提供基底，基底中设置有多个间隔设置的有源区。
参照图17和图18，基底100中设置有源区110，如图18所示，有源区110未暴露于基底100的表面。有源区110的数量可以设置有多个，多个有源区110间隔设置。
示例性的，多个有源区110之间设置浅槽隔离(Shallow Trench Isolation，简称STI)结构，浅槽隔离结构120中设置有氧化硅(SiO 2)，以使多个有源区110之间隔离。有源区110的材质可以包括硅(Si)。
需要说明的是，基底100可以为硅(Si)基底，基底还可以为锗(Ge)基底、绝缘体上硅(Silicon on Insulator，简称SOI)基底、锗化硅(SiGe)基底、碳化硅(SiC)基底或者氮化镓(GaN)基底等。
步骤S102、在基底上依次形成第一叠层结构和第一光刻胶层。
继续参照图17和图18，在基底100上形成第一叠层结构200，第一叠层结构200覆盖基底100的有源区110；在第一叠层结构200上形成第一光刻胶层300，第一光刻胶层300覆盖第一叠层结构200。
在一种可能的示例中，在基底100上依次形成绝缘层210、第一导电层220、硬掩模层230、第一掩膜层240和第一抗反射层250。其中，绝缘层210用于进一步隔离基底100中的有源区110，保护有源区110，其材质包括氮化硅、氧化硅和氮氧化硅中的一种或者多种。第一导电层220的材质包括多晶硅，硬掩模层230的材质包括氧化硅、氮化钛或者氮化硅中的一种或者多种，第一掩膜层240的材质包括SOH，第一抗反射的材质包括氮氧化硅。
形成第一抗反射层250后，在第一抗反射层250上形成第一光刻胶层 300。第一光刻胶层300可以为苯酚-甲醛聚合物，光可以改变光刻胶的化学结构，光刻胶被曝光的部分或者光刻胶未被曝光的部分可以通过化学溶剂去掉。
步骤S103、以第一掩膜板为掩膜对第一光刻胶层进行负显影，形成第一图案。
继续参照图17和图18，第一光刻胶层300上形成有第一掩膜板(第一掩膜板没有在图中画出)，以第一掩膜板为掩膜对第一光刻胶层300进行负显影(英文全称Negative Type Develop，简称NTD)。通过负显影，将第一光刻胶层300中被曝光的部分保留，将第一光刻胶层300中未被曝光的部分去除。
示例性的，负显影的过程中，曝光时间可以为10-15s，负显影时间可以为50-80s，负显影液可以为Tima90。通过进行负显影，在第一光刻胶层300中一次显影形成第一图案，第一图案具有较为密集的图形。如此设置，一方面减少了后续第一叠层结构200的制程，提高半导体结构的制作效率，另一方面避免了两次显影的对准问题，以避免第一叠层结构200刻蚀后出现桥接，从而提高半导体结构的稳定性和半导体器件的性能。
在一些可能的示例中，第一掩膜板的图形可以为多个间隔设置的椭圆形。如此设置，以减少凸台在基底100上的正投影的面积，从而增加位线接触区的面积，从而避免后续形成位线时刻蚀到相邻的凸台。
可以理解的是，相较于相关技术中第一掩膜板的图形为多个间隔设置的圆形，本申请实施例中后续刻蚀第一光刻胶层300、第一叠层结构200和基底100时，第一光刻胶层300形成椭圆柱，第一叠层结构200形成椭圆柱，基底100上形成椭圆形凸台。
如图19所示，当椭圆形的长轴L3与圆形的半径R相等以保证各有源区110隔开时，椭圆形的面积小于圆形的面积，从而增加了两相邻椭圆形之间的距离，减少损伤相邻的凸台的可能性。
步骤S104、沿第一图案刻蚀第一叠层结构，在第一叠层结构中形成第二图案。
继续参照图17和图18，在一种可能的示例中，沿第一图案刻蚀第一抗反射层250、第一掩膜层240、硬掩模层230、绝缘层210和第一导电层220。可以理解的是，沿第一图案刻蚀第一叠层结构200的步骤之后，还包 括去除第一光刻胶层300。
步骤S105、以具有第二图案的第一叠层结构为掩膜，刻蚀基底至预设深度以形成凹陷，并在保留的基底上形成多个间隔设置的凸台，凹陷环绕凸台，凸台之间暴露有有源区。
参照图20和图21，以具有第二图案的第一叠层结构200为掩膜刻蚀基底100，直至预设深度，如图21所示的H处。如图20和图21所示，刻蚀基底100的上部分以形成所需图案，未刻蚀到基底100的下部分，即保留基底100的下部分。
在一种可能的示例中，预设深度可以为基底100厚度的1/5～1/3。即基底100中形成凹陷130，凹陷130的深度为基底100厚度的1/5～1/3，保留的基底100上形成多个间隔设置的凸台。
可以理解的是，如图21所示的基底100的上部区域中，刻蚀掉的区域形成凹陷130，未刻蚀的基底100形成凸台，凹陷130环绕凸台设置，凸台之间暴露有有源区110，即凹陷130的部分底部为有源区110；进一步的，凸台可以为位线触点，位线经过位线触点与晶体管连接。
在图20所示的同一行凸台中，相邻的凸台之间暴露有源区110。凸台将相邻的两个有源区110隔开，例如，凸台覆盖有源区110的两端的部分区域。
本申请实施例提供的半导体结构制作方法包括：提供基底100，基底100设置有多个间隔设置的有源区；在基底100上依次形成第一叠层结构200和第一光刻胶层300；以第一掩膜板为掩膜对第一光刻胶层300进行负显影，形成第一图案；沿第一图案刻蚀第一叠层结构200，在第一叠层结构200中形成第二图案；以具有第二图案的第一叠层结构200为掩膜，刻蚀基底100至预设深度以形成凹陷130，并在保留的基底100上形成多个间隔设置的凸台，凹陷130环绕凸台，凸台之间暴露有有源区110。相较于相关技术中形成两次光刻胶层，且每次光刻胶层都需进行显影，并对中间层800两次刻蚀形成所需图案，本申请实施例通过对第一光刻胶层300一次负显影，且对第一叠层结构200一次刻蚀形成所需图案，避免了两次显影、刻蚀的对准问题，提高了半导体结构的稳定性和半导体器件的性能。此外，第一叠层结构200无需回填，减少了制程，也减少了第一叠层结构200的层数，从而降低第一叠层结构200的复杂度。通过第一叠层结构200 向基底100传递所需图案，降低了凸台之间的桥接的可能性，从而进一步提高半导体结构的稳定性和半导体器件的性能。
需要说明的是，参照图22至图31，以具有第二图案的第一叠层结构为掩膜，刻蚀基底至预设深度以形成凹陷的步骤之后，还包括：
参照图22和图23，去除第一抗反射层250、第一掩膜层240和硬掩模层230，以暴露第一导电层220。如图22和图23所示，基底100上依次保留有绝缘层210和第一导电层220，且绝缘层210覆盖基底100的凸台。
参照图24和图25，去除第一抗反射层250、第一掩膜层240和硬掩模层230之后，在凹陷130内填满第二导电层410，且第二导电层410覆盖第一导电层220。
如图24和图25所示，通过在凹陷130内和第一导电层220上沉积导电材料，形成第二导电层410，即第二导电层410填满凹陷130，覆盖基底100，并覆盖第一导电层220。如图25所示，第二导电层410的上表面齐平。第二导电层410的材质与第一导电层220的材质可以相同，例如第二导电层410和第一导电层220均为多晶硅层。
参照图26和图27，形成第二导电层410后，去除绝缘层210上的部分第二导电层410和全部第一导电层220，使剩余的第二导电层410与绝缘层210齐平。如图26和图27所示，去除背离基底100的部分第二导电层410和全部的第一导电层220，以暴露绝缘层210。绝缘层210的上表面与第二导电层410的上表面齐平，从而使得如图27所示的半导体结构的上表面平整，以便于形成该表面上的其他各层。
通过去除部分第二导电层410和全部第一导电层220，使得后续形成的位线400中的第二位线结构(穿过位线)与基底100之间没有第二导电层410，即第二位线结构与凸台之间的没有第二导电层410，后续形成的位线400中的第一位线结构(自身位线)与基底100之间的第二导电层410厚度也有所减小。
如此设置，后续过程中，位线400之间会形成电容触点，电容触点通常为导电材料，以电连接电容器。位线400与电容触点之间设置绝缘层进行电气隔离，因此，位线400、绝缘层和电容触点通常会形成寄生电容。本申请实施例中，通过去除部分第二导电层410，减少了寄生电容的极板面积，从而降低了寄生电容，提高了位线400信号的稳定性，使得半导体 结构具有较佳的电性参数。
去除绝缘层210上的部分第二导电层410和全部第一导电层220后，在绝缘层210和剩余的第二导电层410上依次形成第三导电层和保护层。第三导电层的材质可以包括钨、钛、铝、镍、氧化钛或者氮化钛中的一种或者多种，保护层的材质可以包括氮化硅。
通过去除部分第二导电层410后形成第三导电层和保护层，在第三导电层和保护层的厚度不变的情况下，降低了保护层的上表面距离基底100的上表面的高度，从而降低了后续形成的位线400的高度，有利于提高位线400的稳定性。
需要说明的是，在一种可能的示例中，参照图28和图29，去除绝缘层210上的部分第二导电层410和全部第一导电层220的步骤之后，还去除绝缘层210和部分第二导电层410，以使剩余的第二导电层410与基底100齐平。
如图28和图29所示，去除绝缘层210上的部分第二导电层410和全部第一导电层220后，还可以继续去除绝缘层210和部分第二导电层410，以暴露基底100，保留的第二导电层410与基底100齐平。去除绝缘层210和部分第二导电层410后，在基底100和第二导电层410上依次形成第三导电层420和保护层430。
继续参照图30和图31，形成第三导电层420和保护层430之后，去除部分保护层430、第三导电层420和剩余的第二导电层410，以形成多条间隔设置的位线400；每条位线400沿第一方向延伸且经过有源区和凸台，多条位线400沿第二方向排布；第一方向与第二方向垂直。
如图30和图31所示，去除部分保护层430、部分第三导电层420和剩余的部分第二导电层410，保留的保护层430、保留的第三导电层420和保留的第二导电层410形成位线400。如图30所示，每条位线400经过竖直方向(如图30所示的Y方向)的有源区110和凸台。
每条位线400沿第一方向延伸，且多条位线400沿第二方向排布。参照图30，每条位线400沿竖直方向延伸，如图30所示的Y方向；多条位线400沿水平方向间隔排布，如图30所示的X方向。
位线400可以包括多个第一位线结构和多个第二位线结构，第一位线结构和第二位线结构沿第一方向交替设置。第一位线结构位于有源区110 上，如图30所示，第一位线结构位于L1处，第一位线结构为自身位线，其经过有源区110；第二位线结构位于凸台上，如图30所示，第二位线结构位于L2处，第二位线结构为穿过位线，其经过凸台。
位线400的高度可以为90-100nm，相较于相关技术中的位线400的高度为130-140nm，本申请实施例中的位线400的高度有所降低，从而提高位线400的稳定性。
需要说明的是，参照图32和图33，去除部分保护层430、第三导电层420和剩余的第二导电层410，以形成多条间隔设置的位线400的步骤具体可以包括：
参照图32和图33，在保护层430上形成第二叠层结构500。在一种可能的示例中，在保护层430上形成第二叠层结构500的步骤包括：在保护层430上依次形成填充层510、第二抗反射层520、第二掩膜层530和第三抗反射层540。其中，填充层510的材质包括非晶碳，第二抗反射层520和第三抗反射层540的材质包括氮氧化硅，第二掩膜层530的材质包括SOH(Spin on Hardmask，旋涂硬掩模组合物)。
继续参照图32和图33，形成第二叠层结构500后，在第二叠层结构500上形成第二光刻胶层600，以第二掩膜板为掩膜对第二光刻胶层600进行正显影，形成第三图案。如图32所示，第二掩膜板的图形为多个平行排布的长方形。第二掩膜板的图形与有源区110和凸台相对应。
形成第三图案后，沿第三图案刻蚀第二叠层结构500，在第二叠层结构500中形成第四图案。通过第二光刻胶层600，将第二掩膜板上的图案传递到第二叠层结构500上。
形成第四图案后，以具有第四图案的第二叠层结构500为掩膜，刻蚀保护层430、第三导电层420和第二导电层410，剩余的保护层430、第三导电层420和第二导电层410形成位线400。一方面，位线400的高度较低，稳定性较好；另一个方面，位线400下的第二导电层410移除，降低了位线400的寄生电容。需要说明的是，如图30和图31所示，形成位线400后，去除剩余的第二叠层结构500。
本申请实施例还提供一种半导体结构，如图30和图31所示，该半导体结构包括位线400，位线400通过上述实施例中的半导体结构制作方法形成，形成的位线400经过基底100的凸台和有源区110，凸台之间的桥 接可能性减小，从而提高半导体结构的稳定性和半导体器件的性能。
所形成的位线400的高度较低，例如位线400的高度为90-100nm，位线400的稳定性较好。此外，后续形成的位线400中的第二位线结构与基底100之间没有第二导电层410，即第二位线结构与凸台之间的没有第二导电层410，后续形成的位线400中的第一位线结构与基底100之间的第二导电层410厚度也有所减小。
如此设置，后续过程中，位线400之间形成电容触点，电容触点为导电材料，以电连接电容器。位线400与电容触点之间通常设置绝缘层进行电气隔离，因此，位线400、绝缘层和电容触点通常会形成寄生电容。本申请实施例中，通过去除部分第二导电层410，减少了寄生电容的极板面积，从而降低了寄生电容，提高了位线400信号的稳定性，使得半导体结构具有较佳的电性参数。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构制作方法，其中，包括：
    提供基底，所述基底中设置有多个间隔设置的有源区；
    在所述基底上依次形成第一叠层结构和第一光刻胶层；
    以第一掩膜板为掩膜对所述第一光刻胶层进行负显影，形成第一图案；
    沿所述第一图案刻蚀所述第一叠层结构，在所述第一叠层结构中形成第二图案；
    以具有所述第二图案的第一叠层结构为掩膜，刻蚀所述基底至预设深度以形成凹陷，并在保留的所述基底上形成多个间隔设置的凸台，所述凹陷环绕所述凸台，所述凸台之间暴露有所述有源区。
  2. 根据权利要求1所述的半导体结构制作方法，其中，所述预设深度为所述基底厚度的1/5～1/3。
  3. 根据权利要求1所述的半导体结构制作方法，其中，所述第一掩膜板的图形为多个间隔设置的椭圆形。
  4. 根据权利要求1所述的半导体结构制作方法，其中，在所述基底上依次形成第一叠层结构和第一光刻胶层的步骤包括：
    在所述基底上依次形成绝缘层、第一导电层、硬掩模层、第一掩膜层和第一抗反射层；
    在所述第一抗反射层上形成第一光刻胶层。
  5. 根据权利要求4所述的半导体结构制作方法，其中，所述绝缘层的材质包括氮化硅，所述第一导电层的材质包括多晶硅，所述硬掩模层的材质包括氧化硅，所述第一掩膜层的材质包括SOH，所述第一抗反射层的材质包括氮氧化硅。
  6. 根据权利要求4所述的半导体结构制作方法，其中，以具有所述第二图案的第一叠层结构为掩膜，刻蚀所述基底至预设深度以形成凹陷的步骤之后，还包括：
    去除所述第一抗反射层、第一掩膜层和硬掩模层，以暴露所述第一导电层；
    在所述凹陷中填满第二导电层，且所述第二导电层覆盖所述第一导电层；
    去除所述绝缘层上的部分所述第二导电层和全部所述第一导电层，使剩余的所述第二导电层与所述绝缘层齐平；
    在所述绝缘层和剩余的所述第二导电层上依次形成第三导电层和保护层；
    去除部分所述保护层、所述第三导电层和剩余的所述第二导电层，以形成多条间隔设置的位线；每条所述位线沿第一方向延伸且经过所述有源区和所述凸台，多条所述位线沿第二方向排布；所述第一方向与所述第二方向垂直。
  7. 根据权利要求6所述的半导体结构制作方法，其中，所述位线包括第一位线结构和第二位线结构，所述第一位线结构和所述第二位线结构交替设置，且所述第一位线结构位于所述有源区上，所述第二位线结构位于所述凸台上。
  8. 根据权利要求6所述的半导体结构制作方法，其中，去除所述绝缘层上的部分所述第二导电层和全部所述第一导电层之后，还包括：
    去除所述绝缘层和部分所述第二导电层，以使剩余的所述第二导电层与所述基底齐平。
  9. 根据权利要求6所述的半导体结构制作方法，其中，所述第三导电层的材质包括钨，所述保护层的材质包括氮化硅。
  10. 根据权利要求6所述的半导体结构制作方法，其中，去除部分所述保护层、所述第三导电层和剩余的所述第二导电层，以形成多条间隔设置的位线之前，还包括：
    在所述保护层上形成第二叠层结构；
    在所述第二叠层结构上形成第二光刻胶层，以第二掩膜板为掩膜对所述第二光刻胶层进行正显影，形成第三图案；
    沿所述第三图案刻蚀所述第二叠层结构，在所述第二叠层结构中形成第四图案；
    以具有所述第四图案的所述第二叠层结构为掩膜，刻蚀所述保护层、所述第三导电层和所述第二导电层，剩余的所述保护层、所述第三导电层和所述第二导电层形成所述位线。
  11. 根据权利要求10所述的半导体结构制作方法，其中，所述位线的高度为90-100nm。
  12. 根据权利要求10所述的半导体结构制作方法，其中，所述第二掩膜板的图形为多个平行排布的长方形。
  13. 根据权利要求10所述的半导体结构制作方法，其中，在所述保护层上形成所述第二叠层结构的步骤包括：
    在所述保护层上依次形成填充层、第二抗反射层、第二掩膜层和第三抗反射层。
  14. 根据权利要求13所述的半导体结构制作方法，其中，所述填充层的材质包括非晶碳，所述第二抗反射层和所述第三抗反射层的材质包括氮氧化硅，所述第二掩膜层的材质包括SOH。
  15. 一种半导体结构，其中，所述半导体结构包括位线，所述位线通过权利要求1所述的半导体结构制作方法形成。
PCT/CN2021/104782 2021-03-31 2021-07-06 半导体结构制作方法及半导体结构 WO2022205659A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/468,920 US11942522B2 (en) 2021-03-31 2021-09-08 Method for manufacturing semiconductor structure and semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110348268.4 2021-03-31
CN202110348268.4A CN113097147B (zh) 2021-03-31 2021-03-31 半导体结构制作方法及半导体结构

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/468,920 Continuation US11942522B2 (en) 2021-03-31 2021-09-08 Method for manufacturing semiconductor structure and semiconductor structure

Publications (1)

Publication Number Publication Date
WO2022205659A1 true WO2022205659A1 (zh) 2022-10-06

Family

ID=76671958

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/104782 WO2022205659A1 (zh) 2021-03-31 2021-07-06 半导体结构制作方法及半导体结构

Country Status (2)

Country Link
CN (1) CN113097147B (zh)
WO (1) WO2022205659A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113707613B (zh) * 2021-08-12 2023-07-04 长鑫存储技术有限公司 半导体结构的形成方法
CN114361259A (zh) * 2022-01-11 2022-04-15 长鑫存储技术有限公司 半导体结构及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140154882A1 (en) * 2012-12-05 2014-06-05 Samsung Electronics Co., Ltd. Methods for fabricating a semiconductor device
US20160035731A1 (en) * 2014-08-04 2016-02-04 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
CN109003938A (zh) * 2018-07-26 2018-12-14 长鑫存储技术有限公司 半导体接触结构、存储器结构及其制备方法
CN112530946A (zh) * 2019-09-18 2021-03-19 长鑫存储技术有限公司 半导体结构及其制作方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101929478B1 (ko) * 2012-04-30 2018-12-14 삼성전자주식회사 매립 채널 어레이를 갖는 반도체 소자

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140154882A1 (en) * 2012-12-05 2014-06-05 Samsung Electronics Co., Ltd. Methods for fabricating a semiconductor device
US20160035731A1 (en) * 2014-08-04 2016-02-04 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
CN109003938A (zh) * 2018-07-26 2018-12-14 长鑫存储技术有限公司 半导体接触结构、存储器结构及其制备方法
CN112530946A (zh) * 2019-09-18 2021-03-19 长鑫存储技术有限公司 半导体结构及其制作方法

Also Published As

Publication number Publication date
CN113097147A (zh) 2021-07-09
CN113097147B (zh) 2022-06-10

Similar Documents

Publication Publication Date Title
KR100308622B1 (ko) 디램 셀 캐패시터 및 제조 방법
CN111799261B (zh) 具有电容连接垫的半导体结构与电容连接垫的制作方法
WO2022179041A1 (zh) 半导体结构及其形成方法
WO2022205659A1 (zh) 半导体结构制作方法及半导体结构
WO2022205739A1 (zh) 一种图案化方法及半导体结构
US6743693B2 (en) Method of manufacturing semiconductor memory
US20230197461A1 (en) Method for Manufacturing Semiconductor Structure, and Semiconductor Structure
US6372575B1 (en) Method for fabricating capacitor of dram using self-aligned contact etching technology
TWI703565B (zh) 記憶體元件及其製造方法
WO2023206685A1 (zh) 半导体结构及半导体结构的制作方法
WO2023000657A1 (zh) 半导体结构及其制备方法
WO2022236980A1 (zh) 存储器的制作方法
WO2022052545A1 (zh) 半导体器件及其制造方法
TWI781559B (zh) 半導體裝置
US11942522B2 (en) Method for manufacturing semiconductor structure and semiconductor structure
WO2022083168A1 (zh) 半导体结构制作方法及半导体结构
WO2024108744A1 (zh) 半导体结构及其形成方法
US20220301931A1 (en) Method for fabricating semiconductor structure, and semiconductor structure
WO2022088734A1 (zh) 半导体结构的制备方法及半导体结构
US20220085021A1 (en) Semiconductor device and method for manufacturing the same
WO2022062548A1 (zh) 存储器的制造方法和存储器
WO2023092827A1 (zh) 半导体结构及其制作方法
US20240008245A1 (en) Method for fabricating semiconductor structure, and semiconductor structure
WO2022095433A1 (zh) 半导体结构制作方法及半导体结构
KR100949899B1 (ko) 반도체 소자의 커패시터 제조 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21934307

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21934307

Country of ref document: EP

Kind code of ref document: A1