WO2022095433A1 - 半导体结构制作方法及半导体结构 - Google Patents

半导体结构制作方法及半导体结构 Download PDF

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Publication number
WO2022095433A1
WO2022095433A1 PCT/CN2021/097381 CN2021097381W WO2022095433A1 WO 2022095433 A1 WO2022095433 A1 WO 2022095433A1 CN 2021097381 W CN2021097381 W CN 2021097381W WO 2022095433 A1 WO2022095433 A1 WO 2022095433A1
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Prior art keywords
contact
substrate
layer
contact pad
semiconductor structure
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PCT/CN2021/097381
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English (en)
French (fr)
Inventor
曹新满
刘忠明
夏军
白世杰
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长鑫存储技术有限公司
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Priority to US17/500,276 priority Critical patent/US20220139923A1/en
Publication of WO2022095433A1 publication Critical patent/WO2022095433A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • Embodiments of the present invention relate to the technical field of semiconductor manufacturing, and in particular, to a method for fabricating a semiconductor structure and a semiconductor structure.
  • Dynamic Random Access Memory (DRAM for short) is gradually applied in various electronic devices due to its higher density and faster read and write speed.
  • Dynamic random access memory consists of multiple repeating memory cells.
  • the memory cell generally includes a capacitor structure and a transistor structure, and the transistor structure is connected with the capacitor structure to read data stored in the capacitor structure through the transistor structure, or write data into the capacitor structure.
  • the transistor structure is disposed in a substrate, a contact structure is disposed on the substrate, and the contact structure is connected to the source of the transistor structure.
  • a conductive layer is first formed on the substrate, and then the conductive layer is etched to form a contact structure composed of multiple contact pads; then the contact structure is sequentially wet-etched for multiple times to remove the carbon on the pad pads base polymer and residual core.
  • the embodiments of the present invention provide a method for fabricating a semiconductor structure and a semiconductor structure, so as to solve the problem of removing residues on the contact pads by multiple wet etchings, and at the same time removing part of the film layer between the contact pads and the substrate, so that the The reduction of the connection area between the contact pad and the substrate may easily lead to the technical problem of breakage of the contact pad.
  • An embodiment of the present invention provides a method for fabricating a semiconductor structure, including: providing a substrate with a plurality of transistor structures arranged at intervals in the substrate; forming a conductive layer on the substrate, and removing part of the conductive layer to A contact structure consisting of a plurality of contact pads is formed, and each of the contact pads is electrically connected to one of the transistor structures; the residual core on the top of the contact pads away from the substrate is removed by dry etching.
  • the method before removing the residual core on the top of the contact pad away from the substrate by dry etching, the method further includes: forming a protective layer on the surface of the contact pad; Removing the residual core on the top of the contact pad away from the substrate by dry etching includes: removing the protective layer on the top of the contact pad and the residual core on the top by dry etching .
  • the method further includes: forming a filling layer, the filling layer filling the adjacent gaps between the contact pads, and the filling layer covers the top ends of the contact pads.
  • the method further includes: removing part of the filling layer to expose the top ends of the contact pads.
  • the method before forming the conductive layer, further includes: forming an insulating structure on the substrate, the insulating structure having a plurality of contact holes, each of the contact holes facing a transistor structure; forming the conductive layer includes: forming the conductive layer in the contact hole and on the insulating structure.
  • removing a portion of the conductive layer to form a contact structure composed of a plurality of contact pads includes forming a pattern transfer layer on the conductive layer, the pattern transfer layer having a plurality of A discrete first pattern, the projection of the first pattern on the insulating structure covers part of the contact hole, and the first pattern is used as a mask to etch part of the insulating structure and part of the conductive layer to A plurality of the contact pads are formed.
  • the method further includes: removing residual polymer on the contact pads by wet etching.
  • forming a pattern transfer layer on the conductive layer includes: sequentially forming a pattern transfer layer and a mask layer on the conductive layer, patterning the mask layer, forming multiple a plurality of discrete second patterns, and the pattern transfer layer is etched by using the second pattern as a mask to form the plurality of discrete first patterns.
  • the method further includes: forming a conductive barrier on the insulating structure, the sidewall of the contact hole and the bottom of the contact hole layer.
  • An embodiment of the present invention further provides a semiconductor structure, including a substrate and a contact structure disposed on the substrate, the substrate has a plurality of transistor structures arranged at intervals, and the contact structure includes a plurality of contact pads, Each of the contact pads is connected to one of the transistor structures; after the contact pads are formed, the residual core on the top of the contact pad away from the substrate is removed by dry etching.
  • a conductive layer is formed on a substrate, and part of the conductive layer is removed to form a contact structure composed of a plurality of contact pads, each of which is electrically connected to a transistor structure on one substrate.
  • connections after the contact pads are formed, the residual core on the top of the contact pads facing away from the substrate is removed by dry etching; dry etching is anisotropic compared to wet etching, etching contacts in the direction towards the substrate Pad, it will not cause damage to the side wall of the contact pad and other films on the plane where the side wall of the contact pad is located, that is to say, the conductive barrier layer between the contact pad and the surface of the insulating structure away from the substrate will not be damaged, ensuring that The connection force between the contact pad and the insulating structure is improved, thereby preventing the contact pad from breaking.
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure provided by an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram after forming a photolithography layer in a method for fabricating a semiconductor structure provided by an embodiment of the present invention
  • Fig. 3 is the top view of Fig. 2;
  • FIG. 4 is a schematic structural diagram of a semiconductor structure fabrication method provided by an embodiment of the present invention after contact pads are formed;
  • Fig. 5 is the top view of Fig. 4;
  • FIG. 6 is a schematic structural diagram of a residual polymer and a residual core on a contact pad in a method for fabricating a semiconductor structure provided by an embodiment of the present invention
  • Fig. 7 is the top view of Fig. 6;
  • FIG. 8 is a schematic structural diagram of a method for fabricating a semiconductor structure provided by an embodiment of the present invention after removing residual polymer by wet etching;
  • Fig. 9 is the top view of Fig. 8.
  • FIG. 10 is a schematic structural diagram after forming a protective layer in a method for fabricating a semiconductor structure provided by an embodiment of the present invention.
  • Fig. 11 is the top view of Fig. 10;
  • FIG. 12 is a schematic structural diagram of a method for fabricating a semiconductor structure provided by an embodiment of the present invention after removing the residual core by dry etching;
  • Fig. 13 is the top view of Fig. 12;
  • FIG. 14 is a schematic structural diagram after forming a filling layer in a method for fabricating a semiconductor structure provided by an embodiment of the present invention.
  • Fig. 15 is the top view of Fig. 14;
  • 16 is a schematic structural diagram of a semiconductor structure fabrication method provided by an embodiment of the present invention after removing part of the filling layer to expose the top of the contact pad;
  • FIG. 17 is a plan view of FIG. 16 .
  • bit line barrier layer bit line barrier layer
  • Dynamic Random Access Memory includes multiple repetitive storage units.
  • the memory cell includes a capacitor structure and a transistor structure.
  • the gate of the transistor structure is connected to the word line
  • the drain of the transistor structure is connected to the bit line
  • the source of the transistor structure is connected to the capacitor structure.
  • the voltage signal on the word line can control the opening of the transistor. or off, and then read the data stored in the capacitance structure through the bit line, or write data into the capacitance structure through the bit line.
  • a plurality of transistor structures are arranged in a substrate at intervals, a contact structure is arranged on the substrate, and the contact structure includes a plurality of contact pads arranged at intervals, and each contact pad is connected to a source of a transistor structure.
  • an insulating structure is first formed on the substrate, and the insulating structure has a plurality of contact holes, each of which is facing the source of a transistor structure; the sidewalls, the bottom of the hole and the insulating structure are conductively formed.
  • a barrier layer, and a conductive layer is formed on the conductive barrier layer, and the conductive layer is filled with contact holes; the conductive layer, conductive barrier layer and insulating structure corresponding to some contact holes are removed by using the amorphous carbon mask layer as a mask to form multiple contacts pads; each contact pad includes a first portion located in the contact hole and a second portion located on the insulating structure; the contact pads are etched by wet etching to remove residues on the sidewalls of the contact pads and the top away from the substrate of carbon-based polymer; wet-etch the contact pad again to remove the residual core on top of the contact pad.
  • the conductive layer as metal tungsten as an example, after the process of etching to form the contact pad, an ashing process is required to remove the mask layer.
  • an ashing process is required to remove the mask layer.
  • the halogen-containing by-products after etching and tungsten react with each other.
  • the halogen-containing by-products are easier to volatilize, and soon the halogen content in the tungsten halides becomes less and less volatile, and the shell-like inclusions of tungsten are formed, which are the residual cores.
  • the residues on the contact pads are removed by multiple wet etchings after the contact pads are formed, during which part of the conductive barrier layer between the contact pads and the surface of the insulating structure facing away from the substrate is removed (Part II).
  • Part II The conductive barrier layer between the contact pad and the insulating structure reduces the connection area between the contact pad and the junction structure, and the contact pad is prone to breakage.
  • the present embodiment provides a method for fabricating a semiconductor structure and a semiconductor structure, in which the residual core located at the top of the contact pad is removed by dry etching; since the dry etching has anisotropy, when etching the top of the contact pad, contact can be avoided.
  • the conductive barrier layer between the pad and the surface of the insulating structure facing away from the substrate is removed, which ensures the connection force between the contact pad and the insulating structure, thereby preventing the contact pad from breaking.
  • This embodiment does not limit the semiconductor structure.
  • the following will take the semiconductor structure as a dynamic random access memory (DRAM) as an example for introduction, but this embodiment is not limited to this, and the semiconductor structure in this embodiment can also be other structures .
  • DRAM dynamic random access memory
  • the semiconductor fabrication method provided in this embodiment includes:
  • S101 Provide a substrate, and the substrate has a plurality of transistor structures arranged at intervals.
  • the substrate 10 may include a plurality of shallow trench isolation structures 102 arranged at intervals, and a transistor structure is disposed between adjacent shallow trench isolation structures 102 , and the transistor structure includes an active region structure 101 .
  • the material of the shallow trench isolation structure 102 may include oxides such as silicon oxide, and the material of the active region structure 101 may include silicon or the like.
  • the substrate 10 also includes a plurality of spaced-apart conductive blocks 103 , each conductive block 103 being bonded to one active area structure 101 .
  • the material of the conductive block 103 may include a conductive material such as polysilicon.
  • bit lines 104 may be disposed between adjacent active region structures 101, and the bit lines 104 may include a first bit line structure 1041, a bit line barrier layer 1043 and a second bit line structure 1042 that are stacked and disposed, wherein The second bit line structure 1042 is disposed close to the active region structure 101 and the shallow trench isolation structure 102; the bit line barrier layer 1043 can prevent the materials between the first bit line structure 1041 and the second bit line structure 1042 from interpenetrating, and the bit line The line barrier layer 1043 may also realize electrical connection between the first bit line structure 1041 and the second bit line structure 1042 .
  • the material of the first bit line structure 1041 may include tungsten or the like
  • the material of the second bit line structure 1042 may include polysilicon or the like
  • the material of the bit line barrier layer 1043 may include titanium nitride or the like.
  • an insulating film may be provided between the conductive block 103 and the bit line 104, and an exemplary material of the insulating film may include silicon nitride, Silicon oxide etc.
  • the method for fabricating the semiconductor structure provided by this embodiment further includes:
  • S102 forming a conductive layer on the substrate, and removing part of the conductive layer to form a contact structure composed of a plurality of contact pads, each of which is electrically connected to a transistor structure.
  • each contact pad 201 is connected to one conductive block 103 is connected to realize the electrical connection between the contact pad 201 and the active region structure 101, and further realize the electrical connection between the contact pad 201 and the transistor structure.
  • the material of the conductive layer 20 may include tungsten, etc.
  • the contact pad 201 is a metal pad made of tungsten, and the contact pad 201 is used for electrical connection with the capacitor structure to realize the reading of data in the capacitor structure, or Write data into the capacitive structure.
  • the contact pad 201 includes a top end away from the substrate 10, a bottom end facing the substrate 10, and a side wall between the top end and the bottom end.
  • the top end of the contact pad 201 is used for electrical connection with the capacitor structure, and the contact pad
  • the bottom end of 201 is used for electrical connection with the transistor structure.
  • the insulating structure 105 before forming the conductive layer 20, it further includes: forming an insulating structure 105 on the substrate 10, and the insulating structure 105 has a plurality of contact holes, and each contact hole is opposite to one Transistor structure; exemplarily, the material of the insulating structure 105 may include silicon nitride, silicon oxide, or the like.
  • the insulating structures 105 are provided on the conductive blocks 103 and the bit lines 104 , and each contact hole is provided on one conductive block 103 . .
  • the conductive layer 20 is formed in the contact hole and on the insulating structure 105 , that is, the conductive layer 20 fills the contact hole and covers the side of the insulating structure 105 facing away from the substrate 10 .
  • the insulating structure 105 can achieve isolation between adjacent contact pads 201 , thereby avoiding contact between adjacent contact pads 201 .
  • a conductive barrier layer 106 is formed on the insulating structure 105 , the sidewalls of the contact holes, and the bottoms of the contact holes. Wherein, the conductive barrier layer 106 is not filled with the contact holes. In the subsequent steps, the conductive layer 20 is formed on the conductive barrier layer 106 and bonded with the conductive barrier layer 106 .
  • the conductive barrier layer 106 can prevent penetration between the contact pad 201 and the conductive block 103, and the conductive barrier layer 106 can also realize the electrical connection between the contact pad 201 and the conductive block 103, thereby improving the performance of the semiconductor structure.
  • the conductive barrier layer 106 may include a first barrier layer 1061 and a second barrier layer 1062, the first barrier layer 1061 is disposed close to the substrate 10, and the second barrier layer 1062 is used for bonding with the contact pad 201; the first barrier layer
  • the material of 1061 may include titanium, and the material of the second barrier layer 1062 may include titanium nitride; this embodiment does not limit the material of the conductive barrier layer 106, as long as it can prevent penetration between the contact pad 201 and the conductive block 103, and achieve The electrical connection between the contact pad 201 and the conductive block 103 is sufficient.
  • the conductive barrier layer 106 before forming the conductive barrier layer 106, it also includes forming an intermediate layer on the side of the conductive block 103 away from the substrate 10, and the material of the intermediate layer may include cobalt silicide (CoSix) or the like, that is, the contact pads 201 sequentially pass the conductive The barrier layer 106 , the intermediate layer and the conductive block 103 achieve electrical connection with the active region structure 101 .
  • CoSix cobalt silicide
  • removing the conductive layer 20 to form a contact structure composed of a plurality of contact pads 201 includes: forming a pattern transfer layer 30 on the conductive layer 20, and the pattern transfer layer has a plurality of discrete The first pattern 301 , the projection of the first pattern 301 on the insulating structure covers part of the contact holes, and the first pattern 301 is used as a mask to etch part of the insulating structure 105 and part of the conductive layer 20 to form a plurality of contact pads 201 .
  • Part of the conductive layer 20 is removed by using the first pattern 301 as a mask to form the contact pad 201 ; in this way, the formed contact pad 201 has high dimensional accuracy and improves the performance of the semiconductor structure.
  • part of the conductive layer 20 may be removed by etching to form the contact pad 201 .
  • the conductive barrier layer 106 and the insulating structure 105 corresponding to the gaps between the adjacent first patterns 301 are simultaneously removed, so that the formed contact pads 201 include the contact pads 201 located in the contact holes.
  • the first part of the contact hole and the second part covering the insulating structure 105 ; reasonable setting of the etching depth can avoid damaging the conductive barrier layer 106 at the bottom of the contact hole and the layers of the conductive barrier layer 106 facing the substrate 10 .
  • forming the pattern transfer layer 30 on the conductive layer 20 includes: sequentially forming the pattern transfer layer 30 and the mask layer 40 on the conductive layer 20 , patterning the mask layer 40 , forming multiple The pattern transfer layer 30 is etched by using the second pattern 403 as a mask to form a plurality of discrete first patterns 301 .
  • the first pattern 301 on the pattern transfer layer 30 is formed through the pattern transfer of the mask layer 40 , and the dimensional accuracy of the first pattern 301 is improved.
  • the material of the pattern transfer layer 30 may include amorphous carbon
  • the material of the mask layer 40 may include silicon oxynitride, silicon oxynitride, silicon oxide, etc.
  • the mask layer 40 may be a single film layer, of course, the mask layer 40 can also be a multi-film layer.
  • the mask layer 40 includes a first mask layer 401 and a second mask layer 402 arranged in layers, and the second mask layer 402 is located in the first mask layer. The upper part of the film layer 401.
  • the mask layer 40 is patterned so that a second pattern 403 is formed on the mask layer 40 , and the pattern transfer layer 30 is etched by using the second pattern 403 as a mask to form the first pattern 301 .
  • the mask layer 40 is patterned to form a plurality of discrete second patterns 403.
  • the second patterns 403 can be formed by intersecting a two-step SADP process. In other embodiments, other patterning methods can also be used to form the second patterns 403. the second pattern 403 .
  • the pattern transfer layer 30 is used as a mask to remove part of the conductive layer 20 to form the contact pad 201, a part of the mask layer 40 will remain on the contact pad 201. Therefore, in the subsequent process, the remaining mask layer needs to be removed 40, so as to expose the top of the contact pad 201, so as to facilitate the electrical connection between the contact pad 201 and the capacitor structure.
  • the method further includes: removing the residual polymer 202 on the contact pads 201 by wet etching. In this way, the residual polymer 202 located on the top and sidewalls of the contact pads 201 can be removed, the connection resistance between the contact pads 201 and the capacitor structure can be reduced, and the performance of the semiconductor structure can be improved.
  • a carbon-based polymer will be formed on the sidewalls.
  • the conductive layer as tungsten as an example, as shown in FIG. 4 to FIG. 6 , after etching to form the contact pad, an ashing process is required to remove the pattern transfer layer 30. Under high temperature conditions, the halogen-containing by-products and tungsten after etching are performed.
  • the halogen-containing by-products are more easily volatilized, and soon the halogen content in the tungsten halide becomes less and less volatile, forming a shell-like inclusion of tungsten, which is the residual core.
  • the method for fabricating the semiconductor structure provided in this embodiment further includes:
  • the gas used may include carbon tetrafluoride (CF4) or trifluoromethane (CHF3) and the like.
  • dry etching has anisotropy.
  • the contact pad 201 is etched toward the substrate 10 , the sidewall of the contact pad 201 and other films on the plane where the sidewall of the contact pad 201 is located will not be affected.
  • Destruction that is, the conductive barrier layer 106 between the second part of the contact pad 201 and the surface of the insulating structure 105 facing away from the substrate 10 will not be damaged, ensuring the connection force between the contact pad 201 and the insulating structure 105, Thereby, breakage of the contact pads 201 is avoided.
  • residual polymer 202 remains on the surface of the sidewall and top of the contact pad 201, and a residual core 203 remains on the top of the contact pad 201, wherein the residual core 203 is located inside the top surface; dry etching Removing the residual core 203 in a manner can further reduce the connection resistance between the contact pad 201 and the capacitor structure, thereby improving the performance of the semiconductor structure.
  • the first pattern 301 of the pattern transfer layer 30 is used as a mask to remove part of the conductive layer 20 to form the contact pad 201
  • residual polymer is formed on the surface of the sidewall and the top of the contact pad 201, and the top of the contact pad 201 is formed with residual polymer. Residual cores are formed on the surface; after the contact pads 201 are formed, wet etching is performed on the contact pads 201 to remove residual polymer, and then dry etching is performed on the contact pads 201 to remove residual cores on the top of the contact pads 201 .
  • a conductive layer 20 is formed on a substrate 10 , and a part of the conductive layer 20 is removed to form a contact structure composed of a plurality of contact pads 201 , each contact pad 201 and a contact pad 201 on the substrate 10
  • the transistor structure is electrically connected; after the contact pad 201 is formed, the residual core 203 on the top of the contact pad 201 away from the substrate 10 is removed by dry etching;
  • the contact pad 201 is etched in the direction of the substrate 10 , the side wall of the contact pad 201 and other films on the plane where the side wall of the contact pad 201 is located will not be damaged, that is, the contact pad 201 and the insulating structure 105 are away from the substrate 10 .
  • the conductive barrier layer 106 between the surfaces of the contact pads will not be damaged, which ensures the connection force between the contact pads 201 and the insulating structure 105, thereby preventing the contact pads 201 from breaking.
  • the method further includes: forming a protective layer 60 on the surface of the contact pad 201 .
  • the protective layer 60 can protect the sidewalls and bottom ends of the contact pads 201 , further preventing the conductive barrier layer 106 between the contact pads 201 and the insulating structure 105 from being damaged, and further preventing the contact pads 201 from breaking.
  • the material of the protective layer 60 may include insulating materials such as silicon nitride.
  • the protective layer 60 can be formed by a process such as atomic deposition (ALD), and the thickness of the protective layer 60 can be 3 nm-7 nm, for example, the thickness of the protective layer 60 can be 5 nm.
  • Removing the residual core 203 on the top of the contact pad 201 away from the substrate 10 by dry etching includes: removing the protective layer 60 on the top of the contact pad 201 and the residual core 203 on the top by dry etching.
  • part of the contact pads 201 at the top can be removed to remove the residual core 203 in the contact pads 201 at the top.
  • the method further includes: forming a filling layer 70 , and the filling layer 70 fills the adjacent contact pad 201 and the filling layer 70 covers the top of the contact pad 201 .
  • the filling layer 70 fills the gaps between adjacent contact pads 201 to support the contact pads 201 , thereby preventing the contact pads 201 from tilting.
  • the material of the filling layer 70 may include insulating materials such as silicon nitride.
  • the material of the filling layer 70 and the material of the protective layer 60 can be the same, so that after the filling layer 70 is formed, the filling layer 70 and the protective layer 60 can form an integral structure, thereby improving the support effect for the contact pad 201 .
  • the method further includes: removing part of the filling layer 70 to expose the top of the contact pad 201 .
  • This arrangement can facilitate the connection between the contact pad 201 and the capacitor structure in the subsequent process.
  • this embodiment further provides a semiconductor structure, including a substrate 10 and a contact structure disposed on the substrate 10, the substrate 10 has a plurality of transistor structures arranged at intervals, and the contact structure includes a plurality of transistor structures.
  • Each contact pad 201 is connected to a transistor structure; after the contact pad 201 is formed, the residual core 203 on the top of the contact pad 201 away from the substrate 10 is removed by dry etching.
  • the semiconductor structure in this embodiment can be fabricated by the method for fabricating the semiconductor structure provided in any of the above embodiments.
  • a conductive layer 20 is formed on the substrate 10 , and part of the conductive layer 20 is removed to form a contact structure composed of a plurality of contact pads 201 , each contact pad 201 and a transistor structure on the substrate 10 Electrical connection; after the contact pad 201 is formed, the residual core 203 on the top of the contact pad 201 away from the substrate 10 is removed by dry etching; When the contact pad 201 is etched in the direction of the bottom 10, the side wall of the contact pad 201 and other films on the plane where the side wall of the contact pad 201 is located will not be damaged, that is, the contact pad 201 and the insulating structure 105 are away from the surface of the substrate 10. The conductive barrier layer 106 between them will not be damaged, which ensures the connection force between the contact pads 201 and the insulating structure 105, thereby preventing the contact pads 201 from breaking.

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Abstract

本发明实施例属于半导体制造技术领域，涉及一种半导体结构制作方法及半导体结构，用于解决的接触垫容易断裂的问题。该半导体结构制作方法包括：在衬底上形成导电层，去除部分导电层以形成由多个接触垫构成的接触结构，每一接触垫与一个衬底上的晶体管结构电连接；在形成接触垫之后，通过干法蚀刻的方式去除接触垫背离衬底的顶端上的残留核心；与湿法蚀刻相比，干法蚀刻具有各向异性，在向衬底的方向蚀刻接触垫时，不会对接触垫侧壁以及接触垫侧壁所在平面的其他膜层造成破坏，也就是说，接触垫与绝缘结构背离衬底的表面之间的导电阻挡层不会被破坏，保证了接触垫与绝缘结构之间的连接力，进而避免接触垫断裂。

Description

半导体结构制作方法及半导体结构
本申请要求于2020年11月4日提交中国专利局、申请号为2020112176857、申请名称为“半导体结构制作方法及半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及半导体制造技术领域，尤其涉及一种半导体结构制作方法及半导体结构。
背景技术
随着存储设备技术的逐渐发展，动态随机存储器(Dynamic Random Access Memory，简称DRAM)以其较高的密度以及较快的读写速度逐渐应用在各种电子设备中。动态随机存储器由多个重复的存储单元组成。存储单元通常包括电容结构和晶体管结构，晶体管结构与电容结构相连，以通过晶体管结构读取存储在电容结构中的数据，或者将数据写入到电容结构中。
相关技术中，晶体管结构设置在衬底内，衬底上设置有接触结构，接触结构与晶体管结构的源极连接。制作时，先在衬底上形成导电层，之后对导电层进行蚀刻，以形成由多个接触垫构成的接触结构；之后依次对接触结构进行多次湿法蚀刻，以去除焊盘垫上的碳基聚合物以及残留核心。
然而，通过多次湿法蚀刻去除接触垫上的残留物的同时，会去除部分接触垫和衬底之间的膜层，使得接触垫与衬底之间的连接面积减小，容易导致接触垫断裂。
发明内容
有鉴于此，本发明实施例提供一种半导体结构制作方法及半导体结构，以解决多次湿法蚀刻去除接触垫上的残留物的同时，会去除部分接触垫和衬底之间的膜层，使得接触垫与衬底之间的连接面积减小，容易导致接触垫断裂的技术问题。
本发明实施例提供了一种半导体结构制作方法，包括：提供衬底，所述衬底内具有多个间隔设置的晶体管结构；在所述衬底上形成导电层，去除部分所述导电层以形成由多个接触垫构成的接触结构，每一所述接触垫与一个所述晶体管结构电连接；通过干法蚀刻的方式去除所述接触垫背离所述衬底的顶端上的残留核心。
在可以包括上述实施例的一些实施例中，通过干法蚀刻的方式去除所述接触垫背离所述衬底的顶端上的残留核心之前还包括：在所述接触垫的表面形成保护层；通过干法蚀刻的方式去除所述接触垫背离所述衬底的顶端上的残留核心包括：通过干法蚀刻的方式去除位于所述接触垫顶端的所述保护层、以及位于顶端的所述残留核心。
在可以包括上述实施例的一些实施例中，通过干法蚀刻的方式去除所述接触垫背离所述衬底的顶端上的残留核心之后还包括：形成填充层，所述填充层填充相邻所述接触垫之间的间隙，并且所述填充层覆盖在所述接触垫的顶端。
在可以包括上述实施例的一些实施例中，形成填充层之后还包括：去除部分所述填充层，以暴露出所述接触垫的顶端。
在可以包括上述实施例的一些实施例中，形成导电层之前还包括：在所述衬底上形成绝缘结构，所述绝缘结构上具有多个接触孔，每一所述接触孔正对一个晶体管结构；形成所述导电层包括：在所述接触孔内以及所述绝缘结构上形成所述导电层。
在可以包括上述实施例的一些实施例中，去除部分所述导电层以形成由多个接触垫构成的接触结构包括：在所述导电层上形成图案转移层，所述图案转移层具有多个分立的第一图案，所述第一图案在所述绝缘结构上的投影覆盖部分所述接触孔，以所述第一图案为掩膜刻蚀部分所述绝缘结构和部分所述导电层，以形成多个所述接触垫。
在可以包括上述实施例的一些实施例中，形成多个接触垫之后还包括：通过湿法蚀刻去除所述接触垫上的残留聚合物。
在可以包括上述实施例的一些实施例中，在所述导电层上形成图案转移层包括：在所述导电层上依次形成图案转移层、掩膜层，图案化所述掩膜层，形成多个分立的第二图案，以所述第二图案为掩膜刻蚀所述图案转移层，形成所述多个分立的第一图案。
在可以包括上述实施例的一些实施例中，在所述衬底上形成绝缘结构之后还包括：在所述绝缘结构上、所述接触孔的侧壁以及所述接触孔的孔底形成导电阻挡层。
本发明实施例还提供一种半导体结构，包括衬底以及设置在所述衬底上的接触结构，所述衬底内具有间隔设置的多个晶体管结构，所述接触结构包括多个接触垫，每一所述接触垫与一个所述晶体管结构连接；形成所述接触垫之后，通过干法蚀刻的方式去除所述接触垫背离所述衬底的顶端上的残留核心。
本实施例提供的半导体结构制作方法及半导体结构，在衬底上形成导电层，去除部分导电层以形成由多个接触垫构成的接触结构，每一接触垫与一个衬底上的晶体管结构电连接；在形成接触垫之后，通过干法蚀刻的方式去除接触垫背离衬底的顶端上的残留核心；与湿法蚀刻相比，干法蚀刻具有各向异性，在向衬底的方向蚀刻接触垫时，不会对接触垫侧壁以及接触垫侧壁所在平面的其他膜层造成破坏，也就是说，接触垫与绝缘结构背离衬底的表面之间的导电阻挡层不会被破坏，保证了接触垫与绝缘结构之间的连接力，进而避免接触垫断裂。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的半导体结构制作方法的流程图；
图2为本发明实施例提供的半导体结构制作方法中形成光刻层之后的结构示意图；
图3为图2的俯视图；
图4为本发明实施例提供的半导体结构制作方法中形成接触垫后的结构示意图；
图5为图4的俯视图；
图6为本发明实施例提供的半导体结构制作方法中接触垫上具有残留聚合物和残留核心的结构示意图；
图7为图6的俯视图；
图8为本发明实施例提供的半导体结构制作方法中通过湿法蚀刻去除残留聚合物后的结构示意图；
图9为图8的俯视图；
图10为本发明实施例提供的半导体结构制作方法中形成保护层后的结构示意图；
图11为图10的俯视图；
图12为本发明实施例提供的半导体结构制作方法中通过干法蚀刻的方式去除残留核心后的结构示意图；
图13为图12的俯视图；
图14为本发明实施例提供的半导体结构制作方法中形成填充层后的结构示意图；
图15为图14的俯视图；
图16为本发明实施例提供的半导体结构制作方法中去除部分填充层以暴露接触垫顶端后的结构示意图；
图17为图16的俯视图。
附图标记说明：
10：衬底；
20：导电层；
30：图案转移层；
40：掩膜层；
60：保护层；
70：填充层
101：有源区结构；
102：浅沟槽隔离结构；
103：导电块；
104：位线；
105：绝缘结构；
106：导电阻挡层；
201：接触垫；
202：残留聚合物；
203：残留核心；
301：第一图案；
403：第二图案；
1041：第一位线结构；
1042：第二位线结构；
1043：位线阻挡层；
1061：第一阻挡层；
1062：第二阻挡层。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
动态随机存储器(Dynamic Random Access Memory，简称DRAM)包括多个重复的存储单元。存储单元包括电容结构和晶体管结构，晶体管结构的栅极与字线相连，晶体管结构的漏极与位线相连，晶体管结构的源极与电容结构相连；字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容结构中的数据，或者通过位线将数据写入到电容结构中。
相关技术中，多个晶体管结构间隔的设置在衬底内，衬底上设置有接触结构，接触结构包括多个间隔设置的接触垫，每一接触垫与一个晶体管结构的源极连接。在制作时，先在衬底上形成绝缘结构，绝缘结构上具有多个接触孔，每一接触孔正对一个晶体管结构的源极；在接触孔的侧壁、孔底以及绝缘结构上形成导电阻挡层，并且在导电阻挡层上形成导电层，导电层充满接触孔；以非晶碳掩膜层为掩膜去除部分接触孔对应的导电层、导电阻挡层以及绝缘结构，以形成多个接触垫；每一接触垫包括位于接触孔内的第一部分以及位于绝缘结构上的第二部分；通过湿法蚀刻的方式对接触垫进行蚀刻，以去除残留在接触垫侧壁和背离基底的顶端上的碳基聚合物；再次对接触垫进行湿法蚀刻，以去除位于接触垫顶端的残留核心。
具体地，以导电层为金属钨为例，在刻蚀形成接触垫的过程后，需要灰化工艺去除掩膜层，高温状态下，在进行蚀刻后的含卤素的副产物和钨反应形成的钨的卤化物，其中含卤素的副产物较容易挥发，很快其钨的卤化物中卤含量变少，较难挥发，形成钨的壳状包附物，即为残留核心。
然而，在形成接触垫后通过多次湿法蚀刻来去除位于接触垫上的残留物，在蚀刻的过程中会去除接触垫与绝缘结构背离衬底的表面之间的部分导电阻挡层(第二部分与绝缘结构之间的导电阻挡层)，使得接触垫与结缘结构之间的连接面积减小，接触垫容易发生断裂。
本实施例提供一种半导体结构制作方法及半导体结构，通过干法蚀刻的方式去除位于接触垫顶端的残留核心；由于干法蚀刻具有各向异性，在对接触垫顶端进行蚀刻时，可以避免接触垫与绝缘结构背离衬底的表面之间的导电阻挡层被去除，保证了接触垫与绝缘结构之间的连接力，进而避免接触垫断裂。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图1所示，本实施例提供的半导体制作方法包括：
S101：提供衬底，衬底内具有多个间隔设置的晶体管结构。
请参照图2和图3，衬底10可以包括间隔设置的多个浅沟槽隔离结构102，相邻的浅沟槽隔离结构102之间设置有晶体管结构，晶体管结构包括有源区结构101。其中，浅沟槽隔离结构102的材质可以包括氧化硅等氧化物，有源区结构101的材质可以包括硅等。
衬底10还包括多个间隔设置的导电块103，每一导电块103与一个有源区结构101接合。示例性的，导电块103的材料可以包括多晶硅等导电材料。
进一步地，在相邻的有源区结构101之间可以设置有位线104，位线104可以包括层叠设置的第一位线结构1041、位线阻挡层1043以及第二位线结构1042，其中第二位线结构1042靠近有源区结构101和浅沟槽隔离结构102设置；位线阻挡层1043可以阻止第一位线结构1041和第二位线结构1042之间的材质互相渗透，并且位线阻挡层1043也可以实现第一位线结构1041和第二位线结构1042之间的电连接。示例性的，第一位线结构1041的材质可以包括钨等，第二位线结构1042的材质可以包括多晶硅等，位线阻挡层1043的材质可以包括氮化钛等。
在上述实现方式中，为了实现导电块103和位线104之间的绝缘连接，可以在导电块103和位线104之间设置有绝缘膜，示例性的绝缘膜的材质可以包括氮化硅、氧化硅等。
继续参照图1，本实施例提供的半导体结构制作方法还包括：
S102：在衬底上形成导电层，去除部分导电层以形成由多个接触垫构成的接触结构，每一接触垫与一个晶体管结构电连接。
请参照图2-图5，在衬底10上设置有多个与导电块103，并且每一导电块103与一个有源区结构101接合的实现方式中，每一接触垫201与一个导电块103连接，以实现接触垫201与有源区结构101之间的电连接，进而实现接触垫201与晶体管结构之间的电连接。
示例性的，导电层20的材质可以包括钨等，相应的，接触垫201为由钨构成的金属垫，接触垫201用于与电容结构电连接，以实现电容结构内数据的读取，或者向电容结构内写入数据。
本实施例中，接触垫201包括背离衬底10的顶端、朝向衬底10的底端以及位于顶端和底端之间的侧壁，接触垫201的顶端用于与电容结构电连接，接触垫201的底端用于与晶体管结构电连接。
继续参照图2-图5，在一些实施例中，在形成导电层20之前还包括：在衬底10上形成绝缘结构105，绝缘结构105上具有多个接触孔，每一接触孔正对一个晶体管结构；示例性的，绝缘结构105的材料可以包括氮化硅、氧化硅等。
在衬底10上设置有与有源区结构101相接合的导电块103的实现方式中，绝缘结构105设置在导电块103和位线104上，并且每一接触孔正对一个导电块103设置。
在形成绝缘结构105之后，在接触孔内以及绝缘结构105上形成导电层20，也就是说，导电层20充满接触孔并且导电层20覆盖在绝缘结构105背离衬底10的一侧。通过上述设置，绝缘结构105可以实现相邻接触垫201之间的隔离，进而避免相邻接触垫201之间接触。
继续参照图2-图5，本实施例中，在衬底10上形成绝缘结构105之后还包括：
在绝缘结构105上、接触孔的侧壁以及接触孔的孔底形成导电阻挡层106。其中，导电阻挡层106并不充满接触孔，在后续步骤中，导电层20形成在导电阻挡层106上，并且与导电阻挡层106接合。
如此设置，导电阻挡层106可以阻止接触垫201与导电块103之间发生渗透，同时导电阻挡层106还可以实现接触垫201与导电块103之间电连接，进而提高了半导体结构的性能。示例性的，导电阻挡层106可以包括第一阻挡层1061和第二阻挡层1062，第一阻挡层1061靠近衬底10设置，第二阻挡层1062用于与接触垫201接合；第一阻挡层1061的材质可以包括钛，第二阻挡层1062的材质可以包括氮化钛；本实施例对导电阻挡层106的材质不作限制，只要能够阻止接触垫201与导电块103之间发生渗透，并且实现接触垫201与导电块103之间的电连接即可。
进一步地，在形成导电阻挡层106之前还包括在导电块103背离衬底10的一侧形成中间层，中间层的材质可以包括硅化钴(CoSix)等，也就是说，接触垫201依次通过导电阻挡层106、中间层以及导电块103实现与有源区结构101的电连接。
继续参照图1-图5，本实施例中，去除导电层20以形成由多个接触垫201构成的接触结构包括：在导电层20上形成图案转移层30，图案转移层具有多个分立的第一图案301，第一图案301在绝缘结构上的投影覆盖部分接触孔，以第一图案301为掩膜刻蚀部分绝缘结构105和部分导电层20，以形成多个接触垫201。
以第一图案301为掩膜去除部分导电层20，进而形成接触垫201；如此设置，形成的接触垫201尺寸精度较高，提高了半导体结构的性能。示例性的，可以通过蚀刻的方式去除部分导电层20，以形成接触垫201。
在上述实现方式中，在去除部分导电层20的过程中，将相邻第一图案301之间缝隙对应的导电阻挡层106以及绝缘结构105同时去除，使得形成的接触垫201包括位于接触孔内的第一部分以及覆盖在绝缘结构105上的第二部分；合理的设置蚀刻深度，可以避免破坏接触孔孔底的导电阻挡层106、以及导电阻挡层106朝向衬底10一侧的各膜层。
继续参照图2-图5，示例性的，在导电层20上形成图案转移层30包括：在导电层20上依次形成图案转移层30、掩膜层40，图案化掩膜层40，形成多个分立的第二图案403，以第二图案403为掩膜刻蚀图案转移层30，形成多个分立的第一图案301。
如此设置，通过掩膜层40的图形转移，进而形成图案转移层30上的第一图案301，提高了第一图案301的尺寸精度。
示例性的，图案转移层30的材质可以包括非晶碳，掩膜层40的材质可以包括氮氧化硅、氮氧化硅、氧化硅等，掩膜层40可以为单膜层，当然掩膜层40也可以为多膜层。示例性的，在掩膜层40为多膜层的实现方式中，掩膜层40包括层叠设置的第一掩膜层401以及第二掩膜层402，第二掩膜层402位于第一掩膜层401上部。图案化掩膜层40，使在掩膜层40上形成第二图案403，以第二图案403为掩膜蚀刻图案转移层30，进而形成第一图案301。图案化掩膜层40，形成多个分立的第二图案403，本实施例中可以用两步SADP工艺交叉形成所述第二图案403，在其它实施例中，也可以使用其它图案化方式形成所述第二图案403。
进一步地，在以图案转移层30为掩膜去除部分导电层20进而形成接触垫201之后，在接触垫201上会残留部分掩膜层40，因此在后续过程中，需去除残留的掩膜层40，以暴露接触垫201的顶端，便于接触垫201与电容结构电连接。
请参照图6-图9，在上述实现方式中，形成接触垫201之后还包括：通过湿法蚀刻的方式去除接触垫201上的残留聚合物202。如此设置，可以去除位于接触垫201顶端和侧壁的残留聚合物202，降低接触垫201与电容结构之间的连接电阻，进而提高半导体结构的性能。
示例性的，即在以第一图案301为掩膜刻蚀绝缘结构105和导电层20时，会在侧壁形成碳基聚合物。以导电层为钨为例，如图4到图6所示，在蚀刻形成接触垫后，需要灰化工艺去图案转移层30，高温状态下，在进行蚀刻后的含卤素的副产物和钨反应形成的钨的卤化物，其中含卤素的副产物较容易挥发，很快其钨的卤化物中卤含量变少，较难挥发，形成钨的壳状包附物，即为残留核心。
继续参照图1，本实施例中，在形成接触结构之后，本实施例提供的半导体结构制作方法还包括：
S103：通过干法蚀刻的方式去除接触垫背离衬底的顶端上的残留核心。
示例性的，在干法蚀刻的过程中，采用的气体可以为包括四氟化碳(CF4)或者三氟甲烷(CHF3)等。请参照图10-图13，干法蚀刻具有各向异性，在向衬底10的方向蚀刻接触垫201时，不会对接触垫201侧壁以及接触垫201侧壁所在平面的其他膜层造成破坏，也就是说，接触垫201的第二部分与绝缘结构105背离衬底10的表面之间的导电阻挡层106不会被破坏，保证了接触垫201与绝缘结构105之间的连接力，进而避免接触垫201断裂。
在一些实施例中，接触垫201的侧壁和顶端的表面上残留有残留聚合物202，接触垫201顶端上还残留有残留核心203，其中残留核心203位于顶端表面的内侧；通过干法蚀刻的方式去除残留核心203，可以进一步降低接触垫201与电容结构之间的连接电阻，进而提高半导体结构的性能。
在以图案转移层30的第一图案301为掩膜去除部分导电层20进而形成接触垫201的实现方式中，在接触垫201的侧壁和顶端的表面形成有残留聚合物，接触垫201顶端表面形成残留核心；在形成接触垫201之后，先对接触垫201进行湿法蚀刻，以去残留聚合物，之后对接触垫201进行干法蚀刻，以去除位于接触垫201顶端的残留核心。
本实施例提供的半导体结构制作方法，在衬底10上形成导电层20，去除部分导电层20以形成由多个接触垫201构成的接触结构，每一接触垫201与一个衬底10上的晶体管结构电连接；在形成接触垫201之后，通过干法蚀刻的方式去除接触垫201背离衬底10的顶端上的残留核心203；与湿法蚀刻相比，干法蚀刻具有各向异性，在向衬底10的方向蚀刻接触垫201时，不会对接触垫201侧壁以及接触垫201侧壁所在平面的其他膜层造成破坏，也就是说，接触垫201与绝缘结构105背离衬底10的表面之间的导电阻挡层106不会被破坏，保证了接触垫201与绝缘结构105之间的连接力，进而避免接触垫201断裂。
继续参照图10-图13，在上述实现方式中，通过干法蚀刻的方式去除接触垫201 背离衬底10的顶端上的残留核心203之前还包括：在接触垫201的表面形成保护层60。如此设置，保护层60可以对接触垫201的侧壁以及底端进行保护，进一步避免接触垫201与绝缘结构105之间的导电阻挡层106被破坏，进一步避免接触垫201断裂。示例性的，保护层60的材料可以包括氮化硅等绝缘材料。可以采用原子沉积(ALD)等工艺形成保护层60，并且保护层60的厚度可以为3nm-7nm，例如：保护层60的厚度可以为5nm。
通过干法蚀刻的方式去除接触垫201背离衬底10的顶端上的残留核心203包括：通过干法蚀刻的方式去除位于接触垫201顶端的保护层60、以及位于顶端的残留核心203。示例性的，可以去除位于顶端的部分接触垫201，以将顶端的接触垫201内的残留核心203一并去除。
请参照图14和图15，进一步地，通过干法蚀刻的方式去除接触垫201背离衬底10的顶端上的残留核心203之后还包括：形成填充层70，填充层70填充相邻接触垫201之间的间隙，并且填充层70覆盖在接触垫201的顶端。
如此设置，填充层70填充相邻接触垫201之间的间隙，以实现对接触垫201的支撑，进而避免接触垫201倾斜。示例性的，填充层70的材料可以包括氮化硅等绝缘材料。在一些实现方式中，填充层70的材料与保护层60的材料可以相同，以在形成填充层70后，填充层70与保护层60可以形成一体结构，进而提高对接触垫201的支撑效果。
请参照图16和图17，本实施例中，在形成填充层70之后还包括：去除部分填充层70，以暴露出接触垫201的顶端。如此设置，可以便于后续过程中，接触垫201与电容结构之间的连接。
继续参照图1-图17，本实施例还提供一种半导体结构，包括衬底10以及设置在衬底10上的接触结构，衬底10内具有间隔设置的多个晶体管结构，接触结构包括多个接触垫201，每一接触垫201与一个晶体管结构连接；形成接触垫201之后，通过干法蚀刻的方式去除接触垫201背离衬底10的顶端上的残留核心203。
本实施例中的半导体结构可以通过上述任一实施例提供的半导体结构制作方法制得。
本实施例提供的半导体结构，在衬底10上形成导电层20，去除部分导电层20以形成由多个接触垫201构成的接触结构，每一接触垫201与一个衬底10上的晶体管结构电连接；在形成接触垫201之后，通过干法蚀刻的方式去除接触垫201背离衬底10的顶端上的残留核心203；与湿法蚀刻相比，干法蚀刻具有各向异性，在向衬底10的方向蚀刻接触垫201时，不会对接触垫201侧壁以及接触垫201侧壁所在平面的其他膜层造成破坏，也就是说，接触垫201与绝缘结构105背离衬底10的表面之间的导电阻挡层106不会被破坏，保证了接触垫201与绝缘结构105之间的连接力，进而避免接触垫201断裂。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技 术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

  1. 一种半导体结构制作方法，其特征在于，包括：
    提供衬底，所述衬底内具有多个间隔设置的晶体管结构；
    在所述衬底上形成导电层，去除部分所述导电层以形成由多个接触垫构成的接触结构，每一所述接触垫与一个所述晶体管结构电连接；
    通过干法蚀刻的方式去除所述接触垫背离所述衬底的顶端上的残留核心。
  2. 根据权利要求1所述的半导体结构制作方法，其特征在于，通过干法蚀刻的方式去除所述接触垫背离所述衬底的顶端上的残留核心之前还包括：在所述接触垫的表面形成保护层；
    通过干法蚀刻的方式去除所述接触垫背离所述衬底的顶端上的残留核心包括：通过干法蚀刻的方式去除位于所述接触垫顶端的所述保护层、以及位于顶端的所述残留核心。
  3. 根据权利要求2所述的半导体结构制作方法，其特征在于，通过干法蚀刻的方式去除所述接触垫背离所述衬底的顶端上的残留核心之后还包括：
    形成填充层，所述填充层填充相邻所述接触垫之间的间隙，并且所述填充层覆盖在所述接触垫的顶端。
  4. 根据权利要求3所述的半导体结构制作方法，其特征在于，形成填充层之后还包括：
    去除部分所述填充层，以暴露出所述接触垫的顶端。
  5. 根据权利要求1所述的半导体结构制作方法，其特征在于，形成导电层之前还包括：在所述衬底上形成绝缘结构，所述绝缘结构上具有多个接触孔，每一所述接触孔正对一个晶体管结构；
    形成所述导电层包括：在所述接触孔内以及所述绝缘结构上形成所述导电层。
  6. 根据权利要求5所述的半导体结构制作方法，其特征在于，去除部分所述导电层以形成由多个接触垫构成的接触结构包括：
    在所述导电层上形成图案转移层，所述图案转移层具有多个分立的第一图案，所述第一图案在所述绝缘结构上的投影覆盖部分所述接触孔，以所述第一图案为掩膜刻蚀部分所述绝缘结构和部分所述导电层，以形成多个所述接触垫。
  7. 根据权利要求6所述的半导体结构制作方法，其特征在于，形成多个接触垫之后还包括：
    通过湿法蚀刻去除所述接触垫上的残留聚合物。
  8. 根据权利要求6所述的半导体结构制作方法，其特征在于，在所述导电层上形成图案转移层包括：
    在所述导电层上依次形成图案转移层、掩膜层，图案化所述掩膜层，形成多个分立的第二图案，以所述第二图案为掩膜刻蚀所述图案转移层，形成所述多个分立的第一图案。
  9. 根据权利要求1-8任一项所述的半导体结构制作方法，其特征在于，在所述衬底上形成绝缘结构之后还包括：
    在所述绝缘结构上、所述接触孔的侧壁以及所述接触孔的孔底形成导电阻挡层。
  10. 一种半导体结构，其特征在于，包括衬底以及设置在所述衬底上的接触结构，所述衬底内具有间隔设置的多个晶体管结构，所述接触结构包括多个接触垫，每一所述接触垫与一个所述晶体管结构连接；
    形成所述接触垫之后，通过干法蚀刻的方式去除所述接触垫背离所述衬底的顶端上的残留核心。
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