WO2022147992A1 - 半导体结构制作方法及半导体结构 - Google Patents

半导体结构制作方法及半导体结构 Download PDF

Info

Publication number
WO2022147992A1
WO2022147992A1 PCT/CN2021/105262 CN2021105262W WO2022147992A1 WO 2022147992 A1 WO2022147992 A1 WO 2022147992A1 CN 2021105262 W CN2021105262 W CN 2021105262W WO 2022147992 A1 WO2022147992 A1 WO 2022147992A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
mask
pattern
region
semiconductor structure
Prior art date
Application number
PCT/CN2021/105262
Other languages
English (en)
French (fr)
Inventor
曹新满
夏军
刘忠明
白世杰
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/509,146 priority Critical patent/US20220216067A1/en
Publication of WO2022147992A1 publication Critical patent/WO2022147992A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

Definitions

  • Embodiments of the present application relate to the technical field of semiconductor manufacturing, and in particular, to a method for fabricating a semiconductor structure and a semiconductor structure.
  • Dynamic Random Access Memory (DRAM for short) is gradually applied in various electronic devices due to its higher density and faster read and write speed.
  • Dynamic random access memory consists of multiple repeating memory cells.
  • the memory cell generally includes a capacitor structure and a transistor structure, and the transistor structure is connected with the capacitor structure to read data stored in the capacitor structure through the transistor structure, or write data into the capacitor structure.
  • the substrate includes an array region and an edge region on one side of the array region.
  • the width of the connecting lines in the edge region is small, and the connecting lines are prone to breakage in the subsequent process.
  • embodiments of the present application provide a method for fabricating a semiconductor structure and a semiconductor structure, so as to solve the problem that the width of the connecting line in the edge region is small, and the connecting line is prone to breakage in the subsequent process.
  • An embodiment of the present application provides a method for fabricating a semiconductor structure, including: providing a substrate, where the substrate includes a first region and a second region adjacent to the first region; and sequentially forming conductive lines on the substrate layer, a protective layer and a mask layer, the mask layer includes a first pattern facing the first region and a second pattern facing the second region; using the mask layer as a mask for etching
  • the protective layer is used to form a restriction pattern in the second area on the protective layer; the conductive layer is etched using the mask layer as a mask to form a contact pad in the first area, and a contact pad in the first area is formed.
  • the connection lines in the second area when the conductive layer is etched, the restriction pattern is used to limit the etching range.
  • the specific steps of forming the contact pads and the connection lines include:
  • the conductive layer is etched again using the mask layer as a mask to form the contact pads and the connection lines.
  • the specific steps of forming the contact pads and the connection lines include:
  • the protective layer and the conductive layer are simultaneously etched using the mask layer as a mask, so as to form the contact pad and the connection line at the same time as the restriction pattern is formed.
  • the first etching conditions for simultaneously etching the protective layer and the conductive layer are the same, but the second etching conditions for simultaneously etching the protective layer and the conductive layer are different.
  • the thickness ratio of the protective layer and the conductive layer along a direction perpendicular to the substrate is not greater than 1:5.
  • the method further includes:
  • the sidewalls of the contact pads and the connection lines are processed to remove residues on the sidewalls of the contact pads and the connection lines.
  • the projected area of the restriction pattern on the substrate is larger than the projected area of the corresponding connection line on the substrate.
  • the method further includes:
  • a filling layer is formed, and the filling layer is filled between the adjacent contact pads and between the adjacent connection lines.
  • the material of the filling layer is the same as the material of the protective layer.
  • the etching ratio of the protective layer is smaller than the etching ratio of the mask layer and the conductive layer.
  • the method before forming the conductive layer, further includes: forming an insulating layer on the substrate, the insulating layer covering the first region and the second region; forming a plurality of contact holes on the insulating layer corresponding to the region;
  • Forming the conductive layer includes: forming a conductive material on the insulating layer, the conductive material is filled in the contact hole, and the conductive material further covers the first area and the second area
  • the insulating layer is on the side facing away from the substrate.
  • the method further includes:
  • a conductive barrier layer is formed on the insulating layer to cover the sidewalls and the bottom of the contact hole, and to cover the side of the insulating layer facing away from the substrate.
  • the conductive barrier layer includes a titanium layer and a titanium nitride layer arranged in a stack, and the titanium nitride layer is arranged away from the substrate.
  • forming the mask layer includes:
  • forming a mask material layer forming a pattern transfer layer on the mask material layer, the pattern transfer layer having a first etching pattern, and using the pattern transfer layer as a mask to remove part of the mask material layer to form A mask layer having the first pattern and the second pattern.
  • forming a pattern transfer layer on the mask material layer, the pattern transfer layer having a first etching pattern includes:
  • a transfer material layer and a photolithography layer are sequentially formed on the mask material layer, and the photolithography layer has a second etching pattern; and the photolithography layer is used as a mask to remove part of the transfer material layer to form a the pattern transfer layer of the first etched pattern.
  • Embodiments of the present application further provide a semiconductor structure, including a substrate and a conductive layer disposed on the substrate, the substrate including a first region and a second region adjacent to the first region;
  • a protective layer and a mask layer are sequentially formed on the conductive layer, and the mask layer includes a first pattern facing the first region and a second pattern facing the second region;
  • the mask layer as a mask to etch the protective layer to form a restriction pattern in the second region on the protective layer; and to etch the conductive layer using the mask layer as a mask to Contact pads in the first area and connection lines in the second area are formed on the conductive layer; when the conductive layer is etched, the protection pattern is used to limit the etching range.
  • the substrate includes a first region and a second region adjacent to the first region; a conductive layer, a protective layer and a mask layer are sequentially formed on the substrate, and the mask layer There is a first pattern facing the first area and a second pattern facing the second area; the mask layer is used as a mask to etch the protective layer to form a restriction pattern located in the second area; the mask layer is used as a mask
  • the conductive layer is etched to form contact pads in the first area and connection lines in the second area; since a protective layer is provided between the conductive layer and the mask layer, and a restriction pattern is formed before the connection lines are formed,
  • the limiting pattern can limit the etching amount of the conductive layer in the second region, thereby preventing the conductive layer in the second region from being etched too much, so as to prevent the formed connecting line from breaking.
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a first region after a photolithography layer is formed in a method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • Fig. 3 is the top view of Fig. 2;
  • FIG. 4 is a schematic structural diagram of a second region after forming a photolithography layer in the method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • Fig. 5 is the top view of Fig. 4;
  • FIG. 6 is a schematic structural diagram of a first region after contact pads are formed in a method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • Fig. 7 is the top view of Fig. 6;
  • FIG. 8 is a schematic structural diagram of a second region after contact pads are formed in the method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • Fig. 9 is the top view of Fig. 8.
  • FIG. 10 is a partial schematic diagram of a semiconductor structure fabrication method provided in an embodiment of the present application after connecting lines are formed in the second region;
  • FIG. 11 is a schematic diagram of residues on a sidewall of a contact pad in a method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • Fig. 12 is the top view of Fig. 11;
  • FIG. 13 is a schematic structural diagram of the first region after the sidewalls of the contact pads and the connection lines are processed in the semiconductor structure fabrication method provided by the embodiment of the present application;
  • Fig. 14 is the top view of Fig. 13;
  • 15 is a schematic diagram of residues on the sidewalls of the connecting lines in the method for fabricating a semiconductor structure provided by an embodiment of the present application
  • Fig. 16 is the top view of Fig. 15;
  • 17 is a schematic structural diagram of the second region after the sidewalls of the contact pads and the connection lines are processed in the semiconductor structure fabrication method provided by the embodiment of the present application;
  • Fig. 18 is the top view of Fig. 17;
  • FIG. 19 is a schematic structural diagram of a first region after forming a filling layer in a method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • FIG. 20 is a schematic structural diagram of a second region after forming a filling layer in the method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • Dynamic Random Access Memory includes multiple repetitive storage units.
  • the memory cell includes a capacitor structure and a transistor structure.
  • the gate of the transistor structure is connected to the word line
  • the drain of the transistor structure is connected to the bit line
  • the source of the transistor structure is connected to the capacitor structure.
  • the voltage signal on the word line can control the opening of the transistor. or off, and then read the data stored in the capacitance structure through the bit line, or write data into the capacitance structure through the bit line.
  • the transistor structure is arranged in the array area of the substrate, the substrate further includes an edge area located on one side of the array area, a contact layer is provided on the substrate, and the contact layer includes a contact pad facing the array area and an edge area facing the edge area.
  • the connection line, the contact pad is used to connect the transistor structure and the capacitor structure, and the connection line has a certain circuit pattern.
  • a conductive layer is first formed on the substrate, then a mask layer is formed on the conductive layer, and the mask layer is etched, so that the mask layer forms a first pattern facing the array area and a first pattern facing the edge area.
  • the conductive layer is etched by using the mask layer as a mask to form contact pads in the array region and connection lines in the edge region.
  • the width of the connection lines in the edge area is small.
  • the width of the second pattern of the mask layer needs to be set smaller; at this time, the conductive layer is etched using the mask layer as a mask.
  • the etching amount is difficult to control, the conductive layer corresponding to the second pattern is etched more, and the connection line is easily broken.
  • This embodiment provides a method for fabricating a semiconductor structure and a semiconductor structure.
  • a protective layer between a conductive layer and a mask layer, when the conductive layer is etched by using the mask layer as a mask, part of the protective layer will be removed first to form a restriction
  • the pattern and limit pattern can control the amount of etching of the conductive layer, thereby preventing the conductive layer from being etched too much and preventing the connection line from being broken.
  • This embodiment does not limit the semiconductor structure.
  • the following will take the semiconductor structure as a dynamic random access memory (DRAM) as an example for introduction, but this embodiment is not limited to this, and the semiconductor structure in this embodiment may also be other structures .
  • DRAM dynamic random access memory
  • the semiconductor fabrication method provided in this embodiment includes:
  • S101 Provide a substrate, where the substrate includes a first region and a second region adjacent to the first region.
  • the substrate 10 may include a plurality of shallow trench isolation structures 101 arranged at intervals, and a transistor structure is disposed between adjacent shallow trench isolation structures 101 , and the transistor structure includes an active region structure 102 .
  • the material of the shallow trench isolation structure 101 may include oxides such as silicon oxide, and the material of the active region structure 102 may include silicon or the like.
  • the substrate 10 also includes a plurality of spaced apart conductive blocks 103 , each conductive block 103 being bonded to an active area structure 102 .
  • the material of the conductive block 103 may include a conductive material such as polysilicon.
  • a bit line structure 104 may be disposed between adjacent conductive blocks 103 , and the bit line structure 104 includes a first bit line structure 1041 , a bit line barrier layer 1043 and a second bit line structure 1042 arranged in layers, wherein The second bit line structure 1042 is disposed close to the active region structure 102 and the shallow trench isolation structure 101; the bit line barrier layer 1043 can prevent the materials between the first bit line structure 1041 and the second bit line structure 1042 from interpenetrating, and the bit line The line barrier layer 1043 may also realize electrical connection between the first bit line structure 1041 and the second bit line structure 1042 .
  • the material of the first bit line structure 1041 may include tungsten
  • the material of the second bit line structure 1042 may include polysilicon
  • the material of the bit line barrier layer 1043 may include titanium nitride.
  • an insulating film layer may be provided between the conductive block 103 and the bit line structure 104, and an exemplary material of the insulating film layer may include Silicon nitride, silicon oxide, etc.
  • the first area is adjacent to the second area.
  • the first area may be an array area
  • the corresponding second area is an edge area located on one side of the array area.
  • the first region may correspond to a capacitive structure to implement data layer storage and reading.
  • the method for fabricating the semiconductor structure provided by this embodiment further includes:
  • S102 forming a conductive layer, a protective layer and a mask layer on the substrate in sequence, where the mask layer includes a first pattern facing the first region and a second pattern facing the second region.
  • the protective layer 30 is located between the conductive layer 20 and the mask layer, and the protective layer 30 is bonded to the conductive layer 20 and the mask layer.
  • the material of the conductive layer 20 may include tungsten or the like
  • the material of the protective layer 30 may include silicon nitride or the like
  • the material of the mask layer may include amorphous carbon or the like.
  • forming the mask layer includes: forming a mask material layer 40 ; forming a pattern transfer layer on the mask material layer 40 , and the pattern transfer layer has a first etching pattern to The pattern transfer layer is a mask to remove part of the mask material layer 40 to form a mask layer having a first pattern 402 and a second pattern 403 .
  • the first pattern 402 and the second pattern 403 are improved dimensional accuracy, thereby improving the performance of the semiconductor structure.
  • forming a pattern transfer layer on the mask material layer 40, the pattern transfer layer having a first etching pattern includes: sequentially forming a transfer material layer 50 and a photolithography layer on the mask material layer 40 60, the photolithography layer 60 has a second etching pattern; using the photolithography layer 60 as a mask to remove part of the transfer material layer 50 to form a pattern transfer layer with a first etching pattern.
  • the material of the pattern transfer layer may include silicon oxynitride or the like, and the material of the photolithography layer 60 may include oxides such as silicon oxide.
  • the method for fabricating a semiconductor structure provided in this embodiment further includes: after forming the first pattern 402 and the second pattern 403:
  • S103 using the mask layer as a mask to etch the protective layer to form a restriction pattern in the second region; to etch the conductive layer using the mask layer as a mask to form contact pads in the first region on the conductive layer, and Connecting lines located in the second region; when the conductive layer is etched, the limiting pattern is used to limit the etching range.
  • a portion of the protective layer 30 is removed by etching to form the restriction pattern 301 .
  • the restriction pattern 301 Before the conductive layer 20 is etched, the restriction pattern 301 has been formed. During the etching of the conductive layer 20, the restriction pattern 301 can limit the etching amount of the conductive layer 20 in the second region, thereby preventing the conductive layer 20 in the second region. The amount of etching is too large to avoid breakage of the connecting lines 202 .
  • the mask layer (the second pattern 403) corresponding to the connection line 202 is also etched at the same time, so that the mask layer corresponding to the connection line 202 is also etched at the same time.
  • the width of the layer (second pattern 403 ) is smaller; due to the provision of the protective layer 30 , the width of the limiting pattern 301 is larger than the width of the mask layer (second pattern 403 ) corresponding to the connection line 202 , thereby limiting the conductive layer corresponding to the limiting pattern 301 20 , so as to avoid excessive etching of the conductive layer 20 in the second region.
  • etching amount of the conductive layer 20 in a region further improves the dimensional accuracy of the formed contact pads 201 to improve the performance of the semiconductor structure.
  • the etching ratio of the protective layer 30 is smaller than the etching ratio of the mask layer and the conductive layer 20 . In this way, during the etching process, the protective layer 30 is etched relatively slowly, which can further limit the etching amount of the conductive layer 20 to further prevent the conductive layer 20 from being etched too much.
  • the projected area of the formed restriction pattern 301 on the substrate 10 can be made larger than the projected area of the second pattern 403 on the substrate 10 and the projected area of the connection line 202 on the substrate 10 to further restrict the conductive layer 20 .
  • the etching amount further prevents the connection line 202 from being broken.
  • the substrate 10 includes a first region and a second region adjacent to the first region; a conductive layer 20, a protective layer 30 and a mask layer are sequentially formed on the substrate 10, and the mask
  • the layer has a first pattern 402 facing the first region and a second pattern 403 facing the second region; the protective layer 30 is etched with the mask layer as a mask to form a restriction pattern 301 located in the second region;
  • the layer is a mask to etch the conductive layer 20 to form the contact pads 201 in the first area and the connection lines 202 in the second area; since the protective layer 30 is arranged between the conductive layer 20 and the mask layer, and in the Before forming the connection line 202, a restriction pattern 301 in the second area is formed.
  • the restriction pattern 301 can limit the etching amount of the conductive layer 20 in the second area, thereby avoiding the second area.
  • the conductive layer 20 in the region is etched too much, so as to prevent the formed connecting line 202 from breaking.
  • the specific steps of forming the contact pads 201 and the connection lines 202 may include: first, using the mask layer as a mask to etch the protective layer 30 to remove part of the protective layer 30, thereby forming a restriction in the second region Pattern 301 ; the conductive layer 20 is etched again using the mask layer as a mask to remove part of the conductive layer 20 , and then the contact pads 201 and the connection lines 202 are formed.
  • the limiting pattern 301 and the connecting lines 202 are formed by different etching steps, and the etching amount of each etching step can be accurately controlled to improve the dimensional accuracy of the connecting lines 202, thereby improving the performance of the semiconductor structure.
  • the specific steps of forming the contact pads 201 and the connection lines 202 may also include: using the mask layer as a mask to etch the protective layer 30 and the conductive layer 20 at the same time, so as to form the confinement pattern 301 while forming the contact Pad 201 and connecting wire 202.
  • the restriction pattern 301 and the connection line 202 are formed through the same etching step, which simplifies the fabrication difficulty of the semiconductor structure.
  • the first etching conditions for etching the protective layer 30 and the conductive layer 20 are the same, but the second etching conditions for etching the protective layer 30 and the conductive layer 20 are different.
  • the first etching condition may be an etching source in the etching process, such as etching gas; the second etching condition may be the gas flow rate or etching energy of etching in the etching process, and the like.
  • the protective layer 30 is etched with the same gas after the restriction pattern 301 is formed, and the etching is continued to etch the conductive layer 20 downward, thereby forming the contact pads 201 and the connection lines 202; etching the protective layer 30 Compared with the conductive layer 20, the corresponding gas flow rate and/or energy is different, and the dimensional accuracy of the obtained contact pads 201 and connection lines 202 can be improved, so as to improve the performance of the semiconductor structure.
  • the thickness ratio of the protective layer 30 and the conductive layer 20 along the direction perpendicular to the substrate 10 is not greater than 1:5. Making the protective layer 30 have a sufficient thickness can improve the protective effect on the conductive layer 20 in the subsequent process of etching the conductive layer 20 .
  • the thickness ratio of the protective layer 30 to the conductive layer 20 is not limited to 1:5, and may also be 1:6, 1:7, or the like.
  • the method for fabricating a semiconductor structure provided in this embodiment further includes, after forming the contact pads 201 and the connection lines 202 : processing the sidewalls of the contact pads 201 and the connection lines 202 to remove the contact pads 201 and the sidewalls of the connection lines 202 .
  • 201 and residues 203 on the sidewalls of the connecting lines 202 Exemplarily, the residues 203 located on the sidewalls of the contact pads 201 and the connection lines 202 can be removed by dry etching or wet etching. Walls are removed.
  • the conductive layer 20 as metal tungsten as an example, after the process of etching to form the contact pad 201, an ashing process is required to remove the mask layer.
  • the halogen-containing by-products after etching react with tungsten to form tungsten.
  • Halide in which the halogen-containing by-product is easier to volatilize, and soon the halogen content in the tungsten halide becomes less, which is more difficult to volatilize, and the shell-like inclusion of tungsten is formed, which is the residue 203.
  • a protective layer 30 is formed between the conductive layer 20 and the mask layer. Since the conductive layer 20 covers the top of the contact pad 201 and the connection line 202 away from the substrate 10, the mask layer is removed when the mask layer is removed. In the process, the formation of residues 203 on the top of the contact pads 201 and the connection lines 202 is avoided, the connection resistance between the contact pads 201 and the capacitor structure is reduced, and the performance of the semiconductor structure is further improved.
  • the method further includes: forming a filling layer 70 , and the filling layer 70 is filled between the adjacent contact pads 201 , and between adjacent connecting lines 202 .
  • the filling layer 70 can support the contact pads 201 and the connection lines 202 to prevent the contact pads 201 and the connection lines 202 from being bent.
  • the material of the filling layer 70 may be the same as the material of the protective layer 30, so that after the filling layer 70 is formed, the filling layer 70 and the protective layer 30 form an integral structure, so as to improve the strength of the filling layer 70 and the protective layer 30; for example :
  • the material of the filling layer 70 and the protective layer 30 can be both silicon nitride.
  • the material of the filling layer 70 and the material of the protective layer 30 may also be different, which is not limited in this embodiment, as long as the filling layer 70 is made of an insulating material.
  • the projected area of the limiting pattern 301 on the substrate 10 is larger than the projected area of the corresponding connecting lines 202; taking the orientation shown in FIG. 10 as an example,
  • the width of the restriction pattern 301 in the horizontal direction is larger than the width of the connection line 202 in the horizontal direction.
  • the method before forming the conductive layer 20 , the method further includes: forming an insulating layer 106 on the substrate 10 , and the insulating layer 106 covers the first region and the second region; A plurality of contact holes are formed on the insulating layer 106 corresponding to the first region. Each contact hole faces an active area structure 102 on one substrate 10 .
  • a conductive material is formed on the insulating layer 106 , the conductive material fills the contact holes, and the conductive material also covers the sides of the insulating layer 106 in the first and second regions away from the substrate 10 .
  • the capacitive structure is connected to the active area structure 102 through the contact pads 201 and the conductive material located in the contact holes.
  • the conductive material in the contact hole can be connected to the conductive block 103, so that the capacitive structure can be connected to the active region structure 102 through the contact pad 201, the conductive material in the contact hole, and the conductive block 103.
  • the method further includes: forming a conductive barrier layer 105 on the insulating layer 106 to cover the sidewall and bottom of the contact hole, and to cover the side of the insulating layer 106 away from the substrate 10 .
  • the conductive barrier can prevent the conductive layer 20 and the conductive barrier layer 105 from interpenetrating between the film layers on the side away from the conductive layer 20 on the basis of realizing the electrical connection between the contact pad 201 and the active region structure 102, so as to improve the performance of semiconductor structures.
  • the conductive barrier layer 105 can prevent the mutual penetration between the conductive block 103 and the conductive layer 20 .
  • the conductive barrier layer 105 includes a stacked titanium layer and a titanium nitride layer, and the titanium nitride layer is disposed away from the substrate 10 .
  • the conductive barrier layer 105 may also be made of other materials, as long as the electrical connection between the contact pad 201 and the active region structure 102 can be achieved while preventing the conductive layer 20 and the conductive barrier layer 105 from deviating The film layers on one side of the conductive layer 20 only need to penetrate each other.
  • this embodiment further provides a semiconductor structure, including a substrate 10 and a conductive layer 20 disposed on the substrate 10, the substrate 10 includes a first region and a second region adjacent to the first region area; after the conductive layer 20 is formed, a protective layer 30 and a mask layer are sequentially formed on the conductive layer 20, and the mask layer includes a first pattern 402 facing the first area and a second pattern 403 facing the second area;
  • the film layer is a mask to etch the protective layer 30 to form a restriction pattern 301 located in the second area on the protective layer 30;
  • This embodiment does not limit the semiconductor structure.
  • the following will take the semiconductor structure as a dynamic random access memory (DRAM) as an example for introduction, but this embodiment is not limited to this, and the semiconductor structure in this embodiment may also be other structures .
  • DRAM dynamic random access memory
  • the substrate 10 includes a first region and a second region adjacent to the first region; a conductive layer 20 , a protective layer 30 and a mask layer are sequentially formed on the substrate 10 , and the mask layer has The first pattern 402 facing the first region and the second pattern 403 facing the second region; the protective layer 30 is etched with the mask layer as a mask to form the restriction pattern 301 in the second region; the mask layer is used to etch the protective layer 30
  • the conductive layer 20 is etched for the mask to form the contact pads 201 in the first area and the connection lines 202 in the second area; since the protective layer 30 is provided between the conductive layer 20 and the mask layer, and in the The restriction pattern 301 is formed before the connection line 202 is formed.
  • the restriction pattern 301 can limit the etching amount of the conductive layer 20 in the second area, thereby avoiding the conductive layer 20 in the second area. It is etched too much to prevent the formed connecting lines 202 from breaking.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本申请实施例属于半导体制造技术领域，涉及一种半导体结构制作方法及半导体结构，用于解决连接线容易断裂的问题。该半导体结构制作方法包括：在衬底上依次形成导电层、保护层以及掩膜层，掩膜层具有正对第一区域的第一图形以及正对第二区域的第二图形；以掩膜层为掩膜蚀刻保护层，形成位于第二区域内的限制图形；以掩膜层为掩膜蚀刻导电层，以形成位于第一区域内的接触垫、以及位于第二区域内的连接线；在形成连接线之前形成限制图形，在对第二区域内的导电层进行蚀刻时，限制图形可以限制第二区域内导电层的蚀刻量，进而避免第二区域内的导电层被蚀刻的过多，以免形成的连接线断裂。

Description

半导体结构制作方法及半导体结构
本申请要求于2021年1月6日提交中国专利局、申请号为202110014071.7，申请名称为“半导体结构制作方法及半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体制造技术领域，尤其涉及一种半导体结构制作方法及半导体结构。
背景技术
随着存储设备技术的逐渐发展，动态随机存储器(Dynamic Random Access Memory，简称DRAM)以其较高的密度以及较快的读写速度逐渐应用在各种电子设备中。动态随机存储器由多个重复的存储单元组成。存储单元通常包括电容结构和晶体管结构，晶体管结构与电容结构相连，以通过晶体管结构读取存储在电容结构中的数据，或者将数据写入到电容结构中。
相关技术中，衬底包括阵列区以及位于阵列区一侧的边缘区，然而边缘区内有的连接线的宽度较小，在后续的工艺制程中容易出现连接线断裂的情况。
发明内容
有鉴于此，本申请实施例提供一种半导体结构制作方法及半导体结构，以解决边缘区内的连接线宽度较小，在后续的工艺制程中容易出现连接线断裂的情况。
本申请实施例提供了一种半导体结构制作方法，包括：提供衬底，所述衬底包括第一区域以及与所述第一区域相邻的第二区域；在所述衬底上依次形成导电层、保护层以及掩膜层，所述掩膜层包括正对所述第一区域的第一图形以及正对所述第二区域的第二图形；以所述掩膜层为掩膜蚀刻所述保护层，以在所述保护层上形成位于所述第二区域内的限制图形；以所述掩膜层为掩膜蚀刻所述导电层，形成位于第一区域内的接触垫，以及位于所述第二区域内的连接线；在对所述导电层进行蚀刻时，所述限制图形用于限制蚀刻范围。
在其中的一个实施例中，形成所述接触垫和所述连接线的具体步骤包括：
先以所述掩膜层为掩膜蚀刻所述保护层，形成位于所述第二区域的限制图形；
再次以所述掩膜层为掩膜蚀刻所述导电层，以形成所述接触垫和所述连接线。
在其中的一个实施例中，形成所述接触垫和所述连接线的具体步骤包括：
以所述掩膜层为掩膜同时蚀刻所述保护层和所述导电层，以在形成限制图形的同时，形成所述接触垫和所述连接线。
在其中的一个实施例中，同时刻蚀所述保护层和所述导电层的第一刻蚀条件相同，但同时刻蚀所述保护层和所述导电层的第二刻蚀条件不同。
在其中的一个实施例中，所述保护层与所述导电层沿垂直于所述衬底方向的厚度比例不大于1:5。
在其中的一个实施例中，形成所述接触垫和所述连接线后还包括：
对所述接触垫和所述连接线的侧壁进行处理，以去除位于所述接触垫和所述连接线侧壁上的残留物。
在其中的一个实施例中，形成所述接触垫和所述连接线后，所述限制图形在所述衬底上的投影面积大于对应的所述连接线在所述衬底上的投影面积。
在其中的一个实施例中，在去除所述接触垫和所述连接线侧壁上的残留物之后，还包括：
形成填充层，所述填充层填充在相邻所述接触垫之间、以及相邻所述连接线之间。
在其中的一个实施例中，所述填充层的材质与所述保护层的材质相同。
在其中的一个实施例中，所述保护层的蚀刻比小于所述掩膜层和所述导电层的蚀刻比。
在其中的一个实施例中，在形成所述导电层之前还包括：在所述衬底上形成绝缘层，所述绝缘层覆盖所述第一区域和所述第二区域；在所述第一区域对应的所述绝缘层上形成多个接触孔；
形成所述导电层包括：在所述绝缘层上形成导电材料，所述导电材料填充在所述接触孔内，所述导电材料还覆盖在所述第一区域和所述第二区域的所述绝缘层背离所述衬底的侧面上。
在其中的一个实施例中，在形成所述接触孔之后，还包括：
在所述绝缘层上形成覆盖所述接触孔侧壁和孔底、以及覆盖绝缘层背离所述衬底的侧面上的导电阻挡层。
在其中的一个实施例中，所述导电阻挡层包括层叠设置的钛层和氮化钛层，所述氮化钛层远离所述衬底设置。
在其中的一个实施例中，形成所述掩膜层包括：
形成掩膜材料层；在所述掩膜材料层上形成图案转移层，所述图案转移层具有第一蚀刻图案，以所述图案转移层为掩膜去除部分所述掩膜材料层，以形成具有所述第一图形和所述第二图形的掩膜层。
在其中的一个实施例中，在所述掩膜材料层上形成图案转移层，所述图案转移层具有第一蚀刻图案包括：
在所述掩膜材料层上依次形成转移材料层以及光刻层，所述光刻层上具有第二蚀刻图形；以所述光刻层为掩膜去除部分所述转移材料层以形成具有所述第一蚀刻图案的所述图案转移层。
本申请实施例还提供一种半导体结构，包括衬底以及设置在所述衬底上导电层，所述衬底包括第一区域以及与所述第一区域相邻的第二区域；
形成导电层之后在所述导电层上依次形成保护层以及掩膜层，所述掩膜层包括正对所述第一区域的第一图形以及正对所述第二区域的第二图形；
以所述掩膜层为掩膜蚀刻所述保护层，以在所述保护层上形成位于所述第二区域内的限制图形；以所述掩膜层为掩膜蚀刻所述导电层，以在所述导电层上形成位于第 一区域内的接触垫，以及位于所述第二区域内的连接线；在对所述导电层进行蚀刻时，所述保护图形用于限制蚀刻范围。
本实施例提供的半导体结构制作方法及半导体结构，衬底包括第一区域以及与第一区域相邻的第二区域；在衬底上依次形成导电层、保护层以及掩膜层，掩膜层具有正对第一区域的第一图形以及正对第二区域的第二图形；以掩膜层为掩膜蚀刻保护层，以形成位于第二区域内的限制图形；以掩膜层为掩膜蚀刻导电层，以形成位于第一区域内的接触垫、以及位于第二区域内的连接线；由于在导电层和掩膜层之间设置了保护层，并且在形成连接线之前形成限制图形，在对第二区域内的导电层进行蚀刻时，限制图形可以限制第二区域内导电层的蚀刻量，进而避免第二区域内的导电层被蚀刻的过多，以免形成的连接线断裂。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的半导体结构制作方法的流程图；
图2为本申请实施例提供的半导体结构制作方法中形成光刻层后第一区域的结构示意图；
图3为图2的俯视图；
图4为本申请实施例提供的半导体结构制作方法中形成光刻层后第二区域的结构示意图；
图5为图4的俯视图；
图6为本申请实施例提供的半导体结构制作方法中形成接触垫后第一区域的结构示意图；
图7为图6的俯视图；
图8为本申请实施例提供的半导体结构制作方法中形成接触垫后第二区域的结构示意图；
图9为图8的俯视图；
图10为本申请实施例提供的半导体结构制作方法中在第二区域形成连接线后的局部示意图；
图11为本申请实施例提供的半导体结构制作方法中接触垫的侧壁具有残留物的示意图；
图12为图11的俯视图；
图13为本申请实施例提供的半导体结构制作方法中对接触垫和连接线的侧壁进行处理后第一区域的结构示意图；
图14为图13的俯视图；
图15为本申请实施例提供的半导体结构制作方法中连接线的侧壁具有残留物的示意图
图16为图15的俯视图；
图17为本申请实施例提供的半导体结构制作方法中对接触垫和连接线的侧壁进行处理后第二区域的结构示意图；
图18为图17的俯视图；
图19为本申请实施例提供的半导体结构制作方法中形成填充层后第一区域的结构示意图；
图20为本申请实施例提供的半导体结构制作方法中形成填充层后第二区域的结构示意图。
附图标记说：
10：衬底；
20：导电层；
30：保护层；
40：掩膜材料层；
50：转移材料层；
60：光刻层；
70：填充层；
101：浅沟槽隔离结构；
102：有源区结构；
103：导电块；
104：位线结构；
105：导电阻挡层；
106：绝缘层；
201：接触垫；
202：连接线；
203：残留物；
301：限制图形；
402：第一图形；
403：第二图形；
1041：第一位线结构；
1042：第二位线结构；
1043：位线阻挡层。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
动态随机存储器(Dynamic Random Access Memory，简称DRAM)包括多个重复的 存储单元。存储单元包括电容结构和晶体管结构，晶体管结构的栅极与字线相连，晶体管结构的漏极与位线相连，晶体管结构的源极与电容结构相连；字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容结构中的数据，或者通过位线将数据写入到电容结构中。
相关技术中，晶体管结构设置在衬底的阵列区，衬底还包括位于阵列区一侧的边缘区，衬底上设置有接触层，接触层包括正对阵列区的接触垫以及正对边缘区的连接线，接触垫用于连接晶体管结构和电容结构，连接线具有一定的电路图形。
制作时，在衬底上先形成导电层，之后在导电层上形成掩膜层，对掩膜层进行蚀刻，以使掩膜层形成正对阵列区的第一图形以及正对边缘区的第二图形，以掩膜层为掩膜对导电层进行蚀刻，即可形成位于阵列区的接触垫以及位于边缘区的连接线。
然而，边缘区内的连接线宽度较小，为了得到较小宽度的连接线，需要将掩膜层的第二图形宽度设置的较小；此时，在以掩膜层为掩膜蚀刻导电层时，蚀刻量难以控制，使得第二图形对应的导电层被蚀刻的较多，容易导致连接线断裂。
本实施例提供一种半导体结构制作方法及半导体结构，通过在导电层和掩膜层之间设置保护层，在以掩膜层为掩膜蚀刻导电层时，会先去除部分保护层以形成限制图形，限制图形可以对蚀刻导电层的蚀刻量进行控制，进而避免导电层被蚀刻的过多，以避免连接线断裂。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图1所示，本实施例提供的半导体制作方法包括：
S101：提供衬底，衬底包括第一区域以及与第一区域相邻的第二区域。
如图2-图5所示，衬底10可以包括间隔设置的多个浅沟槽隔离结构101，相邻的浅沟槽隔离结构101之间设置有晶体管结构，晶体管结构包括有源区结构102。其中，浅沟槽隔离结构101的材质可以包括氧化硅等氧化物，有源区结构102的材质可以包括硅等。
衬底10还包括多个间隔设置的导电块103，每一导电块103与一个有源区结构102接合。示例性的，导电块103的材料可以包括多晶硅等导电材料。
进一步地，在相邻的有导电块103之间可以设置有位线结构104，位线结构104包括层叠设置的第一位线结构1041、位线阻挡层1043以及第二位线结构1042，其中第二位线结构1042靠近有源区结构102和浅沟槽隔离结构101设置；位线阻挡层1043可以阻止第一位线结构1041和第二位线结构1042之间的材质互相渗透，并且位线阻挡层1043也可以实现第一位线结构1041和第二位线结构1042之间的电连接。示例性的，第一位线结构1041的材质可以包括钨，第二位线结构1042的材质可以包括多晶硅，位线阻挡层1043的材质可以包括氮化钛。
在上述实现方式中，为了实现导电块103和位线结构104之间的绝缘连接，可以在导电块103和位线结构104之间设置有绝缘膜层，示例性的绝缘膜层的材质可以包括氮化硅、氧化硅等。
本实施例中，第一区域与第二区域相邻，示例性的，第一区域可以为阵列区，相 应的第二区域为位于阵列区一侧的边缘区。第一区域可以与电容结构对应，以实现数据层存储和读取。
继续参照图1，本实施例提供的半导体结构制作方法还包括：
S102：在衬底上依次形成导电层、保护层以及掩膜层，掩膜层包括正对第一区域的第一图形以及正对第二区域的第二图形。
请参照图2-图5，保护层30位于导电层20和掩膜层之间，且保护层30与导电层20和掩膜层接合。示例性的，导电层20的材质可以包括钨等，保护层30的材质可以包括氮化硅等，掩膜层的材质可以包括非晶碳等。
请参照图6-图9在一些可实现的方式中，形成掩膜层包括：形成掩膜材料层40；在掩膜材料层40上形成图案转移层，图案转移层具有第一蚀刻图案，以图案转移层为掩膜去除部分掩膜材料层40，以形成具有第一图形402和第二图形403的掩膜层。
如此设置，通过将图案转移层的第一蚀刻图案转移至掩膜材料层40上，以形成具有第一图形402和第二图形403的掩膜层，提高了第一图形402和第二图形403的尺寸精度，进而提高了半导体结构的性能。
继续参照图2-图5，进一步地，在掩膜材料层40上形成图案转移层，图案转移层具有第一蚀刻图案包括：在掩膜材料层40上依次形成转移材料层50以及光刻层60，所述光刻层60上具有第二蚀刻图形；以光刻层60为掩膜去除部分转移材料层50以形成具有第一蚀刻图案的图案转移层。
如此设置，通过光刻层60和图案转移层的图形转移，进而获得具有第一图形402和第二图形403的掩膜层，进一步提高了第一图形402和第二图形403的尺寸精度，进而提高了半导体结构的性能。
在上述实现方式中，图案转移层的材质可以包括氮氧化硅等，光刻层60的材质可以包括氧化硅等氧化物。
本实施例提供的半导体结构制作方法，在形成第一图形402和第二图形403之后还包括：
S103：以掩膜层为掩膜蚀刻保护层，形成位于第二区域内的限制图形；以掩膜层为掩膜蚀刻导电层，以在导电层上形成位于第一区域内的接触垫，以及位于第二区域内的连接线；在对导电层进行蚀刻时，限制图形用于限制蚀刻范围。
示例性的，通过蚀刻的方式去除部分保护层30，以形成限制图形301。
在蚀刻导电层20之前，已经形成了限制图形301，在蚀刻导电层20层的过程中，限制图形301可以限制第二区域内导电层20的蚀刻量，进而避免第二区域内导电层20的蚀刻量过大，以避免连接线202断裂。
如图10所示，示例性的，在蚀刻保护层30和导电层20的过程中，连接线202对应的掩膜层(第二图形403)也同时被蚀刻，使得连接线202对应的掩膜层(第二图形403)宽度较小；由于设置了保护层30，限制图形301的宽度大于连接线202对应的掩膜层(第二图形403)宽度，进而限制了限制图形301对应的导电层20的蚀刻量，以避免第二区域内导电层20的蚀刻量过大。
进一步地，在去除部分第二区域内的保护层30以形成限制图形301的同时，去除部分第一区域内的保护层30也形成限制图形301，位于第一区域内的限制图形301可 以限制第一区域内的导电层20的蚀刻量，进而提高了形成的接触垫201的尺寸精度，以提高半导体结构的性能。
在上述实现方式中，保护层30的蚀刻比小于掩膜层和导电层20的蚀刻比。如此设置，在蚀刻的过程中，保护层30被蚀刻的速度较慢，可以进一步限制导电层20的蚀刻量，以进一步避免导电层20被蚀刻的过大。
进一步地，可以使得形成的限制图形301在衬底10上的投影面积大于第二图形403在衬底10上的投影面积和连接线202在基底10上的投影面积，以进一步限制导电层20的蚀刻量，进一步避免连接线202断裂。
本实施例提供的半导体结构制作方法，衬底10包括第一区域以及与第一区域相邻的第二区域；在衬底10上依次形成导电层20、保护层30以及掩膜层，掩膜层具有正对第一区域的第一图形402以及正对第二区域的第二图形403；以掩膜层为掩膜蚀刻保护层30，形成位于第二区域内的限制图形301；以掩膜层为掩膜蚀刻导电层20，形成位于第一区域内的接触垫201、以及位于第二区域内的连接线202；由于在导电层20和掩膜层之间设置了保护层30，并且在形成连接线202之前，形成位于第二区域的限制图形301，在对第二区域内的导电层20进行蚀刻时，限制图形301可以限制第二区域内导电层20的蚀刻量，进而避免第二区域内的导电层20被蚀刻的过多，以免形成的连接线202断裂。
在一些可实现的方式中，形成接触垫201和连接线202的具体步骤可以包括：先以掩膜层为掩膜蚀刻保护层30，以去除部分保护层30，进而形成位于第二区域的限制图形301；再次以掩膜层为掩膜蚀刻导电层20，以去除部分导电层20，进而形成接触垫201和连接线202。
如此设置，限制图形301和连接线202是通过不同的蚀刻步骤形成，可以准确的控制各蚀刻步骤的蚀刻量，以提高连接线202的尺寸精度，进而提高半导体结构的性能。
在其他的实现方式中，形成接触垫201和连接线202的具体步骤也可以包括：以掩膜层为掩膜同时蚀刻保护层30和导电层20，以在形成限制图形301的同时，形成接触垫201和连接线202。
如此设置，限制图形301和连接线202通过同一蚀刻步骤形成，简化了半导体结构的制作难度。
在同一蚀刻步骤中蚀刻保护层30和导电层20的实现方式中，蚀刻保护层30和导电层20的第一蚀刻条件相同，但是，蚀刻保护层30和导电层20的第二蚀刻条件不同。其中，第一蚀刻条件可以为蚀刻过程中的蚀刻源，例如蚀刻气体；第二蚀刻条件可以为蚀刻过程中蚀刻的气体流量或者蚀刻能量等。
示例性的，在同一蚀刻步骤中，使用相同的气体蚀刻保护层30在形成限制图形301后，继续向下蚀刻，以蚀刻导电层20，进而形成接触垫201和连接线202；蚀刻保护层30和导电层20时，对应的气体流量和/或能量不同，可以提高得到的接触垫201和连接线202的尺寸精度，以提高半导体结构的性能。
本实施例中，保护层30与导电层20沿垂直于衬底10方向的厚度比例不大于1:5。使得保护层30具有足够的厚度，可以提高在后续蚀刻导电层20的过程中对导电层20 的保护效果。
在其他实施例中，保护层30与导电层20的厚度比不限于1:5，还可以为1:6、1:7等。
请参照图11-图18，本实施例提供的半导体结构制作方法，在形成接触垫201和连接线202之后还包括：对接触垫201和连接线202的侧壁进行处理，以去除位于接触垫201和连接线202侧壁上的残留物203。示例性的，可以通过干法蚀刻或者湿法蚀刻的方式，位于接触垫201和连接线202侧壁的残留物203，为了将残留物203除尽，可以将接触垫201和连接线202部分侧壁一并去除。
以导电层20为金属钨为例，在刻蚀形成接触垫201的过程后，需要灰化工艺去除掩膜层，高温状态下，在进行蚀刻后的含卤素的副产物和钨反应形成钨的卤化物，其中含卤素的副产物较容易挥发，很快其钨的卤化物中卤含量变少，较难挥发，形成钨的壳状包附物，即为残留物203。
本实例提供的半导体结构制作方法，在导电层20和掩膜层之间形成保护层30，由于导电层20覆盖在接触垫201和连接线202背离衬底10的顶端，在去除掩膜层的过程中，避免了在接触垫201和连接线202的顶端形成残留物203，减小了接触垫201与电容结构之间的连接电阻，以进一步提高半导体结构的性能。
请参照图19和图20，进一步地，在去除接触垫201和连接线202侧壁上的残留物203之后，还包括：形成填充层70，填充层70填充在相邻接触垫201之间、以及相邻连接线202之间。如此设置，填充层70可以实现对接触垫201和连接线202的支撑，以避免接触垫201和连接线202弯曲。
示例性的，填充层70的材质可以与保护层30的材质相同，以在形成填充层70后，填充层70与保护层30形成一体结构，以提高填充层70和保护层30的强度；例如：填充层70和保护层30的材质可以均为氮化硅。当然在其他的实现方式中，填充层70的材质与保护层30的材质也可以不同，本实施例对此不作限制，只要保证填充层70的由绝缘材质构成即可。
继续参照图10，在上述实现方式中，形成接触垫201和连接线202之后，限制图形301在衬底10上投影面积大于对应的连接线202的投影面积；以图10所示方位为例，限制图形301沿水平方向的宽度大于连接线202沿水平方向的宽度。如此设置，可以在对连接线202的侧壁进行处理以去除残留物203时，限制去除连接线202侧壁的厚度，以避免去除连接线202侧壁的残留物203时，被去除的连接线202侧壁过厚，进一步避免连接线202断裂。
继续参照图2-图5，本实施例提供的半导体结构制作方法中，在形成导电层20之前还包括：在衬底10上形成绝缘层106，绝缘层106覆盖第一区域和第二区域；在第一区域对应的绝缘层106上形成多个接触孔。每一接触孔正对一个衬底10上的有源区结构102。
在形成导电层20时，在绝缘层106上形成导电材料，导电材料填充在接触孔内，导电材料还覆盖在第一区域和第二区域的绝缘层106背离衬底10的侧面上。电容结构通过接触垫201和位于接触孔内的导电材料与有源区结构102连接。示例性的，接触孔内的导电材料可以与导电块103连接，使得电容结构可以通过接触垫201、接触孔 内的导电材料以及导电块103与有源区结构102连接。
进一步地，在形成接触孔之后，还包括：在绝缘层106上形成覆盖接触孔侧壁和孔底、以及覆盖绝缘层106背离衬底10的侧面上的导电阻挡层105。如此设置，导电阻挡可以在实现接触垫201与有源区结构102之间电连接的基础上，阻止导电层20与导电阻挡层105背离导电层20一侧的膜层之间互相渗透，以提高半导体结构的性能。在导电层20通过导电块103与有源区结构102连接的实现方式通，导电阻挡层105可以阻止导电块103与导电层20之间的互相渗透。
在上述实现方式中，导电阻挡层105包括层叠设置的钛层和氮化钛层，氮化钛层远离衬底10设置。当然，在其他的实现方式中，导电阻挡层105还可以由其他的材质构成，只要能够实现接触垫201与有源区结构102之间电连接的同时，阻止导电层20与导电阻挡层105背离导电层20一侧的膜层之间互相渗透即可。
继续参照图1-图20，本实施例还提供一种半导体结构，包括衬底10以及设置在衬底10上导电层20，衬底10包括第一区域以及与第一区域相邻的第二区域；形成导电层20之后在导电层20上依次形成保护层30以及掩膜层，掩膜层包括正对第一区域的第一图形402以及正对第二区域的第二图形403；以掩膜层为掩膜蚀刻保护层30，以在保护层30上形成位于第二区域内的限制图形301；以掩膜层为掩膜蚀刻导电层20，以在导电层20上形成位于第一区域内的接触垫201，以及位于第二区域内的连接线202；在对导电层20进行蚀刻时，限制图形301用于限制蚀刻范围。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
本实施例提供的半导体结构，衬底10包括第一区域以及为第一区域相邻的第二区域；在衬底10上依次形成导电层20、保护层30以及掩膜层，掩膜层具有正对第一区域的第一图形402以及正对第二区域的第二图形403；以掩膜层为掩膜蚀刻保护层30，以形成位于第二区域内的限制图形301；以掩膜层为掩膜蚀刻导电层20，以形成位于第一区域内的接触垫201、以及位于第二区域内的连接线202；由于在导电层20和掩膜层之间设置了保护层30，并且在形成连接线202之前形成限制图形301，在对第二区域内的导电层20进行蚀刻时，限制图形301可以限制第二区域内导电层20的蚀刻量，进而避免第二区域内的导电层20被蚀刻的过多，以免形成的连接线202断裂。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (16)

  1. 一种半导体结构制作方法，包括：
    提供衬底，所述衬底包括第一区域以及与所述第一区域相邻的第二区域；
    在所述衬底上依次形成导电层、保护层以及掩膜层，所述掩膜层包括正对所述第一区域的第一图形以及正对所述第二区域的第二图形；
    以所述掩膜层为掩膜蚀刻所述保护层，形成位于所述第二区域内的限制图形；以所述掩膜层为掩膜蚀刻所述导电层，以在所述导电层上形成位于第一区域内的接触垫，以及位于所述第二区域内的连接线；在对所述导电层进行蚀刻时，所述限制图形用于限制蚀刻范围。
  2. 根据权利要求1所述的半导体结构制作方法，其中，形成所述接触垫和所述连接线的具体步骤包括：
    先以所述掩膜层为掩膜蚀刻所述保护层，形成位于所述第二区域的限制图形；
    再次以所述掩膜层为掩膜蚀刻所述导电层，以形成所述接触垫和所述连接线。
  3. 根据权利要求1所述的半导体结构制作方法，其中，形成所述接触垫和所述连接线的具体步骤包括：
    以所述掩膜层为掩膜同时蚀刻所述保护层和所述导电层，以在形成限制图形的同时，形成所述接触垫和所述连接线。
  4. 根据权利要求3所述的半导体结构制作方法，其中，同时刻蚀所述保护层和所述导电层的第一刻蚀条件相同，但同时刻蚀所述保护层和所述导电层的第二刻蚀条件不同。
  5. 根据权利要求4所述的半导体结构制作方法，其中，所述保护层与所述导电层沿垂直于所述衬底方向的厚度比例不大于1:5。
  6. 根据权利要求1所述的半导体结构制作方法，其中，形成所述接触垫和所述连接线后还包括：
    对所述接触垫和所述连接线的侧壁进行处理，以去除位于所述接触垫和所述连接线侧壁上的残留物。
  7. 根据权利要求6所述的半导体结构制作方法，其中，形成所述接触垫和所述连接线后，所述限制图形在所述衬底上的投影面积大于对应的所述连接线在所述衬底上的投影面积。
  8. 根据权利要求3所述的半导体结构制作方法，其中，在去除所述接触垫和所述连接线侧壁上的残留物之后，还包括：
    形成填充层，所述填充层填充在相邻所述接触垫之间、以及相邻所述连接线之间。
  9. 根据权利要求8所述的半导体结构制作方法，其中，所述填充层的材质与所述保护层的材质相同。
  10. 根据权利要求1所述的半导体结构制作方法，其中，所述保护层的蚀刻比小于所述掩膜层和所述导电层的蚀刻比。
  11. 根据权利要求1所述的半导体结构制作方法，其中，
    在形成所述导电层之前还包括：在所述衬底上形成绝缘层，所述绝缘层覆盖所述第一区域和所述第二区域；在所述第一区域对应的所述绝缘层上形成多个接触孔；
    形成所述导电层包括：在所述绝缘层上形成导电材料，所述导电材料填充在所述接触孔内，所述导电材料还覆盖在所述第一区域和所述第二区域的所述绝缘层背离所述衬底的侧面上。
  12. 根据权利要求11所述的半导体结构制作方法，其中，在形成所述接触孔之后，还包括：
    在所述绝缘层上形成覆盖所述接触孔侧壁和孔底、以及覆盖绝缘层背离所述衬底的侧面上的导电阻挡层。
  13. 根据权利要求12所述的半导体结构制作方法，其中，所述导电阻挡层包括层叠设置的钛层和氮化钛层，所述氮化钛层远离所述衬底设置。
  14. 根据权利要求1所述的半导体结构制作方法，其中，形成所述掩膜层包括：
    形成掩膜材料层；在所述掩膜材料层上形成图案转移层，所述图案转移层具有第一蚀刻图案，以所述图案转移层为掩膜去除部分所述掩膜材料层，以形成具有所述第一图形和所述第二图形的掩膜层。
  15. 根据权利要求14所述的半导体结构制作方法，其中，在所述掩膜材料层上形成图案转移层，所述图案转移层具有第一蚀刻图案包括：
    在所述掩膜材料层上依次形成转移材料层以及光刻层，所述光刻层上具有第二蚀刻图形；以所述光刻层为掩膜去除部分所述转移材料层以形成具有所述第一蚀刻图案的所述图案转移层。
  16. 一种半导体结构，包括衬底以及设置在所述衬底上导电层，所述衬底包括第一区域以及与所述第一区域相邻的第二区域；
    形成导电层之后在所述导电层上依次形成保护层以及掩膜层，所述掩膜层包括正对所述第一区域的第一图形以及正对所述第二区域的第二图形；
    以所述掩膜层为掩膜蚀刻所述保护层，以在所述保护层上形成位于所述第二区域内的限制图形；以所述掩膜层为掩膜蚀刻所述导电层，以在所述导电层上形成位于第一区域内的接触垫，以及位于所述第二区域内的连接线；在对所述导电层进行蚀刻时，所述保护图形用于限制蚀刻范围。
PCT/CN2021/105262 2021-01-06 2021-07-08 半导体结构制作方法及半导体结构 WO2022147992A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/509,146 US20220216067A1 (en) 2021-01-06 2021-10-25 Method for manufacturing semiconductor structure and semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110014071.7 2021-01-06
CN202110014071.7A CN112864157B (zh) 2021-01-06 2021-01-06 半导体结构制作方法及半导体结构

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/509,146 Continuation US20220216067A1 (en) 2021-01-06 2021-10-25 Method for manufacturing semiconductor structure and semiconductor structure

Publications (1)

Publication Number Publication Date
WO2022147992A1 true WO2022147992A1 (zh) 2022-07-14

Family

ID=76004411

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/105262 WO2022147992A1 (zh) 2021-01-06 2021-07-08 半导体结构制作方法及半导体结构

Country Status (2)

Country Link
CN (1) CN112864157B (zh)
WO (1) WO2022147992A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112864157B (zh) * 2021-01-06 2022-07-08 长鑫存储技术有限公司 半导体结构制作方法及半导体结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1512272A (zh) * 2002-12-27 2004-07-14 海力士半导体有限公司 利用氟化氩曝光光源制造半导体器件的方法
CN1761036A (zh) * 2004-10-12 2006-04-19 海力士半导体有限公司 利用钨作为牺牲硬掩膜制造半导体器件的方法
US20160202603A1 (en) * 2013-09-10 2016-07-14 Hoya Corporation Mask blank, transfer mask, and method for manufacturing transfer mask
CN108717936A (zh) * 2018-06-27 2018-10-30 长鑫存储技术有限公司 双面电容器结构及其制备方法
CN209045552U (zh) * 2018-09-04 2019-06-28 长鑫存储技术有限公司 存储器
CN112864157A (zh) * 2021-01-06 2021-05-28 长鑫存储技术有限公司 半导体结构制作方法及半导体结构

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100366622B1 (ko) * 2000-06-30 2003-01-09 삼성전자 주식회사 반도체 소자의 도전성 콘택을 형성하는 방법
KR102396583B1 (ko) * 2017-11-09 2022-05-11 삼성전자주식회사 메모리 소자 및 이의 제조방법
US10475648B1 (en) * 2018-05-01 2019-11-12 United Microelectronics Corp. Method for patterning a semiconductor structure
CN111430361B (zh) * 2020-04-09 2023-07-25 长江存储科技有限责任公司 一种3d nand存储器件的制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1512272A (zh) * 2002-12-27 2004-07-14 海力士半导体有限公司 利用氟化氩曝光光源制造半导体器件的方法
CN1761036A (zh) * 2004-10-12 2006-04-19 海力士半导体有限公司 利用钨作为牺牲硬掩膜制造半导体器件的方法
US20160202603A1 (en) * 2013-09-10 2016-07-14 Hoya Corporation Mask blank, transfer mask, and method for manufacturing transfer mask
CN108717936A (zh) * 2018-06-27 2018-10-30 长鑫存储技术有限公司 双面电容器结构及其制备方法
CN209045552U (zh) * 2018-09-04 2019-06-28 长鑫存储技术有限公司 存储器
CN112864157A (zh) * 2021-01-06 2021-05-28 长鑫存储技术有限公司 半导体结构制作方法及半导体结构

Also Published As

Publication number Publication date
CN112864157A (zh) 2021-05-28
CN112864157B (zh) 2022-07-08

Similar Documents

Publication Publication Date Title
US5284787A (en) Method of making a semiconductor memory device having improved electrical characteristics
US4985368A (en) Method for making semiconductor device with no stress generated at the trench corner portion
TW201727874A (zh) 具有增大記憶胞接觸區域的半導體記憶體裝置及其製作方法
CN106356374B (zh) 快闪存储器及其制作方法
KR20090126077A (ko) 메모리 반도체 장치 및 그 제조 방법
US20150380415A1 (en) Semiconductor device and method for fabricating the same
TW497223B (en) Non-volatile memory device and fabrication method thereof
CN114864501A (zh) 三维存储器及其形成方法
WO2022147992A1 (zh) 半导体结构制作方法及半导体结构
US11869930B2 (en) Method for forming semiconductor structure and semiconductor structure
JP2000031088A (ja) 半導体装置のコンタクトホ―ルを形成する方法
JP4159624B2 (ja) 微細コンタクトホールを有する半導体メモリ装置の製造方法
KR101414076B1 (ko) 반도체 소자 및 이의 제조 방법
WO2023272881A1 (zh) 晶体管阵列及其制造方法、半导体器件及其制造方法
WO2023272880A1 (zh) 晶体管阵列及其制造方法、半导体器件及其制造方法
WO2022142266A1 (zh) 半导体结构的制造方法及半导体结构
KR20140086648A (ko) 반도체장치 및 그 제조 방법
WO2022095433A1 (zh) 半导体结构制作方法及半导体结构
JP2005079575A (ja) フラッシュメモリ素子の製造方法
US6905930B2 (en) Memory device and fabrication method thereof
US20220139923A1 (en) Method of manufacturing semiconductor structure and semiconductor structure
US20220216067A1 (en) Method for manufacturing semiconductor structure and semiconductor structure
CN110459507B (zh) 一种半导体存储装置的形成方法
KR20110077687A (ko) 반도체 메모리 장치 및 그 제조방법
US10535670B2 (en) Non-volatile memory having an erase gate formed between two floating gates with two word lines formed on other sides and a method for forming the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21917036

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21917036

Country of ref document: EP

Kind code of ref document: A1