WO2023272880A1 - 晶体管阵列及其制造方法、半导体器件及其制造方法 - Google Patents

晶体管阵列及其制造方法、半导体器件及其制造方法 Download PDF

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Publication number
WO2023272880A1
WO2023272880A1 PCT/CN2021/111315 CN2021111315W WO2023272880A1 WO 2023272880 A1 WO2023272880 A1 WO 2023272880A1 CN 2021111315 W CN2021111315 W CN 2021111315W WO 2023272880 A1 WO2023272880 A1 WO 2023272880A1
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transistor
wafer
gate
forming
array
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PCT/CN2021/111315
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English (en)
French (fr)
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华文宇
骆中伟
张帜
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芯盟科技有限公司
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Priority to KR1020247003681A priority Critical patent/KR20240028479A/ko
Publication of WO2023272880A1 publication Critical patent/WO2023272880A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Definitions

  • the present disclosure relates to the technical field of semiconductors, and relates to but not limited to a transistor array and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof.
  • Transistors are widely used as switching devices or driving devices in electronic equipment.
  • transistors can be used in Dynamic Random Access Memory (DRAM) to control the capacitance in each memory cell.
  • DRAM Dynamic Random Access Memory
  • transistors mainly include planar transistors and buried channel transistors.
  • its source (Source, S) and drain (Drain, D) are located at the gate
  • the source and drain occupy different positions under this structure, making the area of the transistor larger.
  • the source and drain of the transistor will be connected to different structures after being formed. When the source and drain are located on the horizontal sides of the gate, it will easily lead to complicated circuit wiring inside the memory and difficult manufacturing process. big.
  • embodiments of the present disclosure provide a transistor array and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof.
  • an embodiment of the present disclosure provides a method for manufacturing a transistor array, including:
  • the transistor column array includes arrays of A plurality of transistor columns, each of which is located at each lattice point of the grid-shaped trench, and a first preset thickness of the transistor columns is smaller than the initial thickness of the wafer;
  • the first The direction is the thickness direction of the wafer, and the first surface is perpendicular to the first direction;
  • a drain is formed at the second end of the transistor column; wherein, the first end and the second end are respectively opposite ends of the transistor column in the first direction; the source and the The transistor pillar between the drains constitutes the channel region of the transistor.
  • an embodiment of the present disclosure provides a transistor array, the transistor array includes: a plurality of transistors arranged in an array; the transistors include:
  • a source electrode located at the first end of the channel region
  • the drain is located at the second end of the channel region, wherein the first end and the second end are respectively opposite ends of the channel region in a first direction, and the first direction is the thickness direction of the wafer forming the channel region;
  • a gate located on either side of the channel region and corresponding to the channel region;
  • a gate oxide layer located between the channel region and the gate
  • a second isolation layer is disposed on the gate along the first direction and extends along a third direction; wherein, in the third direction, the size of the second isolation layer is larger than that of the channel region size, the third direction is parallel to the column arrangement direction of the transistor array.
  • an embodiment of the present disclosure provides a method for forming a semiconductor device, the method including:
  • each of the memory arrays includes at least: a transistor array; the transistor array includes a plurality of transistors arranged in an array; the transistor includes: a gate, a source, and a drain;
  • the transistor array is manufactured by the method provided in the first aspect above;
  • each of the bit lines is connected to the sources or drains of the plurality of transistors arranged in parallel along the second direction, and the bit lines are used for When the transistor is turned on, a read or write operation is performed on the memory array.
  • an embodiment of the present disclosure provides a semiconductor device, including:
  • Each of the memory arrays at least includes: the transistor array provided in the second aspect above; the transistors at least include: a gate, a source, and a drain; wherein, the third direction intersects the second direction, and the a plane in which the third direction and the second direction lie is perpendicular to the first direction;
  • the gates of the plurality of transistors arranged in parallel along the third direction are used to receive a word line voltage, and control the transistors to be turned on or off by the word line voltage;
  • Each of the bit lines is connected to the sources or drains of a plurality of transistors arranged side by side along the second direction, and the bit lines are used to perform operations on the memory array when the transistors are turned on. read or write operation.
  • the semiconductor device and its manufacturing method since the source and drain of the formed transistor are respectively located at the first end and the second end of the channel region in the first direction, and The first direction is the thickness direction of the wafer forming the channel region, so that the area of the transistor is greatly reduced.
  • the transistor provided by the embodiment of the present disclosure can be used to form a memory. Since the drain and source of the transistor are located on different sides of the wafer, in this way, different structures connected to the source and drain in the memory can be designed on the wafer respectively. In the two sides of the wafer, that is, they are respectively designed on the two opposite sides of the wafer, thereby simplifying the circuit layout inside the memory and reducing the process difficulty of memory manufacturing.
  • FIG. 1A is a schematic structural diagram of a planar transistor in the related art
  • FIG. 1B is a schematic structural diagram of a buried channel transistor in the related art
  • FIG. 1C is a schematic structural diagram of a DRAM memory cell formed by using planar transistors in the related art
  • FIG. 1D is a schematic structural diagram of a DRAM memory cell formed by using a buried channel transistor in the related art
  • FIG. 2A is a schematic structural diagram of a transistor array provided by an embodiment of the present disclosure.
  • FIG. 2B is a schematic structural diagram of another transistor array provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic flowchart of a method for manufacturing a transistor array provided by an embodiment of the present disclosure
  • 4A to 4Q are schematic diagrams of a process for manufacturing a columnar transistor provided by an embodiment of the present disclosure
  • FIG. 5A is a schematic structural diagram of a columnar transistor provided by an embodiment of the present disclosure.
  • FIG. 5B is a schematic structural diagram of another columnar transistor provided by an embodiment of the present disclosure.
  • 6A to 6I are schematic diagrams of the process of a method for manufacturing an L-shaped transistor provided by an embodiment of the present disclosure
  • FIG. 7A is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 7B is a schematic diagram of a partial structure of a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 7C is a schematic structural diagram of a DRAM storage unit provided by an embodiment of the present disclosure.
  • FIG. 7D is a schematic structural diagram of a PCM storage unit provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic flowchart of a method for forming a semiconductor device provided by an embodiment of the present disclosure.
  • the transistors of mainstream memory include planar transistors (Planar) and buried channel array transistors (Buried Channel Array Transistor, BCAT).
  • the drains are located on both horizontal sides of the gate.
  • FIG. 1A is a schematic structural diagram of a planar transistor in the related art
  • FIG. 1B is a schematic structural diagram of a buried channel transistor in the related art.
  • the source and drain of transistors in the related art are respectively located on the horizontal sides of the gate, so that the source and drain occupy different positions on the horizontal plane, so that whether it is a planar transistor
  • the horizontal area of the buried channel transistor is larger.
  • a DRAM is composed of a plurality of memory cells, and each memory cell mainly includes a transistor and a capacitor controlled by the transistor, that is, a DRAM includes a memory cell with one transistor and one capacitor C (1T1C).
  • FIG. 1C is a schematic structural diagram of a DRAM storage unit formed by using planar transistors in the related art
  • FIG. 1D is a schematic structural diagram of a DRAM storage unit formed by using buried channel transistors in the related art.
  • a source (or drain) 101 of a transistor in a DRAM memory cell is connected to a bit line 102
  • a drain (or source) 103 is connected to a capacitor 104 .
  • Chips formed by BCAT are usually packaged in a chip on board (COB) manner to form a memory.
  • COB chip on board
  • bit line and capacitor in the DRAM memory cell will also be located on the same side of the gate, and the subsequent process will also It is necessary to realize the connection between bit lines, transistors and capacitors, and between word lines (Word line, WL) and transistors, etc., resulting in complicated circuit wiring and difficult manufacturing process in the storage array area of DRAM memory.
  • FIG. 2A is a schematic structural diagram of a transistor array 200 provided by an embodiment of the present disclosure.
  • the transistor array 200 includes: a plurality of transistors arranged in an array, and the transistors include columnar transistors 210 .
  • FIG. 2B is a schematic structural diagram of another transistor array 200 provided by an embodiment of the present disclosure.
  • the transistor array 200 includes: a plurality of transistors arranged in an array, and the transistors include an L-shaped transistor 220 .
  • the arrangement of multiple transistors arranged in an array may include: N transistors arranged side by side along the X-axis direction, and M transistors arranged side by side along the Y-axis direction, so that N*M transistors can be formed
  • N N*M transistors
  • a transistor array 200 is formed. It can be understood that both N and M are natural numbers, and the values of N and M are not 1 at the same time.
  • FIG. 2A is a schematic structural diagram of a columnar transistor 210 provided by an embodiment of the present disclosure.
  • the columnar transistor 210 includes:
  • a source 212 located at the first end of the channel region 211;
  • the drain 213 is located at the second end of the channel region 211, wherein the first end and the second end are respectively opposite ends of the channel region 211 in the first direction, and the first direction is the crystal layer forming the channel region 211.
  • the gate 214 is located on either side of the channel region 211 and corresponds to the channel region 211;
  • the second isolation layer 216 is arranged on the gate along the first direction and extends along the third direction; wherein, in the third direction, the size of the second isolation layer is larger than the size of the channel region 211, and the third direction is parallel to the The column arrangement direction of the transistor array 200 is described above.
  • the columnar transistor 210 provided in the embodiment of the present disclosure has a vertical channel (that is, the channel region 211), and the source 212 and the drain 213 of the columnar transistor 210 are respectively located at opposite sides of the vertical channel. two ends (i.e. first end and second end). The positions of the source 212 and the drain 213 are interchangeable.
  • the first direction may be parallel to the Z-axis direction
  • the row arrangement direction of the transistor array 200 may be parallel to the X-axis direction
  • the column arrangement direction of the transistor array 200 may be parallel to the Y-axis direction.
  • each transistor in the same transistor array 200 is located on the same side of the channel region 211 parallel to the first direction.
  • the gate oxide layer 215 is used to electrically isolate the channel region 211 and the gate 214 .
  • the third direction is parallel to the column arrangement direction of the transistor array 200.
  • the column arrangement direction of the transistor array can be parallel to the Y axis.
  • the gate oxide layers of multiple transistors located in the same column are integrated.
  • the gate has an integral structure, so that, in the third direction, the size of the gate oxide layer is larger than the size of the channel region 211 , and the size of the gate is larger than the size of the channel region 211 .
  • the source 212 and the drain are respectively located at opposite ends in the thickness direction of the wafer forming the channel region 211 , that is, the source 212 and the drain of the columnar transistor 210 provided in the embodiment of the present disclosure are located at On opposite sides of the wafer, this greatly reduces the area of the transistors.
  • FIG. 3 is a schematic flowchart of a method for manufacturing a transistor array provided by an embodiment of the present disclosure. As shown in FIG. 3, the method for manufacturing a transistor array provided by an embodiment of the present disclosure includes the following steps:
  • Step S301 providing a wafer
  • Step S302 Partially etch the wafer from the first side of the wafer along the first direction to form grid-like etched trenches and transistor column arrays; wherein the transistor column array includes a plurality of transistors arranged in an array Each transistor column corresponds to each grid point of the grid-shaped trench.
  • the first preset thickness of the transistor column is smaller than the initial thickness of the wafer; the first direction is the thickness direction of the wafer, and the first surface is perpendicular to first direction;
  • Step S303 Depositing an insulating material in the grid-like etched trench to form an insulating layer surrounding each transistor column;
  • Step S304 etching the insulating layer to expose the sidewall of each transistor column
  • Step S305 sequentially forming a gate oxide layer and a gate on the exposed sidewall of each transistor column;
  • Step S306 forming a source at the first end of the transistor column
  • Step S307 forming a drain at the second end of the transistor column
  • the first end and the second end are opposite ends of the transistor column in the first direction respectively, and the transistor column between the source and the drain constitutes a channel region of the transistor.
  • the provided wafer may include at least one transistor array formation area, the transistor array formation area is an area on the wafer for forming a transistor array, and the transistor array formation area can be used to form a plurality of transistor arrays arranged in an array. Each transistor column has an exposed sidewall.
  • the transistor array formation region can also be used to form an insulating layer that wraps other sidewalls of the transistor pillars.
  • the transistor pillar includes an upper surface, a lower surface and sidewalls.
  • the upper surface and the lower surface of the transistor pillar are perpendicular to the first direction.
  • the sidewall of the transistor column is located between the plane where the upper surface of the transistor column is located and the plane where the lower surface is located.
  • the transistor may include a columnar transistor 210.
  • FIG. 4A to FIG. 4Q please refer to further describe the manufacturing method of the columnar transistor 210 provided by the embodiment of the present disclosure in detail.
  • step S301 is performed to provide a wafer 30 .
  • the wafer may include at least one transistor array formation region described above.
  • the constituent materials of the wafer may include semiconductor materials such as silicon and germanium.
  • the first surface of the wafer is any surface of the wafer along the first direction.
  • the thickness direction of the wafer is defined as the first direction.
  • Two second and third directions intersecting each other are defined in the top or bottom surface of the wafer perpendicular to the first direction, and the top or bottom surface of the wafer perpendicular to the first direction can be determined based on the second and third directions. bottom surface.
  • the second direction and the third direction are perpendicular to each other, thus, the first direction, the second direction and the third direction are perpendicular to each other.
  • the first direction may be defined as the Z-axis direction
  • the second direction as the X-axis direction
  • the third direction as the Y-axis direction.
  • the second direction intersects with the third direction but is not perpendicular, that is, the angle between the second direction and the third direction may be any angle.
  • FIG. 4B is a perspective view of a transistor pillar array provided by an embodiment of the present disclosure.
  • FIG. 4C is a cross-sectional view along the first direction of the grid-shaped etched groove provided by the embodiment of the present disclosure, and
  • FIG. 4D is a top view of the grid-shaped etched groove provided by the embodiment of the present disclosure.
  • the wafer 30 is partially etched to form a grid-shaped etching trench 31 and includes multiple A transistor column array of transistor columns 301.
  • Each transistor column 301 is located at a grid point in the grid. The gap between any two adjacent transistor pillars can be equal.
  • each transistor pillar 301 has a first preset thickness A in the Z-axis direction, and the first preset thickness A is smaller than the initial thickness B of the wafer.
  • the first surface 30-1 of the wafer is any surface of the wafer perpendicular to the Z-axis direction.
  • the wafer also includes a second side 30-2 opposite the first side 30-1.
  • the wafer may be etched by a dry etching process, for example, a plasma etching process or a reactive ion etching process. It should be noted that in the embodiment of the present disclosure, the etching of the wafer is a partial etching performed in the thickness direction of the wafer, and the etching process will not cut through the wafer.
  • FIG. 4B only shows a partial area of the transistor column array, and omits the part of the wafer below the transistor column that is not carved through.
  • FIG. 4E is a cross-sectional view along a first direction after an insulating layer is formed in a grid-shaped etched trench according to an embodiment of the present disclosure.
  • FIG. 4F is a top view of an insulating layer formed in grid-like etched trenches according to an embodiment of the present disclosure.
  • an insulating material is deposited in the grid-shaped etched trenches 31 , and the periphery of each transistor column 301 is filled with insulating material, forming an insulating layer 32 .
  • the insulating material may be a silicon dioxide (SiO 2 ) material or other electrically insulating material.
  • the insulating material will cover the upper surface of the transistor column 301, usually after the deposition is completed, the excess insulating material is removed by polishing using a chemical mechanical polishing (CMP) process. material to expose the upper surface of the transistor pillar 301 .
  • CMP chemical mechanical polishing
  • FIG. 4G is a cross-sectional view of the structure obtained after performing step S304 along the first direction according to an embodiment of the present disclosure.
  • FIG. 4H is a top view of the structure obtained after step S304 is performed according to an embodiment of the present disclosure.
  • S304 may include:
  • the insulating layer 32 is partially etched along the first direction, and the insulating layer 32 having a predetermined size in the second direction and a second predetermined thickness in the first direction is removed. layer, forming a plurality of etching grooves 302 arranged side by side along the second direction; wherein, each etching groove 302 correspondingly exposes sidewalls of a plurality of transistor pillars 301 arranged side by side along the third direction.
  • edge position of the transistor column is in contact with the insulating layer, and the remaining insulating material after forming the etching groove 302 forms the insulating layer 321 .
  • the method may further include:
  • the transistor column is partially etched along the first direction, and the transistor column having a predetermined size in the second direction and a second predetermined thickness in the first direction is removed .
  • the above-mentioned plurality of etching grooves arranged in parallel along the second direction can be formed.
  • transistor arrays 200 may be formed on one wafer. In the embodiment of the present disclosure, for convenience of description, only a transistor array 200 composed of a limited number of transistors or a partial area thereof is shown as an example.
  • the manufacturing method of the transistor array 200 before performing step S305, the manufacturing method of the transistor array 200 further includes:
  • a first isolation layer forming insulation is deposited on the bottom of the etched groove.
  • the material of the first isolation layer includes but is not limited to any one of the following: silicon nitride, silicon oxynitride, silicon carbide or silicon dioxide.
  • the first isolation layer is used to electrically isolate the gate of the transistor from the uncut wafer material at the bottom.
  • the etching groove reveals that the sidewall of the transistor pillar 301 is a sidewall 3011, and a first isolation layer 305 is deposited and formed at the bottom of the etching groove (not shown in FIG. 4I).
  • An isolation layer 305 is in contact with the sidewall 3011 .
  • the first isolation layer 305 may be deposited by any suitable deposition process.
  • the etching groove when the etching groove is formed by removing the insulating layer having a second predetermined thickness, and the second predetermined thickness is smaller than the first predetermined thickness of the transistor column, there will be a remaining The insulating layer, the thickness of the remaining insulating layer is the difference between the first preset thickness and the second preset thickness, and this part of the remaining insulating layer can perform the function of the first insulating layer, so that there is no need to additionally form the first insulating layer.
  • step S305 may be performed after the first isolation layer is formed.
  • S305 includes:
  • the conductive layer is etched to remove part of the thickness of the conductive layer in the first direction to form a gate.
  • FIG. 4J is a cross-sectional view along a first direction for forming a gate oxide layer and a gate according to an embodiment of the present disclosure
  • FIG. 4K is a top view for forming a gate oxide layer and a gate according to an embodiment of the present disclosure.
  • the exposed sidewall 3011 of the transistor pillar 301 can be oxidized in-situ by heating or pressing to form the gate oxide layer 215 .
  • the size of the gate oxide layer 215 formed by oxidizing the sidewall of the transistor pillar is substantially the same as that of the transistor pillar 301 .
  • a gate oxide layer can also be formed by deposition, and the gate oxide layer covers the etched groove to expose the sidewall of the transistor pillar. It should be pointed out that the gate oxide layer formed by deposition not only covers the sidewall of the transistor column exposed by the etching groove, but also covers the sidewall of the insulating layer between the adjacent transistor columns exposed by the etching groove, In this way, in the direction of the Y axis, the size of the gate oxide layer formed by deposition can be larger than the size of the transistor pillar.
  • the etching after depositing the first isolation layer 305 can be performed by chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD) or atomic layer deposition (Atomic Layer Deposition, ALD).
  • CVD chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • ALD atomic layer deposition
  • a conductive material is deposited in the groove to form a conductive layer.
  • the conductive material may include polysilicon, conductive metal or conductive alloy, and the like.
  • the conductive metal may include metal tungsten or metal copper.
  • the conductive material formed above is partially etched to form a groove 308 , and the remaining conductive material is used as the gate 214 .
  • S305 includes:
  • the initial gate oxide layer and the conductive layer are etched simultaneously to remove a partial thickness of the initial gate oxide layer and the conductive layer in the first direction to form the gate oxide layer and the gate.
  • the initial gate oxide layer and the conductive material formed above are partially etched simultaneously to form grooves 309.
  • the remaining initial gate oxide layer is the gate oxide layer 215, and the remaining initial gate oxide layer is the gate oxide layer 215.
  • the conductive material is the gate 214 .
  • the above etching process may adopt dry etching technology.
  • the method for manufacturing the transistor array 200 further includes:
  • the material of the second isolation layer includes but not limited to any one of the following: silicon nitride, silicon oxynitride, silicon carbide or silicon dioxide; the material of the second isolation layer is the same as or different from that of the first isolation layer.
  • FIG. 4M is a cross-sectional view of the structure along the first direction after forming the second isolation layer 216 according to an embodiment of the present disclosure
  • FIG. 4N is a top view after forming the second isolation layer according to an embodiment of the present disclosure.
  • the wafer column 301 is located in the projection area of the second isolation layer 216 in the X-axis direction. Moreover, in the Y-axis direction, the size of the wafer column 301 is smaller than the size of the second isolation layer 216 .
  • step S306 is executed.
  • the first end of the transistor column is one end of the transistor column in the Z-axis direction.
  • the source 212 is formed by performing ion implantation on the first end of the transistor pillar.
  • the cross-sectional shape of the source electrode 212 parallel to the preset plane includes any one of the following: square, semicircular, triangle or any polygon; wherein the preset plane is perpendicular to the first direction.
  • the manufacturing method of the transistor before performing step S306, the manufacturing method of the transistor further includes:
  • the wafer is thinned from the second side of the wafer until the second end of the transistor pillar is exposed.
  • the first side of the wafer before performing the thinning process on the second side of the wafer, the first side of the wafer needs to be fixed on a support structure to prevent the thinning process on the second side 30-2 of the wafer.
  • structures for example, structures of transistors
  • FIG. 4P is a schematic structural diagram of a transistor after thinning the second surface of the wafer provided by an embodiment of the present disclosure. As shown in FIG. 4P, the second surface of the wafer is thinned until the transistor column is exposed. The second end 3012 and the insulating layer 321.
  • step S307 is executed. Specifically, as shown in FIG. 4Q , the drain 213 is formed by performing ion implantation on the second end 3012 of the transistor column.
  • the cross-sectional shapes of the source electrode 212 and the drain electrode parallel to the aforementioned predetermined plane may be the same or different.
  • the cross-sectional shape of the drain electrode parallel to the preset plane includes any one of the following: square, semicircular, triangular or any polygon.
  • FIGS. 5A and 5B are schematic diagrams of an optional structure of the columnar transistor 210 provided by the embodiment of the present disclosure.
  • the cross-sectional shapes of the source 212 and the drain of the pillar transistor 210 are both semicircular.
  • the cross-sectional shapes of the source 212 and the drain of the pillar transistor 210 are both triangular.
  • the positions of the source 212 and the drain can be interchanged, and the source 212 can be formed first or the drain can be formed first.
  • the transistor column between the source 212 and the drain constitutes the channel region 211 of the columnar transistor 210 .
  • the source 212 and the drain are respectively located at the first end and the second end of the channel region 211 in the first direction, and the first direction is for forming The wafer thickness direction of the channel region 211, in this way, greatly reduces the area of the transistor.
  • the drain and source 212 of the columnar transistor 210 are located on different sides of the wafer, the source of the memory can be The different structures connected to the 212 and the drain are respectively designed on two sides of the wafer, thereby simplifying the circuit layout inside the memory and reducing the process difficulty of memory manufacturing.
  • FIG. 2B is a schematic structural diagram of an L-shaped transistor 20 provided by an embodiment of the present disclosure.
  • the L-shaped transistor 220 includes:
  • the source 222 is located at the first end of the channel region 221;
  • the drain 223 is located at the second end of the channel region 221, wherein the first end and the second end are respectively opposite ends of the channel region 221 in the first direction, and the first direction is the crystal layer forming the channel region 221.
  • the gate 224 is located on either side of the channel region 221 and corresponds to the channel region 221;
  • a gate oxide layer 225 located between the channel region 221 and the gate 224;
  • the second isolation layer 226 is arranged on the gate 224 along the first direction, and extends along the third direction; wherein, in the third direction, the size of the second isolation layer 226 is larger than the size of the channel region 221, and the third direction is parallel in the column arrangement direction of the transistor array 200 .
  • the transistor column of the L-shaped transistor has an L-shaped surface, and in the XOZ plane, the source 222 , the channel region 221 and the drain of the L-shaped transistor form an L-shaped structure.
  • the source 222 and the drain 223 are located at opposite ends of the wafer thickness direction where the channel region 221 is formed, that is, the source 222 and the drain 223 of the L-shaped transistor provided in the embodiment of the present disclosure. Located on opposite sides of the wafer, this greatly reduces the area of the transistors.
  • step S301 is performed to provide a wafer, which may include at least one transistor array formation region described above, each transistor array formation region may be used to form a transistor array including a plurality of transistors, each transistor includes a transistor column, and each A transistor pillar has an exposed L-shaped surface.
  • step S302 and step S303 may be the same, and the morphology of the formed grid-shaped etched trenches may be the same.
  • FIG. 6A is a cross-sectional view of the structure obtained after performing step S304 along the first direction according to an embodiment of the present disclosure. As shown in FIG. 6A, S304 may include:
  • the insulating layer 32 is partially etched along the first direction, and the part having a predetermined size in the second direction and a third predetermined thickness in the first direction is removed.
  • the bottoms of the etched grooves coincide with the bottoms of the grid-like etched grooves.
  • the bottoms of the etched grooves are relatively close to the second surface 30-2 of the wafer, and the bottoms of the grid-like etched grooves are relatively far away from the second surface 30-2 of the wafer.
  • step S305 is performed to sequentially form a gate oxide layer and a gate on the sidewall of each transistor column.
  • S305 may include:
  • the conductive layer is etched to remove part of the thickness of the conductive layer in the first direction to form the groove 308 , and the remaining conductive layer forms the gate 224 .
  • a gate oxide layer may also be formed by deposition, and the gate oxide layer covers the etched groove to expose the sidewall of the transistor pillar.
  • S305 includes:
  • the initial gate oxide layer and the conductive layer are etched simultaneously to remove part of the thickness of the initial gate oxide layer and the conductive layer in the first direction to form the gate oxide layer 225 and the gate 224 respectively.
  • the initial gate oxide layer and the conductive material formed above are partially etched simultaneously to form a groove 309, and the remaining initial gate oxide layer is gate oxide layer 225, and the remaining initial gate oxide layer is gate oxide layer 225.
  • the conductive layer is the gate 224 .
  • the manufacturing method of the L-shaped transistor further includes:
  • the second isolation layer 226 is deposited and formed in the etching groove 303 , wherein the size of the second isolation layer 226 in the third direction is larger than the size of the transistor pillar in the third direction.
  • the second isolation layer 226 fills the groove 308 (as shown in FIG. 6E ) or the groove 309 .
  • step S306 is performed. Specifically, in the first direction, ion implantation may be performed on the first end of the transistor column to form the source 222 .
  • the manufacturing method of the transistor before performing step S307, the manufacturing method of the transistor further includes:
  • the wafer is thinned from the second surface 30 - 2 of the wafer to remove a fourth predetermined thickness of the wafer, exposing the second end of the transistor column.
  • the fourth preset thickness is smaller than the difference between the initial thickness of the wafer and the second preset thickness.
  • the second surface of the wafer is thinned to remove a fourth predetermined thickness of the wafer, so as to expose the second end 3012 of the transistor column from the second surface of the wafer.
  • the method further includes:
  • An insulating material is filled into the grid-shaped grooves to form an electrical insulating layer; wherein, the grid-shaped electrical insulating layer is used to electrically isolate adjacent L-shaped transistor columns.
  • step S307 is performed, which may include:
  • the ion implantation depth of the drain may be a preset preset depth, and the maximum value of the preset depth may be equal to the difference between the initial thickness of the wafer and the second preset thickness.
  • FIG. 6H is a schematic diagram of an optional structure for forming a drain provided by an embodiment of the present disclosure, where the first preset depth is smaller than the difference between the first preset thickness and the second preset thickness, Meanwhile, an L-shaped channel region 221 is formed between the source electrode 222 and the drain electrode 223 .
  • FIG. 6I is a schematic diagram of an optional structure for forming a drain provided by an embodiment of the present disclosure.
  • the drain 223 is formed by performing ion implantation at a second preset depth on the second end 3012 of the transistor column.
  • the second predetermined depth is substantially equal to the difference between the first predetermined thickness and the second predetermined thickness, and at the same time, a vertical channel region 221 is formed between the source electrode 222 and the drain electrode 223 .
  • the finally formed transistor is an L-shaped transistor, that is, the source 222 , the drain and the channel region 221 of the L-shaped transistor jointly form an L-shaped structure.
  • the channel region 221 of the L-shaped transistor may be an L-shaped channel region (as shown in FIG. 6H ), or a vertical channel region (as shown in FIG. 6I ).
  • FIG. 7A is an optional schematic diagram of a semiconductor device provided by an embodiment of the present disclosure
  • FIG. 7B is a schematic diagram of a partial structure of a semiconductor device provided by an embodiment of the present disclosure.
  • the semiconductor device 40 includes: at least one memory array and a plurality of bit lines 403 arranged side by side along the second direction.
  • Each memory array includes: a plurality of memory cells arranged in an array; the memory cells include at least one transistor provided by the embodiments of the present disclosure. It should be emphasized that the memory array includes the transistor array 200 provided by the embodiment of the present disclosure.
  • the transistors in the semiconductor device include pillar transistors 210 . In some embodiments, the transistors in the semiconductor device may include L-shaped transistors 220 .
  • the connection mode of the transistor in the semiconductor device may be the same.
  • the gates of the plurality of transistors arranged in parallel along the third direction may be a conductive line connected to each other, so that the gates of the plurality of transistors arranged in parallel along the third direction may be used as word lines for The word line voltage is received, and the transistor is controlled to be turned on or off by the word line voltage.
  • Each bit line is connected to sources or drains of a plurality of transistors arranged in parallel along the second direction. The bit line is used to read or write to the memory cell when the transistor is on.
  • the drain of the transistor when the source of the transistor is connected to the bit line 403 , the drain of the transistor is grounded; when the drain of the transistor is connected to the bit line, the source of the transistor is grounded.
  • Semiconductor devices include various types of memories. For example, NAND flash memory (Flash), Nor Flash, DRAM, Static Random Access Memory (Static Random Access Memory, SRAM) and Phase-Change Memory (Phase-Change Memory, PCM).
  • NAND flash memory Flash
  • Nor Flash DRAM
  • Static Random Access Memory Static Random Access Memory
  • Phase-Change Memory Phase-Change Memory
  • the storage unit when the semiconductor device is a DRAM, the storage unit further includes: a storage capacitor.
  • FIG. 7C it is a schematic diagram of an optional structure of a DRAM storage unit provided by an embodiment of the present disclosure. It can be seen that in a DRAM storage unit, one end of the storage capacitor 404 is connected to the drain or source of the columnar transistor 210 The other end of the storage capacitor 404 is used to receive an external electrical signal.
  • the external electrical signal received by the other end of the storage capacitor 404 may include: a ground voltage signal, a test voltage signal, or a control voltage signal.
  • the values of the test voltage signal and the control voltage signal are not zero.
  • one end of the storage capacitor 404 is connected to the drain 223 or the source 222 of the L-shaped transistor 220 , and the other end of the storage capacitor 404 is used to receive an external electrical signal.
  • the storage capacitor 404 is used to store data written into the memory cells.
  • the memory unit when the semiconductor device is a PCM, the memory unit further includes: an adjustable resistor.
  • FIG. 7D it is a schematic diagram of an optional structure of the PCM memory cell provided by the embodiment of the present disclosure. It can be seen that in the PCM memory cell, the adjustable resistor 405 is connected to the bit line 403 and the source of the columnar transistor 210. 212 , or, an adjustable resistor 405 is connected between the bit line 403 and the drain 223 of the pillar transistor 210 .
  • the adjustable resistor 405 is connected between the bit line 403 and the source 222 of the L-shaped transistor 220, or the adjustable resistor 405 is connected between the bit line 403 and the drain of the L-shaped transistor 220 .
  • the adjustable resistor 405 is used to adjust the state of the data stored in the memory cell by the bit line voltage provided through the bit line.
  • the semiconductor device when the semiconductor device includes a plurality of memory cells, the semiconductor device is NAND Flash or Nor Flash. When multiple memory cells are connected in parallel, the semiconductor device is Nor Flash; when multiple memory cells are connected in series, the semiconductor device is NAND Flash.
  • the memory unit when the semiconductor device is an FRAM, the memory unit further includes: a ferroelectric capacitor;
  • the ferroelectric capacitor includes an upper electrode, a lower electrode, and a ferroelectric material layer between the upper electrode and the lower electrode; the upper electrode of the ferroelectric capacitor is connected to the drain of the transistor, and the ferroelectric capacitor The lower electrode of the transistor is connected to the source of the transistor, and the ferroelectric capacitor is used for storing data written in the memory array.
  • the ferroelectric capacitor By controlling the voltage difference between the upper and lower electrodes of the ferroelectric capacitor, the polarity of the ferroelectric material in the ferroelectric material layer is changed, and data is stored in this way.
  • the area of the memory unit is reduced and the storage density of the memory unit is increased by designing the structure of the transistor of the semiconductor device into a novel structure with vertical channels.
  • the source and the drain of the transistor in the embodiments of the present disclosure are located at the upper and lower ends of the vertical channel region, so that, during the formation of the semiconductor device, bit lines or other structures can be respectively arranged on the vertical channels of the channel region. straight sides.
  • bit lines and capacitors of DRAM memory cells can be respectively arranged on the two sides of the same wafer, so that the circuit layout of word lines, bit lines and capacitors can be simplified, and the cost of semiconductor devices can be reduced. Manufacturing process difficulty.
  • FIG. 8 is a flow chart of a method for forming a semiconductor device provided by an embodiment of the present disclosure. The method includes the following steps:
  • Step S501 forming at least one memory array, wherein the memory array at least includes: a transistor array; the transistor array includes a plurality of transistors arranged in an array; the transistor includes: a gate, a source, and a drain; the transistor array adopts this Made by the method provided in the disclosed embodiment;
  • Step S502 forming a plurality of bit lines arranged side by side along the second direction; wherein, each bit line is connected to the source or drain of a plurality of transistors arranged side by side along the second direction, and the bit line is used for conducting When turned on, a read or write operation is performed on the memory unit; the third direction intersects with the second direction, and the plane where the third direction and the second direction are located is perpendicular to the first direction.
  • the memory array includes: a plurality of memory cells arranged in an array; the memory cells include at least one transistor provided by the embodiments of the present disclosure. It should be emphasized that the memory array includes the transistor array provided by the embodiments of the present disclosure.
  • pillar transistor 210 in a memory cell is formed by the following steps:
  • Step 1 Removing a certain thickness (corresponding to the first preset thickness in the above-mentioned embodiment) of the silicon in the first surface part of the first wafer through an etching process to form a grid-like groove with silicon pillars in the middle ( Corresponding to the grid-like etched grooves in the above-mentioned embodiments), fill the grooves with silicon dioxide (corresponding to the insulating layer in the above-mentioned embodiments) and expose the surface of the silicon pillars by chemical mechanical polishing, and finally by etching The part of silicon dioxide close to the silicon pillar is removed to expose the sidewall of the silicon pillar (corresponding to the process of forming the transistor pillar in the above embodiment).
  • Step 2 forming silicon nitride at the bottom of the trench as a spacer structure at the bottom (corresponding to the formation of the first isolation layer in the above embodiment).
  • Step 3 forming silicon oxide as an initial gate oxide layer on the sidewall of the trench by in-situ growth.
  • Step 4 Fill the trench with polysilicon, and remove the top polysilicon to a certain depth by etching, and then remove part of the silicon oxide on the top bare drain (corresponding to the formation of the groove 309 in the above embodiment).
  • Step 5 forming silicon nitride on the top of the trench as an isolation structure on the top (corresponding to the formation of the second isolation layer in the above embodiment).
  • Step 6 Form a source in the transistor region reserved in step 1 (corresponding to the first end of the transistor column in the above embodiment) by ion implantation.
  • Step 7 Form the subsequent first corresponding structure through various processes on the first side of the first wafer; then bond the first wafer to the second wafer, and finally thin the silicon on the back side of the first wafer, Until the isolation structure at the bottom and the second surface of the first wafer (corresponding to the second end of the transistor column in the above embodiment) are exposed.
  • the first corresponding structure includes: forming a bit line, forming a resistor, or forming a capacitor.
  • the implementation process of the wafer bonding process is before the silicon thinning process on the back side, and the second wafer provides support for the first wafer during the thinning process to prevent damage to the first wafer during the thinning process.
  • Step 8 On the second surface of the first wafer, form a drain at a position opposite to the source in step 6 (corresponding to the second end of the above-mentioned transistor column) by ion implantation.
  • Step 9 finally forming a subsequent second corresponding structure on the second surface of the first wafer.
  • the second corresponding structure includes: forming a bit line, forming a resistor, or forming a capacitor.
  • the channel of the columnar transistor 210 is formed in a vertical direction.
  • components such as various logic circuits and sensors can also be formed on the third wafer.
  • the third wafer can be bonded with the thinned first wafer to jointly form a memory. It can be understood that the third wafer can be bonded to the surface of the first wafer on which the bit lines are formed.
  • an L-shaped transistor in a memory cell is formed by:
  • Step 1 Removing a certain thickness (corresponding to the first preset thickness in the above-mentioned embodiment) of the silicon in the first surface part of the first wafer through an etching process to form a grid-like groove with silicon pillars in the middle ( Corresponding to the grid-like etched grooves in the above-mentioned embodiments), fill the grooves with silicon dioxide (corresponding to the insulating layer in the above-mentioned embodiments) and expose the surface of the silicon pillars by chemical mechanical polishing, and finally by etching The part of silicon dioxide close to the silicon pillar is removed to form an exposed L-shaped surface (corresponding to the process of forming the transistor pillar in the above embodiment).
  • Step 2 forming silicon oxide as an initial gate oxide layer on the sidewall and bottom of the trench by in-situ growth.
  • Step 3 Fill the trench with polysilicon (corresponding to the formation of the polysilicon layer in the above embodiment), and remove the top polysilicon to a certain depth by etching, and then remove the exposed silicon oxide on the top (corresponding to the formation of the concave layer in the above embodiment) slot 309).
  • Step 4 forming silicon nitride on the top of the trench as the top isolation structure (corresponding to the formation of the second isolation layer in the above embodiment);
  • Step 5 forming a source electrode in the transistor region reserved in step 1 (corresponding to the first end of the transistor column in the above embodiment) by ion implantation;
  • Step 6 Form the above first corresponding structure on the first side of the first wafer through various processes; then bond the first wafer to the second wafer, and finally thin the silicon on the back side of the first wafer , ensure that the trench region (corresponding to the etched trench in the above embodiment) has a certain thickness of silicon remaining, exposing the second side of the first wafer (corresponding to the second end of the exposed transistor column in the above embodiment);
  • Step 7 On the second side of the first wafer, form a drain at a position opposite to the source in step 5 (corresponding to the second end of the above-mentioned transistor column) by ion implantation;
  • Step 8 finally forming the above-mentioned second corresponding structure on the second surface of the first wafer.
  • the channel of the formed L-shaped transistor is L-shaped.
  • the horizontal cross section of the transistor may be a rectangle (square), semicircle, triangle or any polygon.
  • the positions of the source and the drain of the transistor can be interchanged, and the source and the drain can be processed on both sides of the same wafer respectively. Therefore, the source and the drain The patterns can vary.
  • the bit lines are implemented by forming conductive lines at preset bit line positions.
  • the constituent materials of the conductive lines include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.
  • the transistor structure of the semiconductor device as a novel transistor structure with a vertical channel, the area of the storage unit is reduced and the storage density of the storage unit is increased.
  • the source and drain of the transistor in the embodiments of the present disclosure are located at the upper and lower ends of the vertical channel region, so that, in the formation process of the semiconductor device, combined with wafer bonding and back silicon thinning technology, the Bitlines or other structures may be provided in two opposite sides of the wafer, respectively.
  • the bit lines and capacitors of DRAM memory cells can be respectively arranged on the two sides of the same wafer, so that the circuit arrangement of word lines, bit lines and capacitors can be simplified, and the cost of semiconductor devices can be reduced. Manufacturing process difficulty.
  • the disclosed devices and methods may be implemented in non-target ways.
  • the device embodiments described above are only illustrative.
  • the division of units is only a logical function division.
  • the various components shown or discussed are coupled with each other, or directly coupled.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

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Abstract

本公开提供一种晶体管阵列及其制造方法、半导体器件及其制造方法，晶体管阵列制造方法包括：提供晶圆; 沿第一方向，从晶圆第一面部分刻蚀晶圆，形成网格状刻蚀沟槽和晶体管柱阵列; 晶体管柱阵列包括呈阵列排布的多个晶体管柱，晶体管柱在网格状沟槽格点处，晶体管柱的第一预设厚度小于晶圆初始厚度; 第一方向为晶圆厚度方向，第一面垂直第一方向；在网格状刻蚀沟槽中沉积绝缘材料，形成包围晶体管柱的绝缘层; 刻蚀绝缘层，显露晶体管柱一侧壁; 在晶体管柱显露侧壁上依次形成栅极氧化层和栅极; 在晶体管柱的第一端形成源极; 在晶体管柱的第二端形成漏极; 第一端和第二端为晶体管柱在第一方向上相反端；源极与漏极间的晶体管柱构成晶体管的沟道区。

Description

晶体管阵列及其制造方法、半导体器件及其制造方法
相关申请的交叉引用
本申请基于申请号为202110748544.6、申请日为2021年07月02日、发明名称为“晶体管阵列及其制造方法、半导体器件及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种晶体管阵列及其制造方法、半导体器件及其制造方法。
背景技术
晶体管在电子设备中被广泛地用作开关器件或驱动装置。例如，晶体管可以用于动态随机存储器(Dynamic Random Access Memory，DRAM)中，用于控制每一存储单元中的电容。
相关技术中，晶体管主要包括平面晶体管和填埋式沟道晶体管，然而不论是平面晶体管还是填埋式沟道晶体管，其源极(Source，S)和漏极(Drain，D)均位于栅极(Gate，G)的水平两侧，这种结构下源极和漏极分别占用了不同的位置，使得晶体管的面积较大。另外，在存储器件中，晶体管的源极和漏极形成后会分别连接不同的结构，当源极和漏极位于栅极的水平两侧时，容易导致存储器内部的电路布线复杂，制造工艺难度大。
发明内容
有鉴于此，本公开实施例提供一种晶体管阵列及其制造方法、半导体器件及其制造方法。
第一方面，本公开实施例提供一种晶体管阵列的制造方法，包括：
提供一晶圆；
沿第一方向，从所述晶圆的第一面对所述晶圆进行部分刻蚀，形成网格状刻蚀沟槽和晶体管柱阵列；其中，所述晶体管柱阵列包括呈阵列排布的多个晶体管柱，每一所述晶体管柱对应位于所述网格状沟槽的每一格点处，所述晶体管柱的第一预设厚度小于所述晶圆的初始厚度；所述第一方向为所述晶圆的厚度方向，所述第一面垂直于第一方向；
在所述网格状刻蚀沟槽中沉积绝缘材料，形成包围每一所述晶体管柱的绝缘层；
刻蚀所述绝缘层，以显露每一所述晶体管柱的一侧壁；
在每一所述晶体管柱显露的侧壁上依次形成栅极氧化层和栅极；
在所述晶体管柱的第一端，形成源极；
在所述晶体管柱的第二端，形成漏极；其中，所述第一端和所述第二端分别为所述晶体管柱在第一方向上相对的两端；所述源极和所述漏极之间的晶体管柱构成所述晶体管的沟道区。
第二方面，本公开实施例提供一种晶体管阵列，所述晶体管阵列包括：呈阵列排布的多个晶体管；所述晶体管包括：
沟道区；
源极，位于所述沟道区的第一端；
漏极，位于所述沟道区的第二端，其中，所述第一端和所述第二端分别为所述沟道区在第一方向上相对的两端，所述第一方向为形成所述沟道区的晶圆的厚度方向；
栅极，位于所述沟道区的任一侧，且与所述沟道区对应；
栅极氧化层，位于所述沟道区和所述栅极之间；
第二隔离层，沿所述第一方向设置在所述栅极上，并沿第三方向延伸；其中，在所述第三方向上，所述第二隔离层的尺寸大于所述沟道区的尺寸，所述第三方向平行于所述晶体管阵列的列排布方向。
第三方面，本公开实施例提供一种半导体器件的形成方法，所述方法包括：
形成至少一个存储器阵列；其中，每一所述存储器阵列至少包括：一个晶体管阵列；所述晶体管阵列包括呈阵列排布的多个晶体管；所述晶体管包括：栅极、源极和漏极；所述晶体管阵列通过上述第一方面提供的方法制造；
形成多条沿第二方向并列排布的位线；其中，每一所述位线与沿第二方向并列排布的多个所述晶体管的源极或者漏极连接，所述位线用于在所述晶体管导通时，对所述存储器阵列执行读取或写入操作。
第四方面，本公开实施例提供一种半导体器件，包括：
至少一个存储器阵列和多条沿第二方向并列排布的位线；
每一所述存储器阵列至少包括：上述第二方面提供的晶体管阵列；所述晶体管至少包括：栅极、源极和漏极；其中，所述第三方向和所述第二方向相交，所述第三方向和所述第二方向所在的平面垂直于所述第一方向；
沿所述第三方向并列排布的多个所述晶体管的栅极，用于接收字线电压，并通过所述字线电压控制所述晶体管导通或截止；
每一所述位线与沿所述第二方向并列排布的多个所述晶体管的源极或者漏极连接，所述位线用于在所述晶体管导通时，对所述存储器阵列执行读取或写入操作。
本公开实施例提供的晶体管阵列及其制造方法、半导体器件及其制造方法，由于形成的晶体管的源极和漏极分别位于沟道区在第一方向上的第一端和第二端，而第一方向为形成沟道区的晶圆的厚度方向，如此，极大地缩小了晶体管的面积。且本公开实施例提供的晶体管可以用于形成存储器，由于晶体管的漏极和源极位于晶圆的不同面，如此，可以将存储器中源极和漏极所连接的不同结构分别设计在晶圆的两个面中，即分别设计在晶圆相对的两个面中，从而简化了存储器内部的电路布局，降低了存储器制造的工艺难度。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同 示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1A为相关技术中平面晶体管的结构示意图；
图1B为相关技术中填埋式沟道晶体管的结构示意图；
图1C为相关技术中采用平面晶体管形成的DRAM存储单元的结构示意图；
图1D为相关技术中采用填埋式沟道晶体管形成的DRAM存储单元的结构示意图；
图2A为本公开实施例提供的一种晶体管阵列的结构示意图；
图2B为本公开实施例提供的另一种晶体管阵列的结构示意图；
图3为本公开实施例提供的一个晶体管阵列的制造方法的流程示意图；
图4A至4Q为本公开实施例提供的一种柱形晶体管制造方法的工艺过程示意图；
图5A为本公开实施例提供的一种柱形晶体管的结构示意图；
图5B为本公开实施例提供的另一种柱形晶体管的结构示意图；
图6A至图6I为本公开实施例提供的一种L形晶体管制造方法的工艺过程示意图；
图7A为本公开实施例提供的一种半导体器件的结构示意图；
图7B为本公开实施例提供的一种半导体器件的局部结构示意图；
图7C为本公开实施例提供的一种DRAM存储单元的结构示意图；
图7D为本公开实施例提供的一种PCM存储单元的结构示意图；
图8为本公开实施例提供的一种半导体器件的形成方法流程示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对公开的具体技术方案做进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
在后续的描述中，使用用于表示元件的诸如“模块”或“单元”的后缀仅 为了有利于本公开的说明，其本身没有特定的意义。因此，“模块”或“单元”可以混合地使用。
相关技术中，主流存储器的晶体管包括平面晶体管(Planar)和填埋式沟道晶体管(Buried Channel Array Transistor，BCAT)，然而不论是平面晶体管还是填埋式沟道晶体管，其结构上，源极和漏极均位于栅极的水平两侧。
图1A为相关技术中平面晶体管的结构示意图，图1B为相关技术中填埋式沟道晶体管的结构示意图。如图1A和1B所示，相关技术中的晶体管的源极和漏极分别位于栅极的水平两侧，如此，在水平面上源极和漏极分别占用了不同的位置，使得不论是平面晶体管还是填埋式沟道晶体管的水平面积都较大。
另外，由于晶体管可以制备在硅衬底上，因此，晶体管可以被用在各种存储器中，例如，动态随机存取存储器。通常，DRAM是由多个存储单元构成，每一个存储单元主要包括一个晶体管与一个由晶体管所操控的电容，即DRAM包括1个晶体管1个电容C(1T1C)的存储单元。
图1C为相关技术中采用平面晶体管形成的DRAM存储单元的结构示意图，图1D为相关技术中采用填埋式沟道晶体管形成的DRAM存储单元的结构示意图。如图1C和1D所示，DRAM存储单元中的晶体管的源极(或漏极)101与位线102连接，漏极(或源极)103与电容104连接。对于采用BCAT形成的芯片，通常使用板上芯片封装(Chips on Board，COB)的方式进行封装，以形成存储器。
由于平面晶体管和填埋式沟道晶体管的源极和漏极分别位于栅极水平的两侧，因此，DRAM存储单元中的位线和电容也会位于栅极的同一侧，且后续工艺中还需要实现位线、晶体管和电容之间的连接，字线(Word line，WL)和晶体管之间连接等，从而导致DRAM存储器的存储阵列区中，电路布线较复杂，制造工艺难度较大。
图2A为本公开实施例提供的一种晶体管阵列200的结构示意图。参照图2A所示，晶体管阵列200包括：呈阵列排布的多个晶体管，晶体管包括柱形晶体管210。
图2B为本公开实施例提供的另一种晶体管阵列200的结构示意图。参照图2B所示，晶体管阵列200包括：呈阵列排布的多个晶体管，晶体管包括L形晶体管220。
示例性地，呈阵列排布的多个晶体管的排列方式可包括：沿X轴方向并列设置的N个晶体管，以及沿Y轴方向并列设置的M个晶体管，如此，可形成N*M个晶体管组成的晶体管阵列200。可以理解的是，N和M都为自然数，且N和M的取值不同时为1。
具体地，图2A为本公开实施例提供的一种柱形晶体管210的结构示意图。参照图2A所示，柱形晶体管210包括：
沟道区211；
源极212，位于沟道区211的第一端；
漏极213，位于沟道区211的第二端，其中，第一端和第二端分别为沟道区211在第一方向上相对的两端，第一方向为形成沟道区211的晶圆的厚度方向；
栅极214，位于沟道区211的任一侧，且与沟道区211对应；
栅极氧化层215，位于沟道区211和栅极之间；
第二隔离层216，沿第一方向设置在栅极上，并沿第三方向延伸；其中，在第三方向上，第二隔离层的尺寸大于沟道区211的尺寸，第三方向平行于所述晶体管阵列200的列排布方向。
可以理解的是，本公开实施例提供的柱形晶体管210具有竖直沟道(即沟道区211)，且柱形晶体管210的源极212和漏极213分别位于竖直沟道相对设置的两端(即第一端和第二端)。源极212和漏极213的位置可互换。
示例性地，第一方向可平行于Z轴方向，晶体管阵列200的行排布方向可平行于X轴方向，晶体管阵列200的列排布方向可平行于Y轴方向。
可以理解的是，同一个晶体管阵列200中每一晶体管的栅极位于沟道区211平行于第一方向的相同侧。
栅极氧化层215，用于电隔离沟道区211和栅极214。
第三方向平行于晶体管阵列200的列排布方向，晶体管阵列的列排布方向可平行于Y轴，位于同一列的多个晶体管的栅氧化层为一体结构，位于同一列的多个晶体管的栅极为一体结构，如此，在第三方向上，栅氧化层的尺寸大于沟道区211的尺寸，栅极的尺寸大于沟道区211的尺寸。
本公开实施例中，源极212和漏极分别位于形成沟道区211的晶圆厚度方向上的相对的两端，即本公开实施例提供的柱形晶体管210的源极212和漏极位于晶圆的相对的两个面中，如此，极大地缩小了晶体管的面积。
图3为本公开实施例提供的一种晶体管阵列制造方法的流程示意图。如图3所示，本公开实施例提供的晶体管阵列的制造方法包括以下步骤：
步骤S301：提供一晶圆；
步骤S302：沿第一方向，从晶圆的第一面对晶圆进行部分刻蚀，形成网格状刻蚀沟槽和晶体管柱阵列；其中，晶体管柱阵列包括呈阵列排布的多个晶体管柱，每一晶体管柱对应位于网格状沟槽的每一格点处，晶体管柱的第一预设厚度小于晶圆的初始厚度；第一方向为晶圆的厚度方向，第一面垂直于第一方向；
步骤S303：在网格状刻蚀沟槽中沉积绝缘材料，形成包围每一晶体管柱的绝缘层；
步骤S304：刻蚀绝缘层，以显露每一晶体管柱的一侧壁；
步骤S305、在每一晶体管柱显露的侧壁上依次形成栅极氧化层和栅极；
步骤S306、在晶体管柱的第一端，形成源极；
步骤S307、在晶体管柱的第二端，形成漏极；
其中，第一端和第二端分别为晶体管柱在第一方向上相对的两端，源极和漏极之间的晶体管柱构成晶体管的沟道区。
本公开实施例中，提供的晶圆可包括至少一个晶体管阵列形成区域，晶体管阵列形成区域为晶圆上用于形成晶体管阵列的区域，晶体管阵列形成区域可用于形成有多个呈阵列排布的晶体管柱，每一晶体管柱具有一裸露的侧壁。晶体管阵列形成区域还可用于形成包裹晶体管柱其它侧壁的绝缘层。
可以理解的是，晶体管柱裸露的侧壁没有被绝缘层包裹。晶体管柱包括上表面、下表面和侧壁。晶体管柱的上表面和下表面垂直于第一方向。晶体管柱的侧壁，位于该晶体管柱的上表面所在的平面和下表面所在的平面之间。
在一些实施例中，该晶体管可包括柱形晶体管210，接下来请参考图4A至图4Q，对本公开实施例提供的柱形晶体管210的制造方法进行进一步详细说明。
首先，请参考图4A，执行步骤S301，提供一晶圆30。该晶圆可包括至少一个上述晶体管阵列形成区域。晶圆的组成材料可包括：硅、锗等半导体材料。
S302中，晶圆的第一面为晶圆沿第一方向的任意一个面。
这里，定义晶圆的厚度方向为第一方向。在晶圆垂直于第一方向的顶表面或底表面中定义两彼此相交的第二方向和第三方向，基于第二方向和第三方向可以确定出晶圆垂直于第一方向的顶表面或者底表面。
在一些实施例中，第二方向和第三方向相互垂直，如此，第一方向、第二方向和第三方向两两相互垂直。这里，可以定义第一方向为Z轴方向，第二方向为X轴方向，第三方向为Y轴方向。
在一些实施例中，第二方向和第三方向相交但是不垂直，即第二方向和第三方向的夹角可以为任意角度。
图4B为本公开实施例提供的一种晶体管柱阵列的立体图。图4C为本公开实施例提供的网格状刻蚀沟槽沿第一方向的剖视图，图4D为本公开实施例提供的网格状刻蚀沟槽的俯视图。
结合图4B至4D可以看出，沿Z轴方向，以晶圆的第一面30-1为刻蚀起点，对晶圆30进行部分刻蚀，形成网格状刻蚀沟槽31和包括多个晶体管柱301的晶体管柱阵列。每一晶体管柱301位于网格中的格点处。任意两个相邻晶体管柱之间的间隙可相等。
参照图4C所示，每晶体管柱301在Z轴方向具有第一预设厚度A，第一预设厚度A小于晶圆的初始厚度B。晶圆的第一面30-1为晶圆垂直于Z轴方向的任意一个面。晶圆还包括与第一面30-1相对的第二面30-2。
这里，可以采用干法刻蚀工艺对晶圆进行刻蚀，例如，等离子体刻蚀工艺 或者反应离子刻蚀工艺。值得注意的是，本公开实施例中，对晶圆的刻蚀是在晶圆的厚度方向上进行的部分刻蚀，刻蚀过程不会将晶圆刻穿。
需要指出的是，图4B中仅示出了晶体管柱阵列的局部区域，而省略了晶体管柱下方未被刻穿的部分晶圆。
图4E为本公开实施例提供的在网格状刻蚀沟槽中形成绝缘层后的沿第一方向的剖视图。图4F为本公开实施例提供的在网格状刻蚀沟槽中形成绝缘层后的俯视图。
如图4E和4F所示，在网格状刻蚀沟槽31中沉积绝缘材料，每一晶体管柱301的周围都填充有绝缘材料，形成了绝缘层32。绝缘材料可以是二氧化硅(SiO 2)材料或其他电绝缘材料。
需要说明的是，在实际沉积绝缘材料的过程中，绝缘材料会覆盖在晶体管柱301的上表面，通常在沉积完成后，采用化学机械研磨(Chemical Mechanical Polishing，CMP)工艺，打磨去除多余的绝缘材料，以暴露晶体管柱301的上表面。可以理解的是，晶体管柱的上表面，为沿Z轴方向，晶体管柱相对靠近第一面30-1的表面。
图4G为本公开实施例提供的在执行步骤S304后所得结构沿第一方向的剖视图。图4H为本公开实施例提供的在执行步骤S304后所得结构的俯视图。如图4G和4H所示，S304可包括：
以晶体管柱的边缘位置为刻蚀起点，沿第一方向，对绝缘层32进行部分刻蚀处理，去除在第二方向具有预设尺寸，且在第一方向上具有第二预设厚度的绝缘层，形成多个沿第二方向并列排布的刻蚀凹槽302；其中，每一刻蚀凹槽302对应显露沿第三方向并列排布的多个晶体管柱301的侧壁。
可以理解的是，晶体管柱的边缘位置与绝缘层接触，形成刻蚀凹槽302之后剩余的绝缘材料形成绝缘层321。
在一些实施例中，在执行步骤S304的同时，所述方法还可包括：
以晶体管柱的边缘位置为刻蚀起点，沿第一方向，对晶体管柱进行部分刻蚀处理，去除在第二方向具有预设尺寸，且在第一方向上具有第二预设厚度的 晶体管柱。
可以理解的是，同时去除在第一方向上具有第二预设厚度的绝缘层和晶体管柱后，可形成上述多个沿第二方向并列排布的刻蚀凹槽。
需要说明的是，一个晶圆上可形成很多个晶体管阵列200，本公开实施例中，为了便于说明，只是示例性地示出了有限个数的晶体管组成的一个晶体管阵列200或其局部区域。
在一些实施例中，在执行步骤S305之前，晶体管阵列200的制造方法还包括：
在刻蚀凹槽的底部沉积形成绝缘的第一隔离层。
这里，第一隔离层的材料包括但不限于以下任意一种：氮化硅、氮氧化硅、碳化硅或者二氧化硅。第一隔离层用于将晶体管的栅极与底部未刻穿的晶圆材料电隔离。
下面，以晶圆上的一个晶体管柱为例，说明形成第一隔离层后的结构。
具体地，如图4I所示，刻蚀凹槽显露晶体管柱301的侧壁为侧壁3011，在刻蚀凹槽(图4I中未示出)的底部沉积形成了第一隔离层305，第一隔离层305与侧壁3011接触。这里，可通过任意一种合适的沉积工艺沉积形成第一隔离层305。
在一些实施例中，当通过去除具有第二预设厚度的绝缘层形成刻蚀凹槽，且第二预设厚度小于晶体管柱的第一预设厚度时，刻蚀凹槽底部会存在剩余的绝缘层，剩余的绝缘层的厚度为第一预设厚度与第二预设厚度的差值，这部分剩余的绝缘层可执行第一隔离层的作用，如此，无需额外形成第一隔离层。
在一些实施例中，可在形成第一隔离层后，然后执行步骤S305。
在一些实施例中，S305包括：
通过原位氧化的方式，在晶体管柱显露的侧壁上形成栅极氧化层215；
在形成有栅极氧化层215的刻蚀凹槽中沉积导电材料，形成导电层214；
在第一方向上，对导电层进行刻蚀处理，去除第一方向上的部分厚度导电层，形成栅极。
图4J为本公开实施例提供的形成栅极氧化层和栅极的沿第一方向的剖视图，图4K为本公开实施例提供的形成栅极氧化层和栅极的俯视图。
示例性地，可通过加热或加压的方式，将晶体管柱301暴露的侧壁3011进行原位氧化，形成栅极氧化层215。参照图4K所示，在Y轴方向上，通过氧化晶体管柱侧壁形成的栅极氧化层215的尺寸与晶体管柱301的尺寸基本相同。
在一些实施例中，还可通过沉积的方式形成栅极氧化层，该栅极氧化层覆盖刻蚀凹槽显露晶体管柱的侧壁。需要指出的是，通过沉积形成的栅极氧化层不仅覆盖该刻蚀凹槽显露的晶体管柱的侧壁，还覆盖该刻蚀凹槽显露的相邻晶体管柱之间的绝缘层的侧壁，如此，在Y轴方向上，通过沉积的方式形成的栅极氧化层的尺寸可大于晶体管柱的尺寸。
这里，可以通过化学气相沉积(Chemical Vapor Deposition，CVD)、物理气相沉积(Physical Vapour Deposition，PVD)或者原子层沉积(Atomic Layer Deposition，ALD)等工艺在沉积了第一隔离层305后的刻蚀凹槽中沉积导电材料形成导电层。
示例性地，导电材料可包括多晶硅、导电金属或者导电合金等。导电金属可包括金属钨或者金属铜等。
如图4J所示，沿Z轴方向，对上述形成的导电材料进行部分刻蚀处理，形成凹槽308，剩余的导电材料作为栅极214。
在一些实施例中，S305包括：
通过原位氧化的方式，在晶体管柱显露的侧壁上形成初始栅极氧化层；
在形成有初始栅极氧化层的刻蚀凹槽中沉积导电材料，形成导电层；
在第一方向上，对初始栅极氧化层和导电层同时进行刻蚀处理，去除第一方向上的部分厚度的初始栅极氧化层和导电层，形成栅极氧化层和栅极。
如图4L所示，沿Z轴方向，对上述形成的初始栅极氧化层和导电材料同时进行部分刻蚀处理，形成凹槽309，剩余的初始栅极氧化层为栅极氧化层215，剩余的导电材料为栅极214。
本公开实施例中，上述刻蚀处理的工艺可以采用干法刻蚀技术。
在一些实施例中，在形成栅极氧化层和栅极之后，晶体管阵列200的制造方法还包括：
在刻蚀凹槽中沉积形成第二隔离层；其中，所述第二隔离层在第三方向上的尺寸大于晶体管柱在第三方向上的尺寸。
这里，第二隔离层的材料包括但不限于以下任意一种：氮化硅、氮氧化硅、碳化硅或者二氧化硅；第二隔离层与第一隔离层的材料相同或不同。
图4M为本公开实施例提供的形成第二隔离层216后沿第一方向的结构剖视图，图4N为本公开实施例提供的形成第二隔离层后的俯视图。
如图4N所示，晶圆管柱301位于第二隔离层216在X轴方向上的投影区域内。并且，在Y轴方向上，晶圆管柱301的尺寸小于第二隔离层216的尺寸。
接下来参考图4O，执行步骤S306。这里，晶体管柱的第一端为晶体管柱在Z轴方向上的一端。如图4O所示，通过对晶体管柱的第一端进行离子注入，从而形成源极212。
在一些实施例中，源极212平行于预设平面的截面形状包括以下任意一种：方形、半圆形、三角形或任意多边形；其中，预设平面垂直于第一方向。
在一些实施例中，在执行步骤S306之前，晶体管的制造方法还包括：
从晶圆的第二面对晶圆进行减薄处理，直至暴露出晶体管柱第二端为止。
在一些实施例中，在对晶圆的第二面进行减薄处理之前，需要先将晶圆的第一面固定在一支撑结构上，防止在对晶圆的第二面30-2进行减薄时，破坏形成在晶圆第一面的结构(例如，晶体管的结构)。
图4P为本公开实施例提供的对晶圆的第二面进行减薄后的晶体管的结构示意图，如图4P所示，对晶圆的第二面进行减薄处理，直至暴露出了晶体管柱的第二端3012以及绝缘层321。
接下来，参考图4Q，执行步骤S307。具体地，如图4Q所示，通过对晶体管柱的第二端3012进行离子注入，从而形成漏极213。
在一些实施例中，源极212和漏极平行于上述预设平面的截面形状可以相同或者不同。示例性地，漏极平行于该预设平面的截面形状包括以下任意一种： 方形、半圆形、三角形或任意多边形。
具体地，图5A和5B为本公开实施例提供的柱形晶体管210一种可选的结构示意图。如5A所示，柱形晶体管210的源极212和漏极的横截面形状均为半圆形。如图5B所示，柱形晶体管210的源极212和漏极的横截面形状均为三角形。
需要指出的是，源极212和漏极的位置可以互换，并且可以先形成源极212或者先形成漏极。
请继续参见图4Q，本公开实施例中，在形成源极212和漏极后，源极212与漏极之间的晶体管柱构成柱形晶体管210的沟道区211。
通过本公开实施例提供的制造方法所形成的柱形晶体管210，由于源极212和漏极分别位于沟道区211在第一方向上的第一端和第二端，而第一方向为形成沟道区211的晶圆的厚度方向，如此，极大地缩小了晶体管的面积。
在一些实施例中，当本公开实施例提供的柱形晶体管210应用于存储器中时，由于柱形晶体管210的漏极和源极212位于晶圆的不同面，如此，可以将存储器中源极212和漏极所连接的不同结构分别设计在晶圆的两个面中，从而简化了存储器内部的电路布局，降低了存储器制造的工艺难度。
图2B是本公开实施例提供的一种L形晶体管20的结构示意图。参照图2B所示，L形晶体管220包括：
沟道区221；
源极222，位于沟道区221的第一端；
漏极223，位于沟道区221的第二端，其中，第一端和第二端分别为沟道区221在第一方向上相对的两端，第一方向为形成沟道区221的晶圆的厚度方向；
栅极224，位于沟道区221的任一侧，且与沟道区221对应；
栅极氧化层225，位于沟道区221和栅极224之间；
第二隔离层226，沿第一方向设置在栅极224上，并沿第三方向延伸；其中，在第三方向上，第二隔离层226的尺寸大于沟道区221的尺寸，第三方向 平行于晶体管阵列200的列排布方向。
需要指出的是，L形晶体管220第一端和第二端在第二方向上的尺寸不同。
从图2B中可以看出，L形晶体管的晶体管柱具有一L形面，在XOZ平面内，L形晶体管的源极222、沟道区221和漏极形成L形结构。
本公开实施例中，源极222和漏极223分别位于形成沟道区221的晶圆厚度方向上的相对的两端，即本公开实施例提供的L形晶体管的源极222和漏极223位于晶圆的相对的两个面中，如此，极大地缩小了晶体管的面积。
接下来请参考图6A至6I，对本公开实施例提供的L形晶体管220的制造方法进行详细说明。
首先，执行步骤S301，提供一晶圆，该晶圆可包括至少一个上述晶体管阵列形成区域，每一晶体管阵列形成区域可用于形成包括多个晶体管的晶体管阵列，每一晶体管包括一晶体管柱，每一晶体管柱具有一裸露的L形面。
需要指出的是，对于柱形晶体管210的制造方法和L形晶体管220的制造方法，步骤S302和步骤S303的形成方法及过程可相同，形成的网格状刻蚀沟槽的形貌可相同。
图6A为本公开实施例提供的在执行步骤S304后所得结构沿第一方向的剖视图，如图6A所示，S304可包括：
以晶体管柱的边缘位置为刻蚀起点，沿第一方向，对绝缘层32进行部分刻蚀处理，去除在第二方向上具有预设尺寸、且在第一方向上具有第三预设厚度的绝缘层，形成多个沿第二方向并列排布的刻蚀凹槽303；其中，第三预设厚度大于或等于第二预设厚度，且第三预设厚度小于晶体管柱的第一预设厚度。
需要指出的是，刻蚀凹槽的底部与网格状刻蚀凹槽的底部重合。或者，在第一方向上，刻蚀凹槽的底部相对靠近晶圆的第二面30-2，网格状刻蚀凹槽的底部相对远离晶圆的第二面30-2。
接下来请参见图6B和6C，执行步骤S305，在每一晶体管柱的侧壁上依次形成栅极氧化层和栅极。具体地，S305可包括：
通过原位氧化的方式，在显露的L形面上形成栅极氧化层225；
在具有栅极氧化层225的刻蚀凹槽303中沉积导电材料，形成导电层；
在第一方向上，对导电层进行刻蚀处理，去除第一方向上的部分厚度导电层，形成凹槽308，剩余的导电层形成栅极224。
在一些实施例中，也可通过沉积的方式形成栅极氧化层，该栅极氧化层覆盖刻蚀凹槽显露晶体管柱的侧壁。
在一些实施例中，S305包括：
通过原位氧化的方式，在晶体管柱显露的侧壁上形成初始栅极氧化层；
在形成有初始栅极氧化层的刻蚀凹槽中沉积导电材料，形成导电层；
在第一方向上，对初始栅极氧化层和导电层同时进行刻蚀处理，去除第一方向上的部分厚度的初始栅极氧化层和导电层，分别形成栅极氧化层225和栅极224。
如图6D所示，沿Z轴方向，对上述形成的初始栅极氧化层和导电材料同时进行部分刻蚀处理，形成凹槽309，剩余的初始栅极氧化层为栅极氧化层225，剩余的导电层为栅极224。
在一些实施例中，如图6E所示，在形成栅极氧化层和栅极之后，所述L形晶体管的制造方法还包括：
在刻蚀凹槽303中沉积形成第二隔离层226，其中，第二隔离层226在第三方向上的尺寸大于晶体管柱在第三方向上的尺寸。
可以理解的是，在形成栅极氧化层225和栅极224之后，刻蚀凹槽303剩余的空隙为凹槽308(如图6C所示)或凹槽309(如图6D所示)，因此，第二隔离层226填充凹槽308(如图6E所示)或凹槽309。
接下来参考图6F，执行步骤S306，具体地，在第一方向上，可通过对晶体管柱的第一端进行离子注入，形成源极222。
在一些实施例中，结合图6F和图6G所示，在执行步骤S307之前，所述晶体管的制造方法还包括：
从晶圆的第二面30-2对晶圆进行减薄处理，以去除第四预设厚度的所述晶圆，暴露出所述晶体管柱的第二端。第四预设厚度小于晶圆的初始厚度与所述 第二预设厚度之间的差值。
以晶圆的组成材料是硅为例，本公开实施例中，在对晶圆第二面的硅进行减薄时，要保证刻蚀凹槽303底部要有一定厚度的硅存留。
如图6G所示，对晶圆的第二面进行减薄处理，去除了第四预设厚度的所述晶圆，以从晶圆的第二面暴露出晶体管柱的第二端3012。
在一些实施例中，在对晶圆的第二面进行减薄处理，去除第四预设厚度的晶圆后，所述方法还包括：
从晶圆的第二面对暴露的晶体管柱的第二端进行刻蚀形成网格状的沟槽，以显露绝缘层；
向该网格状的沟槽中填充绝缘材料，以形成电绝缘层；其中，网格状的电绝缘层，用于电隔离相邻的L形晶体管柱。
接下来，参考图6H，执行步骤S307，可包括：
对晶体管柱的第二端3012进行预设深度的离子注入，形成所述漏极，其中，所述预设深度小于或等于所述初始厚度与所述第二预设厚度之间的差值。
这里，对漏极进行离子注入的深度可以是预先设置的预设深度，预设深度的最大值可以等于所述晶圆的初始厚度与所述第二预设厚度之间的差值。
图6H为本公开实施例提供的形成漏极的一种可选的结构示意图，这里，所述第一预设深度小于所述第一预设厚度与第二预设厚度之间的差值，同时，在源极222和漏极223之间形成了L形的沟道区221。
图6I为本公开实施例提供的形成漏极的一种可选的结构示意图，如图6I所示，通过对晶体管柱的第二端3012进行第二预设深度离子注入，从而形成漏极223。所述第二预设深度基本等于所述第一预设厚度与第二预设厚度之间的差值，同时，在源极222和漏极223之间形成了竖直的沟道区221。
本公开实施例中，从整体上来看，最终形成的晶体管为L形晶体管，也就是说，L形晶体管的源极222、漏极和沟道区221共同形成L形结构。其中，所述L形晶体管的沟道区221可以是L形沟道区(如图6H所示)，也可以是竖直的沟道区(如图6I所示)。
图7A为本公开实施例提供的一种半导体器件的可选的示意图，图7B为本公开实施例提供的一种半导体器件局部结构示意图。结合图7A和图7B所示，半导体器件40包括：至少一个存储器阵列和多条沿第二方向并列排布的位线403。
每一存储器阵列包括：呈阵列排布的多个存储器单元；所述存储器单元包括本公开实施例提供的至少一个晶体管。需要强调的是，存储器阵列包括本公开实施例提供的晶体管阵列200。
在一些实施例中，半导体器件中的晶体管包括柱形晶体管210。在一些实施例中，半导体器件中的晶体管可包括L形晶体管220。
可以理解的是，不论半导体器件中的晶体管是柱形晶体管210，还是L形晶体管220，该晶体管在半导体器件中的连接方式可以是相同的。
具体地，沿第三方向并列排布的多个晶体管的栅极可以是彼此电路连接的一个导电线，如此，沿第三方向并列排布的多个晶体管的栅极可作为字线，用于接收字线电压，并通过字线电压控制晶体管导通或截止。每一位线与沿第二方向并列排布的多个晶体管的源极或者漏极连接。位线用于在晶体管导通时，对存储器单元执行读取或写入操作。
在一些实施例中，当晶体管的源极连接位线403时，晶体管的漏极接地；当晶体管的漏极连接位线时，晶体管的源极接地。
本公开实施例提供的半导体器件包括各种类型的存储器。例如，NAND闪存(Flash)、Nor Flash、DRAM、静态随机存取存储器(Static Random Access Memory，SRAM)和相变存储器(Phase-Change Memory，PCM)。
在一些实施例中，当半导体器件为DRAM时，存储单元还包括：存储电容。
如图7C所示，为本公开实施例提供的DRAM存储单元的一种可选的结构示意图，可以看出，DRAM存储单元中，存储电容404的一端与柱形晶体管210的漏极或者源极连接，存储电容404的另一端用于接收外部电信号。
需要指出的是，存储电容404的另一端接收的外部电信号可包括：接地电压信号、测试电压信号或者控制电压信号等。通常，测试电压信号和控制电压 信号的取值不为零。
当晶体管包括L形晶体管时，存储电容404的一端与L形晶体管220的漏极223或者源极222连接，存储电容404的另一端用于接收外部电信号。
存储电容404用于存储写入存储器单元的数据。在一些实施例中，当半导体器件为PCM时，存储单元还包括：可调电阻。
如图7D所示，为本公开实施例提供的PCM存储单元的一种可选的结构示意图，可以看出，PCM存储单元中，可调电阻405连接于位线403和柱形晶体管210的源极212之间，或者，可调电阻405连接于位线403和柱形晶体管210的漏极223之间。
当晶体管包括L形晶体管时，可调电阻405连接于位线403和L形晶体管220的源极222之间，或者，可调电阻405连接于位线403和L形晶体管220的漏极之间。
可调电阻405用于通过位线提供的位线电压调节存储器单元中所存储的数据的状态。在一些实施例中，当半导体器件包括多个存储器单元时，半导体器件为NAND Flash或Nor Flash。当多个存储器单元之间并联时，半导体器件为Nor Flash；当多个存储器单元之间串联时，半导体器件为NAND Flash。
在一些实施例中，当半导体器件为FRAM时，存储单元还包括：铁电电容；
所述铁电电容包括上电极、下电极以及位于所述上电极及下电极之间的铁电材料层；所述铁电电容的上电极与所述晶体管的漏极连接，所述铁电电容的下电极与所述晶体管的源极连接，所述铁电电容用于存储写入所述存储器阵列的数据。通过控制铁电电容的上、下电极之间的电压差来改变铁电材料层中铁电材料的极性，并以此来存储数据。
本公开实施例中，只是示例性地列举了一些常见的半导体器件，本公开的保护范围不限于此，任何包含本公开实施例提供的柱形晶体管210和/或L形晶体管的半导体器件均属于本公开的保护范围。
本公开实施例中，通过将半导体器件的晶体管的结构设计为新型的具有竖直沟道的结构，缩小了存储单元的面积，提高存储单元的存储密度。同时，本 公开实施例中的晶体管中源极和漏极位于竖直沟道区的上下两端，如此，在半导体器件的形成过程中，位线或其他结构可以分别设置于沟道区的竖直两面。
例如，对于DRAM而言，DRAM存储单元的位线和电容可以分别设置于在同一片晶圆的两个面上，如此，可简化字线、位线和电容的电路排布，降低半导体器件的制造工艺难度。
图8为本公开实施例提供的一种半导体器件的形成方法的流程图，所述方法包括以下步骤：
步骤S501、形成至少一个存储器阵列，其中，存储器阵列至少包括：一个晶体管阵列；晶体管阵列包括呈阵列排布的多个晶体管；晶体管包括：栅极、源极和漏极；所述晶体管阵列采用本公开实施例提供的方法制作而成；
步骤S502、形成多条沿第二方向并列排布的位线；其中，每一位线与沿第二方向并列排布的多个晶体管的源极或者漏极连接，位线用于在晶体管导通时，对存储器单元执行读取或写入操作；第三方向和第二方向相交，第三方向和第二方向所在的平面垂直于第一方向。
示例性地，存储器阵列包括：呈阵列排布的多个存储器单元；所述存储器单元包括本公开实施例提供的至少一个晶体管。需要强调的是，存储器阵列包括本公开实施例提供的晶体管阵列。
在一些实施例中，存储器单元中的柱形晶体管210通过以下步骤形成：
步骤一、通过刻蚀工艺将第一晶圆的第一面部分区域的硅去除一定厚度(对应上述实施例中的第一预设厚度)，形成中间为硅柱的网格状的沟槽(对应上述实施例中的网格状刻蚀沟槽)，在沟槽中填充二氧化硅(对应上述实施例中的绝缘层)后经化学机械研磨露出硅柱的表面，最后通过刻蚀的方式将靠近硅柱的二氧化硅的部分去除，裸露出硅柱的侧壁(对应上述实施例中形成晶体管柱的过程)。
步骤二、在沟槽的底部形成氮化硅，以作为底部的隔离(Spacer)结构(对应上述实施例中的形成第一隔离层)。
步骤三、在沟槽的侧壁通过原位生长的方式，形成氧化硅作为初始栅极氧 化层。
步骤四、在沟槽内填充多晶硅，并通过刻蚀将顶部的多晶硅去除一定的深度，然后去除顶部裸漏的部分氧化硅(对应上述实施例中的形成凹槽309)。
步骤五、在沟槽的顶部形成氮化硅，以作为顶部的隔离结构(对应上述实施例中的形成第二隔离层)。
步骤六、通过离子注入在步骤一中预留的晶体管区域(对应上述实施例中晶体管柱的第一端)中形成源极。
步骤七、在第一晶圆的第一面通过各种工艺形成后续的第一相应结构；然后将第一晶圆与第二晶圆键合，最后减薄第一晶圆的背面的硅，直到暴露出底部的隔离结构和第一晶圆的第二面(对应上述实施例中晶体管柱的第二端)。
这里，第一相应结构包括：形成位线、形成电阻或者形成电容等结构。
晶圆键合工艺的实现过程在背面硅减薄工艺之前，第二晶圆在减薄过程中为第一晶圆提供支撑作用，防止第一晶圆在减薄过程中的损坏。
步骤八、在第一晶圆的第二面，通过离子注入在步骤六中与源极相对的位置(对应上述晶体管柱的第二端)形成漏极。
步骤九、最后在第一晶圆的第二面形成后续的第二相应结构。
这里，第二相应结构包括：形成位线、形成电阻或者形成电容等结构。
通过本公开实施例提供的半导体器件的形成方法，形成的柱形晶体管210的沟道为竖直方向。
在一些实施例中，还可在第三晶圆形成各种逻辑电路和传感器等元件。并且，第三晶圆可与减薄之后的第一晶圆键合后共同形成存储器。可以理解的是，第三晶圆可与第一晶圆形成有位线的表面进行键合。
在一些实施例中，存储器单元中的L形晶体管通过以下步骤形成：
步骤一、通过刻蚀工艺将第一晶圆的第一面部分区域的硅去除一定厚度(对应上述实施例中的第一预设厚度)，形成中间为硅柱的网格状的沟槽(对应上述实施例中的网格状刻蚀沟槽)，在沟槽中填充二氧化硅(对应上述实施例中的绝缘层)后经化学机械研磨露出硅柱的表面，最后通过刻蚀的方式将靠近硅柱的 二氧化硅的部分去除，形成一裸露的L形面(对应上述实施例中的形成晶体管柱的过程)。
步骤二、在沟槽的侧壁和底部通过原位生长的方式，形成氧化硅作为初始栅极氧化层。
步骤三、在沟槽内填充多晶硅(对应上述实施例中形成多晶硅层)，并通过刻蚀的方式将顶部的多晶硅去除一定的深度，然后去除顶部裸露的氧化硅(对应上述实施例中形成凹槽309)。
步骤四、在沟槽的顶部形成氮化硅，以作为顶部的隔离结构(对应上述实施例中的形成第二隔离层)；
步骤五、通过离子注入在步骤一中预留的晶体管区域(对应上述实施例中晶体管柱的第一端)中形成源极；
步骤六、在第一晶圆的第一面通过各种工艺形成上述第一相应结构；然后将第一晶圆与第二晶圆键合，最后将第一晶圆的背面的硅进行减薄，保证沟槽区域(对应上述实施例中的刻蚀沟槽)要有一定厚度的硅存留，露出第一晶圆的第二面(对应上述实施例中的露出晶体管柱的第二端)；
步骤七、在第一晶圆的第二面，通过离子注入在步骤五中与源极相对的位置(对应上述晶体管柱的第二端)形成漏极；
步骤八、最后在第一晶圆的第二面形成上述第二相应结构。
通过本公开实施例提供的半导体器件的形成方法，形成的所述L形晶体管的沟道为L形。
本公开实施例形成的半导体器件中，晶体管的水平截面可以是长方形(正方形)，半圆形，三角形以及任意多边形。
本公开实施例形成的半导体器件中，晶体管的源极位置和漏极位置可以互换，源极和漏极可以分别在同一片晶圆的两个面进行加工处理，因此，源极和漏极的图案可以不同。
本公开实施例中，通过在预设位线位置形成导电线来实现位线。导电线的组成材料包括但不限于钨(W)、钴(Co)、铜(Cu)、铝(Al)、多晶硅、掺杂 硅、硅化物或其任何组合。
本公开实施例中，通过将半导体器件的晶体管的结构设计为新型的具有竖直沟道的晶体管结构，缩小了存储单元的面积，提高存储单元的存储密度。
同时，本公开实施例中的晶体管中源极和漏极位于竖直沟道区的上下两端，如此，在半导体器件的形成过程中，结合晶圆键合和背面硅减薄技术，可以将位线或其他结构可以分别设置于晶圆的两个相对的面中。例如，对于DRAM而言，DRAM存储单元的位线和电容可以分别设置于在同一片晶圆的两个面上，如此，可简化字线、位线和电容的电路排布，降低半导体器件的制造工艺难度。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (16)

  1. 一种晶体管阵列的制造方法，所述方法包括：
    提供一晶圆；
    沿第一方向，从所述晶圆的第一面对所述晶圆进行部分刻蚀，形成网格状刻蚀沟槽和晶体管柱阵列；其中，所述晶体管柱阵列包括呈阵列排布的多个晶体管柱，每一所述晶体管柱对应位于所述网格状沟槽的每一格点处，所述晶体管柱的第一预设厚度小于所述晶圆的初始厚度；所述第一方向为所述晶圆的厚度方向，所述第一面垂直于第一方向；
    在所述网格状刻蚀沟槽中沉积绝缘材料，形成包围每一所述晶体管柱的绝缘层；
    刻蚀所述绝缘层，以显露每一所述晶体管柱的一侧壁；
    在每一所述晶体管柱显露的侧壁上依次形成栅极氧化层和栅极；
    在所述晶体管柱的第一端，形成源极；
    在所述晶体管柱的第二端，形成漏极；其中，所述第一端和所述第二端分别为所述晶体管柱在第一方向上相对的两端，所述源极与所述漏极之间的晶体管柱构成所述晶体管的沟道区。
  2. 根据权利要求1所述的方法，其中，所述刻蚀所述绝缘层，以显露每一所述晶体管柱的一侧壁，包括：
    以所述晶体管柱的边缘位置为刻蚀起点，沿所述第一方向，对所述绝缘层进行部分刻蚀处理，去除在第二方向具有预设尺寸，且在所述第一方向上具有第二预设厚度的所述绝缘层，形成多个沿所述第二方向并列排布的所述刻蚀凹槽；
    其中，每一所述刻蚀凹槽对应显露沿第三方向并列排布的多个所述晶体管柱的侧壁，所述第三方向和所述第二方向所在的平面垂直于所述第一方向，所述第三方向和所述第二方向相交；所述预设尺寸小于相邻两个所述晶体管柱在所述第二方向上的间距；所述第二预设厚度小于或等于所述第一预设厚度。
  3. 根据权利要求2所述的方法，其中，在形成所述栅极氧化层和所述栅极之前，所述方法还包括：
    在所述刻蚀凹槽的底部沉积形成第一隔离层；
    所述在每一所述晶体管柱显露的侧壁上依次形成栅极氧化层和栅极，包括：
    在形成所述第一隔离层后，在每一所述晶体管柱显露的侧壁上依次形成栅极氧化层和栅极；其中，所述栅极氧化层和所述栅极并列排布在所述第一隔离层上。
  4. 根据权利要求2所述的方法，其中，所述在每一所述晶体管柱显露的侧壁上依次形成栅极氧化层和栅极，包括：
    通过原位氧化的方式，在所述晶体管柱显露的侧壁上形成所述栅极氧化层；
    在形成有所述栅极氧化层的所述刻蚀凹槽中沉积导电材料，形成导电层；
    在所述第一方向上，对所述导电层进行刻蚀处理，去除所述第一方向上的部分厚度的所述导电层，形成所述栅极。
  5. 根据权利要求2所述的方法，其中，所述在每一所述晶体管柱显露的侧壁上依次形成栅极氧化层和栅极，包括：
    通过原位氧化的方式，在所述晶体管柱显露的侧壁上形成初始栅极氧化层；
    在形成有所述初始栅极氧化层的所述刻蚀凹槽中沉积导电材料，形成导电层；
    在所述第一方向上，对所述初始栅极氧化层和所述导电层进行刻蚀处理，去除所述第一方向上的部分厚度的所述初始栅极氧化层和所述导电层，形成所述栅极氧化层和所述栅极。
  6. 根据权利要求2至5任一项所述的方法，其中，在形成所述栅极氧化层和所述栅极之后，所述方法还包括：
    在所述刻蚀凹槽中沉积形成第二隔离层；其中，所述第二隔离层在第三方向上的尺寸大于所述晶体管柱在所述第三方向上的尺寸。
  7. 根据权利要求1所述的方法，其中，在形成所述漏极之前，所述方法还包括：
    从所述晶圆的第二面开始，对所述晶圆进行减薄处理，直至暴露出所述晶体管柱的第二端为止；其中，所述晶圆的第二面是与所述晶圆的第一面相对的一面。
  8. 根据权利要求1所述的方法，其中，所述源极与所述漏极平行于预设平面的截面形状相同或不同；其中，所述预设平面垂直于所述第一方向；
    所述源极和所述漏极平行于所述预设平面的截面形状包括以下任意一种：方形、半圆形、三角形或任意多边形。
  9. 根据权利要求1所述的方法，其中，
    所述晶体管为柱形晶体管，所述第一端和所述第二端在第二方向上的尺寸基本相同；
    或者，
    所述晶体管为L形晶体管，所述第一端和所述第二端在第二方向上的尺寸不同。
  10. 一种晶体管阵列，所述晶体管阵列包括：呈阵列排布的多个晶体管；所述晶体管包括：
    沟道区；
    源极，位于所述沟道区的第一端；
    漏极，位于所述沟道区的第二端，其中，所述第一端和所述第二端分别为所述沟道区在第一方向上相对的两端，所述第一方向为形成所述沟道区的晶圆的厚度方向；
    栅极，位于所述沟道区的任一侧，且与所述沟道区对应；
    栅极氧化层，位于所述沟道区和所述栅极之间；
    第二隔离层，沿所述第一方向设置在所述栅极上，并沿第三方向延伸；其中，在所述第三方向上，所述第二隔离层的尺寸大于所述沟道区的尺寸，所述第三方向平行于所述晶体管阵列的列排布方向。
  11. 一种半导体器件的形成方法，所述方法包括：
    形成至少一个存储器阵列；其中，每一所述存储器阵列至少包括：一个晶 体管阵列，所述晶体管阵列包括呈阵列排布的多个晶体管；所述晶体管包括：栅极、源极和漏极；所述晶体管阵列通过如权利要求1至9任一项提供的方法制造；
    形成多条沿第二方向并列排布的位线；其中，每一所述位线与沿第二方向并列排布的多个所述晶体管的源极或者漏极连接，所述位线用于在所述晶体管导通时，对所述存储器阵列执行读取或写入操作。
  12. 一种半导体器件，包括：
    至少一个存储器阵列和多条沿第二方向并列排布的位线；
    每一所述存储器阵列包括：如权利要求10所述的晶体管阵列；所述晶体管至少包括：栅极、源极和漏极；其中，所述第三方向和所述第二方向相交，所述第三方向和所述第二方向所在的平面垂直于所述第一方向；
    沿所述第三方向并列排布的多个所述晶体管的栅极，用于接收字线电压，并通过所述字线电压控制所述晶体管导通或截止；
    每一所述位线与沿所述第二方向并列排布的多个所述晶体管的源极或者漏极连接，所述位线用于在所述晶体管导通时，对所述存储器阵列执行读取或写入操作。
  13. 根据权利要求12所述的半导体器件，其中，所述存储器阵列还包括：存储电容；
    所述存储电容的一端与所述晶体管的漏极或者源极连接，所述存储电容的另一端用于接收外部电信号，所述存储电容用于存储写入所述存储器阵列的数据。
  14. 根据权利要求12所述的半导体器件，其中，所述存储器阵列还包括：可调电阻；
    所述可调电阻连接于所述位线和所述晶体管的源极之间，或者，所述可调电阻连接于所述位线和所述晶体管的漏极之间，所述可调电阻用于通过所述位线提供的位线电压调节所述存储器阵列中所存储的数据的状态。
  15. 根据权利要求12所述的半导体器件，其中，所述存储器阵列还包括： 铁电电容；
    所述铁电电容包括：上电极、下电极以及位于所述上电极及下电极之间的铁电材料层；所述铁电电容的上电极与所述晶体管的漏极连接，所述铁电电容的下电极与所述晶体管的源极连接，所述铁电电容用于存储写入所述存储器阵列的数据。
  16. 根据权利要求12所述的半导体器件，其中，当所述半导体器件包括多个所述存储器阵列时，多个所述存储器阵列之间并联或者串联。
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