WO2022222310A1 - 晶体管及其制造方法、半导体器件及其制造方法 - Google Patents

晶体管及其制造方法、半导体器件及其制造方法 Download PDF

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Publication number
WO2022222310A1
WO2022222310A1 PCT/CN2021/111345 CN2021111345W WO2022222310A1 WO 2022222310 A1 WO2022222310 A1 WO 2022222310A1 CN 2021111345 W CN2021111345 W CN 2021111345W WO 2022222310 A1 WO2022222310 A1 WO 2022222310A1
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Prior art keywords
transistor
wafer
gate
forming
drain
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PCT/CN2021/111345
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English (en)
French (fr)
Inventor
华文宇
王喜龙
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芯盟科技有限公司
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Priority claimed from CN202110421932.3A external-priority patent/CN113506736B/zh
Priority claimed from CN202110422036.9A external-priority patent/CN113506737B/zh
Application filed by 芯盟科技有限公司 filed Critical 芯盟科技有限公司
Priority to KR1020237038547A priority Critical patent/KR20240008849A/ko
Priority to US17/782,868 priority patent/US20240179922A1/en
Publication of WO2022222310A1 publication Critical patent/WO2022222310A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices

Definitions

  • the present application relates to the field of semiconductor technology, and relates to, but is not limited to, a transistor and a method for manufacturing the same, a semiconductor device and a method for manufacturing the same.
  • Transistors are widely used as switching devices or driving devices in electronic equipment.
  • transistors may be used in Dynamic Random Access Memory (DRAM) to control the capacitance in each memory cell.
  • DRAM Dynamic Random Access Memory
  • transistors mainly include planar transistors and buried-channel transistors.
  • its source (Source, S) and drain (Drain, D) are located at the gate.
  • Source, S Source
  • Drain, D Drain
  • the source and drain of this structure occupy different positions respectively, so that the area of the transistor is larger.
  • the source and drain of the transistor will be connected to different structures after being formed. When the source and drain are located on the horizontal sides of the gate, it is easy to cause complicated circuit wiring inside the memory and difficult manufacturing process. big.
  • Embodiments of the present application provide a method for manufacturing a transistor, including:
  • a wafer is provided, the wafer has a plurality of transistor formation regions, each of the transistor formation regions has a transistor column, and each of the transistor columns has an exposed gate formation surface;
  • a gate oxide layer and a gate are sequentially formed on the gate formation surface of each of the transistor columns;
  • a drain is formed, wherein the first end and the second end are opposite ends of the transistor column in a first direction, and the first direction is the The thickness direction of the wafer; the transistor column between the source electrode and the drain electrode constitutes the channel region of the transistor.
  • the gate forming surface includes a sidewall or an L-shaped surface
  • the step of sequentially forming a gate oxide layer and a gate on the gate formation surface of each of the transistor columns includes:
  • the gate oxide layer and the gate are sequentially formed on the sidewalls of each of the transistor pillars; or,
  • the gate oxide layer and the gate are sequentially formed on the L-shaped surface of each of the transistor pillars.
  • the transistor formation region further has an insulating layer wrapping other sidewalls of the transistor column; the transistor formation region is formed by:
  • the wafer is partially etched to form a grid-shaped etching groove composed of a plurality of silicon pillars, wherein each 1.
  • the silicon pillar has a first preset thickness, and the first preset thickness is smaller than the initial thickness of the wafer; the first surface of the wafer is any one of the wafer along the first direction noodle;
  • the silicon pillar and the insulating layer are etched to form the transistor pillar with an exposed sidewall or an exposed L-shaped surface, so as to obtain the transistor formation region.
  • etching the silicon pillar and the insulating layer to form the transistor pillar having an exposed sidewall includes:
  • the edge position of the silicon pillar as an etching starting point, along the first direction, partially etching the silicon pillar and the insulating layer, removing the predetermined size in the second direction, and In the first direction, a silicon pillar and an insulating layer with the first predetermined thickness are formed, the transistor pillar with an exposed sidewall is formed, and an etched groove is formed; wherein the predetermined size is is smaller than the initial dimension of the silicon pillar in the second direction; the second direction is perpendicular to the first direction.
  • the method before forming the gate oxide layer and the gate, the method further includes:
  • a first isolation layer is formed by depositing at the bottom of the etching groove
  • forming a gate oxide layer and a gate sequentially on the sidewall of each of the transistor columns includes:
  • the initial gate oxide layer and the polysilicon layer are simultaneously etched to remove a partial thickness of the initial gate oxide layer and the polysilicon layer in the first direction , forming the gate oxide layer and the gate.
  • the method further includes:
  • a second isolation layer is formed by depositing in the etching groove, wherein the second isolation layer is located in the projection area of the transistor column in the second direction, and the second isolation layer is in the third
  • the upward dimension is equal to the dimension of the transistor pillar in the third direction.
  • the method before forming the drain, the method further includes:
  • the wafer is thinned until the first isolation layer and the second ends of the transistor posts are exposed; wherein the second side of the wafer is The side is the side opposite the first side of the wafer.
  • etching the silicon pillar and the insulating layer to form the transistor pillar with an exposed L-shaped surface comprising:
  • the transistor pillar with the L-shaped surface is formed, and an etching groove is formed; wherein the second preset thickness is less than For the first preset thickness, the preset size is smaller than the initial size of the silicon pillar in the second direction; the second direction is perpendicular to the first direction.
  • the L-shaped surface includes a vertical surface and a horizontal surface perpendicular to the vertical surface
  • the step of forming the gate oxide layer and the gate sequentially on the L-shaped surface of each of the transistor pillars includes:
  • the initial gate oxide layer and the polysilicon layer are simultaneously etched to remove a partial thickness of the initial gate oxide layer and the polysilicon layer in the first direction , forming the gate oxide layer and the gate.
  • the method further includes:
  • An isolation layer is deposited in the etching groove, wherein the isolation layer is located in the projection area of the transistor column in the second direction, and the size of the isolation layer in the third direction is the same as the size of the isolation layer in the third direction.
  • the transistor pillars are equal in size in the third direction.
  • the method before forming the drain, the method further includes:
  • a thinning process is performed on the wafer to remove the wafer with a third predetermined thickness and expose the second end of the transistor column; wherein the first Three preset thicknesses are smaller than the difference between the initial thickness and the second preset thickness; wherein, the second side of the wafer is the side opposite to the first side of the wafer.
  • forming a drain at the second end of the transistor column includes:
  • the preset depth is less than or equal to the difference between the initial thickness and the second preset thickness .
  • the source and the drain have the same or different shapes
  • the shape of the source electrode and the drain electrode includes any one of the following: a square, a semicircle, a triangle or an arbitrary polygon.
  • An embodiment of the present application provides a transistor, and the transistor includes:
  • a source electrode located at the first end of the channel region
  • the drain is located at the second end of the channel region, wherein the first end and the second end are opposite ends of the channel region in a first direction, and the first direction is the thickness direction of the wafer forming the channel region;
  • a gate located on either side of the channel region, and corresponding to the channel region;
  • a gate oxide layer is located between the channel region and the gate.
  • the source electrode, the channel region and the drain electrode form an L-shaped structure or a columnar structure.
  • Embodiments of the present application provide a method for forming a semiconductor device, the method comprising:
  • At least one memory cell is formed, wherein each of the memory cells at least comprises: a transistor; the transistor comprises: a gate electrode, a source electrode and a drain electrode; the transistor is manufactured by the above-mentioned method for manufacturing a transistor;
  • the word line is connected to the gate of the transistor, the word line is used to provide a word line voltage, and the transistor is controlled to be turned on or off by the word line voltage;
  • bit line is formed, the bit line is connected to the source or drain of the transistor, and the bit line is used to perform a read or write operation on the memory cell when the transistor is turned on.
  • Embodiments of the present application further provide a semiconductor device, including: at least one memory cell, a word line and a bit line, each of the memory cells at least includes: the above-mentioned transistor; the transistor at least includes: a gate, a source and a drain ;
  • the word line is connected to the gate of the transistor, and the word line is used to provide a word line voltage, and the transistor is controlled to be turned on or off by the word line voltage;
  • the bit line is connected to the source or drain of the transistor, and the bit line is used to perform a read or write operation on the memory cell when the transistor is turned on.
  • the memory unit further comprises: a storage capacitor
  • One end of the storage capacitor is connected to the drain or source of the transistor, and the other end of the storage capacitor is grounded, and the storage capacitor is used for storing data written in the memory cell.
  • the memory cell further comprises: an adjustable resistance
  • the adjustable resistance is connected between the bit line and the source of the transistor, or the adjustable resistance is connected between the bit line and the drain of the transistor, and the adjustable resistance is The state of the data stored in the memory cell is regulated by the bit line voltage provided through the bit line.
  • the semiconductor device when the semiconductor device includes a plurality of the memory cells, the plurality of the memory cells are connected in parallel or in series.
  • the semiconductor device and the method for manufacturing the transistor provided in the embodiments of the present application since the source and drain of the formed transistor are located at the first end and the second end of the channel region in the first direction, respectively, and the third One direction is the thickness direction of the wafer on which the channel region is formed, thus greatly reducing the area of the transistor.
  • the transistors provided in the embodiments of the present application can be used to form memories. Since the drains and sources of the transistors are located on different sides of the wafer, different structures connected to the sources and drains in the memory can be designed on the wafer respectively. In the two sides of the wafer, that is, they are designed in two opposite sides of the wafer, thereby simplifying the circuit layout inside the memory and reducing the process difficulty of memory manufacturing.
  • 1A is a schematic structural diagram of a planar transistor in the related art
  • 1B is a schematic structural diagram of a buried channel transistor in the related art
  • 1C is a schematic structural diagram of a DRAM memory cell formed by using a planar transistor in the related art
  • 1D is a schematic structural diagram of a DRAM memory cell formed by using a buried channel transistor in the related art
  • FIGS. 2A and 2B are schematic diagrams of an optional structure of a transistor provided by an embodiment of the present application.
  • 3A is an optional schematic flowchart of a method for manufacturing a columnar transistor provided by an embodiment of the present application
  • 3B to 3L are schematic structural diagrams of a formation process of a columnar transistor according to an embodiment of the present application.
  • 3M and 3N are schematic diagrams of an optional structure of a columnar transistor provided by an embodiment of the present application.
  • 4A is an optional schematic flowchart of a method for manufacturing an L-type transistor provided by an embodiment of the present application
  • 4B to 4J are schematic structural diagrams of a formation process of an L-type transistor according to an embodiment of the present application.
  • 4K and 4L are schematic structural diagrams of an optional L-type transistor provided by an embodiment of the present application.
  • 5A and 5B are an optional schematic structural diagram of a semiconductor device provided by an embodiment of the present application.
  • 5C and 5D are schematic diagrams of an optional structure of a DRAM memory cell provided by an embodiment of the present application.
  • 5E and 5F are schematic diagrams of an optional structure of a PCM storage unit provided by an embodiment of the present application.
  • FIG. 6 is an optional structural schematic diagram of a method for forming a semiconductor device provided by an embodiment of the present application.
  • the transistors of mainstream memory include planar transistors (Planar) and buried channel transistors (Buried Channel Array Transistor, BCAT).
  • the poles are located on both horizontal sides of the gate.
  • the source S and the drain D of the transistor in the related art are located on horizontal sides of the gate G, respectively.
  • the source electrode and the drain electrode occupy different positions respectively, so that both the planar transistor and the buried channel transistor have a larger area.
  • the transistor can be fabricated on a silicon substrate, the transistor can be used in various memories, eg, DRAM.
  • DRAM is composed of multiple memory cells, each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, that is, DRAM is a memory cell with one transistor and one capacitor C (1T1C).
  • the source (or drain) 101 of the transistor in the DRAM memory cell is connected to the bit line 102
  • the drain (or source) 103 is connected to the capacitor 104 .
  • Chips formed by using BCAT are usually packaged in a chip-on-board (COB) manner to form a memory.
  • COB chip-on-board
  • the bit line and capacitor in the DRAM memory cell are also located on the same side of the gate, and the subsequent process also It is necessary to realize the connection between the bit line, the transistor and the capacitor, the connection between the word line (WL) and the transistor, etc., which leads to complicated circuit wiring in the storage array area of the DRAM memory, and the manufacturing process is difficult.
  • the embodiments of the present application provide a transistor and a method for manufacturing the same, a semiconductor device and a method for manufacturing the same, which can provide a transistor structure with a small area, and the transistor provided by the embodiments of the present application
  • the structure can simplify the circuit layout inside the memory and reduce the process difficulty of the memory manufacturing.
  • the transistor 20 includes: a channel region 201 , a source electrode 202 , a drain electrode 203 , and a gate electrode 204 and gate oxide 205.
  • the channel region 201 has a vertical structure, the source electrode 202 is located at the first end of the channel region 201; the drain electrode 203 is located at the second end of the channel region 201, the source electrode, the channel region and the
  • the drain electrode forms a columnar structure or an L-shaped structure.
  • the first end and the second end are the opposite ends of the channel region in the first direction, and here, the thickness direction of the wafer forming the channel region is defined as the first direction (as shown in FIGS. 2A and 2B ).
  • the Z-axis direction), any direction perpendicular to the first direction is defined as the second direction (the X-axis direction in FIG. 2B ).
  • the positions of the source electrode 202 and the drain electrode 203 may be interchanged.
  • the first end and the second end have the same or different dimensions in the second direction.
  • the gate electrode 204 is located on either side of the channel region 201 , and corresponds to the channel region 201 , and the gate oxide layer 205 is located between the channel region 201 and the gate electrode 204 .
  • the source electrode and the drain electrode are located at opposite ends of the wafer in the thickness direction of the channel region, respectively, that is, the source electrode and the drain electrode of the transistor provided in the embodiment of the present application are located at the opposite two ends of the wafer. In this way, the area of the transistor is greatly reduced.
  • Step 1 Provide a wafer, the wafer has a plurality of transistor formation regions, each of the transistor formation regions has a transistor column, and each of the transistor columns has an exposed gate formation surface.
  • the gate formation surface is a surface on which the gate is formed.
  • Step 2 sequentially forming a gate oxide layer and a gate on the gate formation surface of each of the transistor columns.
  • Step 3 forming a source electrode at the first end of the transistor column.
  • Step 4 forming a drain at the second end of the transistor column, wherein the first end and the second end are opposite ends of the transistor column in the first direction, and the first end and the second end are respectively opposite ends of the transistor column in the first direction.
  • the direction is the thickness direction of the wafer; the transistor column between the source electrode and the drain electrode constitutes the channel region of the transistor.
  • the gate formation surface includes a sidewall or an L-shaped surface; correspondingly, the gate oxide layer and the gate are sequentially formed on the gate formation surface of each transistor column,
  • the method includes: sequentially forming the gate oxide layer and the gate on the sidewall of each of the transistor pillars; or, sequentially forming the gate on the L-shaped surface of each of the transistor pillars oxide layer and the gate.
  • the transistors provided in the embodiments of the present application include pillar-shaped transistors, and the pillar-shaped transistors can be formed by the manufacturing methods of the transistors provided in the following embodiments.
  • FIG. 3A is an optional schematic flowchart of a method for manufacturing a columnar transistor provided by an embodiment of the present application. As shown in FIG. 3A , the method for manufacturing a columnar transistor includes the following steps:
  • Step S301 providing a wafer, the wafer has a plurality of transistor formation regions, each of the transistor formation regions has a transistor column, and each of the transistor columns has an exposed sidewall.
  • Step S302 forming a gate oxide layer and a gate sequentially on the sidewall of each of the transistor columns.
  • Step S303 forming a source electrode at the first end of the transistor column.
  • Step S304 forming a drain at the second end of the transistor column.
  • the first end and the second end are opposite ends of the transistor column in a first direction, and the first direction is the thickness direction of the wafer; the source and the The transistor pillars between the drains constitute the channel region of the transistor.
  • FIG. 3B to FIG. 3L for further detailed description of the manufacturing method of the transistor provided by the embodiment of the present application.
  • the transistor formation regions are regions on a wafer for forming transistors, each of the transistor formation regions has a transistor column, and each transistor column has an exposed sidewall.
  • the transistor forming region also has an insulating layer wrapping other sidewalls of the transistor pillars.
  • step S301 is performed to provide a wafer, the wafer has a plurality of transistor formation regions, each of the transistor formation regions has a transistor column, and each of the transistor columns has a Exposed sidewalls.
  • the transistor formation region is formed by:
  • Step S3011 along the first direction, with the first surface of the wafer as an etching starting point, partially etch the wafer to form a grid-shaped etching trench composed of a plurality of silicon pillars.
  • each of the silicon pillars has a first predetermined thickness, and the first predetermined thickness is smaller than the initial thickness of the wafer; the first surface of the wafer is the wafer along the first direction any side of .
  • the thickness direction of the wafer is defined as the first direction.
  • Two second and third directions intersecting with each other are defined in the top surface or the bottom surface of the wafer perpendicular to the first direction. Based on the second direction and the third direction, it can be determined that the wafer is perpendicular to the first direction. the top surface or the bottom surface in the first direction.
  • the second direction and the third direction are perpendicular to each other.
  • the first direction, the second direction and the third direction are perpendicular to each other.
  • the first direction may be defined as the Z-axis direction
  • the second direction may be defined as the X-axis direction
  • the third direction may be defined as the Y-axis direction.
  • FIG. 3B is a cross-sectional view of the grid-shaped etching trench provided by the embodiment of the present application along the first direction
  • FIG. 3C is a top view of the grid-shaped etching trench provided by the embodiment of the present application.
  • each of the silicon pillars 301 has a first predetermined thickness A in the Z-axis direction, and the first predetermined thickness is smaller than the initial thickness B of the wafer; the first surface of the wafer 30-1 is any surface of the wafer along the Z-axis direction.
  • the wafer also includes a second side 30-2 opposite the first side 30-1.
  • the wafer may be etched by a dry etching process, for example, a plasma etching process or a reactive ion etching process. It is worth noting that, in the embodiment of the present application, the etching of the wafer is a partial etching performed in the thickness direction of the wafer, that is, the etching process will not etch through the wafer.
  • Step S3012 depositing insulating material in the grid-shaped etch trenches to form an insulating layer surrounding each of the silicon pillars.
  • the insulating material may be a silicon dioxide material or other insulating materials.
  • 3D is a top view of forming an insulating layer in a grid-shaped etching trench provided by an embodiment of the present application. As shown in FIG. 3D, an insulating material SiO 2 is deposited in the grid-shaped etching trench 31, and each silicon pillar is The periphery of 301 is filled with insulating material SiO 2 to form insulating layer 32 .
  • the insulating material SiO 2 will cover the surface of the silicon pillar 301 , and usually after the deposition is completed, a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process is used to polish and remove the excess The insulating material SiO 2 is used to expose the surface of the silicon pillar 301 .
  • CMP Chemical Mechanical Polishing
  • Step S3013 etching the silicon pillar and the insulating layer to form the transistor pillar with an exposed sidewall to obtain the transistor formation region.
  • the etching the silicon pillar and the insulating layer to form the transistor pillar with an exposed sidewall includes: taking an edge position of the silicon pillar as an etching starting point, Partially etch the silicon pillars and the insulating layer along the first direction to remove the silicon pillars and the insulating layer that have a preset size in the second direction and have the first preset thickness in the first direction.
  • a silicon pillar and an insulating layer are formed, the transistor pillar with an exposed sidewall is formed, and an etched groove is formed.
  • FIG. 3E is a top view of a transistor column provided by an embodiment of the present application.
  • the silicon column and the insulating layer are etched along the X-axis direction with the edge position of the silicon column as an etching starting point.
  • the preset size C is smaller than the initial size D of the silicon pillar 301 in the X-axis direction.
  • transistors will be formed on one wafer. Therefore, there are multiple transistor formation regions in one wafer. In the embodiments of the present application, for the convenience of description, only a limited number of transistors are exemplarily shown form a region.
  • step S302 is performed, and a gate oxide layer and a gate electrode are sequentially formed on the sidewalls of each of the transistor columns.
  • the method for manufacturing the transistor before step S302 is performed, the method for manufacturing the transistor further includes:
  • Step S10 depositing and forming a first isolation layer at the bottom of the etching groove.
  • the material of the first isolation layer includes but is not limited to any one of the following: silicon nitride, silicon oxynitride, silicon carbide or silicon dioxide.
  • FIG. 3F is a schematic structural diagram of forming a first isolation layer according to an embodiment of the present application.
  • a first isolation layer 304 is deposited and formed at the bottom of the etching groove (not shown in FIG. 3F ).
  • the first isolation layer may be formed by deposition through any suitable deposition process.
  • the above process of forming the gate oxide layer and the gate electrode is performed, and the gate oxide layer and the gate electrode are sequentially formed on the sidewall of each of the transistor columns, Include the following steps:
  • Step S3021 forming an initial gate oxide layer on the sidewall of the transistor column by in-situ oxidation.
  • FIG. 3G is a schematic structural diagram of forming an initial gate oxide layer according to an embodiment of the present application, as shown in FIG. 3G and FIG. 3F .
  • the exposed part of the sidewall of the transistor column 301 may be heated or pressurized.
  • 302-1' is oxidized in-situ to form an initial gate oxide layer 305'.
  • Step S3022 depositing a polysilicon material in the etching groove to form a polysilicon layer.
  • the etching after depositing the first isolation layer 304 may be performed by a chemical vapor deposition (Chemical Vapor Deposition, PVD), a physical vapor deposition (Physical Vapour Deposition, PVD) or an atomic layer deposition (Atomic Layer Deposition, ALD) process
  • PVD chemical Vapor Deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • a polysilicon layer is formed by depositing a polysilicon material in the groove.
  • Step S3023 In the first direction, the initial gate oxide layer and the polysilicon layer are simultaneously etched to remove a partial thickness of the initial gate oxide layer and all the polysilicon layers in the first direction.
  • the polysilicon layer is formed to form the gate oxide layer and the gate.
  • 3H is a schematic structural diagram of forming a gate oxide layer and a gate provided by an embodiment of the present application. As shown in FIG. 3H , along the Z-axis direction, partial etching is performed on the above-formed initial gate oxide layer and polysilicon layer at the same time , the gate oxide layer 305 and the gate electrode 306 are obtained. In this embodiment of the present application, a dry etching technique may be used to etch the initial gate oxide layer and the polysilicon layer.
  • the method of fabricating the transistor further includes:
  • Step S11 depositing a second isolation layer in the etching groove, wherein the second isolation layer is located in the projection area of the transistor column in the second direction, and the second isolation layer is The dimensions in the third direction are equal to the dimensions of the transistor pillars in the third direction.
  • the third direction, the second direction and the first direction are perpendicular to each other. It should be noted that, in other embodiments, the third direction may not be perpendicular to the second direction, and the included angle between the third direction and the second direction may be any angle.
  • the material of the second isolation layer includes but is not limited to any one of the following: silicon nitride, silicon oxynitride, silicon carbide or silicon dioxide; the second isolation layer is made of the same material as the first isolation layer or different.
  • FIG. 3I is a schematic structural diagram of forming a second isolation layer according to an embodiment of the present application.
  • the second isolation layer 307 is located in the projection area of the transistor column 302 in the X-axis direction, and the second isolation layer
  • the size in the Y-axis direction is equal to the size of the transistor column in the Y-axis direction.
  • step S303 is performed, and a source electrode is formed at the first end of the transistor column.
  • FIG. 3J is a schematic structural diagram of forming a source electrode according to an embodiment of the present application. As shown in FIG. 3J , the source electrode 308 is formed by performing ion implantation on the first end of the transistor column.
  • the shape of the source electrode includes any one of the following: a square, a semicircle, a triangle, or an arbitrary polygon.
  • the method for manufacturing the transistor before step S304 is performed, the method for manufacturing the transistor further includes:
  • Step S12 starting from the second side of the wafer, thinning the wafer until the first isolation layer and the second end of the transistor column are exposed.
  • the second side 30-2 of the wafer is the side opposite to the first side of the wafer.
  • the first side of the wafer needs to be fixed on a support structure to prevent the thinning of the second side 30-2 of the wafer from being thinned. When thin, it destroys the structure of the transistor already formed.
  • 3K is a schematic structural diagram of a transistor after thinning the second side of the wafer according to an embodiment of the present application. As shown in FIG. 3K , the second side of the wafer is thinned to expose the first isolation layer 304 and the second end 309' of the transistor post.
  • step S304 is performed, and a drain is formed at the second end of the transistor column.
  • FIG. 3L is a schematic structural diagram of forming a drain according to an embodiment of the present application. As shown in FIG. 3L , the drain 309 is formed by performing ion implantation on the second end 309 ′ of the transistor column.
  • the shape of the drain includes any one of the following: square, semicircle, triangle or any polygon.
  • 3M and 3N are schematic diagrams of an optional structure of the columnar transistor provided by the embodiment of the present application.
  • the cross-sectional shapes of the source and the drain of the columnar transistor are both semicircular, as shown in FIG.
  • the cross-sectional shapes of the source electrode and the drain electrode of the columnar transistor are both triangular.
  • the positions of the source electrode and the drain electrode may be interchanged, and the shapes of the source electrode and the drain electrode of the columnar transistor formed in the embodiment of the present application may be the same or different.
  • the transistor column between the source electrode and the drain electrode constitutes the channel region 310 of the transistor.
  • the source and the drain are located at the first end and the second end of the channel region in the first direction, respectively, and the first direction is the formation of The thickness direction of the wafer in the channel region, thus, greatly reduces the area of the transistor.
  • the drain and source of the columnar transistor are located on different sides of the wafer, the source and drain of the memory can be The different structures connected are designed on two sides of the wafer, thereby simplifying the circuit layout inside the memory and reducing the process difficulty of memory manufacturing.
  • the transistors provided in the embodiments of the present application further include L-type transistors, and the L-type transistors can be formed by the manufacturing methods of the transistors provided in the following embodiments.
  • FIG. 4A is an optional schematic flowchart of a method for manufacturing an L-type transistor provided by an embodiment of the present application. As shown in FIG. 4A , the method for manufacturing an L-type transistor includes the following steps:
  • Step S401 providing a wafer, the wafer has a plurality of transistor formation regions, each of the transistor formation regions has a transistor column, and each of the transistor columns has an exposed L-shaped surface.
  • Step S402 forming a gate oxide layer and a gate sequentially on the L-shaped surface of each of the transistor columns.
  • Step S403 forming a source electrode at the first end of the transistor column.
  • Step S404 forming a drain at the second end of the transistor column.
  • first end and the second end are opposite ends of the transistor column in the first direction, respectively, and the dimensions of the first end and the second end in the second direction are different;
  • the first direction is the thickness direction of the wafer, and the second direction is perpendicular to the first direction;
  • the transistor column between the source electrode and the drain electrode constitutes a channel region of the transistor.
  • FIG. 4B to FIG. 4D for further detailed description of the manufacturing method of the L-type transistor provided by the embodiments of the present application.
  • the transistor formation regions are regions on the wafer for forming transistors, each of the transistor formation regions has a transistor column, and each transistor column has an exposed L-shaped surface.
  • the transistor formation region also has an insulating layer wrapping the sidewalls of the transistor pillars.
  • the formation process of the transistor formation region is the same as the formation process of the transistor region in the above-mentioned embodiment, and is not repeated here.
  • FIG. 4B is a cross-sectional view of a transistor column provided by an embodiment of the present application along a first direction
  • FIG. 4C is a top view of the transistor column provided by an embodiment of the present application.
  • the wafer forming the silicon column has Opposite the first surface 40-1 and the second surface 40-2, the first surface 40-1 is any surface of the wafer along the Z-axis direction. Taking the edge position of the silicon pillar as the etching starting point, along the X-axis direction, the silicon pillar and the insulating layer are etched to remove the predetermined size C in the X-axis direction and the Z-axis direction.
  • the second predetermined thickness E of the silicon pillars and the insulating layer forms transistor pillars 402 and etched grooves 403 , and further forms a transistor formation region 40 ′ in the wafer 40 .
  • the preset size C is smaller than the initial size D of the silicon pillar in the X-axis direction
  • the second preset thickness E is smaller than the first preset thickness A
  • the The first preset thickness A is smaller than the initial thickness B of the wafer in the Z-axis direction.
  • each silicon pillar is not shown in FIG. 4B .
  • FIG. 4D is a perspective view of the transistor column provided by the embodiment of the present application. It can be seen from the figure that the transistor column 402 has an L-shaped surface.
  • the L-shaped surface includes a vertical surface 402-1' and a horizontal surface 402-2' perpendicular to the vertical surface.
  • transistors will be formed on one wafer. Therefore, there are multiple transistor formation regions in one wafer. In the embodiments of the present application, for the convenience of description, only a limited number of transistors are exemplarily shown form a region.
  • step S402 is performed, and a gate oxide layer and a gate electrode are sequentially formed on the sidewalls of each of the transistor columns.
  • the step of sequentially forming a gate oxide layer and a gate on the L-shaped surface of each of the transistor columns includes the following steps:
  • Step S4021 forming an initial gate oxide layer on the vertical plane and the horizontal plane respectively by in-situ oxidation.
  • FIG. 4E which is a schematic structural diagram of forming an initial gate oxide layer provided by an embodiment of the present application, here, the horizontal plane 402-2' and the vertical plane 402-2' can be heated or pressurized. 1' is oxidized in-situ to form an initial gate oxide layer 404'.
  • Step S4022 depositing a polysilicon material in the etching groove with the initial gate oxide layer to form a polysilicon layer.
  • Step S4023 in the first direction, perform an etching process on the initial gate oxide layer and the polysilicon layer at the same time, and remove a partial thickness of the initial gate oxide layer and all the polysilicon layers in the first direction.
  • the polysilicon layer is formed to form the gate oxide layer and the gate.
  • FIG. 4F is a schematic structural diagram of forming a gate oxide layer and a gate provided by an embodiment of the present application. As shown in FIG. 4F, along the Z-axis direction, partial etching is performed on the above-formed initial gate oxide layer and polysilicon layer at the same time. , the gate oxide layer 404 and the gate electrode 405 are obtained. In this embodiment of the present application, a dry etching technique may be used to etch the initial gate oxide layer and the polysilicon layer.
  • the manufacturing method of the L-type transistor further includes:
  • Step S20 depositing an isolation layer in the etching groove, wherein the isolation layer is located in the projection area of the transistor column in the second direction, and the size of the isolation layer in the third direction is equal to the size of the transistor pillar in the third direction.
  • the third direction, the second direction and the first direction are perpendicular to each other. It should be noted that, in other embodiments, the third direction may not be perpendicular to the second direction, and the included angle between the third direction and the second direction may be any angle.
  • the material of the isolation layer includes but is not limited to any one of the following: silicon nitride, silicon oxynitride, silicon carbide or silicon dioxide.
  • FIG. 4G is a schematic structural diagram of forming an isolation layer according to an embodiment of the present application.
  • the isolation layer 406 is located in the projection area of the transistor column 402 in the X-axis direction, and the isolation layer is in the Y-axis direction.
  • the dimensions are equal to the dimensions of the transistor pillars in the Y-axis direction.
  • step S403 is performed, and a source electrode is formed at the first end of the transistor column.
  • FIG. 4H is a schematic structural diagram of forming a source electrode according to an embodiment of the present application. As shown in FIG. 4H , the source electrode 407 is formed by performing ion implantation on the first end of the transistor column.
  • the shape of the source electrode includes any one of the following: a square, a semicircle, a triangle, or an arbitrary polygon.
  • the method for manufacturing the transistor before performing step S404, the method for manufacturing the transistor further includes:
  • Step S21 starting from the second side of the wafer, performing a thinning process on the wafer to remove the wafer with a third predetermined thickness and expose the second end of the transistor column.
  • the third predetermined thickness is smaller than the difference between the initial thickness of the wafer and the second predetermined thickness. That is, in the embodiment of the present application, when thinning the silicon on the second surface of the first wafer, it is necessary to ensure that a certain thickness of silicon remains at the bottom of the etching groove.
  • the first side of the wafer needs to be fixed on a support structure to prevent the thinning of the second side 40-2 of the wafer from being thinned. When thin, it destroys the structure of the transistor already formed.
  • FIG. 4I is a schematic structural diagram of a transistor after thinning the second side of the wafer according to an embodiment of the present application. As shown in FIG. 4I , the second side of the wafer is thinned, and the third preset is removed. thickness of the wafer, exposing the second ends 408' of the transistor posts.
  • step S404 is performed, and a drain is formed at the second end of the transistor column.
  • the forming the drain at the second end of the transistor column includes: performing ion implantation at the second end of the transistor column with a predetermined depth to form the drain, wherein the drain is formed.
  • the preset depth is less than or equal to the difference between the initial thickness and the second preset thickness.
  • the depth of ion implantation into the drain may be a preset preset depth, and the maximum value of the preset depth may be equal to the difference between the initial thickness of the wafer and the second preset thickness.
  • FIG. 4J is an optional structural schematic diagram of forming a drain provided by an embodiment of the present application.
  • the drain 408 is formed by performing ion implantation on the second end 408 ′ of the transistor column with a predetermined depth.
  • the preset depth is equal to the difference between the first preset thickness and the second preset thickness, while a vertical channel region 409 is formed between the source electrode 407 and the drain electrode 408 .
  • the shape of the drain includes any one of the following: square, semicircle, triangle or any polygon.
  • the finally formed transistor is an L-type transistor, that is, the source electrode, the drain electrode and the channel region of the transistor together form an L-type structure.
  • 4K and 4L are schematic diagrams of an optional structure of the L-type transistor provided by the embodiment of the present application.
  • the cross-sectional shapes of the source electrode and the drain electrode of the L-type transistor are semi-circular, as shown in FIG.
  • the cross-sectional shapes of the source and the drain of the L-type transistor are both triangular.
  • the positions of the source electrode and the drain electrode can be interchanged, that is, the source electrode or the drain electrode can be formed first, and the shapes of the source electrode and the drain electrode of the L-type transistor formed in the embodiment of the present application can be the same, or can be different.
  • the source electrode and the drain electrode are respectively located at the first end and the second end of the channel region in the first direction, and the first direction is the formation of The thickness direction of the wafer in the channel region, thus, greatly reduces the area of the transistor.
  • the L-type transistor provided by the embodiments of the present application when the L-type transistor provided by the embodiments of the present application is applied to a memory, since the drain and source of the L-type transistor are located on different sides of the wafer, the source and drain of the memory can be The different structures connected are designed on two sides of the wafer, thereby simplifying the circuit layout inside the memory and reducing the process difficulty of memory manufacturing.
  • FIGS. 5A and 5B are an optional schematic structural diagram of the semiconductor device provided by the embodiment of the present application.
  • the semiconductor device 50 includes: at least one memory Cell, word line 502 and bit line 503.
  • each of the memory cells includes at least one transistor, such as a pillar-shaped transistor 501a or an L-type transistor 501b, and the pillar-shaped transistor 501a or the L-type transistor 501b at least includes a gate G, a source S and a drain D .
  • the columnar transistor 501a or the L-type transistor 501b further includes a channel region, the source of each columnar transistor is located at the first end of the channel region; the drain of each columnar transistor is located in the channel region The second end of the thickness direction.
  • the columnar transistor 501a or the L-type transistor 501b in the embodiment of the present application has a vertical channel, and the source and drain of the columnar transistor 501a are located at two ends of the vertical channel, respectively.
  • the word line 502 is connected to the gate G of the columnar transistor 501a, and the word line is used to provide a wordline voltage, and the columnar transistor 501a is controlled to conduct by the wordline voltage.
  • the word line 502 is connected to the gate G of the L-type transistor 501b, the word line is used to provide a word line voltage, and the L-type transistor 501b is controlled by the word line voltage to conduct pass or cut off.
  • the bit line 503 is connected to the source S or the drain D of the columnar transistor 501a, and the bit line is used to perform a read or write operation on the memory cell when the columnar transistor is turned on Alternatively, the bit line 503 is connected to the source S or the drain D of the L-type transistor 501b, and the bit line is used to read or read the memory cell when the column transistor is turned on. write operation
  • the drain of the column transistor when the source S of the column transistor 501a is connected to the bit line 503, the drain of the column transistor is grounded; when the drain of the column transistor 501a is connected to the bit line 503, the The source of the column transistor is grounded; or, when the source S of the L-type transistor 501b is connected to the bit line 503, the drain of the L-type transistor is grounded; when the drain of the L-type transistor 501b is connected to the bit line When line 503 is connected, the source of the L-type transistor is grounded.
  • the semiconductor devices provided by the embodiments of the present application include various types of memories.
  • NAND Flash Flash
  • Nor Flash DRAM
  • Static Random Access Memory SRAM
  • Phase-Change Memory PCM
  • Ferroelectric Memory Magnetic Change Memory or Resistive Memory .
  • the storage unit when the semiconductor device is a DRAM, the storage unit further includes: a storage capacitor.
  • FIGS. 5C and 5D are an optional structural schematic diagram of a DRAM storage unit provided by an embodiment of the present application, it can be seen that in the DRAM storage unit 50 ′, one end of the storage capacitor 504 is connected to the columnar transistor 501 a The drain or source of the storage capacitor 504 is connected to the drain or source, or, one end of the storage capacitor 504 is connected to the drain or source of the L-type transistor 501b; the other end of the storage capacitor 504 is grounded, and the storage capacitor 504 is used for storage write data to the memory cell.
  • the memory cell when the semiconductor device is a PCM, the memory cell further comprises: an adjustable resistance.
  • FIGS. 5E and 5F are an optional structural schematic diagram of a PCM storage unit provided by an embodiment of the present application, it can be seen that, in the PCM storage unit 50 ′′, the adjustable resistor 505 is connected to the bit line 503 and the bit line 503 ”. Between the source or drain of the columnar transistor 501a, or the adjustable resistor 505 is connected between the bit line 503 and the source or drain of the columnar L-type transistor 501b, the The adjustable resistor 505 is used to adjust the state of the data stored in the memory cell by the bit line voltage provided by the bit line.
  • the semiconductor device when the semiconductor device includes a plurality of the memory cells, the semiconductor device is NAND Flash or Nor Flash. When a plurality of the memory cells are connected in parallel, the semiconductor device is a Nor Flash; when a plurality of the memory cells are connected in series, the semiconductor device is a NAND Flash.
  • the structure of the transistor of the semiconductor device as a novel structure with a vertical channel, the area of the memory cell is reduced and the storage density of the memory cell is improved.
  • the source electrode and the drain electrode are located at the upper and lower ends of the vertical channel region.
  • bit lines or other structures can be respectively arranged in the channel region. the vertical sides.
  • the bit lines and capacitors of DRAM memory cells can be arranged on two sides of the same wafer, so that the circuit arrangement of word lines, bit lines and capacitors can be simplified, and the cost of semiconductor devices can be reduced. Manufacturing process difficulty.
  • FIG. 6 is an optional structural schematic diagram of the method for forming a semiconductor device provided by an embodiment of the present application. As shown in FIG. 6 , the The method includes the following steps:
  • Step S601 forming at least one memory cell, wherein each of the memory cells at least includes: a transistor; and the transistor includes a gate, a source, and a drain.
  • the transistors include columnar transistors or L-type transistors.
  • Step S602 forming a word line, the word line is connected to the gate of the transistor, the word line is used to provide a word line voltage, and the transistor is controlled to be turned on or off by the word line voltage.
  • Step S603 forming a bit line, where the bit line is connected to the source or drain of the transistor, and the bit line is used to perform a read or write operation on the memory cell when the transistor is turned on.
  • the columnar transistors in the memory cells are formed by:
  • Step S6011 removing a certain thickness (corresponding to the first preset thickness in the above-mentioned embodiment) of the silicon in the partial region of the first surface of the first wafer by an etching process to form a grid-shaped groove with silicon pillars in the middle ( Corresponding to the grid-shaped etching trench in the above-mentioned embodiment), fill the trench with silicon dioxide (corresponding to the insulating layer in the above-mentioned embodiment), and then expose the surface of the silicon column by chemical mechanical polishing, and finally by etching Parts of the silicon pillars are removed to expose the sidewalls of the silicon pillars (corresponding to the process of forming the transistor pillars in the above embodiment).
  • step S6012 silicon nitride is formed at the bottom of the trench to serve as a bottom spacer structure (corresponding to the formation of the first spacer layer in the above-mentioned embodiment).
  • step S6013 silicon oxide is formed on the sidewall of the trench by in-situ growth as a gate oxide layer (corresponding to the formation of the initial gate oxide layer in the above embodiment).
  • step S6014 polysilicon is filled in the trench (corresponding to the formation of the polysilicon layer in the above-mentioned embodiment), and the polysilicon on the top is removed to a certain depth by etching, and then the exposed silicon oxide on the top is removed (corresponding to the above-mentioned embodiment. Step S3023).
  • step S6015 silicon nitride is formed on the top of the trench to serve as the top isolation structure (corresponding to the formation of the second isolation layer in the above embodiment).
  • step S6016 a source terminal is formed in the transistor region reserved in step S6011 (corresponding to the first terminal of the transistor column in the above embodiment) by ion implantation.
  • Step S6017 forming subsequent corresponding structures on the first side of the first wafer through various processes; then bonding the first wafer with the second wafer, and finally thinning the silicon on the backside of the first wafer, Until the bottom isolation structure and the second side of the first wafer are exposed (corresponding to step S12 in the above embodiment).
  • the subsequent corresponding structures include structures such as forming bit lines, forming resistors, or forming capacitors.
  • the second wafer is provided with various logic circuits, sensors and other components, and the second wafer and the first wafer are bonded together to form a memory.
  • the wafer bonding process is implemented before the backside silicon thinning process, and the second wafer provides support for the first wafer during the thinning process, preventing the first wafer from being thinned during the thinning process. of damage.
  • step S6018 on the second surface of the first wafer, a drain is formed at a position opposite to the source in step S5016 (corresponding to the second end of the transistor column) by ion implantation.
  • step S6019 the subsequent corresponding structures are finally formed on the second surface of the first wafer.
  • the subsequent corresponding structures include structures such as forming bit lines, forming resistors, or forming capacitors.
  • the L-type transistors in the memory cells are formed by:
  • Step S7011 removing a certain thickness of silicon (corresponding to the first preset thickness in the above-mentioned embodiment) from the partial region of the first surface of the first wafer by an etching process to form a grid-shaped trench with silicon pillars in the middle ( Corresponding to the grid-shaped etching trench in the above-mentioned embodiment), fill the trench with silicon dioxide (corresponding to the insulating layer in the above-mentioned embodiment), and then expose the surface of the silicon column by chemical mechanical polishing, and finally by etching Part of the silicon pillar is removed to form an exposed L-shaped surface (corresponding to the process of forming the transistor pillar in the above embodiment).
  • Step S7012 forming silicon oxide as a gate oxide layer on the sidewall and bottom of the trench by in-situ growth (corresponding to the formation of the initial gate oxide layer in the above embodiment).
  • step S7013 polysilicon is filled in the trench (corresponding to the formation of the polysilicon layer in the above-mentioned embodiment), and the polysilicon on the top is removed to a certain depth by etching, and then the exposed silicon oxide on the top is removed (corresponding to the above-mentioned embodiment. Step S4023).
  • step S7014 silicon nitride is formed on the top of the trench to serve as an isolation structure on the top (corresponding to the formation of the isolation layer in the above embodiment).
  • step S7015 a source terminal is formed in the transistor region reserved in step S7011 (corresponding to the first terminal of the transistor column in the above-mentioned embodiment) by ion implantation.
  • Step S7016 forming subsequent corresponding structures on the first surface of the first wafer through various processes; then bonding the first wafer with the second wafer, and finally thinning the silicon on the backside of the first wafer, It is ensured that the trench region (corresponding to the etching trench in the above embodiment) has a certain thickness of silicon remaining, exposing the second surface of the first wafer (corresponding to step S21 in the above embodiment).
  • the subsequent corresponding structures include structures such as forming bit lines, forming resistors, or forming capacitors.
  • the second wafer is provided with various logic circuits, sensors and other components, and the second wafer and the first wafer are bonded together to form a memory.
  • the wafer bonding process is implemented before the backside silicon thinning process, and the second wafer provides support for the first wafer during the thinning process, preventing the first wafer from being thinned during the thinning process. of damage.
  • step S7017 on the second surface of the first wafer, a drain is formed at a position opposite to the source in step S5015 (corresponding to the second end of the transistor column) by ion implantation.
  • Step S7018 Finally, a subsequent corresponding structure is formed on the second surface of the first wafer.
  • the subsequent corresponding structures include structures such as forming bit lines, forming resistors, or forming capacitors.
  • the horizontal cross-section of the formed columnar transistor or L-type transistor can be rectangular (square), semicircular, triangular, and any polygon.
  • the source and drain of the columnar transistor or the L-type transistor can be interchanged, and the source and drain can be processed on two sides of the same wafer respectively. Therefore, the source and drain patterns can be different.
  • word lines and bit lines are implemented by forming metal lines at predetermined word line positions and predetermined bit line positions.
  • the metal lines include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, suicide, or any combination thereof.
  • the structure of the transistor of the semiconductor device as a novel transistor structure with a vertical channel, the area of the memory cell is reduced and the storage density of the memory cell is improved.
  • the source and drain of the transistor in the embodiment of the present application are located at the upper and lower ends of the vertical channel region.
  • the Bit lines or other structures may be provided in two opposing sides of the wafer, respectively.
  • the bit lines and capacitors of DRAM memory cells can be arranged on two sides of the same wafer, so that the circuit arrangement of word lines, bit lines and capacitors can be simplified, and the cost of semiconductor devices can be reduced. Manufacturing process difficulty.
  • the disclosed apparatus and method may be implemented in a non-target manner.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the various components shown or discussed are coupled to each other, or directly coupled.
  • the unit described above as a separate component may or may not be physically separated, and the component displayed as a unit may or may not be a physical unit, that is, it may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • Embodiments of the present application provide a transistor and a method for fabricating the same, a semiconductor device and a method for fabricating the same.
  • the method for fabricating the transistor includes: providing a wafer, the wafer has a plurality of transistor formation regions, and each transistor is formed The area has a transistor column, and each transistor column has an exposed gate formation surface; a gate oxide layer and a gate are sequentially formed on the gate formation surface of each transistor column; The first end forms a source electrode; the second end of the transistor column forms a drain electrode, wherein the first end and the second end are opposite ends of the transistor column in the first direction respectively , the first direction is the thickness direction of the wafer; the transistor column between the source electrode and the drain electrode constitutes a channel region of the transistor.

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Abstract

本申请实施例提供一种晶体管及其制造方法、半导体器件及其制造方法，所述晶体管的制造方法包括：提供一晶圆，所述晶圆具有多个晶体管形成区域，每一所述晶体管形成区域具有一晶体管柱，每一所述晶体管柱具有一裸露的栅极形成面；在每一所述晶体管柱的栅极形成面上依次形成栅极氧化层和栅极；在所述晶体管柱的第一端，形成源极；在所述晶体管柱的第二端，形成漏极，其中，所述第一端和所述第二端分别为所述晶体管柱在第一方向上相对的两端，所述第一方向为所述晶圆的厚度方向；所述源极与所述漏极之间的晶体管柱构成所述晶体管的沟道区。

Description

晶体管及其制造方法、半导体器件及其制造方法
相关申请的交叉引用
本申请基于“申请号为202110422036.9、申请日为2021年04月20日、发明名称为‘柱形晶体管及其制造方法、半导体器件及其制造方法’”和“申请号为202110421932.3、申请日为2021年04月20日、发明名称为‘L型晶体管及其制造方法、半导体器件及其制造方法’”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体技术领域，涉及但不限于一种晶体管及其制造方法、半导体器件及其制造方法。
背景技术
晶体管在电子设备中被广泛地用作开关器件或驱动装置。例如，晶体管可以用于动态随机存储器(Dynamic Random Access Memory，DRAM)中，用于控制每一存储单元中的电容。
相关技术中，晶体管主要包括平面晶体管和填埋式沟道晶体管，然而不论是平面晶体管还是填埋式沟道晶体管，其源极(Source，S)和漏极(Drain，D)均位于栅极(Gate，G)的水平两侧，这种结构下源极和漏极分别占用了不同的位置，使得晶体管的面积较大。另外，在存储器件中，晶体管的源极和漏极形成后会分别连接不同的结构，当源极和漏极位于栅极的水平两侧时，容易导致存储器内部的电路布线复杂，制造工艺难度大。
发明内容
本申请实施例提供一种晶体管的制造方法，包括：
提供一晶圆，所述晶圆具有多个晶体管形成区域，每一所述晶体管形成区域具有一晶体管柱，每一所述晶体管柱具有一裸露的栅极形成面；
在每一所述晶体管柱的栅极形成面上依次形成栅极氧化层和栅极；
在所述晶体管柱的第一端，形成源极；
在所述晶体管柱的第二端，形成漏极，其中，所述第一端和所述第二端分别为所述晶体管柱在第一方向上相对的两端，所述第一方向为所述晶圆的厚度方向；所述源极和所述漏极之间的晶体管柱构成所述晶体管的沟道区。
在一些实施例中，所述栅极形成面包括一侧壁或一L型面；
所述在每一所述晶体管柱的栅极形成面上依次形成栅极氧化层和栅极，包括：
在每一所述晶体管柱的所述侧壁上依次形成所述栅极氧化层和所述栅极；或者，
在每一所述晶体管柱的所述L型面上依次形成所述栅极氧化层和所述栅极。
在一些实施例中，所述晶体管形成区域还具有包裹所述晶体管柱其它侧壁的绝缘层；所述晶体管形成区域通过以下方式形成：
沿所述第一方向，以所述晶圆的第一面为刻蚀起点，对所述晶圆进行部分刻蚀，形成由多个硅柱组成的网格状刻蚀沟槽，其中，每一所述硅柱具有第一预设厚度，所述第一预设厚度小于所述晶圆的初始厚度；所述晶圆的第一面为所述晶圆沿所述第一方向的任意一个面；
在所述网格状刻蚀沟槽中沉积绝缘材料，形成包围每一所述硅柱的绝缘层；
刻蚀所述硅柱和所述绝缘层，形成具有一裸露的所述侧壁或一裸露的所述L型面的所述晶体管柱，得到所述晶体管形成区域。
在一些实施例中，刻蚀所述硅柱和所述绝缘层，形成具有一裸露的所述侧壁的所述晶体管柱，包括：
以所述硅柱的边缘位置为刻蚀起点，沿所述第一方向，对所述硅柱和所述绝缘层进行部分刻蚀处理，去除在所述第二方向具有预设尺寸，且在所述第一方向上具有所述第一预设厚度的硅柱和绝缘层，形成具有一裸露的所述侧壁的所述晶体管柱，并形成一刻蚀凹槽；其中，所述预设尺寸小于所述硅柱在所述第二方向上的初始尺寸；所述第二方向垂直于所述第一方向。
在一些实施例中，在形成所述栅极氧化层和所述栅极之前，所述方法还包括：
在所述刻蚀凹槽的底部沉积形成第一隔离层；
对应地，所述在每一所述晶体管柱的侧壁上依次形成栅极氧化层和栅极，包括：
通过原位氧化的方式，在所述晶体管柱的所述侧壁上形成初始栅极氧化层；
在所述刻蚀凹槽中沉积多晶硅材料，形成多晶硅层；
在所述第一方向上，对所述初始栅极氧化层和所述多晶硅层同时进行刻蚀处理，去除所述第一方向上的部分厚度的所述初始栅极氧化层和所述多晶硅层，形成所述栅极氧化层和所述栅极。
在一些实施例中，在形成所述栅极氧化层和所述栅极之后，所述方法还包括：
在所述刻蚀凹槽中沉积形成第二隔离层，其中，所述第二隔离层位于所述晶体管柱在所述第二方向上的投影区域内，且所述第二隔离层在第三方向上的尺寸与所述晶体管柱在所述第三方向上的尺寸相等。
在一些实施例中，在形成所述漏极之前，所述方法还包括：
从所述晶圆的第二面开始，对所述晶圆进行减薄处理，直至暴露出所述第一隔离层和所述晶体管柱的第二端为止；其中，所述晶圆的第二面是与所述晶圆的第一面相对的一面。
在一些实施例中，刻蚀所述硅柱和所述绝缘层，形成具有一裸露的所述L型面的所述晶体管柱，包括：
以所述硅柱的边缘位置为刻蚀起点，沿所述第一方向，对所述硅柱和所述绝缘层进行部分刻蚀处理，去除在所述第二方向上具有预设尺寸，且在所述第一方向上具有第二预设厚度的硅柱和绝缘层，形成具有所述L型面的所述晶体管柱，并形成一刻蚀凹槽；其中，所述第二预设厚度小于所述第一预设厚度，所述预设尺寸小于所述硅柱在所述第二方向上的初始尺寸；所述第二方向垂直于所述第一方向。
在一些实施例中，所述L型面包括一竖直面和与所述竖直面垂直的一水平面；
所述在每一所述晶体管柱的所述L型面上依次形成所述栅极氧化层和所述栅极，包括：
通过原位氧化的方式，在所述竖直面和所述水平面上分别形成初始栅极氧化层；
在具有所述初始栅极氧化层的所述刻蚀凹槽中沉积多晶硅材料，形成多晶硅层；
在所述第一方向上，对所述初始栅极氧化层和所述多晶硅层同时进行刻蚀处理，去除所述第一方向上的部分厚度的所述初始栅极氧化层和所述多晶硅层，形成所述栅极氧化层和所述栅极。
在一些实施例中，在形成所述栅极氧化层和所述栅极之后，所述方法还包括：
在所述刻蚀凹槽中沉积形成隔离层，其中，所述隔离层位于所述晶体管柱在所述第二方向上的投影区域内，且所述隔离层在第三方向上的尺寸与所述晶体管柱在所述第三方向上的尺寸相等。
在一些实施例中，在形成所述漏极之前，所述方法还包括：
从所述晶圆的第二面开始，对所述晶圆进行减薄处理，以去除第三预设厚度的所述晶圆，暴露出所述晶体管柱的第二端；其中，所述第三预设厚度小于所述初始厚度与所述第二预设厚度之间的差值；其中，所述晶圆的第二面是与所述晶圆的第一面相对的一面。
在一些实施例中，所述在所述晶体管柱的第二端，形成漏极，包括：
对所述晶体管柱的第二端进行预设深度的离子注入，形成所述漏极，其中，所述预设深度小于或等于所述初始厚度与所述第二预设厚度之间的差值。
在一些实施例中，所述源极与所述漏极的形状相同或不同；
所述源极和所述漏极的形状包括以下任意一种：方形、半圆形、三角形或任意多边形。
本申请实施例提供一种晶体管，所述晶体管包括：
沟道区；
源极，位于所述沟道区的第一端；
漏极，位于所述沟道区的第二端，其中，所述第一端和所述第二端分别为所述沟道区在第一方向上相对的两端，所述第一方向为形成所述沟道区的晶圆的厚度方向；
栅极，位于所述沟道区的任一侧，且与所述沟道区对应；
栅极氧化层，位于所述沟道区和所述栅极之间。
在一些实施例中，所述源极、所述沟道区和所述漏极形成L型结构或柱形结构。
本申请实施例提供一种半导体器件的形成方法，所述方法包括：
形成至少一个存储器单元，其中，每一所述存储器单元至少包括：晶体管；所述晶体管包括：栅极、源极和漏极；所述晶体管通过上述晶体管的制造方法制造；
形成字线，所述字线与所述晶体管的栅极连接，所述字线用于提供字线电压，并通过所述字线电压控制所述晶体管导通或截止；
形成位线，所述位线与所述晶体管的源极或者漏极连接，所述位线用于在所述晶体管导通时，对所述存储器单元执行读取或写入操作。
本申请实施例还提供一种半导体器件，包括：至少一个存储器单元、字线和位线，每一所述存储器单元至少包括：上述晶体管；所述晶体管至少包括：栅极、源极和漏极；
所述字线与所述晶体管的栅极连接，所述字线用于提供字线电压，并通过所述字线电压控制所述晶体管导通或截止；
所述位线与所述晶体管的源极或者漏极连接，所述位线用于在所述晶体管导通时，对所述存储器单元执行读取或写入操作。
在一些实施例中，所述存储器单元还包括：存储电容；
所述存储电容的一端与所述晶体管的漏极或者源极连接，所述存储电容的另一端接地，所述存储电容用于存储写入所述存储器单元的数据。
在一些实施例中，所述存储器单元还包括：可调电阻；
所述可调电阻连接于所述位线和所述晶体管的源极之间，或者，所述可调电阻连接于所述位线和所述晶体管的漏极之间，所述可调电阻用于通过所述位线提供的位线电压调节所述存储器单元中所存储的数据的状态。
在一些实施例中，当所述半导体器件包括多个所述存储器单元时，多个所述存储器单元之间并联或者串联。
本申请实施例提供的晶体管及其制造方法、半导体器件及其制造方法，由于形成的晶体管的源极和漏极分别位于沟道区在第一方向上的第一端和第二端，而第一方向为形成沟道区的晶圆的厚度方向，如此，极大地缩小了晶体管的面积。且本申请实施例提供的晶体管可以用于形成存储器，由于晶体管的漏极和源极位于晶圆的不同面，如此，可以将存储器中源极和漏极所连接的不同结构分别设计在晶圆的两个面中，即分别设计在晶圆相对的两个面中，从而简化了存储器内部的电路布局，降低了存储器制造的工艺难度。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1A为相关技术中平面晶体管的结构示意图；
图1B为相关技术中填埋式沟道晶体管的结构示意图；
图1C为相关技术中采用平面晶体管形成的DRAM存储单元的结构示意图；
图1D为相关技术中采用填埋式沟道晶体管形成的DRAM存储单元的结构示意图；
图2A和2B为本申请实施例提供的晶体管的一种可选的结构示意图；
图3A为本申请实施例提供的柱形晶体管的制造方法的一个可选的流程示意图；
图3B～3L为本申请实施例提供的柱形晶体管的形成过程的结构示意图；
图3M和3N为本申请实施例提供的柱形晶体管一种可选的结构示意图；
图4A为本申请实施例提供的L型晶体管的制造方法的一个可选的流程示意图；
图4B～4J为本申请实施例提供的L型晶体管的形成过程的结构示意图；
图4K和4L为本申请实施例提供的L型晶体管一种可选的结构示意图；
图5A和5B为本申请实施例提供的半导体器件的一种可选的结构示意图；
图5C和5D为本申请实施例提供的DRAM存储单元的一种可选的结构示意图；
图5E和5F为本申请实施例提供的PCM存储单元的一种可选的结构示意图；
图6为本申请实施例提供的半导体器件的形成方法的一种可选的结构示意。
具体实施方式
下面将结合本申请实施例中的附图，对发明的技术方案做进一步详细描述。以下实施例用于说明本申请，但不用来限制本申请的范围。
在后续的描述中，使用用于表示元件的诸如“模块”或“单元”的后缀仅为了有利于本申请的说明，其本身没有特定的意义。因此，“模块”或“单元”可以混合地使用。
相关技术中，主流存储器的晶体管包括平面晶体管(Planar)和填埋式沟道晶体管(Buried Channel Array Transistor，BCAT)，然而不论是平面晶体管还是填埋式沟道晶体管，其结构上源极和漏极均位于栅极的水平两侧。如图1A和1B所示，相关技术中的晶体管的源极S和漏极D分别位于栅极G的水平两侧。这种结构下，源极和漏极分别占用了不同的位置，使得不论是平面晶体管还是填埋式沟道晶体管的面积都较大。
另外，由于晶体管可以制备在硅衬底上，因此，晶体管可以被用在各种存储器中，例如，DRAM。通常，DRAM是由多个存储单元构成，每一个存储单元主要是由一个晶体管与一个由晶体管所操控的电容构成，即DRAM是1个晶体管1个电容C(1T1C)的存储单元。如图1C和1D所示，DRAM存储单元中的晶体管的源极(或漏极)101与位线102连接，漏极(或源极)103与电容104连接。对于采用BCAT形成的芯片，通常使用板上芯片封装(Chips on Board，COB)的方式进行封装，以形成存储器。由于平面晶体管和填埋式沟道晶体管的源极和漏极分别位于栅极水平的两侧，因此，DRAM存储单元中的位线和电容也会位于栅极的同一侧，且后续工艺中还需要实现位线、晶体管和电容之间的连接，字线(Word line，WL)和晶体管之间连接等，从而导致DRAM存储器的存储阵列区中，电路布线较复杂，制造工艺难度较大。
基于相关技术中存在的上述问题，本申请实施例提供一种晶体管及其制造方法、半导体器件及其制造方法，能够提供一种具有较小面积的晶体管结构，且通过本申请实施例提供的晶体管结构，可以简化存储器内部的电路布局，降低存储器制造的工艺难度。
图2A和2B为本申请实施例提供的晶体管的一种可选的结构示意图，如图2A和2B所示，所述晶体管20包括：沟道区201、源极202、漏极203、栅极204和栅极氧化层205。
其中，所述沟道区201具有竖直结构，源极202位于沟道区201的第一端；漏极203位于沟道区201的第二端，所述源极、所述沟道区和所述漏极形成柱形结构或者L型结构。其中，第一端和第二端分别为沟道区在第一方向上相对的两端，这里，定义形成所述沟道区的晶圆的厚度方向为第一方向(如图2A和2B中的Z轴方向)，定义垂直于第一方向的任意一个方向为第二方向(如图2B中的X轴方向)。本申请实施例中，源极202和漏极203的位置可以互换。
在一些实施例中，所述第一端和所述第二端在第二方向上的尺寸相同或不同。
栅极204位于沟道区201的任一侧，且与沟道区201对应，栅极氧化层205位于沟道区201和栅极204之间。
本申请实施例中，源极和漏极分别位于形成沟道区的晶圆厚度方向上的相对的两端，即本申请实施例提供的晶体管的源极和漏极位于晶圆的相对的两个面中，如此，极大地缩小了晶体管的面积。
本申请实施例提供的晶体管的制造方法包括以下步骤：
步骤一：提供一晶圆，所述晶圆具有多个晶体管形成区域，每一所述晶体管形成区域具有一晶体管柱，每一所述晶体管柱具有一裸露的栅极形成面。
其中，所述栅极形成面为形成所述栅极的一个表面。
步骤二：在每一所述晶体管柱的栅极形成面上依次形成栅极氧化层和栅极。
步骤三：在所述晶体管柱的第一端，形成源极。
步骤四：在所述晶体管柱的第二端，形成漏极，其中，所述第一端和所述第二端分别为所述晶体管柱在第一方向上相对的两端，所述第一方向为所述晶圆的厚度方向；所述源极与所述漏极之间的晶体管柱构成所述晶体管的沟道区。
在一些实施例中，所述栅极形成面包括一侧壁或一L型面；对应地，所述在每一所述晶体管柱的栅极形成面上依次形成栅极氧化层和栅极，包括：在每一所述晶体管柱的所述侧壁上依次形成所述栅极氧化层和所述栅极；或者，在每一所述晶体管柱的所述L型面上依次形成所述栅极氧化层和所述栅极。
本申请实施例所提供的晶体管包括柱形晶体管，柱形晶体管可以通过下述实施例提供的晶体 管的制造方法形成。
图3A为本申请实施例提供的柱形晶体管的制造方法的一个可选的流程示意图，如图3A所示，所述柱形晶体管的制造方法包括以下步骤：
步骤S301、提供一晶圆，所述晶圆具有多个晶体管形成区域，每一所述晶体管形成区域具有一晶体管柱，每一所述晶体管柱具有一裸露的侧壁。
步骤S302、在每一所述晶体管柱的侧壁上依次形成栅极氧化层和栅极。
步骤S303、在所述晶体管柱的第一端，形成源极。
步骤S304、在所述晶体管柱的第二端，形成漏极。
其中，所述第一端和所述第二端分别为所述晶体管柱在第一方向上相对的两端，所述第一方向为所述晶圆的厚度方向；所述源极和所述漏极之间的晶体管柱构成所述晶体管的沟道区。
接下来请参考图3B至图3L，对本申请实施例提供的晶体管的制造方法进行进一步地详细说明。
本申请实施例中，所述晶体管形成区域为晶圆上用于形成晶体管的区域，每一所述晶体管形成区域具有一晶体管柱，每一晶体管柱具有一裸露的侧壁。所述晶体管形成区域还具有包裹所述晶体管柱其它侧壁的绝缘层。
首先，请参考图3B至图3E，执行步骤S301，提供一晶圆，所述晶圆具有多个晶体管形成区域，每一所述晶体管形成区域具有一晶体管柱，每一所述晶体管柱具有一裸露的侧壁。在一些实施例中，所述晶体管形成区域通过以下步骤形成：
步骤S3011、沿所述第一方向，以所述晶圆的第一面为刻蚀起点，对所述晶圆进行部分刻蚀，形成由多个硅柱组成的网格状刻蚀沟槽。
其中，每一所述硅柱具有第一预设厚度，所述第一预设厚度小于所述晶圆的初始厚度；所述晶圆的第一面为所述晶圆沿所述第一方向的任意一个面。
这里，定义所述晶圆的厚度方向为第一方向。在晶圆垂直于所述第一方向的顶表面或底表面中定义两彼此相交的第二方向和第三方向，基于所述第二方向和所述第三方向可以确定出晶圆垂直于所述第一方向的顶表面或者底表面。例如，所述第二方向和所述第三方向相互垂直，如此，所述第一方向、所述第二方向和所述第三方向两两相互垂直。这里，可以定义所述第一方向为Z轴方向，所述第二方向为X轴方向，所述第三方向为Y轴方向。
图3B为本申请实施例提供的网格状刻蚀沟槽沿第一方向的剖视图，图3C为本申请实施例提供的网格状刻蚀沟槽的俯视图，结合图3B和3C，可以看出，沿Z轴方向，以所述晶圆的第一面30-1为刻蚀起点，对晶圆30进行部分刻蚀，形成由多个硅柱301组成的网格状刻蚀沟槽31，其中，每一硅柱301位于网格中的交点处，任意两个相邻硅柱之间存在相等的间隙。本申请实施例中，每一所述硅柱301在Z轴方向具有第一预设厚度A，所述第一预设厚度小于所述晶圆的初始厚度B；所述晶圆的第一面30-1为所述晶圆沿Z轴方向的任意一个面。所述晶圆还包括与所述第一面30-1相对的第二面30-2。
这里，可以采用干法刻蚀工艺对晶圆进行刻蚀，例如，等离子体刻蚀工艺或者反应离子刻蚀工艺。值得注意的是，本申请实施例中，对所述晶圆的刻蚀是在所述晶圆的厚度方向上进行的部分刻蚀，即所述刻蚀过程不会将晶圆刻穿。
步骤S3012、在所述网格状刻蚀沟槽中沉积绝缘材料，形成包围每一所述硅柱的绝缘层。
本申请实施例中，所述绝缘材料可以是二氧化硅材料或其他绝缘材料。图3D为本申请实施例提供的在网格状刻蚀沟槽中形成绝缘层的俯视图，如图3D所示，在网格状刻蚀沟槽31中沉积绝缘材料SiO 2，每一硅柱301的周围都填充有绝缘材料SiO 2，形成了绝缘层32。
需要说明的是，在实际沉积绝缘材料的过程中，绝缘材料SiO 2会覆盖在硅柱301的表面，通常在沉积完成后，采用化学机械研磨(Chemical Mechanical Polishing，CMP)工艺，打磨去除多余的绝缘材料SiO 2，以暴露出硅柱301的表面。
步骤S3013、刻蚀所述硅柱和所述绝缘层，形成具有一裸露的所述侧壁的所述晶体管柱，得到所述晶体管形成区域。
在一些实施例中，所述刻蚀所述硅柱和所述绝缘层，形成具有一裸露的所述侧壁的所述晶体管柱，包括：以所述硅柱的边缘位置为刻蚀起点，沿第一方向，对所述硅柱和所述绝缘层进行部分刻蚀处理，去除在所述第二方向具有预设尺寸，且在所述第一方向上具有所述第一预设厚度的硅柱和绝缘层，形成具有一裸露的所述侧壁的所述晶体管柱，并形成一刻蚀凹槽。
图3E为本申请实施例提供的晶体管柱的俯视图，如图3E所示，以所述硅柱的边缘位置为刻 蚀起点，沿X轴方向，对所述硅柱和所述绝缘层进行刻蚀处理，去除在X轴方向具有预设尺寸C、且在Z轴方向具有第一预设厚度A的硅柱和绝缘层，形成晶体管柱302和一刻蚀凹槽303，进而形成了晶体管形成区域30'，其中，所述晶体管柱具有一裸露侧壁302-1。本申请实施例中，所述预设尺寸C小于所述硅柱301在X轴方向上的初始尺寸D。
需要说明的是，一个晶圆上会形成很多个晶体管，因此，一个晶圆中存在多个晶体管形成区域，本申请实施例中，为了便于说明，只是示例性地示出了有限个数的晶体管形成区域。
接下来请参见图3F和图3G，执行步骤S302，在每一所述晶体管柱的侧壁上依次形成栅极氧化层和栅极。
在一些实施例中，在执行步骤S302之前，所述晶体管的制造方法还包括：
步骤S10、在所述刻蚀凹槽的底部沉积形成第一隔离层。
这里，所述第一隔离层的材料包括但不限于以下任意一种：氮化硅、氮氧化硅、碳化硅或者二氧化硅。
下面，以晶圆上的一个晶体管柱为例，说明后续的形成过程。图3F为本申请实施例提供的形成第一隔离层的结构示意图，如图3F所示，在刻蚀凹槽(图3F中未示出)的底部沉积形成了第一隔离层304。这里，可以通过任意一种合适的沉积工艺沉积形成所述第一隔离层。
在一些实施例中，在形成第一隔离层之后，执行上述形成栅极氧化层和栅极的过程，所述在每一所述晶体管柱的侧壁上依次形成栅极氧化层和栅极，包括以下步骤：
步骤S3021、通过原位氧化的方式，在所述晶体管柱的所述侧壁上形成初始栅极氧化层。
图3G为本申请实施例提供的形成初始栅极氧化层的结构示意图，如图3G和图3F所示，这里，可以通过加热或者加压的方式，将所述晶体管柱301暴露的部分侧壁302-1'进行原位氧化，形成初始栅极氧化层305'。
步骤S3022、在所述刻蚀凹槽中沉积多晶硅材料，形成多晶硅层。
这里，可以通过化学气相沉积(Chemical Vapor Deposition，PVD)、物理气相沉积(Physical Vapour Deposition，PVD)或者原子层沉积(Atomic Layer Deposition，ALD)的工艺在沉积了第一隔离层304后的刻蚀凹槽中沉积多晶硅材料形成多晶硅层。
步骤S3023、在所述第一方向上，对所述初始栅极氧化层和所述多晶硅层同时进行刻蚀处理，去除所述第一方向上的部分厚度的所述初始栅极氧化层和所述多晶硅层，形成所述栅极氧化层和所述栅极。
图3H为本申请实施例提供的形成栅极氧化层和栅极的结构示意图，如图3H所示，沿Z轴方向，对上述形成的初始栅极氧化层和多晶硅层同时进行部分刻蚀处理，得到栅极氧化层305和栅极306。本申请实施例中，可以采用干法刻蚀技术，刻蚀所述初始栅极氧化层和所述多晶硅层。
在一些实施例中，在形成栅极氧化层和栅极之后，所述晶体管的制造方法还包括：
步骤S11、在所述刻蚀凹槽中沉积形成第二隔离层，其中，所述第二隔离层位于所述晶体管柱在所述第二方向上的投影区域内，且所述第二隔离层在第三方向上的尺寸与所述晶体管柱在所述第三方向上的尺寸相等。
本申请实施例中，所述第三方向与所述第二方向和所述第一方向两两相互垂直。需要说明的是，在其他实施例中，所述第三方向也可以不与所述第二方向垂直，所述第三方向与所述第二方向之间的夹角可以为任意角度。
这里，所述第二隔离层的材料包括但不限于以下任意一种：氮化硅、氮氧化硅、碳化硅或者二氧化硅；所述第二隔离层与所述第一隔离层的材料相同或不同。
图3I为本申请实施例提供的形成第二隔离层的结构示意图，如图3I所示，所述第二隔离层307位于晶体管柱302在X轴方向上的投影区域内，且第二隔离层在Y轴方向上的尺寸与晶体管柱在Y轴方向上的尺寸相等。
接下来参考图3J，执行步骤S303，在所述晶体管柱的第一端，形成源极。
这里，所述晶体管柱的第一端为晶体管柱在Z轴方向上的一端。图3J为本申请实施例提供的形成源极的结构示意图，如图3J所示，通过对晶体管柱的第一端进行离子注入，从而形成源极308。
在一些实施例中，所述源极的形状包括以下任意一种：方形、半圆形、三角形或任意多边形。
在一些实施例中，在执行步骤S304之前，所述晶体管的制造方法还包括：
步骤S12、从所述晶圆的第二面开始，对所述晶圆进行减薄处理，直至暴露出所述第一隔离层和所述晶体管柱第二端为止。
这里，请继续参见图3J，所述晶圆的第二面30-2是与所述晶圆的第一面相对的一面。本申请实施例中，在对晶圆的第二面进行减薄处理之前，需要先将晶圆的第一面固定在一支撑结构上，防止在对晶圆的第二面30-2进行减薄时，破坏已经形成的晶体管的结构。
所述第一端和所述第二端分别为所述晶体管柱在第一方向上相对的两端。图3K为本申请实施例提供的对晶圆的第二面进行减薄后的晶体管的结构示意图，如图3K所示，对晶圆的第二面进行减薄处理，暴露出了第一隔离层304和所述晶体管柱的第二端309'。
接下来，参考图3L，执行步骤S304，在所述晶体管柱的第二端，形成漏极。
图3L为本申请实施例提供的形成漏极的结构示意图，如图3L所示，通过对晶体管柱的第二端309'进行离子注入，从而形成漏极309。
在一些实施例中，所述漏极的形状包括以下任意一种：方形、半圆形、三角形或任意多边形。
图3M和3N为本申请实施例提供的柱形晶体管一种可选的结构示意图，如3M所示，所述柱形晶体管的源极和漏极的横截面形状均为半圆形，如图3N所示，所述柱形晶体管的源极和漏极的横截面形状均为三角形。
本申请实施例中，源极和漏极的位置可以互换，且本申请实施例形成的柱形晶体管源极和漏极的形状可以相同，也可以不同。
请继续参见图3L，本申请实施例中，在形成源极和漏极后，源极与漏极之间的晶体管柱构成所述晶体管的沟道区310。
通过本申请实施例提供的柱形晶体管制造方法所形成的柱形晶体管，由于源极和漏极分别位于沟道区在第一方向上的第一端和第二端，而第一方向为形成沟道区的晶圆的厚度方向，如此，极大地缩小了晶体管的面积。
在一些实施例中，当本申请实施例提供的柱形晶体管应用于存储器中时，由于柱形晶体管的漏极和源极位于晶圆的不同面，如此，可以将存储器中源极和漏极所连接的不同结构分别设计在晶圆的两个面中，从而简化了存储器内部的电路布局，降低了存储器制造的工艺难度。
本申请实施例所提供的晶体管还包括L型晶体管，L型晶体管可以通过下述实施例提供的晶体管的制造方法形成。
图4A为本申请实施例提供的L型晶体管的制造方法的一个可选的流程示意图，如图4A所示，所述L型晶体管的制造方法包括以下步骤：
步骤S401、提供一晶圆，所述晶圆具有多个晶体管形成区域，每一所述晶体管形成区域具有一晶体管柱，每一所述晶体管柱具有一裸露的L型面。
步骤S402、在每一所述晶体管柱的所述L型面上依次形成栅极氧化层和栅极。
步骤S403、在所述晶体管柱的第一端，形成源极。
步骤S404、在所述晶体管柱的第二端，形成漏极。
其中，所述第一端和所述第二端分别为所述晶体管柱在第一方向上相对的两端，所述第一端和所述第二端在第二方向上的尺寸不同；所述第一方向为所述晶圆的厚度方向，所述第二方向垂直于所述第一方向；所述源极与所述漏极之间的晶体管柱构成所述晶体管的沟道区。
接下来请参考图4B至图4D，对本申请实施例提供的L型晶体管的制造方法进行进一步地详细说明。
本申请实施例中，所述晶体管形成区域为晶圆上用于形成晶体管的区域，每一所述晶体管形成区域具有一晶体管柱，每一晶体管柱具有一裸露的L型面。所述晶体管形成区域还具有包裹所述晶体管柱侧壁的绝缘层。
本申请实施例中，所述晶体管形成区域的形成过程与上述实施例中的晶体管区域的形成过程相同，这里，不再赘述。
图4B为本申请实施例提供的晶体管柱沿第一方向的剖视图，图4C为本申请实施例提供的晶体管柱的俯视图，结合图4B和图4C所示，形成所述硅柱的晶圆具有相对的第一面40-1和第二面40-2，所述第一面40-1为所述晶圆沿Z轴方向的任意一个面。以所述硅柱的边缘位置为刻蚀起点，沿X轴方向，对所述硅柱和所述绝缘层进行刻蚀处理，去除在X轴方向具有预设尺寸C、且在Z轴方向具有第二预设厚度E的硅柱和绝缘层，形成晶体管柱402和一刻蚀凹槽403，进而在晶圆40中形成了晶体管形成区域40'。本申请实施例中，所述预设尺寸C小于所述硅柱在所述X轴方向上的初始尺寸D，且所述第二预设厚度E小于所述第一预设厚度A，所述第一预设厚度A小于晶圆在Z轴方向上的初始厚度B。
需要说明的是，为了便于理解，图4B中未示出填充在每一硅柱周围的绝缘材料。
图4D为本申请实施例提供的晶体管柱的一个立体图，从图中可以看出，所述晶体管柱402具有一L型面。所述L型面包括一竖直面402-1'和与所述竖直面垂直的一水平面402-2'。
需要说明的是，一个晶圆上会形成很多个晶体管，因此，一个晶圆中存在多个晶体管形成区域，本申请实施例中，为了便于说明，只是示例性地示出了有限个数的晶体管形成区域。
接下来请参见图4E和4F，执行步骤S402，在每一所述晶体管柱的侧壁上依次形成栅极氧化层和栅极。
在一些实施例中，所述在每一所述晶体管柱的所述L型面上依次形成栅极氧化层和栅极，包括以下步骤：
步骤S4021、通过原位氧化的方式，在所述竖直面和所述水平面上分别形成初始栅极氧化层。
如图4E所示，为本申请实施例提供的形成初始栅极氧化层的结构示意图，这里，可以通过加热或者加压的方式，对所述水平面402-2'和所述竖直面402-1'进行原位氧化，形成初始栅极氧化层404'。
步骤S4022、在具有所述初始栅极氧化层的所述刻蚀凹槽中沉积多晶硅材料，形成多晶硅层。
步骤S4023、在所述第一方向上，对所述初始栅极氧化层和所述多晶硅层同时进行刻蚀处理，去除所述第一方向上的部分厚度的所述初始栅极氧化层和所述多晶硅层，形成所述栅极氧化层和所述栅极。
图4F为本申请实施例提供的形成栅极氧化层和栅极的结构示意图，如图4F所示，沿Z轴方向，对上述形成的初始栅极氧化层和多晶硅层同时进行部分刻蚀处理，得到栅极氧化层404和栅极405。本申请实施例中，可以采用干法刻蚀技术，刻蚀所述初始栅极氧化层和所述多晶硅层。
在一些实施例中，在形成栅极氧化层和栅极之后，所述L型晶体管的制造方法还包括：
步骤S20、在所述刻蚀凹槽中沉积形成隔离层，其中，所述隔离层位于所述晶体管柱在所述第二方向上的投影区域内，且所述隔离层在第三方向上的尺寸与所述晶体管柱在所述第三方向上的尺寸相等。
本申请实施例中，所述第三方向与所述第二方向和所述第一方向两两相互垂直。需要说明的是，在其他实施例中，所述第三方向也可以不与所述第二方向垂直，所述第三方向与所述第二方向之间的夹角可以为任意角度。
这里，所述隔离层的材料包括但不限于以下任意一种：氮化硅、氮氧化硅、碳化硅或者二氧化硅。
图4G为本申请实施例提供的形成隔离层的结构示意图，如图4G所示，所述隔离层406位于晶体管柱402在X轴方向上的投影区域内，且隔离层在Y轴方向上的尺寸与晶体管柱在Y轴方向上的尺寸相等。
接下来参考图4H，执行步骤S403，在所述晶体管柱的第一端，形成源极。
这里，所述晶体管柱的第一端为晶体管柱在Z轴方向上的一端。图4H为本申请实施例提供的形成源极的结构示意图，如图4H所示，通过对晶体管柱的第一端进行离子注入，从而形成源极407。
在一些实施例中，所述源极的形状包括以下任意一种：方形、半圆形、三角形或任意多边形。
在一些实施例中，在执行步骤S404之前，所述晶体管的制造方法还包括：
步骤S21、从所述晶圆的第二面开始，对所述晶圆进行减薄处理，以去除第三预设厚度的所述晶圆，暴露出所述晶体管柱的第二端。
请继续参见图4H，这里，所述晶圆的第二面40-2是与所述晶圆的第一面相对的一面。所述第三预设厚度小于所述晶圆的初始厚度与所述第二预设厚度之间的差值。即本申请实施例中，在对第一晶圆的第二面的硅进行减薄时，要保证刻蚀凹槽底部要有一定厚度的硅存留。
在其它实施例中，在对晶圆的第二面进行减薄处理之前，需要先将晶圆的第一面固定在一支撑结构上，防止在对晶圆的第二面40-2进行减薄时，破坏已经形成的晶体管的结构。
所述第一端和所述第二端分别为所述晶体管柱在第一方向上相对的两端。图4I为本申请实施例提供的对晶圆的第二面进行减薄后的晶体管的结构示意图，如图4I所示，对晶圆的第二面进行减薄处理，去除了第三预设厚度的所述晶圆，暴露出所述晶体管柱的第二端408'。
接下来，参考图4J，执行步骤S404，在所述晶体管柱的第二端，形成漏极。
在一些实施例中，所述在所述晶体管柱的第二端，形成漏极，包括：对所述晶体管柱的第二端进行预设深度的离子注入，形成所述漏极，其中，所述预设深度小于或等于所述初始厚度与所述第二预设厚度之间的差值。
这里，对漏极进行离子注入的深度可以是预先设置的预设深度，预设深度的最大值可以等于所述晶圆的初始厚度与所述第二预设厚度之间的差值。
本申请实施例中，当减薄去除第三预设厚度的晶圆，所述第三预设厚度为初始厚度与第一预设厚度之间的差值时，在所述晶体管柱的第二端形成漏极时的最大注入深度为第一预设厚度与第二预设厚度之间的差值。图4J为本申请实施例提供的形成漏极的一种可选的结构示意图，如图4J所示，通过对晶体管柱的第二端408'进行预设深度离子注入，从而形成漏极408。这里，所述预设深度等于所述第一预设厚度与第二预设厚度之间的差值，同时，在源极407和漏极408之间形成了竖直的沟道区409。
在一些实施例中，所述漏极的形状包括以下任意一种：方形、半圆形、三角形或任意多边形。
本申请实施例中，从整体上来看，最终形成的晶体管为L型晶体管，也就是说，晶体管的源极、漏极和沟道区共同形成L型结构。
图4K和4L为本申请实施例提供的L型晶体管一种可选的结构示意图，如4K所示，所述L型晶体管的源极和漏极的横截面形状均为半圆形，如图4L所示，所述L型晶体管的源极和漏极的横截面形状均为三角形。
本申请实施例中，源极和漏极的位置可以互换，即可以先形成源极或者先形成漏极，且本申请实施例形成的L型晶体管源极和漏极的形状可以相同，也可以不同。
通过本申请实施例提供的L型晶体管制造方法所形成的L型晶体管，由于源极和漏极分别位于沟道区在第一方向上的第一端和第二端，而第一方向为形成沟道区的晶圆的厚度方向，如此，极大地缩小了晶体管的面积。
在一些实施例中，当本申请实施例提供的L型晶体管应用于存储器中时，由于L型晶体管的漏极和源极位于晶圆的不同面，如此，可以将存储器中源极和漏极所连接的不同结构分别设计在晶圆的两个面中，从而简化了存储器内部的电路布局，降低了存储器制造的工艺难度。
本申请实施例提供一种半导体器件，图5A和5B为本申请实施例提供的半导体器件的一种可选的结构示意图，如图5A和5B所示，所述半导体器件50包括：至少一个存储器单元、字线502和位线503。
其中，每一所述存储器单元包括至少一个晶体管，例如柱形晶体管501a或L型晶体管501b，所述柱形晶体管501a或所述L型晶体管501b至少包括栅极G、源极S和漏极D。
所述柱形晶体管501a或L型晶体管501b还包括沟道区，每一所述柱形晶体管的源极位于沟道区的第一端；每一所述柱形晶体管的漏极位于沟道区的第二端；其中，所述第一端和所述第二端分别为所述沟道区在第一方向上相对的两端，所述第一方向为形成所述沟道区的晶圆的厚度方向。
本申请实施例中的柱形晶体管501a或L型晶体管501b具有竖直沟道，且所述柱形晶体管501a的源极和漏极分别位于竖直沟道的两端。
本申请实施例中，所述字线502与所述柱形晶体管501a的栅极G连接，所述字线用于提供字线电压，并通过所述字线电压控制所述柱形晶体管501a导通或截止；或者，所述字线502与所述L型晶体管501b的栅极G连接，所述字线用于提供字线电压，并通过所述字线电压控制所述L型晶体管501b导通或截止。
所述位线503与所述柱形晶体管501a的源极S或者漏极D连接，所述位线用于在所述柱形晶体管导通时，对所述存储器单元执行读取或写入操作；或者，所述位线503与所述L型晶体管501b的源极S或者漏极D连接，所述位线用于在所述柱形晶体管导通时，对所述存储器单元执行读取或写入操作
在一些实施例中，当所述柱形晶体管501a的源极S连接位线503时，所述柱形晶体管的漏极接地；当所述柱形晶体管501a的漏极连接位线503时，所述柱形晶体管的源极接地；或者，当所述L型晶体管501b的源极S连接位线503时，所述L型晶体管的漏极接地；当所述L型晶体管501b的漏极连接位线503时，所述L型晶体管的源极接地。
本申请实施例提供的半导体器件包括各种类型的存储器。例如，NAND闪存(Flash)、Nor Flash、DRAM、静态随机存取存储器(Static Random Access Memory，SRAM)、相变存储器(Phase-Change Memory，PCM)、铁电存储器、磁变存储器或者阻变存储器。
在一些实施例中，当所述半导体器件为DRAM时，所述存储单元还包括：存储电容。
如图5C和5D所示，为本申请实施例提供的DRAM存储单元的一种可选的结构示意图，可以看出，DRAM存储单元50'中，存储电容504的一端与所述柱形晶体管501a的漏极或者源极连 接，或者，所述存储电容504的一端与所述L型晶体管501b的漏极或者源极连接；所述存储电容504的另一端接地，所述存储电容504用于存储写入所述存储器单元的数据。
在一些实施例中，当所述半导体器件为PCM时，所述存储单元还包括：可调电阻。
如图5E和5F所示，为本申请实施例提供的PCM存储单元的一种可选的结构示意图，可以看出，PCM存储单元50”中，可调电阻505连接于所述位线503和所述柱形晶体管501a的源极或漏极之间，或者，所述可调电阻505连接于所述位线503和所述柱形L型晶体管501b的源极或漏极之间，所述可调电阻505用于通过所述位线提供的位线电压调节所述存储器单元中所存储的数据的状态。
在一些实施例中，当所述半导体器件包括多个所述存储器单元时，所述半导体器件为NAND Flash或Nor Flash。当多个所述存储器单元之间并联时，所述半导体器件为Nor Flash；当多个所述存储器单元之间串联时，所述半导体器件为NAND Flash。
本申请实施例中，只是示例性地列举了一些常见的半导体器件，本申请的保护范围不限于此，任何包含本申请实施例提供的柱形晶体管的半导体器件均属于本申请的保护范围。
本申请实施例中，通过将半导体器件的晶体管的结构设计为新型的具有竖直沟道的结构，缩小了存储单元的面积，提高存储单元的存储密度。同时，本申请实施例中的柱形晶体管中源极和漏极位于竖直沟道区的上下两端，如此，在半导体器件的形成过程中，位线或其他结构可以分别设置于沟道区的竖直两面。例如，对于DRAM而言，DRAM存储单元的位线和电容可以分别设置于在同一片晶圆的两个面上，如此，可简化字线、位线和电容的电路排布，降低半导体器件的制造工艺难度。
除此之外，本申请实施例还提供一种半导体器件的形成方法，图6为本申请实施例提供的半导体器件的形成方法的一种可选的结构示意图，如图6所示，所述方法包括以下步骤：
步骤S601、形成至少一个存储器单元，其中，每一所述存储器单元至少包括：晶体管；所述晶体管包括：栅极、源极和漏极。
本申请实施例中，所述晶体管包括柱形晶体管或者L型晶体管。
步骤S602、形成字线，所述字线与所述晶体管的栅极连接，所述字线用于提供字线电压，并通过所述字线电压控制所述晶体管导通或截止。
步骤S603、形成位线，所述位线与所述晶体管的源极或者漏极连接，所述位线用于在所述晶体管导通时，对所述存储器单元执行读取或写入操作。
在一些实施例中，所述存储器单元中的柱形晶体管通过以下步骤形成：
步骤S6011、通过刻蚀工艺将第一晶圆的第一面部分区域的硅去除一定厚度(对应上述实施例中的第一预设厚度)，形成中间为硅柱的网格状的沟槽(对应上述实施例中的网格状刻蚀沟槽)，在沟槽中填充二氧化硅(对应上述实施例中的绝缘层)后经化学机械研磨露出硅柱的表面，最后通过刻蚀的方式将硅柱的部分去除，裸漏出硅柱的侧壁(对应上述实施例中的形成晶体管柱的过程)。
步骤S6012、在沟槽的底部形成氮化硅，以作为底部的隔离(Spacer)结构(对应上述实施例中的形成第一隔离层)。
步骤S6013、在沟槽的侧壁通过原位生长的方式，形成氧化硅以作为栅极氧化层(对应上述实施例中形成初始栅极氧化层)。
步骤S6014、在沟槽内填充多晶硅(对应上述实施例中形成多晶硅层)，并通过刻蚀的方式将顶部的多晶硅去除一定的深度，然后去除顶部裸漏的氧化硅(对应上述实施例中的步骤S3023)。
步骤S6015、在沟槽的顶部形成氮化硅，以作为顶部的隔离结构(对应上述实施例中的形成第二隔离层)。
步骤S6016、通过离子注入在步骤S6011中预留的晶体管区域(对应上述实施例中晶体管柱的第一端)中形成源极端。
步骤S6017、在第一晶圆的第一面通过各种工艺形成后续的相应结构；然后将第一晶圆与第二晶圆键合，最后将第一晶圆的背面的硅进行减薄，直到暴露出底部的隔离结构和第一晶圆的第二面(对应上述实施例中的步骤S12)。
这里，所述后续相应的结构包括：形成位线、形成电阻或者形成电容等结构。所述第二晶圆中设置有各种逻辑电路和传感器等元件，所述第二晶圆与所述第一晶圆键合后共同形成存储器。
在一些实施例中，晶圆键合工艺的实现过程在背面硅减薄工艺之前，第二晶圆在减薄过程中为第一晶圆提供支撑作用，防止第一晶圆在减薄过程中的损坏。
步骤S6018、在第一晶圆的第二面，通过离子注入在步骤S5016中与源极相对的位置(对应上述晶体管柱的第二端)形成漏极。
步骤S6019、最后在第一晶圆的第二面形成后续的相应结构。
这里，所述后续相应的结构包括：形成位线、形成电阻或者形成电容等结构。
在一些实施例中，所述存储器单元中的L型晶体管通过以下步骤形成：
步骤S7011、通过刻蚀工艺将第一晶圆的第一面部分区域的硅去除一定厚度(对应上述实施例中的第一预设厚度)，形成中间为硅柱的网格状的沟槽(对应上述实施例中的网格状刻蚀沟槽)，在沟槽中填充二氧化硅(对应上述实施例中的绝缘层)后经化学机械研磨露出硅柱的表面，最后通过刻蚀的方式将硅柱的部分去除，形成一裸露的L型面(对应上述实施例中的形成晶体管柱的过程)。
步骤S7012、在沟槽的侧壁和底部通过原位生长的方式，形成氧化硅以作为栅极氧化层(对应上述实施例中形成初始栅极氧化层)。
步骤S7013、在沟槽内填充多晶硅(对应上述实施例中形成多晶硅层)，并通过刻蚀的方式将顶部的多晶硅去除一定的深度，然后去除顶部裸漏的氧化硅(对应上述实施例中的步骤S4023)。
步骤S7014、在沟槽的顶部形成氮化硅，以作为顶部的隔离结构(对应上述实施例中的形成隔离层)。
步骤S7015、通过离子注入在步骤S7011中预留的晶体管区域(对应上述实施例中晶体管柱的第一端)中形成源极端。
步骤S7016、在第一晶圆的第一面通过各种工艺形成后续的相应结构；然后将第一晶圆与第二晶圆键合，最后将第一晶圆的背面的硅进行减薄，保证沟槽区域(对应上述实施例中的刻蚀沟槽)要有一定厚度的硅存留，露出第一晶圆的第二面(对应上述实施例中的步骤S21)。
这里，所述后续相应的结构包括：形成位线、形成电阻或者形成电容等结构。所述第二晶圆中设置有各种逻辑电路和传感器等元件，所述第二晶圆与所述第一晶圆键合后共同形成存储器。
在一些实施例中，晶圆键合工艺的实现过程在背面硅减薄工艺之前，第二晶圆在减薄过程中为第一晶圆提供支撑作用，防止第一晶圆在减薄过程中的损坏。
步骤S7017、在第一晶圆的第二面，通过离子注入在步骤S5015中与源极相对的位置(对应上述晶体管柱的第二端)形成漏极。
步骤S7018、最后在第一晶圆的第二面形成后续的相应结构。
这里，所述后续相应的结构包括：形成位线、形成电阻或者形成电容等结构。
通过本申请实施例提供的半导体器件的形成方法，形成的所述柱形晶体管或L型晶体管的水平截面可以是长方形(正方形)，半圆型，三角形以及任意多边形。本申请实施例中半导体器件中，柱形晶体管或L型晶体管的源极和漏极可以互换，源极和漏极可以分别在同一片晶圆的两个面进行加工处理，因此，源极和漏极的图案可以不同。
本申请实施例中，通过在预设字线位置和预设位线位置形成金属线来实现字线和位线。所述金属线包括但不限于钨(W)、钴(Co)、铜(Cu)、铝(Al)、多晶硅、掺杂硅、硅化物或其任何组合。
本申请实施例中，通过将半导体器件的晶体管的结构设计为新型的具有竖直沟道的晶体管结构，缩小了存储单元的面积，提高存储单元的存储密度。同时，本申请实施例中的晶体管中源极和漏极位于竖直沟道区的上下两端，如此，在半导体器件的形成过程中，结合晶圆键合和背面硅减薄技术，可以将位线或其他结构可以分别设置于晶圆的两个相对的面中。例如，对于DRAM而言，DRAM存储单元的位线和电容可以分别设置于在同一片晶圆的两个面上，如此，可简化字线、位线和电容的电路排布，降低半导体器件的制造工艺难度。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
本申请所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合， 得到新的方法实施例或设备实施例。
以上所述，仅为本申请的一些实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。
工业实用性
本申请实施例提供一种晶体管及其制造方法、半导体器件及其制造方法，所述晶体管的制造方法包括：提供一晶圆，所述晶圆具有多个晶体管形成区域，每一所述晶体管形成区域具有一晶体管柱，每一所述晶体管柱具有一裸露的栅极形成面；在每一所述晶体管柱的栅极形成面上依次形成栅极氧化层和栅极；在所述晶体管柱的第一端，形成源极；在所述晶体管柱的第二端，形成漏极，其中，所述第一端和所述第二端分别为所述晶体管柱在第一方向上相对的两端，所述第一方向为所述晶圆的厚度方向；所述源极与所述漏极之间的晶体管柱构成所述晶体管的沟道区。

Claims (20)

  1. 一种晶体管的制造方法，包括：
    提供一晶圆，所述晶圆具有多个晶体管形成区域，每一所述晶体管形成区域具有一晶体管柱，每一所述晶体管柱具有一裸露的栅极形成面；
    在每一所述晶体管柱的栅极形成面上依次形成栅极氧化层和栅极；
    在所述晶体管柱的第一端，形成源极；
    在所述晶体管柱的第二端，形成漏极，其中，所述第一端和所述第二端分别为所述晶体管柱在第一方向上相对的两端，所述第一方向为所述晶圆的厚度方向；所述源极与所述漏极之间的晶体管柱构成所述晶体管的沟道区。
  2. 根据权利要求1所述的方法，其中，所述栅极形成面包括一侧壁或一L型面；
    所述在每一所述晶体管柱的栅极形成面上依次形成栅极氧化层和栅极，包括：
    在每一所述晶体管柱的所述侧壁上依次形成所述栅极氧化层和所述栅极；或者，
    在每一所述晶体管柱的所述L型面上依次形成所述栅极氧化层和所述栅极。
  3. 根据权利要求2所述的方法，其中，所述晶体管形成区域还具有包裹所述晶体管柱其它侧壁的绝缘层；所述晶体管形成区域通过以下方式形成：
    沿所述第一方向，以所述晶圆的第一面为刻蚀起点，对所述晶圆进行部分刻蚀，形成由多个硅柱组成的网格状刻蚀沟槽，其中，每一所述硅柱具有第一预设厚度，所述第一预设厚度小于所述晶圆的初始厚度；所述晶圆的第一面为所述晶圆沿所述第一方向的任意一个面；
    在所述网格状刻蚀沟槽中沉积绝缘材料，形成包围每一所述硅柱的绝缘层；
    刻蚀所述硅柱和所述绝缘层，形成具有一裸露的所述侧壁或一裸露的所述L型面的所述晶体管柱，得到所述晶体管形成区域。
  4. 根据权利要求3所述的方法，其中，刻蚀所述硅柱和所述绝缘层，形成具有一裸露的所述侧壁的所述晶体管柱，包括：
    以所述硅柱的边缘位置为刻蚀起点，沿所述第一方向，对所述硅柱和所述绝缘层进行部分刻蚀处理，去除在所述第二方向具有预设尺寸，且在所述第一方向上具有所述第一预设厚度的硅柱和绝缘层，形成具有一裸露的所述侧壁的所述晶体管柱，并形成一刻蚀凹槽；其中，所述预设尺寸小于所述硅柱在所述第二方向上的初始尺寸；所述第二方向垂直于所述第一方向。
  5. 根据权利要求4所述的方法，其中，在形成所述栅极氧化层和所述栅极之前，所述方法还包括：
    在所述刻蚀凹槽的底部沉积形成第一隔离层；
    对应地，所述在每一所述晶体管柱的侧壁上依次形成栅极氧化层和栅极，包括：
    通过原位氧化的方式，在所述晶体管柱的所述侧壁上形成初始栅极氧化层；
    在所述刻蚀凹槽中沉积多晶硅材料，形成多晶硅层；
    在所述第一方向上，对所述初始栅极氧化层和所述多晶硅层同时进行刻蚀处理，去除所述第一方向上的部分厚度的所述初始栅极氧化层和所述多晶硅层，形成所述栅极氧化层和所述栅极。
  6. 根据权利要求3至5任一项所述的方法，其中，在形成所述栅极氧化层和所述栅极之后，所述方法还包括：
    在所述刻蚀凹槽中沉积形成第二隔离层，其中，所述第二隔离层位于所述晶体管柱在所述第二方向上的投影区域内，且所述第二隔离层在第三方向上的尺寸与所述晶体管柱在所述第三方向上的尺寸相等。
  7. 根据权利要求6所述的方法，其中，在形成所述漏极之前，所述方法还包括：
    从所述晶圆的第二面开始，对所述晶圆进行减薄处理，直至暴露出所述第一隔离层和所述晶体管柱的第二端为止；其中，所述晶圆的第二面是与所述晶圆的第一面相对的一面。
  8. 根据权利要求3所述的方法，其中，刻蚀所述硅柱和所述绝缘层，形成具有一裸露的所述L型面的所述晶体管柱，包括：
    以所述硅柱的边缘位置为刻蚀起点，沿所述第一方向，对所述硅柱和所述绝缘层进行部分刻蚀处理，去除在所述第二方向上具有预设尺寸，且在所述第一方向上具有第二预设厚度的硅柱和绝缘层，形成具有所述L型面的所述晶体管柱，并形成一刻蚀凹槽；其中，所述第二预设厚度小于所述第一预设厚度，所述预设尺寸小于所述硅柱在所述第二方向上的初始尺寸；所述第二方向 垂直于所述第一方向。
  9. 根据权利要求8所述的方法，其中，所述L型面包括一竖直面和与所述竖直面垂直的一水平面；所述在每一所述晶体管柱的所述L型面上依次形成所述栅极氧化层和所述栅极，包括：
    通过原位氧化的方式，在所述竖直面和所述水平面上分别形成初始栅极氧化层；
    在具有所述初始栅极氧化层的所述刻蚀凹槽中沉积多晶硅材料，形成多晶硅层；
    在所述第一方向上，对所述初始栅极氧化层和所述多晶硅层同时进行刻蚀处理，去除所述第一方向上的部分厚度的所述初始栅极氧化层和所述多晶硅层，形成所述栅极氧化层和所述栅极。
  10. 根据权利要求9所述的方法，其中，在形成所述栅极氧化层和所述栅极之后，所述方法还包括：
    在所述刻蚀凹槽中沉积形成隔离层，其中，所述隔离层位于所述晶体管柱在所述第二方向上的投影区域内，且所述隔离层在第三方向上的尺寸与所述晶体管柱在所述第三方向上的尺寸相等。
  11. 根据权利要求10所述的方法，其中，在形成所述漏极之前，所述方法还包括：
    从所述晶圆的第二面开始，对所述晶圆进行减薄处理，以去除第三预设厚度的所述晶圆，暴露出所述晶体管柱的第二端；其中，所述第三预设厚度小于所述初始厚度与所述第二预设厚度之间的差值；其中，所述晶圆的第二面是与所述晶圆的第一面相对的一面。
  12. 根据权利要求11所述的方法，其中，所述在所述晶体管柱的第二端，形成漏极，包括：
    对所述晶体管柱的第二端进行预设深度的离子注入，形成所述漏极，其中，所述预设深度小于或等于所述初始厚度与所述第二预设厚度之间的差值。
  13. 根据权利要求1所述的方法，其中，所述源极与所述漏极的形状相同或不同；
    所述源极和所述漏极的形状包括以下任意一种：方形、半圆形、三角形或任意多边形。
  14. 一种晶体管，包括：
    沟道区；源极，位于所述沟道区的第一端；
    漏极，位于所述沟道区的第二端，其中，所述第一端和所述第二端分别为所述沟道区在第一方向上相对的两端，所述第一方向为形成所述沟道区的晶圆的厚度方向；
    栅极，位于所述沟道区的任一侧，且与所述沟道区对应；
    栅极氧化层，位于所述沟道区和所述栅极之间。
  15. 根据权利要求14所述的晶体管，其中，所述源极、所述沟道区和所述漏极形成L型结构或柱形结构。
  16. 一种半导体器件的形成方法，包括：
    形成至少一个存储器单元，其中，每一所述存储器单元至少包括：晶体管；所述晶体管包括：栅极、源极和漏极；所述晶体管通过上述权利要求1至13任一项提供的晶体管的制造方法制造；
    形成字线，所述字线与所述晶体管的栅极连接，所述字线用于提供字线电压，并通过所述字线电压控制所述晶体管导通或截止；
    形成位线，所述位线与所述晶体管的源极或者漏极连接，所述位线用于在所述晶体管导通时，对所述存储器单元执行读取或写入操作。
  17. 一种半导体器件，包括：至少一个存储器单元、字线和位线，每一所述存储器单元至少包括：如权利要求14或15所述的晶体管；所述晶体管至少包括：栅极、源极和漏极；
    所述字线与所述晶体管的栅极连接，所述字线用于提供字线电压，并通过所述字线电压控制所述晶体管导通或截止；
    所述位线与所述晶体管的源极或者漏极连接，所述位线用于在所述晶体管导通时，对所述存储器单元执行读取或写入操作。
  18. 根据权利要求17所述的半导体器件，其中，所述存储器单元还包括：存储电容；
    所述存储电容的一端与所述晶体管的漏极或者源极连接，所述存储电容的另一端接地，所述存储电容用于存储写入所述存储器单元的数据。
  19. 根据权利要求17所述的半导体器件，其中，所述存储器单元还包括：可调电阻；
    所述可调电阻连接于所述位线和所述晶体管的源极之间，或者，所述可调电阻连接于所述位线和所述晶体管的漏极之间，所述可调电阻用于通过所述位线提供的位线电压调节所述存储器单元中所存储的数据的状态。
  20. 根据权利要求17所述的半导体器件，其中，当所述半导体器件包括多个所述存储器单元时，多个所述存储器单元之间并联或者串联。
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