WO2023168752A1 - 半导体结构及其制造方法、存储器及其制造方法 - Google Patents

半导体结构及其制造方法、存储器及其制造方法 Download PDF

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WO2023168752A1
WO2023168752A1 PCT/CN2022/082188 CN2022082188W WO2023168752A1 WO 2023168752 A1 WO2023168752 A1 WO 2023168752A1 CN 2022082188 W CN2022082188 W CN 2022082188W WO 2023168752 A1 WO2023168752 A1 WO 2023168752A1
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transistor
material layer
transistor array
channel
memory
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PCT/CN2022/082188
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English (en)
French (fr)
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邵光速
邱云松
肖德元
苏星松
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长鑫存储技术有限公司
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Priority to US17/806,609 priority Critical patent/US20230292486A1/en
Publication of WO2023168752A1 publication Critical patent/WO2023168752A1/zh

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    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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Definitions

  • the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure and a manufacturing method thereof, a memory and a manufacturing method thereof.
  • embodiments of the present disclosure propose a semiconductor structure and a manufacturing method thereof, a memory and a manufacturing method thereof.
  • Embodiments of the present disclosure provide a semiconductor structure, which includes at least one transistor, where the transistor includes:
  • a channel the channel includes a first material layer and a second material layer arranged around the first material layer; the resistivity of the first material layer is greater than a first preset value, and the resistivity of the second material layer The resistivity is less than the second preset value, and the first preset value is greater than the second preset value;
  • a gate covering at least one side of the channel
  • the source electrode and the drain electrode are located at both ends of the extending direction of the channel.
  • the semiconductor structure includes a plurality of transistors, and a plurality of channels corresponding to the plurality of transistors are arranged in an array along a first direction and a second direction; the first direction and the second direction are both Perpendicular to the extension direction of the channel; wherein,
  • the gate electrodes of each transistor in each row of transistors arranged along the first direction are physically connected to each other; the gate electrodes of two adjacent rows of transistors arranged along the first direction are electrically isolated from each other.
  • the material of the first material layer and/or the material of the second material layer includes indium oxide, gallium oxide, zinc oxide, indium gallium oxide, indium zinc oxide, gallium zinc oxide, and indium gallium zinc oxide. of at least one.
  • the gate is arranged around the channel.
  • Embodiments of the present disclosure provide a method of manufacturing a transistor.
  • the semiconductor structure includes at least one transistor.
  • the method of manufacturing a transistor includes:
  • the channel includes a first material layer and a second material layer arranged around the first material layer; the resistivity of the first material layer is greater than a first preset value, and the second material layer The resistivity is less than the second preset value, and the first preset value is greater than the second preset value;
  • the source electrode and the drain electrode of the transistor are respectively formed at both ends in the extending direction of the channel.
  • the semiconductor structure includes a plurality of transistors, and a plurality of channels corresponding to the plurality of transistors are arranged in an array along a first direction and a second direction; the first direction and the second direction are both Perpendicular to the extension direction of the channel; wherein,
  • the gate electrodes of each transistor in each row of transistors arranged along the first direction are physically connected to each other; the gate electrodes between two adjacent rows of transistors arranged along the first direction are electrically isolated from each other.
  • the material of the first material layer and/or the material of the second material layer includes indium oxide, gallium oxide, zinc oxide, indium gallium oxide, indium zinc oxide, gallium zinc oxide, and indium gallium zinc oxide. of at least one.
  • forming the channel includes:
  • the first hole formed with the second material layer is filled to form the first material layer.
  • the second material layer is formed on the side wall and bottom of the first hole, including:
  • the second material layer is formed through an atomic layer deposition process in an oxygen-free atmosphere
  • Filling the first hole formed with the second material layer to form the first material layer includes:
  • the first material layer is formed by in-situ deposition in an oxygen atmosphere.
  • the method further includes:
  • the first conductive material and the second dielectric layer are filled in sequence, the first conductive material and the second dielectric layer are etched to form grooves, and the insulating material is filled in the grooves to form a gate isolation structure.
  • This embodiment of the present disclosure further provides a memory, including:
  • a plurality of first memory cells arranged in an array along the first direction and the second direction;
  • a first transistor array located on the plurality of first memory cells; the first transistor array includes a plurality of transistors described in the above solution; the gates of each row of transistors in the first transistor array along the first direction The gate electrodes are physically connected to each other, and the physically connected gate electrodes form a first word line; each of the memory cells is respectively connected to the source or drain electrode of a transistor in the transistor array; the first direction and the third Both directions are perpendicular to the extending direction of the channel of the transistor;
  • a plurality of first-order lines arranged side by side along the second direction are located on the first transistor array; each of the first-order lines is respectively connected to a first-order line arranged along the second direction in the first transistor array.
  • the drain or source connections of a row of transistors are located on the first transistor array; each of the first-order lines is respectively connected to a first-order line arranged along the second direction in the first transistor array.
  • the memory includes: dynamic random access memory, ferroelectric memory, phase change memory, magnetic change memory or resistive change memory.
  • the memory includes: a dynamic random access memory, and the memory unit includes: a capacitor; the capacitor includes a columnar second electrode, a dielectric covering the side walls and bottom of the second electrode, and a dielectric covering the second electrode. The first electrode of the dielectric.
  • the memory also includes a plurality of second memory cells, a second transistor array, and a plurality of second bit lines; wherein,
  • the plurality of second memory cells are located on the first bit line and are arranged in an array along the first direction and the second direction;
  • the second transistor array is located on the plurality of second memory cells; the second transistor array includes the transistors described in the above solution; the second transistor array along the first direction of each row of transistors Gates are physically connected to each other, and the physically connected gates form a second word line; each of the second memory cells is respectively connected to the source or drain of a transistor in the second transistor array;
  • the plurality of second bit lines are located on the second transistor array, the plurality of second bit lines are arranged side by side along the second direction, and each of the second bit lines is connected to the second transistor array respectively.
  • the drains or sources of a row of transistors arranged along the second direction in the transistor array are connected.
  • An embodiment of the present disclosure also provides a memory manufacturing method, which method includes:
  • a first transistor array is formed on the plurality of first memory cells; the first transistor array is manufactured by the transistor manufacturing method described in the above solution; the first transistor array along the first direction The gates of each row of transistors are physically connected to each other, and the physically connected gates form a first word line; each of the first memory cells is connected to the source or drain of one transistor in the first transistor array. ; The first direction and the second direction are both perpendicular to the extension direction of the channel of the transistor;
  • a plurality of first-order lines arranged in parallel along the second direction are formed on the first transistor array, and each first-order line is respectively connected to a first-order line arranged along the second direction in the transistor array.
  • the drain or source connections of a row of transistors are formed on the first transistor array, and each first-order line is respectively connected to a first-order line arranged along the second direction in the transistor array.
  • forming a plurality of first first lines arranged side by side along the second direction includes:
  • the second dielectric layer is partially etched to form a plurality of second trenches extending along the second direction; the second trenches expose part of the sidewalls of the trench;
  • the second trench is filled with a second conductive material to form the bit line surrounding an end of the trench.
  • the first storage unit includes a capacitor
  • the forming of multiple first storage units includes:
  • the second hole formed with the first electrode and the dielectric layer is filled to form a plurality of second electrodes; each of the second electrodes is respectively connected to the source or drain of one transistor in the transistor array.
  • the method includes:
  • a plurality of second memory cells are formed on the first bit line, and the plurality of second memory cells are arranged in an array along the first direction and the second direction;
  • a second transistor array is formed on the plurality of second memory cells; the second transistor array is manufactured by the transistor manufacturing method in the above solution; each row of the second transistor array along the first direction The gates of the transistors are physically connected to each other, and the physically connected gates form a second word line; each of the second memory cells is respectively connected to the source or drain of one transistor in the second transistor array;
  • a plurality of second bit lines arranged in parallel along the second direction are formed on the second transistor array, and each of the second bit lines is respectively connected with the second transistor array arranged along the second direction.
  • the drain or source connections of a row of transistors are formed on the second transistor array, and each of the second bit lines is respectively connected with the second transistor array arranged along the second direction.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, a memory and a manufacturing method thereof, wherein the semiconductor structure includes at least one transistor, the transistor includes a channel, and the channel includes a first material layer and a second material layer arranged around the first material layer; the resistivity of the first material layer is greater than the first preset value, the resistivity of the second material layer is less than the second preset value, and the resistivity of the first material layer is greater than the first preset value.
  • a preset value is greater than the second preset value; a gate electrode covers at least one side of the channel; a source electrode and a drain electrode are located at both ends of the extension direction of the channel.
  • the source and drain of the transistor are arranged along the extension direction of the transistor, so that the area occupied by a single transistor in the horizontal direction is reduced, and the number of transistors that can be arranged in a unit area is increased.
  • the channel is composed of a first material layer and a second material layer with different resistivities.
  • the second material layer with low resistivity helps to increase the threshold voltage of the transistor, and the first material layer with high resistivity
  • the material layer helps to improve the field effect mobility of the transistor.
  • the channel including the first material layer and the second material layer enables the transistor to have both a higher field effect mobility and a higher threshold. voltage to meet the high performance requirements of transistors.
  • Figure 1a is a schematic three-dimensional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 1b is a schematic three-dimensional structural diagram of another semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 2 is a schematic flow diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • 3a to 3j are schematic three-dimensional structural diagrams of a manufacturing process of a semiconductor structure provided by embodiments of the present disclosure
  • Figure 4a is a schematic three-dimensional structural diagram of a memory provided by an embodiment of the present disclosure.
  • Figure 4b is a schematic three-dimensional structural diagram of another memory provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic flow diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • 6a to 6g are schematic three-dimensional structural diagrams of a manufacturing process of a memory provided by an embodiment of the present disclosure.
  • 10-memory unit/capacitor 100-substrate; 101-third dielectric layer; SCH-second hole; 102-first electrode; 103-dielectric layer; 104-second electrode; SC-capacitor;
  • 20-transistor/transistor array 201-first dielectric layer; CH-first hole; C-channel; 202-second material layer; 203-first material layer; S-source; D-drain; 204 -Gate oxide layer; 205-gate; 206-gate isolation structure; 207-second dielectric layer; AT/AT1/AT2-each row of transistors; GT-groove; GIT-gate isolation trench/groove ;
  • spatial relational terms such as “under”, “under”, “under”, “under”, “on”, “above”, etc., are used here It may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “under” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Transistors can be used in various memories, such as dynamic random access memory (DRAM, DRAM).
  • DRAM dynamic random access memory
  • DRAM is a structure including one transistor T (Transistor) and one capacitor C (Capacitance) (1T1C).
  • TFTs thin-film transistors
  • ⁇ FE threshold voltage
  • Vth threshold voltage
  • Transistors in related technologies cannot have both high ⁇ FE and high Vth, making it difficult to meet high-performance requirements.
  • embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, a memory and a manufacturing method thereof.
  • Figure 1a is a schematic three-dimensional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure (which can be understood as a three-dimensional schematic diagram of a transistor in the semiconductor structure cut along the X-Z plane and the Y-Z plane respectively. ), the semiconductor structure includes at least one transistor, and the transistor 20 includes:
  • the channel C includes a first material layer 203 and a second material layer 202 arranged around the first material layer 203; the resistivity of the first material layer 203 is greater than the first preset value, so The resistivity of the second material layer 202 is less than the second preset value, and the first preset value is greater than the second preset value;
  • Gate 205 covers at least one side of the channel
  • the source S and the drain D are located at both ends of the channel C in the extending direction.
  • the transistor provided by the embodiment of the present disclosure may include a vertical transistor, and the gate is a transistor with a buried gate.
  • FIG. 1a also shows the dielectric layer required to bury the gate 205 (such as the first dielectric layer 201 and the second dielectric layer 207 described below).
  • the first material layer 203 and the second material layer 202 in the channel C have different emphasis on improving the transistor performance.
  • the first material layer 203 with a resistivity greater than the first preset value is disposed inside the channel C (understood as pointing toward the channel core in the radial direction of the channel in the X-Y plane) away from the gate 205
  • One side of the second material layer 202 is mainly used to increase the threshold voltage Vth of the transistor and the resistivity is less than the second preset value, and is disposed outside the channel C (understood as along the X-Y plane)
  • the side of the channel (away from the channel core in the radial direction) and close to the gate 205 is mainly used to increase the electron mobility ⁇ FE of the transistor.
  • the channel C including the first material layer 203 and the second material layer 202 with differential resistivity can enable the transistor to have both high ⁇ FE and high Vth that meet the requirements.
  • a continuous smooth low-resistivity second material layer 202 is formed on the outside of the high-resistivity first material layer 203, due to the passivation of defects and the high-quality homogeneous junction interface, the switching (ON/OFF) ratio, Vth and ⁇ FE are significantly improved.
  • the second material layer 202 not only affects the value of Vth, but also has a great impact on ⁇ FE.
  • the first preset value is a higher resistivity value
  • the second preset value is a higher resistivity value.
  • the first preset value and the second preset value can be adjusted according to actual conditions.
  • the first preset value may be 100 M ⁇ cm
  • the second preset value may be 0.1 ⁇ cm. That is to say, the resistivity of the first material layer 203 is greater than 100 M ⁇ cm, and the resistivity of the second material layer 202 is less than 0.1 ⁇ cm.
  • the first material layer 203 that meets the resistivity requirements can be obtained through material selection, doping concentration (P-type/N-type carrier) selection, and manufacturing process parameter (oxidizing atmosphere/reducing atmosphere) selection. and the second material layer 202.
  • the selected material itself has high resistivity, it is more suitable for forming the second material layer 202.
  • the selected material itself has low resistivity, it is more suitable for forming the second material layer 202.
  • Second material layer 202 Second material layer 202.
  • the doping concentration of carriers when the doping concentration of carriers is low, a material layer with high resistivity is easily formed, and when the doping concentration of carriers is high, a material layer with low resistivity is easily formed. Therefore, when forming the first material layer 203 with high resistivity, a higher carrier doping concentration can be given during its formation process; when forming the second material layer 202 with low resistivity, A higher carrier doping concentration can be given during its formation.
  • a material layer with high resistivity is easily formed in an oxidizing atmosphere (oxygen-containing atmosphere), and a material layer with low resistivity is easily formed in a reducing atmosphere (oxygen-free atmosphere). Therefore, when forming the first material layer 203 with high resistivity, it can be performed in an oxidizing atmosphere; when forming the second material layer 202 with low resistivity, it can be performed in an oxygen-free atmosphere.
  • the thickness of the first material layer 203 is relatively thick, while the thickness of the second material layer 202 is relatively thin.
  • the thickness of the first material layer 203 along the radial direction of the channel hole is 1-10 times the thickness of the second material layer 202 along the radial direction of the channel hole. times. It is considered that after the thickness of the low-resistivity second material layer is increased beyond about 10 nm, the effect becomes weaker.
  • the thickness of the second material layer along the radial direction of the channel hole ranges from 1 nm to 10 nm
  • the thickness of the first material layer along the radial direction of the channel hole ranges from 1 nm to 10 nm. 10nm-100nm.
  • the material of the first material layer 203 and the material of the second material layer 202 may be the same or different.
  • the material of the first material layer and/or the material of the second material layer includes an amorphous semiconductor material. It should be noted that amorphous semiconductor materials have higher ⁇ FE than crystalline (such as single crystal, polycrystalline) semiconductor materials.
  • the material of the first material layer 203 and/or the material of the second material layer 202 includes indium oxide, gallium oxide, zinc oxide, indium gallium oxide, indium zinc oxide, gallium zinc oxide, oxide At least one of indium gallium zinc; or, the material of the first material layer 203 and/or the material of the second material layer 202 includes indium oxide, gallium oxide, zinc oxide, indium gallium oxide, indium zinc oxide, gallium oxide A mixture formed by at least one compound of zinc and indium gallium zinc oxide doped with at least one element of cobalt, nickel, tin, aluminum, magnesium, zirconium, hafnium, titanium, tantalum and tungsten.
  • the first material layer 203 and the second material layer 202 may both be made of indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • InGaZn Oxide can drive large amounts of current, which makes the memory write faster when InGaZn Oxide transistors are used in memory, and when the InGaZn Oxide transistor is turned off, very little charge leaks out. , which makes the bits last longer.
  • the gate 205 is disposed around the channel C. That is to say, the vertical transistor in the embodiment of the present disclosure may be a full surround gate transistor. It should be noted that the vertical transistors in the embodiments of the present disclosure are not limited to full surround gate transistors, but may also include other types of vertical transistors, such as semi-surround gate transistors, pillar gate transistors, etc. In practical applications, a gate oxide layer 204 is also formed between the gate electrode 205 and the channel C, that is, between the gate electrode 205 and the second material layer 202 .
  • the positions of the source S and the drain D can be interchanged.
  • the source S is located at the first end of the channel C; the drain D is located at the second end of the channel C; or, the drain D is located at the first end of the channel C; the source S is located at the The second end of channel C.
  • the first end and the second end are respectively two opposite ends of the channel C in the third direction.
  • the third direction is the extending direction of the channel C.
  • the semiconductor structure includes a plurality of transistors, and a plurality of channels C corresponding to the plurality of transistors are arranged in an array along the first direction X and the second direction Y;
  • the first direction X and the second direction Y are both perpendicular to the extension direction of the channel C;
  • each transistor in each row of transistors AT arranged along the first direction are physically connected to each other; the gates of two adjacent rows of transistors AT1 and AT2 arranged along the first direction are electrically connected to each other. isolation.
  • FIG. 1b also shows the dielectric layer required to bury the gate 205 (such as the first dielectric layer 201, the gate isolation structure 206 and the second dielectric layer 207 described below).
  • the first direction intersects the second direction, and the angle between the first direction and the second direction may be any angle between 0 and 90 degrees; for example, The first direction may be perpendicular to the second direction. It can be understood that the angle between the first direction and the second direction establishes the positional relationship of the array arrangement of the transistors along the first direction and the second direction.
  • the first direction and the second direction are expressed as two orthogonal directions parallel to the substrate plane; the third direction is a direction perpendicular to the substrate plane, that is, the third direction.
  • the direction is the extension direction of the channel; wherein, the substrate plane can be understood as a plane perpendicular to the extension direction of the channel.
  • the first direction is represented by the X direction in the drawing; the second direction is represented by the Y direction in the drawing; and the third direction is represented by the Z direction in the drawing.
  • the cross-sectional shape of the channel C perpendicular to the third direction and passing through the channel C may be circular, square, elliptical or diamond-shaped.
  • the selection can be made according to the specific process; for example, a circular channel hole is formed by etching through a patterning process, and the channel C is deposited in the circular channel hole.
  • the channel C is formed along a vertical direction.
  • the cross-sectional shape in the third direction and passing through the channel C is circular.
  • the source and drain of the transistor are arranged along the extension direction of the transistor, so that the area occupied by a single transistor in the horizontal direction is reduced, and the number of transistors that can be arranged in a unit area is increased.
  • the channel is composed of a first material layer and a second material layer with different resistivities.
  • the second material layer with low resistivity helps to increase the threshold voltage of the transistor, and the first material layer with high resistivity
  • the material layer helps to improve the field effect mobility of the transistor.
  • the channel including the first material layer and the second material layer enables the transistor tube to have both high field effect mobility and high threshold voltage to meet the high performance requirements of transistors.
  • the transistor provided in the above embodiments of the present disclosure includes a channel composed of a first material layer and a second material layer with different resistivities; further, by measuring the resistivity value and thickness of the first material layer and/or the second material layer , material composition and other parameters can be appropriately selected to further improve the ⁇ FE and Vth of the transistor and obtain a higher-performance transistor.
  • the semiconductor structure provided by the embodiments of the present disclosure can be formed by the manufacturing method of the semiconductor structure provided by the following embodiments.
  • the semiconductor structure manufactured by the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure is similar to the semiconductor structure in the above-mentioned embodiments.
  • the manufacturing method of the semiconductor structure described in the embodiments of the present disclosure is not limited to manufacturing a specific number of transistors: it can be a manufacturing method of manufacturing a single transistor, or it can be a manufacturing method of manufacturing a transistor array.
  • the following text and figures illustrate an exemplary manufacturing method for manufacturing a transistor array.
  • 3a to 3j are schematic three-dimensional structural diagrams of a manufacturing process of a semiconductor structure provided by embodiments of the present disclosure. It should be understood that the steps shown in Figures 3a to 3j are not exclusive, and other steps may be performed before, after, or between any steps in the operations shown; each step shown in Figures 3a to 3j may be performed according to Adjust the order according to actual needs.
  • FIG. 2 is a schematic flow diagram of a manufacturing method of a semiconductor structure provided by an embodiment of the disclosure
  • FIGS. 3a to 3j are schematic three-dimensional structural diagrams of a manufacturing process of a semiconductor structure provided by an embodiment of the disclosure.
  • the semiconductor structure includes at least one transistor
  • the manufacturing method of the transistor includes:
  • Step 2001 Form a channel; the channel includes a first material layer and a second material layer arranged around the first material layer; the resistivity of the first material layer is greater than a first preset value, and the resistivity of the first material layer is greater than a first preset value.
  • the resistivity of the two material layers is less than a second preset value, and the first preset value is greater than the second preset value;
  • Step 2002 forming a gate of a transistor covering at least one side of the channel
  • Step 2003 Form the source electrode and the drain electrode of the transistor respectively at both ends in the extending direction of the channel.
  • Step 2001 is executed, as shown in Figures 3a to 3d, to form the channel C.
  • forming channel C includes:
  • the second material layer 202 is formed on the sidewall and bottom of the first hole CH;
  • the first hole formed with the second material layer 202 is filled to form the first material layer 203 .
  • a first dielectric layer 201 is provided.
  • the material of the first dielectric layer 201 may include but is not limited to silicon oxide.
  • the first dielectric layer 201 can be formed through a physical vapor deposition (Physical Vapor Deposition, PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, an atomic layer deposition (Atomic Layer Deposition, ALD) process, etc. .
  • the first dielectric layer 201 can be selected and formed on the substrate according to actual requirements of the device.
  • the material of the substrate may include silicon (Si), germanium (Ge), silicon germanium (SiGe) substrate, etc.; the substrate (not shown) may also be silicon-on-insulator (SiGe). Silicon-on-insulator (SOI) or Germanium-on-Insulator (GOI), the substrate is doped with certain impurity ions as needed, and the impurity ions can be N-type impurity ions or P-type impurities ions; in one embodiment, the doping includes well region doping and source and drain region doping, and an active layer (not shown) is formed in the substrate.
  • the first dielectric layer 201 may not be formed on the substrate, for example, it may also be formed on other functional thin film layers.
  • a first hole CH is formed in the first dielectric layer 201; the first hole CH penetrating the first dielectric layer 201 may be formed through an etching process.
  • dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation and other processes may be used to form the first hole CH in the first dielectric layer 201 .
  • the second material layer 202 is formed on the side wall and bottom of the first hole CH; the first hole CH formed with the second material layer 202 is filled to form the first material layer. 203.
  • the second material layer 202 and the first material layer 203 may be formed through one or more deposition processes. The process includes but is not limited to PVD process, CVD process, ALD process or any combination thereof.
  • the second material layer 202 and the first material layer 203 may be formed through an atomic layer deposition process.
  • forming the second material layer on the sidewall and bottom of the first hole includes: forming the second material layer through an atomic layer deposition process in an oxygen-free atmosphere;
  • Filling the first hole formed with the second material layer and forming the first material layer includes: forming the first material layer through in-situ deposition in an oxygen atmosphere.
  • a reaction gas containing the material of the second material layer 202 is introduced, and the first hole CH is formed on the side wall and bottom of the first hole CH.
  • the resistivity of the first material layer 203 and the second material layer 202 is significantly changed by the influence of the surrounding atmosphere (such as oxidizing gas or reducing gas) when they are formed.
  • the resistivity of the second material layer 202 formed in an oxygen-free atmosphere in practical applications, it is not absolutely oxygen-free, but the oxygen content in the atmosphere is controlled as low as possible to an acceptable range for the process) Lower; the resistivity of the first material layer 203 is adjusted by controlling the introduction of a certain proportion of oxygen. The greater the oxygen content, the greater the resistivity of the first material layer 203 formed.
  • Steps 2002 and 2003 are performed, as shown in Figures 3e to 3j, to form the gate of the transistor covering at least one side of the channel; and to form the source of the transistor at both ends in the extension direction of the channel. and drain.
  • the method further includes:
  • the first conductive material and the second dielectric layer 207 are filled in sequence, the first conductive material and the second dielectric layer are etched to form grooves, and the insulating material is filled in the grooves to form the gate isolation structure 206 .
  • the first dielectric layer 201 is partially etched to form an exposed second material layer 202; a groove GT may be formed through an etching process to expose the sidewalls of the second material layer 202.
  • dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation and other processes may be used to form the groove GT of the exposed sidewalls of the second material layer 202 .
  • the groove GT does not penetrate the first dielectric layer 201 in the third direction.
  • the depth of the groove GT in the third direction may be smaller than the thickness of the channel C in the third direction.
  • a gate oxide layer 204 is formed on the exposed second material layer 202; the second material layer 202 can be oxidized in situ to have exposed sidewalls in the corresponding groove GT, at least in The exposed sidewalls of each channel C (that is, the exposed sidewalls of the second material layer 202 ) form a gate oxide layer 204 .
  • each channel C (that is, the exposed sidewalls of the second material layer 202 ) can be oxidized in situ by heating or pressurizing to form a gate oxide layer.
  • Silica silica
  • the gate oxide layer 204 is disposed around the channel C, that is, the gate oxide layer 204 is formed around the second material layer 202.
  • the first conductive material 205' and the second dielectric layer 207 are filled in sequence; the first conductive material 205' and the second dielectric layer 207 can be deposited in the groove GT with the gate oxide layer 204 through a PVD process, a CVD process or an ALD process.
  • a conductive material 205' is then used to deposit a second dielectric layer 207 in the groove GT having the gate oxide layer 204 and the first conductive material 205' formed through an etching back process.
  • the first conductive material 205' may be a metal material or a semiconductor conductive material, such as copper, cobalt, tungsten, molybdenum, doped silicon, polysilicon or any combination thereof;
  • the material of the second dielectric layer 207 includes But it is not limited to silicon nitride, silicon oxynitride, silicon carbide, silicon dioxide or any combination thereof.
  • the first conductive material 205' and the second dielectric layer 207 are etched to form a groove GIT; the groove GIT can be formed through an etching process, and the groove GIT penetrates the third direction in the third direction.
  • a conductive material 205' In practical applications, dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation and other processes may be used to form the groove GIT penetrating the first conductive material 205' in the third direction. It can be understood that the groove GIT separates the first conductive material 205' into a plurality of gate electrodes 205, and the adjacent gate electrodes 205 in the first direction are separated by the groove GIT. separated.
  • the groove GIT simultaneously penetrates the first conductive material 205' and the first dielectric layer 201 in the third direction; the groove GIT simultaneously penetrates the first conductive material 205' and the first dielectric layer 201 in the first direction. the first conductive material 205' and the first dielectric layer 201.
  • the gate 205 is disposed around the channel C.
  • a gate oxide layer 204 is also formed between the gate electrode 205 and the channel C, that is, between the gate electrode 205 and the second material layer 202 .
  • the groove GIT is filled with insulating material to form the gate isolation structure 206;
  • the insulating material can be deposited in the groove GT through a PVD process, a CVD process or an ALD process, and the insulating material can be Chemical Mechanical Polishing (CMP) is performed to make the surface of the insulating material flush with the surface of the second dielectric layer 207 to form the gate isolation structure 206 .
  • CMP Chemical Mechanical Polishing
  • the insulating material includes but is not limited to silicon nitride, silicon oxynitride, silicon carbide or silicon dioxide.
  • the semiconductor structure includes a plurality of transistors, and a plurality of channels C corresponding to the plurality of transistors are arranged in an array along a first direction X and a second direction Y; the first direction X and The second direction Y is perpendicular to the extension direction of the channel C; wherein,
  • each transistor in each row of transistors AT arranged along the first direction are physically connected to each other; the gates of two adjacent rows of transistors AT1 and AT2 arranged along the first direction are electrically connected to each other. isolation.
  • the manufacturing method of the transistor array described in the embodiment of the present disclosure is used to manufacture including but not limited to manufacturing a specific number of transistors, and may also be a manufacturing method for manufacturing a single transistor.
  • the manufacturing method of the transistor array (the above-mentioned Figure 1b) in the embodiment of the present disclosure can be understood with reference to the steps of the aforementioned Figures 3a to 3j, and will not be described again here.
  • FIG. 4a is a schematic three-dimensional structural diagram of a memory provided by an embodiment of the present disclosure.
  • the memory 30 includes: a plurality of first memory cells 10 arranged in an array along the first direction and the second direction;
  • the first transistor array 20 is located on the plurality of first memory cells 10; the first transistor array 20 includes a plurality of transistors according to the embodiments of the present disclosure; each of the first transistor array 20 along the first direction
  • the gates 205 of a row of transistors are physically connected to each other, and the physically connected gates form the first word line WL1;
  • each memory cell SC is respectively connected to the source S or the drain D of a transistor in the transistor array 20 Connection; the first direction and the second direction are both perpendicular to the extension direction of the channel C of the transistor;
  • a plurality of first bit lines BL1 arranged side by side along the second direction are located on the first transistor array 20; each of the first bit lines BL1 is respectively connected to the center of the first transistor array 20 along the first transistor array 20.
  • the drains D or sources S of a row of transistors arranged in the second direction are connected.
  • the first word line WL1 is connected to the gate 205 of each transistor array 20.
  • the first word line WL1 is used to provide a word line voltage, and controls each transistor through the word line voltage.
  • the channel region in the transistor is turned on or off.
  • the first bit line BL1 extending along the first direction
  • the memory unit 10 performs read or write operations.
  • the materials of the first word line WL1 and the first bit line BL1 include but are not limited to tungsten, cobalt, molybdenum, copper, aluminum, polysilicon, doped silicon, silicide or any combination thereof.
  • each memory cell SC is respectively connected to the source S of a transistor in the transistor array 20, then each first bit line BL1 is respectively connected to the first bit line BL1.
  • the drain D of a row of transistors arranged along the second direction in a transistor array 20 is connected; or, if each memory cell SC is connected to the drain D of a transistor in the transistor array 20, then Each first bit line BL1 is respectively connected to the source S of a row of transistors arranged along the second direction in the first transistor array 20 .
  • the memory provided by embodiments of the present disclosure includes various types of memory.
  • NAND flash memory Flash
  • Nor Flash DRAM
  • static random access memory Static Random Access Memory, SRAM
  • phase change memory Phase-Change Memory, PCM
  • ferroelectric memory magnetic change memory or resistive memory .
  • the memory includes: DRAM, and the memory unit includes: a capacitor SC; the capacitor SC includes a columnar second electrode 104, and a dielectric layer 103 covering the side walls and bottom of the second electrode 104, and a first electrode 102 covering the dielectric 103 .
  • the second electrode 104 may be connected to the source S of a transistor in the transistor array, the first electrode 102 may be connected to ground, and the capacitor SC may be used to store written data.
  • the memory includes a resistive switching memory
  • the memory unit includes an adjustable resistor connected to the first bit line BL1 and the source S of a transistor in the transistor array 20 between; or, the adjustable resistor is connected between the first bit line BL1 and the drain D of a transistor in the transistor array 20, and the adjustable resistor is used to pass the first bit line BL1.
  • the bit line voltage provided by line BL1 regulates the state of the stored data.
  • the memory may include multiple layers of stacked memory cells, such as two layers of memory cells stacked along a third direction.
  • the memory also includes a plurality of second memory cells 11, a second transistor array 21, and a plurality of second bit lines BL2; wherein,
  • the plurality of second memory cells 11 are located on the first bit line BL1 and are arranged in an array along the first direction and the second direction;
  • the second transistor array 21 is located on the plurality of second memory cells 11; the second transistor array 21 includes transistors provided by embodiments of the present disclosure; each of the second transistor array 21 along the first direction
  • the gates 205 of a row of transistors are physically connected to each other, and the physically connected gates form a second word line WL2; each second memory cell SC2 is connected to the source S of one transistor in the second transistor array 21 respectively. or drain D connection;
  • the plurality of second bit lines BL2 are located on the second transistor array 21.
  • the plurality of second bit lines BL2 are arranged in parallel along the second direction.
  • Each of the second bit lines BL2 is respectively connected to The drains D or sources S of a row of transistors arranged along the second direction in the second transistor array 21 are connected.
  • the transistor can be manufactured at a relatively low temperature and is therefore compatible with back-end processes. This enables moving the periphery of the memory below the memory cell array, which significantly reduces the memory chip's footprint.
  • back-end processing opens up routes for stacking individual DRAM cells, enabling three-dimensional 3D-DRAM architectures.
  • the DRAM provided by the embodiments of the present disclosure can play a key role in demanding applications such as cloud computing and artificial intelligence.
  • FIG. 5 is a schematic flow diagram of a manufacturing method of a semiconductor structure provided by an embodiment of the disclosure
  • FIGS. 6a to 6g are schematic three-dimensional structural diagrams of a manufacturing process of a memory provided by an embodiment of the disclosure.
  • the manufacturing method includes:
  • Step 5001 form a plurality of first memory cells 10, and the plurality of first memory cells 10 are arranged in an array along the first direction and the second direction;
  • Step 5002 Form a first transistor array 20 on the plurality of first memory cells 10; the first transistor array 20 is manufactured by the transistor manufacturing method described in the embodiment of the present disclosure; the first transistor array 20 The gates 205 of each row of transistors along the first direction are physically connected to each other, and the physically connected gates 205 form a first word line WL1; each of the first memory cells 10 is connected to the first word line WL1 respectively.
  • the source S or the drain D of one transistor in the transistor array 20 is connected; the first direction and the second direction are both perpendicular to the extension direction of the channel C of the transistor;
  • Step 5003 Form a plurality of first bit lines BL1 arranged side by side along the second direction on the first transistor array 20.
  • Each of the first bit lines BL1 is connected to a center edge of the transistor array 20.
  • the drains D or sources S of a row of transistors arranged in the second direction are connected.
  • Step 5001 is executed to form a plurality of first memory cells 10, which are arranged in an array along the first direction and the second direction.
  • Figures 6a to 6d are schematic three-dimensional structural diagrams of a manufacturing process of a capacitor (which can be understood as a memory unit) according to an embodiment of the present disclosure.
  • the first storage unit includes a capacitor SC
  • the formation of multiple first storage units 10 includes:
  • a plurality of second holes SCH arranged in an array along the first direction and the second direction are formed in the third dielectric layer 101;
  • the first electrode 102 is formed on the sidewall and bottom of the second hole SCH and the top surface of the third dielectric layer 101;
  • the second hole SCH formed with the first electrode 102 and the dielectric layer 103 is filled to form a plurality of second electrodes 104; each of the second electrodes 104 is respectively connected to the source or source of one transistor in the transistor array. drain connection.
  • a third dielectric layer 101 is provided.
  • the material of the third dielectric layer 101 may include but is not limited to silicon oxide.
  • the third dielectric layer 101 can be formed through PVD process, CVD process, ALD and other processes.
  • the third dielectric layer 101 can be formed on the substrate 100 according to actual requirements of the device.
  • the material of the substrate 100 may refer to the material of the aforementioned substrate.
  • a plurality of second holes SCH arranged in an array along the first direction and the second direction are formed in the third dielectric layer 101; they can be formed through the third dielectric layer through an etching process. 101's second hole sch.
  • dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation and other processes may be used to form the second hole SCH in the third dielectric layer 101 .
  • a first electrode 102 is formed on the sidewall and bottom of the second hole SCH and the top surface of the third dielectric layer 101; a dielectric layer 103 is formed on the first electrode 102.
  • the first electrode 102 and the dielectric layer 103 may be formed sequentially through one or more deposition processes.
  • the process includes but is not limited to PVD process, CVD process, ALD process or any combination thereof.
  • the first electrode 102 and the dielectric layer 103 may be formed through an atomic layer deposition process.
  • the material of the first electrode 102 may be a metal material or a semiconductor conductive material, such as copper, cobalt, tungsten, doped silicon, polysilicon or any combination thereof.
  • the material of the dielectric layer 103 may be a dielectric material having a larger dielectric constant than SiO 2 (k ⁇ 3.9).
  • the materials of the dielectric layer 103 may include Ta 2 O 5 (k ⁇ 26), TiO 2 (k ⁇ 80), ZrO 2 (k ⁇ 25), Al 2 O 3 (k ⁇ 9), HfSiO x (k ⁇ 4-25) and HfO 2 (k ⁇ 25).
  • the second hole SCH formed with the first electrode 102 and the dielectric layer 103 is filled to form a plurality of second electrodes 104; the first electrode 104 can be formed by one or more deposition processes.
  • a second electrode material is deposited in an electrode 102 and the second hole SCH of the dielectric layer 103, and the second electrode material is subjected to a CMP process so that the surface of the second electrode material is in contact with the surface of the dielectric layer 103. flush to form the second electrode 104 .
  • the process includes but is not limited to PVD process, CVD process, ALD process or any combination thereof.
  • the second electrode 104 may be formed through an atomic layer deposition process.
  • the second electrode material may be a metal material or a semiconductor conductive material, such as copper, cobalt, tungsten, molybdenum, doped silicon, polysilicon or any combination thereof.
  • the capacitance (can be understood as the capacitance SC in the first storage unit 10) includes a first electrode 102, a dielectric layer 103, and a second electrode 104 formed in each of the second holes SCH.
  • the second electrode 104 of the capacitor is connected to the source S of a transistor in the transistor array, the first electrode 102 of the capacitor is grounded, and the capacitor is used to store written data.
  • Execute step 5002 please refer to FIG. 6e to form a first transistor array 20 on the plurality of first memory cells 10; the first transistor array 20 is manufactured by the transistor manufacturing method described in the embodiment of the present disclosure; so The gates 205 of each row of transistors in the first transistor array 20 along the first direction are physically connected to each other, and the physically connected gates 205 form a first word line WL1; each of the first memory cells 10 They are respectively connected to the source S or the drain D of one transistor in the first transistor array 20 ; the first direction and the second direction are both perpendicular to the extending direction of the channel C of the transistor.
  • the gate oxide layer 204 is shown in the first transistor array 20 .
  • the gate oxide layer 204 is not distinguished from the first dielectric layer 201, the gate isolation structure 206 and the second dielectric layer 207 by filling the background color.
  • the materials of the gate oxide layer 204, the first dielectric layer 201, the gate isolation structure 206 and the second dielectric layer 207 are all insulating materials, and their materials can be the same or different.
  • Step 5003 is executed to form a plurality of first bit lines BL1 arranged side by side along the second direction on the first transistor array 20 , and each of the first bit lines BL1 is connected to the middle edge of the transistor array 20 respectively.
  • the drains D or sources S of a row of transistors arranged in the second direction are connected.
  • forming a plurality of first bit lines BL1 arranged side by side along the second direction includes:
  • the second dielectric layer 207 is partially etched to form a plurality of second trenches BLT extending along the second direction; the second trenches BLT expose part of the sidewalls of the channel C;
  • the second trench BLT is filled with a second conductive material to form the first first line BL1 surrounding the end of the channel C.
  • the part of the second dielectric layer 207 and part of the gate isolation structure 206 may be removed through an etching process to form a plurality of second trenches BLT extending along the second direction.
  • the two trenches BLT expose part of the sidewall of the trench C.
  • dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation and other processes may be used to form the second trench BLT that exposes part of the sidewalls of the channel C.
  • the depth of the groove GT in the third direction is less than half of the thickness of the channel C in the third direction. In practical applications, the depth of the groove GT in the third direction should be equivalent to the diffusion depth of the source S or drain D in the channel C along the third direction.
  • the second conductive material can be deposited in the second trench BLT through a PVD process, a CVD process or an ALD process, and the second conductive material can be subjected to a CMP process, so that the second conductive material The surface is flush with the surface of the second dielectric layer 207 to form the first first line BL1 surrounding the end of the channel C.
  • the second conductive material may be a metal material or a semiconductor conductive material, such as copper, cobalt, tungsten, molybdenum, doped silicon, polysilicon or any combination thereof.
  • Another memory manufacturing method provided by an embodiment of the present disclosure also includes:
  • a plurality of second memory cells 11 are formed on the first bit line BL1, and the plurality of second memory cells 11 are arranged in an array along the first direction and the second direction;
  • a second transistor array 21 is formed on the plurality of second memory cells 11; the second transistor array 21 is manufactured by the transistor manufacturing method described in the embodiment of the present disclosure; the second transistor array 21 is formed along the first The gates 205 of each row of transistors in the direction are physically connected to each other, and the physically connected gates form the second word line WL2; each of the second memory cells SC2 is respectively connected to a Source S or drain D connection;
  • a plurality of second bit lines BL2 are formed on the second transistor array 21 and are arranged in parallel along the second direction. Each of the second bit lines BL2 is connected to the second bit line BL2 along the second transistor array 21 .
  • the drains D or sources S of a row of transistors arranged in the second direction are connected.
  • the memory shown in Figure 4b can be understood as being formed by a three-dimensional stack of two structures shown in Figure 6g along the third direction.
  • the manufacturing method of the memory described in the embodiment of the present disclosure is not limited to manufacturing a specific number of three-dimensional stacks. It can also form a three-dimensional stack of two or more structures as shown in Figure 6g along the third direction. memory.
  • the manufacturing method of the memory provided by the embodiments of the present disclosure is similar to the memory in the above-mentioned embodiments.
  • technical features that are not disclosed in detail in the embodiments of the present disclosure please refer to the above-mentioned embodiments for understanding, and will not be described again here.
  • the channel including the first material layer and the second material layer in the embodiment of the present disclosure allows the transistor to have both a higher field effect mobility and a higher threshold voltage, thereby meeting the high performance requirements of the transistor.

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Abstract

本公开实施例提出了一种半导体结构及其制造方法、存储器及其制造方法，其中，所述半导体结构包括至少一个晶体管，所述晶体管，包括：沟道，所述沟道包括第一材料层和环绕所述第一材料层设置的第二材料层；所述第一材料层的电阻率大于第一预设值，所述第二材料层的电阻率小于第二预设值，所述第一预设值大于所述第二预设值；栅极，覆盖所述沟道的至少一个侧面；源极和漏极，位于所述沟道的延伸方向的两端。

Description

半导体结构及其制造方法、存储器及其制造方法
相关申请的交叉引用
本公开基于申请号为202210220471.8、申请日为2022年03月08日、发明名称为“半导体结构及其制造方法、存储器及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种半导体结构及其制造方法、存储器及其制造方法。
背景技术
随着半导体器件，如存储器尺寸的不断缩小，半导体器件中的晶体管尺寸也在被不断缩小，缩小的尺寸对晶体管的性能带来了更大的挑战。相关技术中的晶体管受限于尺寸，难以兼顾高性能。
发明内容
为解决相关技术问题，本公开实施例提出了一种半导体结构及其制造方法、存储器及其制造方法。
本公开实施例提供了一种半导体结构，所述半导体结构包括至少一个晶体管，所述晶体管包括：
沟道，所述沟道包括第一材料层和环绕所述第一材料层设置的第二材料层；所述第一材料层的电阻率大于第一预设值，所述第二材料层的电阻率小于第二预设值，所述第一预设值大于所述第二预设值；
栅极，覆盖所述沟道的至少一个侧面；
源极和漏极，位于所述沟道的延伸方向的两端。
上述方案中，所述半导体结构包括多个晶体管，所述多个晶体管对应的多个所述沟道沿第一方向和第二方向阵列排布；所述第一方向和所述第二方向均与所述沟道的延伸方向垂直；其中，
沿所述第一方向排布的每一排晶体管中每个晶体管的栅极相互物理连接；沿所述第一方向排布的相邻的两排晶体管的栅极之间相互电隔离。
上述方案中，所述第一材料层的材料和/或所述第二材料层的材料包含氧化铟、氧化镓、氧化锌、氧化铟镓、氧化铟锌、氧化镓锌、氧化铟镓锌中的至少一种。
上述方案中，所述栅极环绕所述沟道设置。
本公开实施例提供了一种晶体管的制造方法，所述半导体结构包括至少一个晶体管，所述晶体管的制造方法包括：
形成沟道，所述沟道包括第一材料层和环绕所述第一材料层设置的第二材料层；所述第一材料层的电阻率大于第一预设值，所述第二材料层的电阻率小于第二预设值，所述第一预设值大于所述第二预设值；
形成覆盖所述沟道的至少一个侧面的晶体管的栅极；
在所述沟道的延伸方向的两端分别形成所述晶体管的源极和漏极。
上述方案中，所述半导体结构包括多个晶体管，所述多个晶体管对应的多个所述沟道沿第一方向和第二方向阵列排布；所述第一方向和所述第二方向均与所述沟道的延伸方向垂直；其中，
沿所述第一方向排布的每一排晶体管中每个晶体管的栅极相互物理连接；沿所述第一方向排布的相邻的两排晶体管之间的栅极相互电隔离。
上述方案中，所述第一材料层的材料和/或所述第二材料层的材料包含氧化铟、氧化镓、氧化锌、 氧化铟镓、氧化铟锌、氧化镓锌、氧化铟镓锌中的至少一种。
上述方案中，所述形成沟道，包括：
提供第一介质层；
在所述第一介质层中形成第一孔；
在所述第一孔的侧壁和底部形成所述第二材料层；
填充形成有第二材料层的第一孔，形成所述第一材料层。
上述方案中，，在所述第一孔的侧壁和底部形成所述第二材料层，包括：
通过原子层沉积工艺，在无氧的气氛中，形成所述第二材料层，
填充形成有第二材料层的第一孔，形成所述第一材料层，包括：
通过原位沉积方式，在有氧的气氛中，形成所述第一材料层。
上述方案中，形成所述第一材料层之后，所述方法还包括：
部分刻蚀所述第一介质层，形成暴露的第二材料层；
在所述暴露的第二材料层上形成栅极氧化层；
依次填充第一导电材料和第二介质层，刻蚀所述第一导电材料和第二介质层形成凹槽，在所述凹槽中填充绝缘材料形成栅极隔离结构。
本公开实施例又提供了一种存储器，包括：
多个第一存储单元，沿第一方向和第二方向阵列排布；
第一晶体管阵列，位于所述多个第一存储单元上；所述第一晶体管阵列包括多个上述方案中所述的晶体管；所述第一晶体管阵列沿第一方向的每一排晶体管的栅极相互物理连接，所述物理连接的栅极形成第一字线；每一所述存储单元分别与所述晶体管阵列中一晶体管的源极或漏极连接；所述第一方向和所述第二方向均与所述晶体管的沟道的延伸方向垂直；
多条沿所述第二方向并列排布的第一位线，位于所述第一晶体管阵列上；每一所述第一位线分别与所述第一晶体管阵列中沿所述第二方向排布的一排晶体管的漏极或源极连接。
上述方案中，所述存储器包括：动态随机存取存储器、铁电存储器、相变存储器、磁变存储器或者阻变存储器。
上述方案中，所述存储器包括：动态随机存取存储器，所述存储器单元包括：电容；所述电容包括柱状的第二电极，覆盖所述第二电极侧壁及底部的电介质，以及覆盖所述电介质的第一电极。
上述方案中，所述存储器还包括多个第二存储单元、第二晶体管阵列，多条第二位线；其中，
所述多个第二存储单元位于所述第一位线上，且沿所述第一方向和所述第二方向阵列排布；
所述第二晶体管阵列位于所述多个第二存储单元上；所述第二晶体管阵列包括上述方案中所述的晶体管；所述第二晶体管阵列沿所述第一方向的每一排晶体管的栅极相互物理连接，所述物理连接的栅极形成第二字线；每一所述第二存储单元分别与所述第二晶体管阵列中一个晶体管的源极或漏极连接；
所述多条第二位线位于在所述第二晶体管阵列上，所述多条第二位线沿所述第二方向并列排布，每一所述第二位线分别与所述第二晶体管阵列中沿所述第二方向排布的一排晶体管的漏极或源极连接。
本公开实施例又提供了一种存储器的制造方法，所述方法包括：
形成多个第一存储单元，所述多个第一存储单元沿第一方向和第二方向阵列排布；
在所述多个第一存储单元上形成第一晶体管阵列；所述第一晶体管阵列通过上述方案中所述的晶体管的制造方法制造得到；所述第一晶体管阵列中沿所述第一方向的每一排晶体管的栅极相互物理连接，所述物理连接的栅极形成第一字线；每一所述第一存储单元分别与所述第一晶体管阵列中一个晶体管的源极或漏极连接；所述第一方向和所述第二方向均与所述晶体管的沟道的延伸方向垂直；
在所述第一晶体管阵列上形成多条沿所述第二方向并列排布的第一位线，每一所述第一位线分别与所述晶体管阵列中沿所述第二方向排布的一排晶体管的漏极或源极连接。
上述方案中，所述形成多条沿所述第二方向并列排布的第一位线，包括：
形成覆盖所述栅极的第二介质层；
部分蚀刻所述第二介质层，形成多个均沿所述第二方向延伸的第二沟槽；所述第二沟槽使得所述沟道的部分侧壁暴露；
在所述第二沟槽中填充第二导电材料，形成环绕所述沟道端部的所述位线。
上述方案中，所述第一存储单元包括电容；
所述形成多个第一存储单元，包括：
提供第三介质层；
在所述第三介质层中形成沿所述第一方向和所述第二方向阵列排布的多个第二孔；
在所述第二孔的侧壁和底部以及所述第三介质层的顶面形成第一电极；
在所述第一电极上形成电介质层；
填充形成有所述第一电极和所述电介质层的第二孔，形成多个第二电极；每一所述第二电极分别与所述晶体管阵列中一个晶体管的源极或漏极连接。
上述方案中，所述方法包括：
在所述第一位线上形成多个第二存储单元，所述多个第二存储单元沿所述第一方向和所述第二方向阵列排布；
在所述多个第二存储单元上形成第二晶体管阵列；所述第二晶体管阵列通过上述方案中所述晶体管的制造方法制造得到；第二晶体管阵列中沿所述第一方向的每一排晶体管的栅极相互物理连接，所述物理连接的栅极形成第二字线；每一所述第二存储单元分别与所述第二晶体管阵列中一个晶体管的源极或漏极连接；
在所述第二晶体管阵列上形成多条沿所述第二方向并列排布的第二位线，每一所述第二位线分别与所述第二晶体管阵列中沿所述第二方向排布的一排晶体管的漏极或源极连接。
本公开实施例提出了一种半导体结构及其制造方法、存储器及其制造方法，其中，所述半导体结构包括至少一个晶体管，所述晶体管，包括：沟道，所述沟道包括第一材料层和环绕所述第一材料层设置的第二材料层；所述第一材料层的电阻率大于第一预设值，所述第二材料层的电阻率小于第二预设值，所述第一预设值大于所述第二预设值；栅极，覆盖所述沟道的至少一个侧面；源极和漏极，位于所述沟道的延伸方向的两端。本公开各实施例中，晶体管的源极、漏极沿晶体管延伸方向设置，从而单个晶体管在水平方向上所占的面积减少，单位面积内可设置的晶体管的数量增加，如此，可以满足晶体管小尺寸的需求；同时，沟道的构成包括不同电阻率的第一材料层和第二材料层，低电阻率的第二材料层有助于提高所述晶体管的阈值电压，高电阻率的第一材料层有助于提高所述晶体管的场效应迁移率，本公开实施例中包括第一材料层和第二材料层的沟道使得晶体管兼具有较高的场效应迁移率和较高的阈值电压，从而可以满足晶体管高性能的需求。
附图说明
图1a为本公开实施例提供的一种半导体结构的立体结构示意图；
图1b为本公开实施例提供的另一种半导体结构的立体结构示意图；
图2为本公开实施例提供的一种半导体结构的制造方法的实现流程示意图；
图3a至图3j为本公开实施例提供的一种半导体结构的制造过程的立体结构示意图；
图4a为本公开实施例提供的一种存储器的立体结构示意图；
图4b为本公开实施例提供的另一种存储器的立体结构示意图；
图5为本公开实施例提供的一种半导体结构的制造方法的实现流程示意图；
图6a至图6g为本公开实施例提供的一种存储器的制造过程的立体结构示意图。
附图标记说明
10-存储单元/电容；100-衬底；101-第三介质层；SCH-第二孔；102-第一电极；103-电介质层；104-第二电极；SC-电容；
20-晶体管/晶体管阵列；201-第一介质层；CH-第一孔；C-沟道；202-第二材料层；203-第一材料层；S-源极；D-漏极；204-栅极氧化层；205-栅极；206-栅极隔离结构；207-第二介质层；AT/AT1/AT2-每一排晶体管；GT-凹槽；GIT-栅极隔离槽/凹槽；
30-存储器；10-多个第一存储单元；11-多个第二存储单元；20-第一晶体管阵列；21-第二晶体管阵列；BLT-第二沟槽；BL1-第一位线；BL2-第二位线；WL1-第一字线；WL1-第二字线；SC1-第一存储单元/电容；SC2-第二存储单元/电容。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例 性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了能够更加详尽地了解本公开实施例的特点与技术内容，下面结合附图对本公开实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本公开实施例。
晶体管可以被用在各种存储器中，例如，动态随机存取存储器(Dynamic Random Access Memory，DRAM，DRAM)。通常，DRAM是包括1个晶体管T(Transistor)和1个电容C(Capacitance)(1T1C)的架构。
随着存储器的尺寸减小，存储区域的晶体管尺寸也在不断缩小，晶体管的尺寸越做越小，受限于晶体管的沟道尺寸影响，相关技术中的晶体管难以具有高性能。具体地，一些晶体管，如薄膜晶体管(Thin-Film Transistors，TFTs)的场效应迁移率(Field-Effect mobility，μFE)高，但是阈值电压(threshold Voltage，Vth)低；或者，另一些晶体管的Vth高，但是μFE较低。相关技术中的晶体管不能兼具高μFE和高Vth，难以满足高性能的要求。为了解决上述问题中的至少之一，本公开实施例提供了一种半导体结构及其制造方法、存储器及其制造方法。
本公开实施例提供一种半导体结构，图1a为本公开实施例提供的一种半导体结构的立体结构示意图(可以理解为沿X-Z平面和Y-Z平面分别对半导体结构中一个晶体管进行剖开的立体示意图)，所述半导体结构包括至少一个晶体管，所述晶体管20包括：
沟道C，所述沟道C包括第一材料层203和环绕所述第一材料层203设置的第二材料层202；所述第一材料层203的电阻率大于第一预设值，所述第二材料层202的电阻率小于第二预设值，所述第一预设值大于所述第二预设值；
栅极205，覆盖所述沟道的至少一个侧面；
源极S和漏极D，位于所述沟道C的延伸方向的两端。
需要说明的是，本公开实施例提供的晶体管可以包括垂直晶体管，栅极为掩埋栅极的晶体管。图1a中除了对晶体管的各组成部件进行了示意，还示出了掩埋栅极205所需要的介质层(如下文所述的第一介质层201，以及第二介质层207)。
这里，所述沟道C中所述第一材料层203和所述第二材料层202对于所述晶体管性能提高的侧重点有所不同。电阻率大于第一预设值的所述第一材料层203，设置于所述沟道C内侧(理解为在X-Y平面内沿沟道径向方向指向沟道芯部)远离所述栅极205的一侧，主要用于包括提高所述晶体管的阈值电压Vth，电阻率小于第二预设值的所述第二材料层202，设置于所述沟道C外侧(理解为在X-Y平面内沿沟道径向方向远离沟道芯部)靠近所述栅极205的一侧，主要用于包括提高所述晶体管的电子迁移率μFE。
可以理解的是，本公开实施例中，包括电阻率差异化设置的第一材料层203和第二材料层202的所述沟道C可以使得所述晶体管兼具满足要求的高μFE和高Vth。当在高电阻率的第一材料层203 的外侧形成连续平滑的低电阻率的第二材料层202时，由于缺陷的钝化和高质量的同质结界面，开关(ON/OFF)比、Vth和μFE显着提高。第二材料层202不仅影响Vth的值，对μFE的影响也很大。
这里，所述第一预设值为一个较高的电阻率值，所述第二预设值为一个较高的电阻率值。实际应用中，所述第一预设值和所述第二预设值可以根据实际情况进行调整。在一些实施例中，所述第一预设值可以为100MΩ·cm，所述第二预设值可以为0.1Ω·cm。也就是说，所述第一材料层203的电阻率大于100MΩ·cm，所述第二材料层202的电阻率小于0.1Ω·cm。
实际应用中，可以通过材料选择、掺杂浓度(P型/N型载流子)选择、制造工艺参数(氧化性气氛/还原性气氛)选择得到满足电阻率需求的所述第一材料层203和所述第二材料层202。
示例性地，当选择的材料本身就具有高电阻率，则其较适合用于形成所述第二材料层202，当选择的材料本身就具有低电阻率，则其较适合用于形成所述第二材料层202。
示例性地，当载流子的掺杂浓度较低易形成高电阻率的材料层，当载流子的掺杂浓度较高易形成低电阻率的材料层。由此，在形成高电阻率的所述第一材料层203时，可以在其形成过程中给予较高的载流子掺杂浓度；在形成低电阻率的所述第二材料层202时，可以在其形成过程中给予较高的载流子掺杂浓度。
示例性地，在氧化性气氛(有氧气氛中)中易形成高电阻率的材料层，在还原性性气氛(无氧气氛中)中易形成低电阻率的材料层。由此，在形成高电阻率的所述第一材料层203时，可以在氧化性气氛进行；在形成低电阻率的所述第二材料层202时，可以在无氧气氛中进行。
实际应用中，所述第一材料层203的厚度比较厚，而第二材料层202的厚度比较薄。在一些实施例中，所述第一材料层203的沿所述沟道孔径向方向上的厚度为所述第二材料层202的沿所述沟道孔径向方向上的厚度的1倍-10倍。考虑到，在低电阻率的第二材料层的厚度增加超过约10nm后，影响变弱。在一些实施例中，所述第二材料层的沿所述沟道孔径向方向上的厚度范围为1nm-10nm，所述第一材料层的沿所述沟道孔径向方向上的厚度范围为10nm-100nm。
在一些实施例中，所述第一材料层203的材料与所述第二材料层202的材料可以相同，也可以不同。
在一些实施例中，所述第一材料层的材料和/或所述第二材料层的材料包含非晶半导体材料。需要说明的是，非晶半导体材料相对于晶体(如单晶、多晶)半导体材料具有较高的μFE。在一些实施例中，所述第一材料层203的材料和/或所述第二材料层202的材料包含氧化铟、氧化镓、氧化锌、氧化铟镓、氧化铟锌、氧化镓锌、氧化铟镓锌中的至少一种；或者，所述第一材料层203的材料和/或第二材料层202的材料包含氧化铟、氧化镓、氧化锌、氧化铟镓、氧化铟锌、氧化镓锌、氧化铟镓锌中的至少一种化合物掺杂钴、镍、锡、铝、镁、锆、铪、钛、钽、钨元素中的至少一种元素形成的混合物。
在一具体示例中，所述第一材料层203和所述第二材料层202的材料可以均为氧化铟镓锌(IGZO)。
可以理解的是，氧化铟镓锌可以驱动大量电流，这使得氧化铟镓锌晶体管用在存储器中时，存储器的写入速度更快，并且当氧化铟镓锌晶体管关闭时，泄漏的电荷很少，这使得比特的使用寿命更长。
在一些实施例中，所述栅极205环绕所述沟道C设置。也就是说，本公开实施例中的垂直晶体管具体可以是全环绕型栅极晶体管。需要说明的是，本公开实施例中的垂直晶体管并不限于全环绕型栅极晶体管，还可以包括其他类型的垂直晶体管，如半环绕型栅极晶体管，柱型栅极晶体管等。实际应用中，所述栅极205与所述沟道C之间，即所述栅极205与所述第二材料层202之间还形成有栅极氧化层204。
在一些实施例中，如图1a所示，源极S和漏极D的位置可以互换。源极S位于所述沟道C的第一端；漏极D位于所述沟道C的第二端；或者，漏极D位于所述沟道C的第一端；源极S位于所述沟道C的第二端。其中，所述第一端和所述第二端分别为所述沟道C在第三方向上相对的两端。这里，所述第三方向为所述沟道C的延伸方向。
请参考图1b，在一些实施例中，所述半导体结构包括多个晶体管，所述多个晶体管对应的多个所述沟道C沿第一方向X和第二方向Y阵列排布；所述第一方向X和所述第二方向Y均与所述沟道C的延伸方向垂直；其中，
沿所述第一方向排布的每一排晶体管AT中每个晶体管的栅极相互物理连接；沿所述第一方向排布的相邻的两排晶体管AT1、AT2的栅极之间相互电隔离。
实际应用中，图1b中还示出了掩埋栅极205所需要的介质层(如下文所述的第一介质层201，栅极隔离结构206以及第二介质层207)。可以理解的是，沿所述第一方向X排布的每一排晶体管AT中每个晶体管的栅极205相互物理连接构成了字线，所述字线构成为埋入式字线(Buried Word Line)；沿所述第一方向X排布的相邻的两排晶体管AT1、AT2的栅极205之间被所述栅极隔离结构206电隔离；沿所述第三方向Z上所述栅极205通过所述第一介质层201和所述第二介质层207与其他部件相隔离。
在一些实施例中，所述第一方向与所述第二方向相交，所述第一方向与所述第二方向之间的夹角可以为0-90度之间的任意角度；例如，所述第一方向可以垂直于所述第二方向。可以理解的是，所述第一方向与所述第二方向之间的夹角构建了所述晶体管的沿所述第一方向与所述第二方向的阵列排布的位置关系。
这里及下文中，为了便于描述本公开实施例中第一方向和第二方向表示为与衬底平面平行的两个正交方向；第三方向为垂直于衬底平面的方向，也就是第三方向为所述沟道的延伸方向；其中，所述衬底平面可以理解为与所述沟道的延伸方向垂直的平面。第一方向表示为附图中的X方向；第二方向表示为附图中的Y方向；第三方向表示为附图中的Z方向。
在一些实施例中，所述沟道C沿垂直于所述第三方向且穿过沟道C的横截面形状可以是圆形、方形、椭圆形或者菱形。实际应用中，可以根据具体工艺进行选择；例如通过图案化工艺蚀刻形成圆形的沟道孔，在所述圆形的沟道孔中沉积形成所述沟道C，所述沟道C沿垂直于所述第三方向且穿过沟道C的横截面形状为圆形。
本公开各实施例中，晶体管的源极、漏极沿晶体管延伸方向设置，从而单个晶体管在水平方向上所占的面积减少，单位面积内可设置的晶体管的数量增加，如此，可以满足晶体管小尺寸的需求；同时，沟道的构成包括不同电阻率的第一材料层和第二材料层，低电阻率的第二材料层有助于提高所述晶体管的阈值电压，高电阻率的第一材料层有助于提高所述晶体管的场效应迁移率，本公开实施例中包括第一材料层和第二材料层的沟道使得晶体管道兼具有较高的场效应迁移率和较高的阈值电压，从而可以满足晶体管高性能的需求。
本公开上述实施例中提供的晶体管包括不同电阻率的第一材料层和第二材料层构成的沟道；进一步地，通过对第一材料层和/或第二材料层的电阻率值、厚度、材料构成等参数进行适当地选择，可以进一步地提高晶体管的μFE和Vth，得到性能更高的晶体管。
本公开实施例所提供的半导体结构可以通过下述实施例提供的半导体结构的制造方法形成。本公开实施例提供的半导体结构的制造方法制造得到的半导体结构与上述实施例中的半导体结构类似，对于本公开实施例未详尽披露的技术特征，请参照上述实施例进行理解，这里，不再赘述。
可以理解的是，本公开实施例中所描述的半导体结构的制造方法并不局限于制作某一具体数量的晶体管：可以是制作单一晶体管的制造方法，也可以是制作晶体管阵列的制造方法。以下行文中及附图以制作晶体管阵列的制造方法进行示例性的描述。图3a至图3j为本公开实施例提供的一种半导体结构的制造过程的立体结构示意图。应当理解，图3a至图3j中所示的步骤并非排他的，也可以在所示操作中的任何步骤之前、之后或之间执行其他步骤；图3a至图3j中所示的各步骤可以根据实际需求进行顺序调整。
下面结合图2和图3a至图3j对本公开实施例提供的半导体结构的制造方法进行详细地说明。
图2为本公开实施例提供的一种半导体结构的制造方法的实现流程示意图；图3a至图3j对本公开实施例提供的半导体结构的制造过程的立体结构示意图。
请参考图2，在一些实施例中，所述半导体结构包括至少一个晶体管，所述晶体管的制造方法包括：
步骤2001，形成沟道；所述沟道包括第一材料层和环绕所述第一材料层设置的第二材料层；所述第一材料层的电阻率大于第一预设值，所述第二材料层的电阻率小于第二预设值，所述第一预设值大于所述第二预设值；
步骤2002，形成覆盖所述沟道的至少一个侧面的晶体管的栅极；
步骤2003，在所述沟道的延伸方向的两端分别形成所述晶体管的源极和漏极。
执行步骤2001，如图3a至图3d所示，形成所述沟道C。
在一些实施例中，所述形成沟道C，包括：
提供第一介质层201；
在所述第一介质层201中形成第一孔CH；
在所述第一孔CH的侧壁和底部形成所述第二材料层202；
填充形成有第二材料层202的第一孔，形成所述第一材料层203。
请参考图3a，提供第一介质层201，所述第一介质层201的材料可以包括但不限于氧化硅。实际应用中，所述第一介质层201可以通过物理气相沉积(Physical Vapor Deposition，PVD)工艺、化学气相沉积(Chemical Vapor Deposition，CVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)等工艺形成。
在一些实施例中，所述第一介质层201可以根据器件的实际需求进行选择在衬底上形成。所述衬底(未示出)的材料可以包括硅(Si)、锗(Ge)、锗化硅(SiGe)衬底等；所述衬底(未示出)的还可以是绝缘体上硅(Silicon-on-insulator，SOI)或者绝缘体上锗(Germanium-on-Insulator，GOI)，所述衬底中根据需要掺杂一定的杂质离子，所述杂质离子可以为N型杂质离子或P型杂质离子；在一实施例中，所述掺杂包括阱区掺杂和源漏区掺杂，在所述衬底中形成有源层(未示出)。在另一些实施例中，所述第一介质层201也可以不衬底上形成，如也可以在其他功能薄膜层上形成。
请参考图3b，在所述第一介质层201中形成第一孔CH；可以通过蚀刻工艺形成贯穿所述第一介质层201的第一孔CH。实际应用中，可以用干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀等工艺在所述第一介质层201中形成第一孔CH。
请参考图3c和图3d，在所述第一孔CH的侧壁和底部形成所述第二材料层202；填充形成有第二材料层202的第一孔CH，形成所述第一材料层203。可通过一种或多种沉积工艺形成第二材料层202和所述第一材料层203。该工艺包括但不限于PVD工艺、CVD工艺、ALD工艺或其任何组合。例如，可以通过原子层沉积工艺形成第二材料层202和第一材料层203。
在一些实施例中，在所述第一孔的侧壁和底部形成所述第二材料层，包括：通过原子层沉积工艺，在无氧的气氛中，形成所述第二材料层；
填充形成有第二材料层的第一孔，形成所述第一材料层，包括：通过原位沉积方式，在有氧的气氛中，形成所述第一材料层。实际应用中，通过原子层沉积工艺，在无氧的气氛中，通入含有所述第二材料层202的材料的反应气体，在所述第一孔CH的侧壁和底部形成具有所述第二材料层202；紧接着，停止通入含有所述第二材料层202的材料的反应气体，并通入含有所述第一材料层203的材料的反应气体，与此同时通入一定比例的氧气，这样通过原位沉积方式，在有氧的气氛中，在所述第二材料层202上形成所述第一材料层203。可以理解的是，所述第一材料层203和所述第二材料层202的电阻率受其形成时周围气氛(如氧化性气体或还原性气体)影响而明显改变。以此，通过无氧的气氛(实际应用中非绝对的无氧，而是尽可能的控制气氛中的氧含量低至工艺可接受的范围)中形成的所述第二材料层202的电阻率较低；控制通入一定比例的氧气的方式，调控所述第一材料层203的电阻率，通入的氧气含有越大形成的所述第一材料层203的电阻率越大。
需要说明的是，对于本公开实施例未详尽披露的所述第一材料层203和所述第二材料层202相关的技术特征：如电阻率、厚度、材料构成等参数选择，请参照前述实施例进行理解，这里，不再赘述。
执行步骤2002和2003，如图3e至图3j所示，形成覆盖所述沟道的至少一个侧面的晶体管的栅极；在所述沟道的延伸方向的两端分别形成所述晶体管的源极和漏极。
在一些实施例中，形成所述第二材料层202之后，所述方法还包括：
部分刻蚀所述第一介质层201，形成暴露的第二材料层202；
在所述暴露的第二材料层202上形成栅极氧化层204；
依次填充第一导电材料和第二介质层207，刻蚀所述第一导电材料和第二介质层形成凹槽，在所述凹槽中填充绝缘材料形成栅极隔离结构206。
请参考图3e，部分刻蚀所述第一介质层201，形成暴露的第二材料层202；可以通过蚀刻工艺形成凹槽GT，以暴露的第二材料层202的侧壁。实际应用中，可以用干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀等工艺形成暴露的第二材料层202的侧壁的所述凹槽GT。
在一些实施例中，所述凹槽GT在所述第三方向上并不贯穿所述第一介质层201。实际应用中，所述凹槽GT在所述第三方向上的深度可以小于所述沟道C在所述第三方向上厚度。
请参考图3f，在所述暴露的第二材料层202上形成栅极氧化层204；可以通过原位氧化所述第二材料层202在相应凹槽GT中具有裸露侧壁的方式，至少在每一所述沟道C的裸露的侧壁(也即所述第二材料层202的裸露的侧壁)形成栅极氧化层204。
这里，可以通过加热或者加压的方式，对每一所述沟道C的裸露的侧壁(也即所述第二材料层202的裸露的侧壁)进行原位氧化，形成栅极氧化层二氧化硅。
在一些实施例中，所述栅极氧化层204环绕所述沟道C设置，即所述栅极氧化层204环绕于所 述第二材料层202而形成。
请参考图3g和图3h，依次填充第一导电材料205’和第二介质层207；可以通过PVD工艺、CVD工艺或ALD等工艺在形成了具有栅极氧化层204的凹槽GT中沉积第一导电材料205’，再通过回蚀刻工艺，在形成了具有栅极氧化层204和第一导电材料205’的凹槽GT中沉积第二介质层207。
这里，所述第一导电材料205’可以是金属材料或者半导体导电材料，例如，铜、钴、钨、钼、掺杂硅、多晶硅或其任何组合等；所述第二介质层207的材料包括但不限于氮化硅、氮氧化硅、碳化硅、二氧化硅或其任何组合等。
请参考图3i，刻蚀所述第一导电材料205’和第二介质层207形成凹槽GIT；可以通过蚀刻工艺形成凹槽GIT，所述凹槽GIT在所述第三方向上贯穿所述第一导电材料205’。实际应用中，可以用干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀等工艺形成在所述第三方向上贯穿所述第一导电材料205’的所述凹槽GIT。可以理解的是，所述凹槽GIT将所述第一导电材料205’分隔为多个所述栅极205，在所述第一方向上相邻的所述栅极205被所述凹槽GIT分隔开。
在一些实施例中，所述凹槽GIT在所述第三方向上同时贯穿所述第一导电材料205’和所述第一介质层201；所述凹槽GIT在所述第一方向上同时将所述第一导电材料205’和所述第一介质层201。
在一些实施例中，所述栅极205环绕所述沟道C设置。实际应用中，所述栅极205与所述沟道C之间，即所述栅极205与所述第二材料层202之间还形成有栅极氧化层204。
请参考图3j，在所述凹槽GIT中填充绝缘材料形成栅极隔离结构206；可以通过PVD工艺、CVD工艺或ALD等工艺在所述凹槽GT中沉积绝缘材料，对所述绝缘材料进行化学机械抛光(Chemical Mechanical Polishing，CMP)处理，使得所述绝缘材料的表面与所述第二介质层207的表面平齐，形成所述栅极隔离结构206。这里，所述绝缘材料包括但不限于氮化硅、氮氧化硅、碳化硅或者二氧化硅等。
在一些实施例中，所述半导体结构包括多个晶体管，所述多个晶体管对应的多个所述沟道C沿第一方向X和第二方向Y阵列排布；所述第一方向X和所述第二方向Y均与所述沟道C的延伸方向垂直；其中，
沿所述第一方向排布的每一排晶体管AT中每个晶体管的栅极相互物理连接；沿所述第一方向排布的相邻的两排晶体管AT1、AT2的栅极之间相互电隔离。
可以理解的是，本公开实施例中所描述的晶体管阵列的制造方法用于制造包括并不局限于制作某一具体数量的晶体管，也可以是制作单一晶体管的制造方法。本公开实施例中晶体管阵列(上述图1b)的制造方法参考前述图3a至图3j的步骤进行理解，这里，不再赘述。
应当理解的是，参考前述图3a至图3j的步骤进行制作单一晶体管的制作过程中，有些步骤是可以不需要，例如图3i和图3j中形成的栅极隔离结构206是不必要的。本公开实施例中单个晶体管(上述图1a)制造方法参考前述图3a至图3h的步骤进行理解，这里，不再赘述。
本公开实施例提供一种存储器，图4a为本公开实施例提供的一种存储器的立体结构示意图。
请参考图4a，在一些实施例中，所述存储器30包括：多个第一存储单元10，沿第一方向和第二方向阵列排布；
第一晶体管阵列20，位于所述多个第一存储单元10上；所述第一晶体管阵列20包括多个本公开实施例所述的晶体管；所述第一晶体管阵列20沿第一方向的每一排晶体管的栅极205相互物理连接，所述物理连接的栅极形成第一字线WL1；每一所述存储单元SC分别与所述晶体管阵列20中一晶体管的源极S或漏极D连接；所述第一方向和所述第二方向均与所述晶体管的沟道C的延伸方向垂直；
多条沿所述第二方向并列排布的第一位线BL1，位于所述第一晶体管阵列20上；每一所述第一位线BL1分别与所述第一晶体管阵列20中沿所述第二方向排布的一排晶体管的漏极D或源极S连接。
实际应用中，所述第一字线WL1与每一所述晶体管阵列20的栅极205连接，所述第一字线WL1用于提供字线电压，并通过所述字线电压控制每一所述晶体管中所述沟道区的导通或截止。沿所述第一方向X延伸的所述第一位线BL1与每一所述晶体管阵列20的漏极D连接，所述第一位线BL1用于在每一所述晶体管导通时，对所述存储单元10执行读取或写入操作。
本公开实施例中，所述第一字线WL1和所述第一位线BL1的材料包括但不限于钨、钴、钼、铜、铝、多晶硅、掺杂硅、硅化物或其任何组合。
可以理解的是，在所述存储器中，如果每一所述存储单元SC分别与所述晶体管阵列20中一晶体管的源极S连接，则每一所述第一位线BL1分别与所述第一晶体管阵列20中沿所述第二方向排布的一排晶体管的漏极D连接；或者，如果每一所述存储单元SC分别与所述晶体管阵列20中一晶体管的漏极D连接，则每一所述第一位线BL1分别与所述第一晶体管阵列20中沿所述第二方向排布的一排晶体管的源极S连接。
在一些实施例中，本公开实施例提供的存储器包括各种类型的存储器。例如，NAND闪存(Flash)、Nor Flash、DRAM、静态随机存取存储器(Static Random Access Memory，SRAM)、相变存储器(Phase-Change Memory，PCM)、铁电存储器、磁变存储器或者阻变存储器。
在一些实施例中，所述存储器包括：DRAM，所述存储器单元包括：电容SC；所述电容SC包括柱状的第二电极104，覆盖所述第二电极104侧壁及底部的电介质层103，以及覆盖所述电介质103的第一电极102。实际应用中，可以是所述第二电极104端所述晶体管阵列中一晶体管的源极S连接，所述第一电极102端接地，所述电容SC用于存储写入的数据。
在一些实施例中，所述存储器包括阻变存储器，所述存储单元包括可调电阻，所述可调电阻连接于所述第一位线BL1和所述晶体管阵列20中一晶体管的源极S之间；或者，所述可调电阻连接于所述第一位线BL1和所述所述晶体管阵列20中一晶体管的漏极D之间，所述可调电阻用于通过所述第一位线BL1提供的位线电压调节存储的数据的状态。
本公开实施例中，只是示例性地列举了一些常见的存储器，本公开的保护范围不限于此，任何包含本公开实施例提供的晶体管的存储器均属于本公开的保护范围。
如实际应用中，为了提高存储器的集成度，所述存储器可以包括多层堆叠的存储单元，如两层沿第三方向堆叠的存储单元。
在一些实施例中，如图4b所示，所述存储器还包括多个第二存储单元11、第二晶体管阵列21，多条第二位线BL2；其中，
所述多个第二存储单元11位于所述第一位线BL1上，且沿所述第一方向和所述第二方向阵列排布；
所述第二晶体管阵列21位于所述多个第二存储单元11上；所述第二晶体管阵列21包括本公开实施例提供的晶体管；所述第二晶体管阵列21沿所述第一方向的每一排晶体管的栅极205相互物理连接，所述物理连接的栅极形成第二字线WL2；每一所述第二存储单元SC2分别与所述第二晶体管阵列21中一个晶体管的源极S或漏极D连接；
所述多条第二位线BL2位于在所述第二晶体管阵列21上，所述多条第二位线BL2沿所述第二方向并列排布，每一所述第二位线BL2分别与所述第二晶体管阵列21中沿所述第二方向排布的一排晶体管的漏极D或源极S连接。
本公开各实施例中，晶体管可以在相对较低的温度下制造，因此与后段工艺兼容。这使能够将存储器的外围移动到存储单元阵列下方，这大大减少了存储器芯片的占用空间。此外，后段工艺处理开辟了堆叠单个DRAM元的路线，从而实现了三维3D-DRAM架构。本公开实施例提供的DRAM能够在云计算和人工智能等要求苛刻的应用中发挥关键作用。
下面结合图5和图6a至图6g对本公开实施例提供的存储器的制造方法进行详细地说明。
图5为本公开实施例提供的一种半导体结构的制造方法的实现流程示意图；图6a至图6g为本公开实施例提供的一种存储器的制造过程的立体结构示意图。
请参考图5，在一些实施例中，所述制造方法包括：
步骤5001，形成多个第一存储单元10，所述多个第一存储单元10沿第一方向和第二方向阵列排布；
步骤5002，在所述多个第一存储单元10上形成第一晶体管阵列20；所述第一晶体管阵列20通过本公开实施例所述的晶体管的制造方法制造得到；所述第一晶体管阵列20中沿所述第一方向的每一排晶体管的栅极205相互物理连接，所述物理连接的栅极205形成第一字线WL1；每一所述第一存储单元10分别与所述第一晶体管阵列20中一个晶体管的源极S或漏极D连接；所述第一方向和所述第二方向均与所述晶体管的沟道C的延伸方向垂直；
步骤5003，在所述第一晶体管阵列20上形成多条沿所述第二方向并列排布的第一位线BL1，每一所述第一位线BL1分别与所述晶体管阵列20中沿所述第二方向排布的一排晶体管的漏极D或源极S连接。
执行步骤5001，形成多个第一存储单元10，所述多个第一存储单元10沿第一方向和第二方向阵列排布。请参考图6a至图6d为本公开实施例提供的一种电容(可理解为存储单元)的制造过程 的立体结构示意图。
在一些实施例中，请参考图6d，所述第一存储单元包括电容SC；
所述形成多个第一存储单元10，包括：
提供第三介质层101；
在所述第三介质层101中形成沿所述第一方向和所述第二方向阵列排布的多个第二孔SCH；
在所述第二孔SCH的侧壁和底部以及所述第三介质层101的顶面形成第一电极102；
在所述第一电极102上形成电介质层103；
填充形成有所述第一电极102和所述电介质层103的第二孔SCH，形成多个第二电极104；每一所述第二电极104分别与所述晶体管阵列中一个晶体管的源极或漏极连接。
请参考图6a，提供第三介质层101，所述第三介质层101的材料可以包括但不限于氧化硅。实际应用中，所述第三介质层101可以通过PVD工艺、CVD工艺、ALD等工艺形成。
在一些实施例中，所述第三介质层101可以根据器件的实际需求选择在是否在衬底100上形成。所述衬底100的材料可以参照前述的衬底的材料。
请参考图6b，在所述第三介质层101中形成沿所述第一方向和所述第二方向阵列排布的多个第二孔SCH；可以通过蚀刻工艺形成贯穿所述第三介质层101的第二孔SCH。实际应用中，可以用干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀等工艺在所述第三介质层101中形成第二孔SCH。
请参考图6c，在所述第二孔SCH的侧壁和底部以及所述第三介质层101的顶面形成第一电极102；在所述第一电极102上形成电介质层103。可通过一种或多种沉积工艺依次形成所述第一电极102和所述电介质层103。该工艺包括但不限于PVD工艺、CVD工艺、ALD工艺或其任何组合。例如，可以通过原子层沉积工艺形成所述第一电极102和所述电介质层103。
实际应用中，所述第一电极102的材料可以是金属材料或者半导体导电材料，例如，铜、钴、钨、掺杂硅、多晶硅或其任何组合等。
这里，所述电介质层103的材料可以是具有比SiO 2(k～3.9)更大的介电常数的介电材料。实际应用中，所述电介质层103的材料可以包括Ta 2O 5(k～26)、TiO 2(k～80)、ZrO 2(k～25)、Al 2O 3(k～9)、HfSiO x(k～4-25)和HfO 2(k～25)。
请参考图6d，填充形成有所述第一电极102和所述电介质层103的第二孔SCH，形成多个第二电极104；可通过一种或多种沉积工艺，在形成有所述第一电极102和所述电介质层103的第二孔SCH中沉积第二电极材料，对所述第二电极材料进行CMP工艺处理，使得所述第二电极材料的表面与所述电介质层103的表面平齐，形成所述第二电极104。该工艺包括但不限于PVD工艺、CVD工艺、ALD工艺或其任何组合。例如，可以通过原子层沉积工艺形成第二电极104。实际应用中，所述第二电极材料可以是金属材料或者半导体导电材料，例如，铜、钴、钨、钼、掺杂硅、多晶硅或其任何组合等。
所述电容(可理解为所述第一存储单元10中的电容SC)包括在每个所述第二孔SCH中形成的第一电极102、电介质层103、第二电极104。
实际应用中，所述电容的第二电极104与所述晶体管阵列中一晶体管的源极S连接，所述电容的第一电极102接地，所述电容用于存储写入的数据。
执行步骤5002，请参考图6e，在所述多个第一存储单元10上形成第一晶体管阵列20；所述第一晶体管阵列20通本公开实施例所述的晶体管的制造方法制造得到；所述第一晶体管阵列20中沿所述第一方向的每一排晶体管的栅极205相互物理连接，所述物理连接的栅极205形成第一字线WL1；每一所述第一存储单元10分别与所述第一晶体管阵列20中一个晶体管的源极S或漏极D连接；所述第一方向和所述第二方向均与所述晶体管的沟道C的延伸方向垂直。
需要说明的是，图3f至图3j以及图1a至图1b中，所述第一晶体管阵列20中示出了栅极氧化层204。为了便于行文方便，图6e至图6g以及图4a至图4b中，所述第一晶体管阵列20(和/或所述第二晶体管阵列21)中仅示出了栅极与沟道之间的栅极氧化层204，并与所述的第一介质层201、栅极隔离结构206以及第二介质层207未做填充底色的区分。实际应用中，栅极氧化层204、第一介质层201、栅极隔离结构206以及第二介质层207的材料均为绝缘材料，它们的材料可以相同也可以不同。
执行步骤5003，在所述第一晶体管阵列20上形成多条沿所述第二方向并列排布的第一位线BL1，每一所述第一位线BL1分别与所述晶体管阵列20中沿所述第二方向排布的一排晶体管的漏极D或源极S连接。
在一些实施例中，如图6f和图6g所示，所述形成多条沿所述第二方向并列排布的第一位线BL1，包括：
形成覆盖所述栅极205的第二介质层207；
部分蚀刻所述第二介质层207，形成多个均沿所述第二方向延伸的第二沟槽BLT；所述第二沟槽BLT使得所述沟道C的部分侧壁暴露；
在所述第二沟槽BLT中填充第二导电材料，形成环绕所述沟道C端部的所述第一位线BL1。
在一些实施例中，可以通过蚀刻工艺去除所述部分所述第二介质层207以及部分栅极隔离结构206，形成多个均沿所述第二方向延伸的第二沟槽BLT，所述第二沟槽BLT使得所述沟道C的部分侧壁暴露。实际应用中，可以用干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀等工艺形成暴露的所述沟道C的部分侧壁的所述第二沟槽BLT。
在一些实施例中，所述凹槽GT在所述第三方向上的深度小于所述沟道C在所述第三方向上厚度的二分之一。实际应用中，所述凹槽GT在所述第三方向上的深度应与所述源极S或漏极D在所述沟道C中沿所述第三方向上的扩散深度相当。
实际应用中，可以通过PVD工艺、CVD工艺或ALD等工艺在所述第二沟槽BLT中沉积第二导电材料，对所述第二导电材料进行CMP工艺处理，使得所述第二导电材料的表面与所述第二介质层207的表面平齐，形成环绕所述沟道C端部的所述第一位线BL1。本公开实施例中，所述第二导电材料可以是金属材料或者半导体导电材料，例如，铜、钴、钨、钼、掺杂硅、多晶硅或其任何组合等。
在一些实施例中，请参考上述图4b，本公开实施例提供的另一种存储器的制造方法还包括：
在所述第一位线BL1上形成多个第二存储单元11，所述多个第二存储单元11沿所述第一方向和所述第二方向阵列排布；
在所述多个第二存储单元11上形成第二晶体管阵列21；所述第二晶体管阵列21通过本公开实施例所述晶体管的制造方法制造得到；第二晶体管阵列21中沿所述第一方向的每一排晶体管的栅极205相互物理连接，所述物理连接的栅极形成第二字线WL2；每一所述第二存储单元SC2分别与所述第二晶体管阵列21中一个晶体管的源极S或漏极D连接；
在所述第二晶体管阵列21上形成多条沿所述第二方向并列排布的第二位线BL2，每一所述第二位线BL2分别与所述第二晶体管阵列21中沿所述第二方向排布的一排晶体管的漏极D或源极S连接。
需要说明的是，如图4b所示的存储器可以理解为由2个如图6g所示的结构沿第三方向上的三维堆叠形成。本公开实施例中所描述的存储器的制造方法并不局限于制作某一具体数量的三维堆叠，还可以形成由2个或2个以上如图6g所示的结构沿第三方向上的三维堆叠的存储器。
本公开实施例提供的存储器的制造方法与上述实施例中的存储器类似，对于本公开实施例未详尽披露的技术特征，请参照上述实施例进行理解，这里，不再赘述。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本公开的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例中包括第一材料层和第二材料层的沟道使得晶体管兼具有较高的场效应迁移率和较高的阈值电压，从而可以满足晶体管高性能的需求。

Claims (18)

  1. 一种半导体结构，所述半导体结构包括至少一个晶体管，所述晶体管包括：
    沟道，所述沟道包括第一材料层和环绕所述第一材料层设置的第二材料层；所述第一材料层的电阻率大于第一预设值，所述第二材料层的电阻率小于第二预设值，所述第一预设值大于所述第二预设值；
    栅极，覆盖所述沟道的至少一个侧面；
    源极和漏极，位于所述沟道的延伸方向的两端。
  2. 根据权利要求1所述的半导体结构，其中，所述半导体结构包括多个晶体管，所述多个晶体管对应的多个所述沟道沿第一方向和第二方向阵列排布；所述第一方向和所述第二方向均与所述沟道的延伸方向垂直；其中，
    沿所述第一方向排布的每一排晶体管中每个晶体管的栅极相互物理连接；沿所述第一方向排布的相邻的两排晶体管的栅极之间相互电隔离。
  3. 根据权利要求1所述的半导体结构，其中，所述第一材料层的材料和/或所述第二材料层的材料包含氧化铟、氧化镓、氧化锌、氧化铟镓、氧化铟锌、氧化镓锌、氧化铟镓锌中的至少一种。
  4. 根据权利要求1所述的半导体结构，其中，所述栅极环绕所述沟道设置。
  5. 一种半导体结构的制造方法，所述半导体结构包括至少一个晶体管，所述晶体管的制造方法包括：
    形成沟道，所述沟道包括第一材料层和环绕所述第一材料层设置的第二材料层；所述第一材料层的电阻率大于第一预设值，所述第二材料层的电阻率小于第二预设值，所述第一预设值大于所述第二预设值；
    形成覆盖所述沟道的至少一个侧面的晶体管的栅极；
    在所述沟道的延伸方向的两端分别形成所述晶体管的源极和漏极。
  6. 根据权利要求5所述的方法，其中，所述半导体结构包括多个晶体管，所述多个晶体管对应的多个所述沟道沿第一方向和第二方向阵列排布；所述第一方向和所述第二方向均与所述沟道的延伸方向垂直；其中，
    沿所述第一方向排布的每一排晶体管中每个晶体管的栅极相互物理连接；沿所述第一方向排布的相邻的两排晶体管之间的栅极相互电隔离。
  7. 根据权利要求5所述的方法，其中，所述第一材料层的材料和/或所述第二材料层的材料包含氧化铟、氧化镓、氧化锌、氧化铟镓、氧化铟锌、氧化镓锌、氧化铟镓锌中的至少一种。
  8. 根据权利要求5所述的方法，其中，所述形成沟道，包括：
    提供第一介质层；
    在所述第一介质层中形成第一孔；
    在所述第一孔的侧壁和底部形成所述第二材料层；
    填充形成有所述第二材料层的所述第一孔，形成所述第一材料层。
  9. 根据权利要求8所述的方法，其中，在所述第一孔的侧壁和底部形成所述第二材料层，包括：
    通过原子层沉积工艺，在无氧的气氛中，形成所述第二材料层，
    填充形成有第二材料层的第一孔，形成所述第一材料层，包括：
    通过原位沉积方式，在有氧的气氛中，形成所述第一材料层。
  10. 根据权利要求8所述的方法，其中，形成所述第一材料层之后，所述方法还包括：
    部分刻蚀所述第一介质层，形成暴露的第二材料层；
    在所述暴露的第二材料层上形成栅极氧化层；
    依次填充第一导电材料和第二介质层，刻蚀所述第一导电材料和第二介质层形成凹槽，在所述凹槽中填充绝缘材料形成栅极隔离结构。
  11. 一种存储器，包括：
    多个第一存储单元，沿第一方向和第二方向阵列排布；
    第一晶体管阵列，位于所述多个第一存储单元上；所述第一晶体管阵列包括多个如权利要求1至4任一项所述的晶体管；所述第一晶体管阵列沿第一方向的每一排晶体管的栅极相互物理连接，所述物理连接的栅极形成第一字线；每一所述存储单元分别与所述晶体管阵列中一晶体管的源极或漏极连接；所述第一方向和所述第二方向均与所述晶体管的沟道的延伸方向垂直；
    多条沿所述第二方向并列排布的第一位线，位于所述第一晶体管阵列上；每一所述第一位线分别与所述第一晶体管阵列中沿所述第二方向排布的一排晶体管的漏极或源极连接。
  12. 根据权利要求11所述的存储器，其中，所述存储器包括：动态随机存取存储器、铁电存储器、相变存储器、磁变存储器或者阻变存储器。
  13. 根据权利要求12所述的存储器，其中，所述存储器包括：动态随机存取存储器，所述存储器单元包括：电容；所述电容包括柱状的第二电极，覆盖所述第二电极侧壁及底部的电介质，以及覆盖所述电介质的第一电极。
  14. 根据权利要求11所述的存储器，其中，所述存储器还包括多个第二存储单元、第二晶体管阵列，多条第二位线；其中，
    所述多个第二存储单元位于所述第一位线上，且沿所述第一方向和所述第二方向阵列排布；
    所述第二晶体管阵列位于所述多个第二存储单元上；所述第二晶体管阵列包括如权利要求1至4任一项所述的晶体管；所述第二晶体管阵列沿所述第一方向的每一排晶体管的栅极相互物理连接，所述物理连接的栅极形成第二字线；每一所述第二存储单元分别与所述第二晶体管阵列中一个晶体管的源极或漏极连接；
    所述多条第二位线位于在所述第二晶体管阵列上，所述多条第二位线沿所述第二方向并列排布，每一所述第二位线分别与所述第二晶体管阵列中沿所述第二方向排布的一排晶体管的漏极或源极连接。
  15. 一种存储器的制造方法，所述方法包括：
    形成多个第一存储单元，所述多个第一存储单元沿第一方向和第二方向阵列排布；
    在所述多个第一存储单元上形成第一晶体管阵列；所述第一晶体管阵列通过权利要求5至10任一项所述的晶体管的制造方法制造得到；所述第一晶体管阵列中沿所述第一方向的每一排晶体管的栅极相互物理连接，所述物理连接的栅极形成第一字线；每一所述第一存储单元分别与所述第一晶体管阵列中一个晶体管的源极或漏极连接；所述第一方向和所述第二方向均与所述晶体管的沟道的延伸方向垂直；
    在所述第一晶体管阵列上形成多条沿所述第二方向并列排布的第一位线，每一所述第一位线分别与所述晶体管阵列中沿所述第二方向排布的一排晶体管的漏极或源极连接。
  16. 根据权利要求15所述的方法，其中，所述形成多条沿所述第二方向并列排布的第一位线，包括：
    形成覆盖所述栅极的第二介质层；
    部分蚀刻所述第二介质层，形成多个均沿所述第二方向延伸的第二沟槽；所述第二沟槽使得所述沟道的部分侧壁暴露；
    在所述第二沟槽中填充第二导电材料，形成环绕所述沟道端部的所述第一位线。
  17. 根据权利要求15所述的方法，其中，所述第一存储单元包括电容；
    所述形成多个第一存储单元，包括：
    提供第三介质层；
    在所述第三介质层中形成沿所述第一方向和所述第二方向阵列排布的多个第二孔；
    在所述第二孔的侧壁和底部以及所述第三介质层的顶面形成第一电极；
    在所述第一电极上形成电介质层；
    填充形成有所述第一电极和所述电介质层的所述第二孔，形成多个第二电极；每一所述第二电极分别与所述晶体管阵列中一个晶体管的源极或漏极连接。
  18. 根据权利要求15所述的方法，其中，所述方法包括：
    在所述第一位线上形成多个第二存储单元，所述多个第二存储单元沿所述第一方向和所述第二方向阵列排布；
    在所述多个第二存储单元上形成第二晶体管阵列；所述第二晶体管阵列通过权利要求5至10任一项所述晶体管的制造方法制造得到；所述第二晶体管阵列中沿所述第一方向的每一排晶体管的栅极相互物理连接，所述物理连接的栅极形成第二字线；每一所述第二存储单元分别与所述第二晶体管阵列中一个晶体管的源极或漏极连接；
    在所述第二晶体管阵列上形成多条沿所述第二方向并列排布的第二位线，每一所述第二位线分别与所述第二晶体管阵列中沿所述第二方向排布的一排晶体管的漏极或源极连接。
PCT/CN2022/082188 2022-03-08 2022-03-22 半导体结构及其制造方法、存储器及其制造方法 WO2023168752A1 (zh)

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