WO2023197440A1 - 半导体结构及其制作方法、存储器 - Google Patents

半导体结构及其制作方法、存储器 Download PDF

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Publication number
WO2023197440A1
WO2023197440A1 PCT/CN2022/099562 CN2022099562W WO2023197440A1 WO 2023197440 A1 WO2023197440 A1 WO 2023197440A1 CN 2022099562 W CN2022099562 W CN 2022099562W WO 2023197440 A1 WO2023197440 A1 WO 2023197440A1
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Prior art keywords
sub
conductive
layer
semiconductor
conductive pillar
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PCT/CN2022/099562
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English (en)
French (fr)
Inventor
黄娟娟
白卫平
肖德元
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长鑫存储技术有限公司
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Priority to US17/884,007 priority Critical patent/US20230328959A1/en
Publication of WO2023197440A1 publication Critical patent/WO2023197440A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure, a manufacturing method thereof, and a memory.
  • the memory array architecture of dynamic random access memory is an array composed of memory cells (i.e., 1T1C memory cells) including a transistor and a capacitor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • a semiconductor structure including:
  • each transistor includes a semiconductor body extending along a first direction and a gate structure covering at least one side of the semiconductor body; the first direction is the thickness direction of the semiconductor layer ;
  • each conductive pillar is located on the top surface of a corresponding semiconductor body and is in direct contact with the corresponding semiconductor body;
  • a storage structure covers the plurality of conductive pillars.
  • each of the conductive pillars includes N sub-conductive pillars stacked along the first direction, where N is a positive integer greater than or equal to 1; accordingly, the storage structure includes N sub-conductive pillars stacked along the first direction.
  • Set N sub-storage structures
  • the semiconductor structure includes:
  • a first sub-conductive pillar located on the top surface of each semiconductor body; a first sub-storage structure covering the sidewall of the first sub-conductive pillar;
  • a second sub-conductive pillar located on the top surface of each first sub-conductive pillar; a second sub-storage structure covering the side wall of the second sub-conductive pillar;
  • a third sub-conductive pillar located on the top surface of each second sub-conductive pillar; a third sub-storage structure covering the top surface and side walls of the third sub-conductive pillar;
  • first sub-conductive pillar, the second sub-conductive pillar and the third sub-conductive pillar are in direct contact with each other, and the first sub-storage structure, the second sub-storage structure and the third sub-storage structure are in direct contact with each other. touch.
  • the first sub-storage structure includes: a plurality of lower electrode conductive layers covering the side walls of each first sub-conductive pillar, a plurality of dielectric layers covering each of the lower electrode conductive layers, and a plurality of The upper electrode conductive layer on the top surface of the dielectric layer and the semiconductor layer between the two adjacent dielectric layers is located in the upper electrode conductive layer, and the conductive material layer and the dielectric material layer are sequentially stacked;
  • the second sub-storage structure includes: a plurality of lower electrode conductive layers covering the sidewalls of each second sub-conductive pillar, a plurality of dielectric layers covering each of the lower electrode conductive layers, a plurality of the dielectric layers covering a plurality of the dielectric layers and
  • the upper electrode conductive layer on the top surface of the dielectric material layer is located in the upper electrode conductive layer, and the conductive material layer and the dielectric material layer are sequentially stacked;
  • the third sub-storage structure includes: a plurality of upper electrode conductive layers covering the sidewalls and top surfaces of each of the third sub-conductive pillars, a plurality of dielectric layers covering each of the upper electrode conductive layers, and a plurality of upper electrode conductive layers covering a plurality of the upper electrode conductive layers.
  • the dielectric layer and the lower electrode conductive layer on the top surface of the dielectric material layer, the conductive material layer located in the lower electrode conductive layer and on the top surface;
  • the upper and lower electrode conductive layers in the first, second and third sub-storage structures are connected to each other to form complete upper and lower electrode layers;
  • the media layers in the first, second and third sub-storage structures are connected to each other to form a complete media layer.
  • the transistor further includes: a source electrode and a drain electrode respectively provided at two ends of the semiconductor body in the first direction.
  • the semiconductor structure further includes: a plurality of bit lines;
  • Each bit line is in direct contact with bottom surfaces of a plurality of semiconductor bodies.
  • the conductive pillar is formed through an epitaxial growth process; and the memory structure is at least formed through a selective deposition process.
  • a memory including: the semiconductor structure as described in any one of the above-mentioned embodiments of the present disclosure.
  • a method for manufacturing a semiconductor structure including:
  • a plurality of transistors are formed in the semiconductor layer, each of the transistors including a semiconductor body extending along a first direction and a gate structure covering at least one side of the semiconductor body; the first direction is the semiconductor body.
  • Conductive pillars are formed on the exposed top surface of each semiconductor body
  • a storage structure is formed covering the conductive pillars.
  • each of the conductive pillars includes N sub-conductive pillars stacked along the first direction, where N is a positive integer greater than or equal to 1; accordingly, the storage structure includes N sub-conductive pillars stacked along the first direction.
  • Forming the conductive pillar and the storage structure includes:
  • (N-1) sub-conductive pillars and corresponding (N-1) sub-storage structures are formed in sequence.
  • a first sub-conductive pillar is formed on the exposed top surface of each semiconductor body
  • a second sub-conductive pillar is formed on the exposed top surface of each first sub-conductive pillar; the first sub-conductive pillar is in direct contact with the corresponding second sub-conductive pillar;
  • a third sub-conductive pillar is formed on the exposed top surface of each second sub-conductive pillar; the third sub-conductive pillar is in direct contact with the corresponding second sub-conductive pillar;
  • a third sub-storage structure covering the third sub-conductive pillar is formed; the third sub-storage structure is in direct contact with the second sub-storage structure.
  • forming the first sub-storage structure covering the first sub-conductive pillar includes:
  • a selective deposition process a plurality of dielectric layers covering each of the lower electrode conductive layers are formed; a first gap is formed between two adjacent dielectric layers;
  • An upper electrode conductive layer covering a plurality of dielectric layers and a plurality of bottoms of the first gaps is formed.
  • the method also includes:
  • each first sub-conductive pillar Before forming the second sub-conductive pillar on the exposed top surface of each first sub-conductive pillar, sequentially forming a conductive material layer and a dielectric material layer in a plurality of first gaps where the upper electrode conductive layer is formed;
  • the material of the conductive pillar is the same as or different from the material of the conductive material layer.
  • forming a second sub-storage structure covering the second sub-conductive pillar includes:
  • a selective deposition process a plurality of dielectric layers covering each of the upper electrode conductive layers are formed; a second gap is formed between two adjacent dielectric layers;
  • An upper electrode conductive layer covering a plurality of the dielectric layers and a plurality of second gap bottoms is formed; the upper electrode conductive layer of the second sub-storage structure is directly connected to the upper electrode conductive layer of the first sub-storage structure. touch.
  • the method also includes:
  • each second sub-conductive pillar Before forming the third sub-conductive pillar on the exposed top surface of each second sub-conductive pillar, sequentially forming a conductive material layer and a dielectric material layer in a plurality of second gaps where the upper electrode conductive layer is formed;
  • forming a third sub-storage structure covering the third sub-conductive pillar includes:
  • a selective deposition process a plurality of dielectric layers covering each of the lower electrode conductive layers are formed; a third gap is formed between two adjacent dielectric layers;
  • the method also includes:
  • the upper and lower electrode conductive layers in the first, second and third sub-storage structures are connected to each other to form complete upper and lower electrode layers;
  • the media layers in the first, second and third sub-storage structures are connected to each other to form a complete media layer.
  • multiple transistors are formed in the semiconductor layer, including:
  • a source electrode and a drain electrode of the transistor are respectively formed at two opposite ends of the semiconductor body along the first direction.
  • the method further includes: forming a plurality of bit lines in the semiconductor layer;
  • Each bit line is in direct contact with bottom surfaces of a plurality of semiconductor bodies.
  • Figure 1a is a schematic circuit connection diagram of a DRAM transistor provided in an embodiment of the present disclosure
  • Figure 1b is a schematic structural diagram of a memory provided in an embodiment of the present disclosure.
  • Figure 2a is a schematic diagram of the buried gate structure arrangement provided by an embodiment of the present disclosure.
  • Figure 2b is a schematic diagram of the ring gate structure arrangement provided by an embodiment of the present disclosure.
  • Figure 2c is a schematic diagram of a hexagonal closest packing structure provided by an embodiment of the present disclosure.
  • Figure 2d is a schematic diagram of a square stacking structure provided by an embodiment of the present disclosure.
  • Figure 3 is a schematic flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • 4a to 4d are schematic cross-sectional views of a manufacturing process of a semiconductor structure provided by embodiments of the present disclosure.
  • 5a to 5i are cross-sectional schematic diagrams of a manufacturing process of another semiconductor structure provided by embodiments of the present disclosure.
  • FIG. 6 is a schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure.
  • spatially relative terms such as “on”, “over”, “over”, “on”, “upper”, etc. may be used herein to describe the figures. The relationship of one element or feature to another element or feature.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • the term "substrate” refers to a material on which subsequent layers of material are added.
  • the substrate itself can be patterned.
  • the material added on top of the substrate can be patterned or can remain unpatterned.
  • the substrate may include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, arsenide, indium phosphide, and the like.
  • the substrate may be made of non-conductive material, such as glass, plastic or sapphire wafers.
  • the term "layer" refers to a portion of material that includes a region having a thickness.
  • a layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure.
  • the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal plane at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along inclined surfaces.
  • a layer can include multiple sub-layers.
  • an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.
  • first the terms “first”, “second”, etc. are configured to distinguish similar objects and are not necessarily configured to describe a specific order or sequence.
  • Embodiments of the present disclosure relate to semiconductor structures that are at least part of a device that will be configured in subsequent processes to form a final device structure.
  • the final device may include a memory, and the memory includes but is not limited to a dynamic random access memory. The following only takes the dynamic random access memory as an example for description.
  • the size of memory cells is getting smaller and smaller, and its array architecture has changed from 8F 2 to 6F 2 to 4F 2 ; in addition, based on the demand for ions and leakage current in dynamic random access memory , the memory architecture has changed from Planar Array Transistor to Recess Gate Array Transistor, then from Recess Gate Array Transistor to Buried Channel Array Transistor, and then from Buried Channel Array Transistor. channel array transistor to vertical channel array transistor (Vertical Channel Array Transistor).
  • the dynamic random access memory is composed of multiple memory cell structures.
  • Each memory cell structure mainly consists of a transistor and a memory cell controlled by the transistor.
  • (storage capacitor) structure that is, the dynamic random access memory includes a transistor (T, Transistor) and a capacitor (C, Capacitor) (1T1C) architecture.
  • Figure 1a is a schematic diagram of a control circuit using a 1T1C architecture provided in an embodiment of the disclosure.
  • Figure 1b is a schematic structural diagram of a DRAM memory array formed by transistors using an 1T1C architecture provided in an embodiment of the disclosure;
  • Figure 1a As shown in Figure 1b, the drain of transistor T is electrically connected to the bit line (BL, Bit Line), the source area of transistor T is electrically connected to one of the electrode plates of capacitor C, and the other electrode plate of capacitor C can be connected to the reference voltage.
  • the reference voltage can be the ground voltage or other voltages.
  • the gate of the transistor T is connected to the word line (WL, Word Line); applying a voltage through the word line WL controls the on or off of the transistor T, and the bit line BL is configured to When the transistor T is turned on, a read or write operation is performed on the transistor T.
  • the size of dynamic random access memory is also continuously reduced, and its memory cell array develops from the buried gate (BWL, Buried Word Line) structural arrangement (refer to Figure 2a) to a ring-shaped gate structure (GAA, Gate All Around) that occupies a smaller area (refer to Figure 2b); at the same time, the capacitor size in DRAM has also been adjusted, evolving from the hexagonal densest packing (refer to Figure 2c) Stacked in a quadrilateral shape (refer to Figure 2d); where the radius of the capacitor also becomes smaller, retreating from a cup-shaped structure to a columnar structure.
  • BWL Buried Word Line
  • GAA Gate All Around
  • the capacitor height can be increased.
  • the increase in capacitor height will result in a higher aspect ratio (Aspect Ratio).
  • This large aspect ratio structure will increase the process difficulty and limit the height of the capacitor.
  • multiple capacitors can be stacked. However, in the process of stacking capacitors, the interaction between multiple capacitors Accuracy is more difficult.
  • FIG. 3 is a schematic flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. As shown in Figure 3, the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:
  • S100 Provides semiconductor layer
  • S200 Form a plurality of transistors in the semiconductor layer, each of the transistors including a semiconductor body extending along a first direction and a gate structure covering at least one side of the semiconductor body; the first direction is the The thickness direction of the semiconductor layer;
  • S400 Form a storage structure covering the conductive pillar.
  • 4a to 4d are schematic cross-sectional views of a manufacturing process of a semiconductor structure provided by embodiments of the present disclosure. The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIG. 3 and FIG. 4a to FIG. 4d.
  • step S100 referring to Figure 4a, a semiconductor layer 30 is provided.
  • the material of the semiconductor layer may include silicon (Si), germanium (Ge), silicon germanium (SiGe), etc.; in some specific embodiments, the semiconductor layer may also be silicon-on-insulator (SOI, Silicon-On- Insulator) or Germanium-On-Insulator (GOI, Germanium-On-Insulator).
  • SOI Silicon-On- Insulator
  • GOI Germanium-On-Insulator
  • the method further includes: providing a substrate; and forming a semiconductor layer on the substrate.
  • the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, arsenide, indium phosphide, and the like.
  • the substrate material includes silicon
  • the semiconductor layer includes silicon germanium.
  • the semiconductor layer may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD), or other processes.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the method further includes forming a plurality of bit lines 301 in the semiconductor layer before forming a plurality of transistors.
  • bit line 301 is configured to perform a read or write operation on the transistor 302 when the transistor 302 is turned on.
  • the material of the bit line 301 includes but is not limited to metal tungsten.
  • the bit line 301 can be formed by PVD, CVD or ALD processes.
  • step S200 a plurality of transistors 302 are formed in the semiconductor layer 30.
  • the transistor 302 is in direct contact with the bit line 301.
  • the type of transistor includes one of the following:
  • the gate in the columnar gate transistor, the gate is formed in a columnar form on one side of the channel area; in the semi-surround gate transistor, the gate half surrounds the channel area; in the full surround gate transistor, the gate is completely Surround the channel area.
  • the transistor types in the embodiments of the present disclosure may include the above-mentioned types, but are not limited thereto.
  • the following embodiments take a full surround gate transistor as an example.
  • the description of transistor types in the following embodiments is only configured to illustrate the present disclosure and is not used to limit the scope of the present disclosure.
  • a plurality of transistors 302 are formed in the semiconductor layer 30, including:
  • the semiconductor layer 30 is etched from the surface of the semiconductor layer 30 along a first direction to form a semiconductor body of a transistor (not shown in FIG. 4a ).
  • a source (S, Source) 3021 and a drain (D, Drain) 3022 of the transistor are respectively formed at two opposite ends of the semiconductor body along the first direction.
  • the region between the source and the drain in the semiconductor body is the channel region 3023.
  • the first direction is the direction in which the semiconductor body extends, and the first direction is also a direction perpendicular to the semiconductor layer 30 .
  • the first direction may be the Z-axis direction shown in Figure 4a.
  • the source electrode and the drain electrode are respectively opposite ends of the channel region in the Z-axis direction, and the source electrode and the drain electrode can interchange positions.
  • the drain electrode is located at the bottom of the semiconductor body and is connected to the bit line as an example.
  • the bit line 301 is connected to the bottom surface of the semiconductor body (i.e., the drain electrode) of the plurality of transistors 302. Extremely 3022) direct contact. Among them, the top surface of the semiconductor body (ie, the source electrode 3021) is exposed.
  • the source electrode 3021 and the drain electrode 3022 may be formed by a doping or diffusion process, or other suitable methods.
  • doping is achieved through an ion implantation process to form the source electrode 3021 and the drain electrode 3022.
  • the drain electrode 3022 close to one end of the bit line 301 may be formed first, and then the source electrode 3021 distant from the end of the bit line 301 may be formed.
  • the method further includes: forming a gate structure 3024 of a surrounding transistor on the side of the semiconductor body.
  • the gate structure 3024 here includes a gate (G, Gate) 3024a and a gate oxide layer (Gate oxide layer) 3024b; wherein, the gate oxide layer 3024b is located between the gate 3024a and the channel region 3023, configured To electrically isolate the channel region 3023 and the gate 3024a, reduce the hot carrier effect of the transistor.
  • G, Gate gate
  • Gate oxide layer gate oxide layer
  • the material of the gate 3024a may include metal or polysilicon (Poly), or the like.
  • the material of the gate oxide layer 3024b may include, but is not limited to, silicon oxide.
  • the formation method of the gate 3024a includes but is not limited to PVD, CVD or ALD.
  • the formation method of the gate oxide layer 3024b includes but is not limited to in-situ oxidation.
  • the gate 3024a can be located on one side of the channel region 3023; it can also be located on opposite sides of the channel region 3023; it can also be located on the channel.
  • Around Road District 3023 The specific location may depend on the type of transistor; in a full-surround gate transistor, the gate 3024a is located around the channel region 3023.
  • the method further includes forming an insulating layer 303 in the gaps between the plurality of transistors 302 in the semiconductor layer.
  • the insulating layer 303 can be configured to electrically isolate the plurality of transistors 302; it can also be configured to play a supporting role.
  • the material of the insulating layer 303 includes but is not limited to silicon nitride (SiN).
  • Methods for forming the insulating layer include but are not limited to PVD, CVD or ALD processes.
  • step S300 referring to FIG. 4b, conductive pillars 304 are formed on the exposed top surface of each semiconductor body.
  • the material of the conductive pillar 304 may be other conductive materials that can grow unidirectionally along the first direction.
  • the material of the conductive pillar 304 includes silicon germanium.
  • the conductive pillars 304 may be formed through an epitaxial growth process.
  • epitaxial growth refers to growing a layer of material with certain requirements and the same crystal orientation as the semiconductor body on the exposed top surface of the semiconductor body.
  • the second direction is perpendicular to the first direction and perpendicular to the surface of the semiconductor layer.
  • the second direction may be the X-axis direction shown in FIG. 4b.
  • the plurality of transistors 302 formed in the semiconductor layer 30 may be along the second direction and the third direction respectively (here, the third direction and the first direction and the second direction are both vertical) in an array, at this time, correspondingly, the plurality of conductive pillars 304 are arranged in an array along the second direction and the third direction.
  • step S400 referring to FIG. 4c, a memory structure 306 covering the conductive pillar is formed in the gap 305.
  • the storage structure 306 is configured to store data.
  • the storage structure 306 includes a capacitor.
  • forming the storage structure 306 includes:
  • a lower electrode conductive layer 3061 covering the conductive pillar is formed;
  • a dielectric layer 3062 covering the surface of the lower electrode conductive layer is formed;
  • the lower electrode conductive layer 3061 is configured as the lower electrode of the capacitor; the dielectric layer 3062 is configured as the dielectric of the capacitor; and the upper electrode conductive layer 3063 is configured as the upper electrode of the capacitor.
  • the selective deposition process refers to selectively depositing the lower electrode conductive layer on the surface of the conductive pillar; and selectively depositing the dielectric layer on the surface of the lower electrode conductive layer.
  • the material of the conductive pillar 304 and the material of the lower electrode conductive layer 3061 or the upper electrode conductive layer 3063 may be the same or different.
  • the materials of both the lower electrode conductive layer 3061 and the upper electrode conductive layer 3063 may include, but are not limited to, titanium nitride (TiN).
  • the material of the dielectric layer 3062 includes a high-k material.
  • a high-k material generally refers to a material with a dielectric constant higher than 3.9, and is usually significantly higher than this value.
  • the material of the dielectric layer 3062 may include but is not limited to hafnium oxide (HfO 2 ).
  • the material configured to form the lower electrode conductive layer 3061 in the process of forming the lower electrode conductive layer 3061 through a selective deposition process, can only grow on the surface of the conductive pillar 304, or Formed on other selected materials without being formed on the top surface of the insulating layer 303, see Figure 4c.
  • the material configured to form the dielectric layer 3062 in the process of forming the dielectric layer 3062 through a selective deposition process, can be formed only on the surface of the lower electrode conductive layer 3061 and not on the top surface of the insulating layer 303, see FIG. 4c.
  • the embodiment of the present disclosure uses an epitaxial growth process to form the conductive pillars 304 and a selective deposition process to form the memory structure 306, which can also avoid the use of photomask technology to form etching holes (configured to form a memory structure) in the semiconductor layer. , the multiple overlapping photolithography problems that occur.
  • the upper electrode conductive layer 3063 covering the dielectric layer 3062 and located on the top surface of the insulating layer 303 is connected as a whole. In this way, the surface area of the upper electrode conductive layer 3063 can be increased, thereby improving the memory structure. storage capacity.
  • the method of forming the upper electrode conductive layer 3063 includes but is not limited to processes such as PVD, CVD, or ALD. It can be understood that the upper electrode conductive layer 3063 does not need to adopt a selective deposition process.
  • the upper electrode conductive layer 3063 can directly fill the gap between two adjacent dielectric layers 3062.
  • the conductive material layer 307 is filled in the gap of the upper electrode conductive layer 3063.
  • the material of the conductive material layer 307 may include but is not limited to silicon germanium.
  • the conductive material layer 307 is also configured to enhance the robustness of the semiconductor structure.
  • the conductive pillars can be formed only at the positions in direct contact with the semiconductor body through the epitaxial growth process, thereby reducing the difficulty of aligning the transistors and the conductive pillars, increasing the process window, and improving the reliability of the semiconductor structure; at the same time, , through a selective deposition process, a memory structure can be formed in a gap with a larger aspect ratio, increasing the process window, reducing process difficulty, and improving the reliability of the semiconductor structure.
  • the height of the conductive pillar determines the size and storage capacity of the storage structure; based on this, in some embodiments of the present disclosure, in order to increase the storage capacity of the storage structure and increase the height of the conductive pillar, another method is proposed A semiconductor structure and a manufacturing method thereof.
  • each of the conductive pillars includes N sub-conductive pillars stacked along the first direction, where N is a positive integer greater than or equal to 1; accordingly, the storage structure includes N sub-conductive pillars stacked along the first direction. N sub-storage structures stacked in one direction;
  • Forming the conductive pillar and the storage structure includes:
  • (N-1) sub-conductive pillars and corresponding (N-1) sub-storage structures are formed in sequence.
  • the total height of the conductive pillars is increased, thereby increasing the surface of the memory structure and increasing the storage capacity of the memory.
  • a plurality of stacked conductive sub-pillars are formed above the semiconductor layer (i.e., one end of both sides of the source electrode away from the channel region) through an epitaxial growth process, and a plurality of sub-conducting pillars are covered in the corresponding Sub-storage structures on the surface of sub-conductive pillars.
  • the sub-conductive pillars correspond to the sub-storage structures one-to-one.
  • N stacked sub-conductive pillars can be formed above the semiconductor layer; and in order to reduce the process difficulty of forming the sub-storage structure, after each sub-conductive pillar is formed, a corresponding sub-conductive pillar is formed. Storage structure.
  • N sub-conductive pillars stacked along the Z-axis direction correspond to N sub-storage structures stacked along the Z-axis direction.
  • the sub-storage structure located at the top is different from the sub-storage structures not at the top (the first to N-th sub-storage structures). Specifically, the non-top sub-storage structure only covers the sidewalls of the corresponding sub-conductive pillars, while the top sub-storage structure covers the top and sidewalls of the corresponding sub-conductive pillars.
  • a partial sub-storage structure is formed on top of the N-th sub-conductive pillar, so that the sub-storage structures located on the top of the N-th sub-conductive pillar
  • the structure is connected to the storage structure on the side wall to form a complete Nth sub-storage structure.
  • the first to N-1th sub-conductive pillars and the corresponding first to N-1th sub-storage structures are formed first; then the N-th sub-conductive pillar is formed; and then the N-th sub-conductive pillar is formed simultaneously.
  • the top and side walls of the sub-conductive pillars are sub-storage structures.
  • forming the conductive pillars and the storage structure includes sequentially forming (N-1) sub-conductive pillars and corresponding (N-1) sub-storage structures stacked along the Z-axis direction; wherein, after each sub-conductive pillar is formed, , forming the corresponding sub-storage structure.
  • the N-th sub-conductive pillar is formed on the N-1-th sub-conductive pillar; and the N-th sub-storage structure covering the top and side walls of the N-th sub-conductive pillar is formed.
  • the timing of forming the sub-storage structure located on top of the Nth sub-conductive pillar can be selected according to actual requirements.
  • each conductive pillar including three sub-conductive pillars and each storage structure including three sub-storage structures.
  • the conductive pillar includes a first sub-conductive pillar, a second sub-conductive pillar located on the first sub-conductive pillar, and a third sub-conductive pillar located on the second sub-conductive pillar. sub conductive pillar.
  • the storage structure includes a first sub-storage structure covering the first sub-conductive pillar, a second sub-storage structure covering the second sub-conductive pillar, and a third sub-storage structure covering the third sub-conductive pillar. Storage structure.
  • forming the conductive pillars and the memory structure includes:
  • a first sub-conductive pillar is formed on the exposed top surface of each semiconductor body
  • a second sub-conductive pillar is formed on the exposed top surface of each first sub-conductive pillar; the first sub-conductive pillar is in direct contact with the corresponding second sub-conductive pillar;
  • a third sub-conductive pillar is formed on the exposed top surface of each second sub-conductive pillar; the third sub-conductive pillar is in direct contact with the corresponding second sub-conductive pillar;
  • a third sub-storage structure covering the third sub-conductive pillar is formed; the third sub-storage structure is in direct contact with the second sub-storage structure.
  • a semiconductor layer 50 is provided, which is the same as the semiconductor layer 30 in the previous embodiment;
  • the semiconductor layer 50 includes a plurality of transistors 502; one end of the transistor 502 (ie, the end surface where the semiconductor body is exposed) is substantially flush with the top surface of the semiconductor layer 50; this has been mentioned before and will not be described again here.
  • a first sub-conductive pillar 5041 is formed on the exposed top surface of each semiconductor body through epitaxial growth.
  • gaps 505 between the plurality of first sub-conductive pillars.
  • the first sub-storage structure 5061 includes a lower electrode conductive layer 5061a, a dielectric layer 5061b and an upper electrode conductive layer 5061c.
  • forming the first sub-storage structure covering the first sub-conductive pillar includes:
  • a plurality of dielectric layers 5061b covering each of the lower electrode conductive layers 5061a are formed; a first gap (not shown in Figure 5b) is formed between two adjacent dielectric layers 5061b;
  • An upper electrode conductive layer 5061c is formed covering the plurality of dielectric layers 5061b and the bottoms of the plurality of first gaps.
  • the lower electrode conductive layer 5061a can be formed only on the top surface and sidewalls of the first sub-conductive pillar 5041 through a selective deposition process, without forming the lower electrode conductive layer 5061a on the bottom of the first gap.
  • the dielectric layer 5061b can be formed only on the sidewalls of the lower electrode conductive layer 5061a through a selective deposition process.
  • the lower electrode conductive layer 5061a and the dielectric layer 5061b can be formed in the gap 505 with a relatively deep depth-to-width ratio, thereby increasing the process window, reducing process difficulty, and improving device reliability.
  • the upper electrode conductive layer 5061c does not need to adopt a selective deposition process.
  • the method of forming the upper electrode conductive layer 5061c includes but is not limited to PVD, CVD or ALD processes.
  • the upper electrode conductive layer 5061c covering the dielectric layer 5061b and located on the top surface of the insulating layer is connected as a whole. In this way, the storage capacity of the sub-storage structure can be increased.
  • the method also includes:
  • the first support layer 507 is formed in a plurality of first gaps where the upper electrode conductive layer is formed.
  • the first support layer 507 includes a first conductive material layer 5071 and a first dielectric material layer 5072 located above the first conductive material layer 5071 .
  • a first conductive material layer 5071 is formed in a plurality of first gaps between the first sub-storage structures 5061 and on the top surface of the upper electrode conductive layer 5061c through a process such as PVD or CVD.
  • the materials of the first conductive material layer 5071 and the conductive pillars 504 can be the same or different; the actual situation can be selected and set according to actual needs.
  • the constituent material of the first conductive material layer 5071 includes but is not limited to silicon germanium.
  • the first conductive material layer 5071 is etched to remove the first conductive material layer 5071 located on the top surface of the upper electrode conductive layer 5061c, and part of the first conductive material layer 5071 located in the first gap. .
  • the top surface of the remaining first conductive material layer 5071 in the first gap is lower than the top surface of the upper electrode conductive layer 5061c.
  • a first dielectric material layer 5072 is formed on the top surface of the upper electrode conductive layer 5061c and the top surface of the first conductive material layer 5071.
  • the material of the first dielectric material layer 5072 includes but is not limited to silicon nitride (SiN).
  • the method of forming the first dielectric material layer 5072 includes but is not limited to PVD, CVD, or ALD processes.
  • the first dielectric material layer here uses silicon nitride, so that in the subsequent process, the second sub-conductive pillars 5042 are formed through epitaxial growth, and the second sub-conductive pillars 5042 are not formed on the first dielectric material layer (nitrogen). silicon) and when forming the lower electrode conductive layer and dielectric layer in the second sub-storage structure through selective deposition, the lower electrode conductive layer and dielectric layer of the second sub-storage structure are not formed on the first dielectric material layer (nitrogen silicon).
  • the method further includes:
  • the removal process includes, but is not limited to, chemical mechanical polishing (CMP, Chemical Mechanical Polish).
  • a second sub-conductive pillar 5042 is formed on the exposed top surface of each first sub-conductive pillar 5041.
  • the second sub-conductive pillar 5042 and the first sub-conductive pillar 5041 are made of the same material and formed by the same method, which has been mentioned before and will not be described again here.
  • the second sub-storage structure 5062 includes a lower electrode conductive layer 5061a, a dielectric layer 5061b and an upper electrode conductive layer 5061c.
  • the materials of both the lower electrode conductive layer 5061a and the upper electrode conductive layer 5061c may include, but are not limited to, titanium nitride.
  • forming the second sub-storage structure 5062 covering the second sub-conductive pillar 5042 includes:
  • a plurality of lower electrode conductive layers 5061a covering the top surface and sidewalls of each second sub-conductive pillar 5042 are formed; the lower electrode conductive layer 5061a of the second sub-storage structure 5062 is connected with the first The lower electrode conductive layer 5061a of a sub-storage structure 5061 is in direct contact;
  • a plurality of dielectric layers 5061b covering the upper electrode conductive layer of each second sub-conductive pillar 5042 are formed; wherein the dielectric layer 5061b of the second sub-storage structure 5062 and the first sub-storage structure 5062 are formed.
  • the dielectric layer 5061b of the storage structure 5061 is in direct contact; and a second gap is formed between two adjacent dielectric layers;
  • an upper electrode conductive layer 5061c covering a plurality of the dielectric layers and a plurality of second gap bottoms; the upper electrode conductive layer 5061c of the second sub-storage structure 5062 and the upper electrode of the first sub-storage structure 5061
  • the conductive layer 5061c is in direct contact.
  • the lower electrode conductive layer 5061a is formed only on the top surface and sidewalls of the second sub-conductive pillar 5042; and the dielectric layer 5061b is formed only on the sidewalls of the lower electrode conductive layer 5061a.
  • a sub-storage structure can be formed in a gap with a higher aspect ratio; the process window is increased, the process difficulty is reduced, and the reliability of the semiconductor structure is improved.
  • a second support layer 508 is formed in a plurality of second gaps where the upper electrode conductive layer is formed.
  • the second support layer 508 includes a second conductive material layer 5081 and a second dielectric material layer 5082 located above the second conductive material layer 5081 .
  • the second conductive material layer 5081 may be formed first, and then the second dielectric material layer 5082 above the second conductive material layer 5081.
  • the second support layer 508 is the same as the first support layer 507; wherein the second conductive material layer 5081 is the same as the first conductive material layer 5071; the second dielectric material layer 5082 is the same as the first dielectric material layer 5072; Its materials and formation methods have been mentioned before and will not be described again here.
  • the method further includes:
  • a third sub-conductive pillar 5043 is formed on the exposed top surface of each second sub-conductive pillar 5042.
  • the third sub-conductive pillar 5043 is made of the same material as the first sub-conductive pillar 5041 and the second sub-conductive pillar 5042, and the formation method is the same, which has been mentioned before and will not be described again here.
  • the third sub-storage structure 5063 includes a lower electrode conductive layer 5061a, a dielectric layer 5061b and an upper electrode conductive layer 5061c.
  • forming a third sub-storage structure 5063 covering the third sub-conductive pillar 5043 includes:
  • each third sub-conductive pillar 5043 Through a selective deposition process, a plurality of lower electrode conductive layers 5061a covering the top surface and side walls of each third sub-conductive pillar 5043 are formed; the lower electrode conductive layer 5061a of the third sub-storage structure 5063 is connected with the third The lower electrode conductive layers 5061a of the two sub-storage structures 5062 are in direct contact;
  • the dielectric layer 5061b covering the plurality of third sub-storage structures 5063 and the upper electrode conductive layer 5061c at the bottom of the plurality of third gaps; wherein, the third conductive layer 5061c located on the side wall of the third sub-conductive pillar 5043 is formed.
  • the lower electrode conductive layer 5061a of the sub-storage structure 5063 is in direct contact with the lower electrode conductive layer 5061a of the second sub-storage structure 5062.
  • the method further includes:
  • a third conductive material layer 509 is formed in the plurality of third gaps where the upper electrode conductive layer is formed and on the top of the upper electrode conductive layer.
  • filling the third conductive material layer 509 in the third gap can reduce the process difficulty compared with filling the third gap with other materials; in addition, the third conductive material layer 509 can also be configured to fix a plurality of third sub-storage structures. Enhance the reliability of semiconductor structures.
  • the upper and lower electrode conductive layers in the first sub-storage structure, the second sub-storage structure and the third sub-storage structure are connected to each other to form complete upper and lower electrode layers;
  • the media layers in the first sub-storage structure, the second sub-storage structure, and the third sub-storage structure are connected to each other to form a complete media layer.
  • a fourth sub-conductive pillar, a fifth sub-conductive pillar, etc. can also be formed on the third sub-conductive pillar in the semiconductor structure. ; Correspondingly, a fourth sub-storage structure covering the fourth sub-conductive pillar is formed, and a fifth sub-storage structure covering the fifth sub-conductive pillar is formed, etc.
  • the conductive pillars can be formed only at the positions in direct contact with the semiconductor body through the epitaxial growth process, thereby reducing the difficulty of aligning the transistors and the conductive pillars, increasing the process window, and improving the reliability of the semiconductor structure; at the same time, , through the selective deposition process, the memory structure can be formed in the gap with a larger aspect ratio, increasing the process window and reducing the process difficulty.
  • the size of the memory structure in the semiconductor structure can be increased as the size of the conductive pillars increases, thereby further
  • the size of the storage structure can be set according to actual needs to increase the storage capacity of the storage structure.
  • An embodiment of the present disclosure also provides a semiconductor structure, which includes:
  • each transistor includes a semiconductor body extending along a first direction and a gate structure covering at least one side of the semiconductor body; the first direction is the thickness direction of the semiconductor layer ;
  • each conductive pillar is located on the top surface of a corresponding semiconductor body and is in direct contact with the corresponding semiconductor body;
  • a storage structure covers the plurality of conductive pillars.
  • each of the conductive pillars includes N sub-conductive pillars stacked along the first direction, where N is a positive integer greater than or equal to 1; accordingly, the storage structure includes N sub-conductive pillars stacked along the first direction. N sub-storage structures set by direction stacking.
  • the N 3, and the semiconductor structure includes:
  • a first sub-conductive pillar located on the top surface of each semiconductor body; a first sub-storage structure covering the sidewall of the first sub-conductive pillar;
  • a second sub-conductive pillar located on the top surface of each first sub-conductive pillar; a second sub-storage structure covering the side wall of the second sub-conductive pillar;
  • a third sub-conductive pillar located on the top surface of each second sub-conductive pillar; a third sub-storage structure covering the top surface and side walls of the third sub-conductive pillar;
  • first sub-conductive pillar, the second sub-conductive pillar and the third sub-conductive pillar are in direct contact with each other, and the first sub-storage structure, the second sub-storage structure and the third sub-storage structure are in direct contact with each other. touch.
  • the first sub-storage structure includes: a plurality of lower electrode conductive layers covering the sidewalls of each first sub-conductive pillar, a plurality of dielectric layers covering each of the lower electrode conductive layers, and a plurality of lower electrode conductive layers covering a plurality of The upper electrode conductive layer on the top surface of the semiconductor layer between the dielectric layer and the two adjacent dielectric layers is located in the upper electrode conductive layer, and the conductive material layer and the dielectric material layer are sequentially stacked;
  • the second sub-storage structure includes: a plurality of lower electrode conductive layers covering the side walls of each second sub-conductive pillar, a plurality of dielectric layers covering each of the lower electrode conductive layers, a plurality of the dielectric layers covering a plurality of the dielectric layers and
  • the upper electrode conductive layer on the top surface of the dielectric material layer is located in the upper electrode conductive layer, and the conductive material layer and the dielectric material layer are sequentially stacked;
  • the third sub-storage structure includes: a plurality of upper electrode conductive layers covering the sidewalls and top surfaces of each of the third sub-conductive pillars, a plurality of dielectric layers covering each of the upper electrode conductive layers, and a plurality of upper electrode conductive layers covering a plurality of the upper electrode conductive layers.
  • the dielectric layer and the lower electrode conductive layer on the top surface of the dielectric material layer, the conductive material layer located in the lower electrode conductive layer and on the top surface;
  • the upper and lower electrode conductive layers in the first, second and third sub-storage structures are connected to each other to form complete upper and lower electrode layers;
  • the media layers in the first, second and third sub-storage structures are connected to each other to form a complete media layer.
  • the transistor further includes: a source electrode and a drain electrode respectively disposed at two ends of the semiconductor body in the first direction.
  • the semiconductor structure further includes: a plurality of bit lines;
  • Each bit line is in direct contact with bottom surfaces of a plurality of semiconductor bodies.
  • the conductive pillar is formed by an epitaxial growth process; the memory structure is at least formed by a selective deposition process.
  • An embodiment of the present disclosure also provides a memory, the memory including: the semiconductor structure as described in any one of the above-mentioned embodiments of the present disclosure.

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Abstract

本公开实施例公开了一种半导体结构及其制作方法、存储器，其中，所述半导体结构包括：多个晶体管，位于半导体层中；每个晶体管均包括沿第一方向延伸的半导体主体及覆盖所述半导体主体的至少一个侧面的栅极结构；所述第一方向为所述半导体层的厚度方向；多个导电柱；每一导电柱位于相应的一个半导体主体的顶面上，且与所述相应的一个半导体主体直接接触；存储结构，覆盖所述多个导电柱。

Description

半导体结构及其制作方法、存储器
相关申请的交叉引用
本公开基于申请号为202210376236.X、名称为“半导体结构及其制作方法”、申请日为2022年04月11日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构及其制作方法、存储器。
背景技术
动态随机存取存储器(DRAM，Dynamic Random Access Memory)的存储阵列架构是由包括一个晶体管和一个电容器的存储单元(即1T1C的存储单元)组成的阵列。晶体管的栅极与字线相连，漏极与位线相连，源极与电容器相连。
随着动态随机存取存储器的尺寸不断缩小，电容器的尺寸也随之缩小。如何保证动态随机存取存储器中电容器的性能，成为亟待解决的问题。
发明内容
根据本公开的一个方面，提供了一种半导体结构，包括：
多个晶体管，位于半导体层中；每个晶体管均包括沿第一方向延伸的半导体主体及覆盖所述半导体主体的至少一个侧面的栅极结构；所述第一方向为所述半导体层的厚度方向；
多个导电柱；每一导电柱位于相应的一个半导体主体的顶面上，且与所述相应的一个半导体主体直接接触；
存储结构，覆盖所述多个导电柱。
上述方案中，每一所述导电柱包括沿所述第一方向堆叠设置的N个子导电柱，N为大于或者等于1的正整数；相应地，所述存储结构包括沿所述第一方向堆叠设置的N个子存储结构。
上述方案中，所述第一方向堆叠设置的三个子存储结构，所述半导体结构包括：
位于每一所述半导体主体顶面上的第一子导电柱；覆盖所述第一子导电柱侧壁的第一子存储结构；
位于每一所述第一子导电柱顶面上的第二子导电柱；覆盖所述第二子导电柱侧壁的第二子存储结构；
位于每一所述第二子导电柱顶面上的第三子导电柱；覆盖所述第三子导电柱顶面和侧壁的第三子存储结构；
其中，所述第一子导电柱、第二子导电柱、所述第三子导电柱之间直接接触，所述第一子存储结构、第二子存储结构、第三子存储结构之间直接接触。
上述方案中，第一子存储结构包括：覆盖每一所述第一子导电柱侧壁的多个下电极导电层，覆盖每一所述下电极导电层的多个介质层，覆盖多个所述介质层及相邻的两个所述介质层之间的半导体层的顶面的上电极导电层，位于所述上电极导电层中依次层叠设置的导电材料层和介 质材料层；
第二子存储结构包括：覆盖每一所述第二子导电柱侧壁的多个下电极导电层，覆盖每一所述下电极导电层的多个介质层，覆盖多个所述介质层及所述介质材料层顶面的上电极导电层，位于所述上电极导电层中依次层叠设置的导电材料层和介质材料层；
第三子存储结构包括：覆盖每一所述第三子导电柱侧壁和顶面的多个上电极导电层，覆盖每一所述上电极导电层的多个介质层，覆盖多个所述介质层及所述介质材料层顶面的下电极导电层，位于所述下电极导电层中及顶面的导电材料层；
其中，第一、二、三子存储结构中上、下电极导电层相互连接形成完整上、下电极层；
第一、二、三子存储结构中介质层相互连接形成完整介质层。
上述方案中，所述晶体管还包括：分别在所述第一方向上设置在所述半导体主体的两个端部处的源极和漏极。
上述方案中，所述半导体结构还包括：多条位线；
每一所述位线与多个所述半导体主体的底面直接接触。
上述方案中，所述导电柱通过外延生长工艺形成；所述存储结构至少通过选择性沉积工艺形成。
根据本公开的另一个方面，提供了一种存储器，包括：如本公开上述多个实施例中任一项所述的半导体结构。
根据本公开的再一个方面，提供了一种半导体结构的制作方法，所述方法包括：
提供半导体层；
在所述半导体层中形成多个晶体管，每个所述晶体管均包括沿第一方向延伸的半导体主体及覆盖所述半导体主体的至少一个侧面的栅极结构；所述第一方向为所述半导体层的厚度方向；
在每一所述半导体主体暴露的顶面均形成导电柱；
形成覆盖所述导电柱的存储结构。
上述方案中，每一所述导电柱包括沿所述第一方向堆叠设置的N个子导电柱，N为大于或者等于1的正整数；相应地，所述存储结构包括沿所述第一方向堆叠设置的N个子存储结构；
形成所述导电柱和所述存储结构，包括：
在所述半导体主体上形成一个子导电柱和相应的一个子存储结构；
沿所述第一方向，依次形成(N-1)个子导电柱和相应的(N-1)个子存储结构。
上述方案中，所述N＝3，所述形成所述导电柱和所述存储结构，包括：
在每一所述半导体主体暴露的顶面上均形成第一子导电柱；
形成覆盖所述第一子导电柱的第一子存储结构；
在每一所述第一子导电柱暴露的顶面上均形成第二子导电柱；所述第一子导电柱与相应的所述第二子导电柱直接接触；
形成覆盖所述第二子导电柱的第二子存储结构；所述第一子存储结构与所述第二子存储结构直接接触；
在每一所述第二子导电柱暴露的顶面上均形成第三子导电柱；所述第三子导电柱与相应的所述第二子导电柱直接接触；
形成覆盖所述第三子导电柱的第三子存储结构；所述第三子存储结构与所述第二子存储结构直接接触。
上述方案中，所述形成覆盖所述第一子导电柱的第一子存储结构，包括：
通过选择性沉积工艺，形成覆盖每一所述第一子导电柱顶面和侧壁的多个下电极导电层；
通过选择性沉积工艺，形成覆盖每一所述下电极导电层的多个介质层；相邻的两个所述介质层之间形成第一间隙；
形成覆盖多个所述介质层及多个所述第一间隙底部的上电极导电层。
上述方案中，所述方法还包括：
在每一所述第一子导电柱暴露的顶面上均形成第二子导电柱之前，在形成有上电极导电层多个第一间隙中依次形成导电材料层和介质材料层；
去除所述第一子导电柱顶面的下电极导电层、介质层及上电极导电层，以暴露所述第一子导电柱的顶面；其中，所述介质材料层的顶面与所述第一子导电柱暴露的顶面基本齐平。
上述方案中，所述导电柱的材料与所述导电材料层的材料相同或不同。
上述方案中，形成覆盖所述第二子导电柱的第二子存储结构，包括：
通过选择性沉积工艺，形成覆盖每一所述第二子导电柱顶面和侧壁的多个下电极导电层；
通过选择性沉积工艺，形成覆盖每一所述上电极导电层的多个介质层；相邻的两个所述介质层之间形成第二间隙；
形成覆盖多个所述介质层及多个所述第二间隙底部的上电极子导电层；所述第二子存储结构的上电极导电层与所述第一子存储结构的上电极导电层直接接触。
上述方案中，所述方法还包括：
在每一所述第二子导电柱暴露的顶面上均形成第三子导电柱之前，在形成有上电极导电层多个第二间隙中依次形成导电材料层和介质材料层；
去除所述第二子导电柱顶面的下电极导电层、介质层及上电极导电层，以暴露所述第二子导电柱的顶面；其中，所述介质材料层的顶面与所述上电极导电柱暴露的顶面基本齐平。
上述方案中，形成覆盖所述第三子导电柱的第三子存储结构，包括：
通过选择性沉积工艺，形成覆盖每一所述第三子导电柱顶面和侧壁的多个下电极导电层；
通过选择性沉积工艺，形成覆盖每一所述下电极导电层的多个介质层；相邻的两个所述介质层之间形成第三间隙；
形成覆盖多个所述介质层及多个所述第三间隙底部的上电极导电层；
所述方法还包括：
在形成有所述上电极导电层多个第三间隙中及所述上电极导电层的顶部形成第三导电材料层；
其中，第一、二、三子存储结构中上、下电极导电层相互连接形成完整上、下电极层；
第一、二、三子存储结构中介质层相互连接形成完整介质层。
上述方案中，在所述半导体层中形成多个晶体管，包括：
从所述半导体层的表面沿第一方向刻蚀所述半导体层，形成晶体管的半导体主体；
在所述半导体主体的至少一个侧面形成晶体管的栅极结构；
在所述半导体主体沿所述第一方向上相对的两端分别形成晶体管的源极和漏极。
上述方案中，所述方法还包括：在所述半导体层中形成多条位线；
每一所述位线与多个所述半导体主体的底面直接接触。
附图说明
图1a为本公开实施例中提供的一种DRAM晶体管的电路连接示意图；
图1b为本公开实施例中提供的一种存储器的结构示意图；
图2a为本公开实施例提供的掩埋式栅极结构排布示意图；
图2b为本公开实施例提供的环形栅极结构排布示意图；
图2c为本公开实施例提供的六方形最密堆积结构示意图；
图2d为本公开实施例提供的四方形堆积结构示意图；
图3为本公开实施例提供的半导体结构的制造方法的流程示意图；
图4a至图4d为本公开实施例提供的一种半导体结构的制造过程的剖面示意图；
图5a至5i为本公开实施例提供的另一种半导体结构的制造过程的剖面示意图；
图6为本公开实施例提供的一种半导体结构的剖面示意图。
附图标记说明：
30-半导体层；301-位线；302-晶体管；3021-源极；3022-漏极；3023-沟道区；3024-栅极结构；3024a-栅极；3024b-栅氧化层；303-绝缘层；304-导电柱；305-间隙；306-存储结构；3061-下电极导电层；3062-介质层；3063-上电极导电层；307-导电材料层；50-半导体层；502-晶体管；5041-第一子导电柱；5042-第二子导电柱；5043-第三子导电柱；505-间隙；5061-第一子存储结构；5062-第二子存储结构；5063-第三子存储结构；5061a-下电极导电层；5061b-介质层；5061c-上电极导电层；507-第一支撑层；5071-第一导电材料层；5072-第一介质材料层；508-第二支撑层；5081-第二导电材料层；5082-第二介质材料层；509-第三导电材料层。
在上述附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
具体实施方式
为使本公开实施例的技术方案和优点更加清楚，下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻的理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
可以理解的是，本公开中的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读，以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义，而且还包括在某物“上”且其间有居间特征或层的含义。
此外，为了便于描述，可以在本文中使用诸如“在……上”、“在……之上”、“在……上方”、“上”“上部”等的空间相对术语来描述如图所示的一个元件或特征与另一个元件或特征的关系。除了在附图中所描绘的取向之外，空间相对术语旨在涵盖设备在使用或操作中的不同取向。装置可以以其它方式定向(旋转90度或处于其它取向)并且同样可以相应地解释本文使用的空间相对描述词。
在本公开实施例中，术语“衬底”是指在其上添加后续材料层的材料。衬底本身可以被图案化。被添加在衬底顶部的材料可以被图案化或者可以保持未被图案化。此外，衬底可以包括多种半导体材料，例如硅、锗化硅、锗、砷化嫁、磷化锢等。替代地，衬底可以由非导电材料制成，例如玻璃、塑料或蓝宝石晶圆。
在本公开实施例中，术语“层”是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构厚度的均质或非均质连续结构的区域。例如，层可位于连续结构的顶表面和底表面之间，或者层可在连续结构顶表面和底表面处的任何水平面对之间。层可以水平、垂直和/或沿倾斜表面延伸。层可以包括多个子层。例如，互连层可包括一个或多个导体和接触子层(其中形成互连线和/或过孔触点)、以及一个或多个电介质子层。
在本公开实施例中，术语“第一”、“第二”等是配置为区别类似的对象，而不必配置为描述特定的顺序或先后次序。
本公开实施例涉及的半导体结构是将被配置为后续制程以形成最终的器件结构的至少一部 分。这里，所述最终的器件可以包括存储器，所述存储器包括但不限于动态随机存取存储器，以下仅以动态随机存取存储器为例进行说明。
但需要说明的是，以下实施例关于动态随机存取存储器的描述仅用来说明本公开，并不用来限制本公开的范围。
随着动态随机存取存储器技术的发展，存储单元的尺寸越来越小，其阵列架构由8F 2到6F 2再到4F 2；另外，基于动态随机存取存储器中对离子和漏电流的需求，存储器的架构从平面阵列晶体管(Planar Array Transistor)到凹栅阵列晶体管(Recess Gate Array Transistor)，又从凹栅阵列晶体管到掩埋式沟道阵列晶体管(Buried Channel Array Transistor)，再从掩埋式沟道阵列晶体管到垂直沟道阵列晶体管(Vertical Channel Array Transistor)。
本公开的一些实施例中，不论是平面晶体管还是掩埋式晶体管，动态随机存取存储器均由多个存储单元结构构成，每一个存储单元结构主要是由一个晶体管与一个由晶体管所操控的存储单元(存储电容)构成，即动态随机存取存储器包括1个晶体管(T，Transistor)和1个电容(C，Capacitor)(1T1C)的架构。
图1a为本公开实施例中提供的一种采用1T1C的架构的控制电路示意图，图1b为本公开实施例中提供的一种采用1T1C架构的晶体管形成DRAM存储阵列的结构示意图；如图1a、图1b所示，晶体管T的漏极与位线(BL，Bit Line)电连接，晶体管T的源区与电容C的其中一个电极板电连接，电容C的另外一个电极板可以连接参考电压，所述参考电压可以是地电压也可以是其他电压，晶体管T的栅极与字线(WL，Word Line)连接；通过字线WL施加电压控制晶体管T导通或截止，位线BL配置为在晶体管T导通时，对所述晶体管T执行读取或写入操作。
随着电子产品的集成度越来越高，动态随机存取存储器的尺寸也在不断减小，其存储单元阵列从掩埋式栅极(BWL，Buried Word Line)结构排布(参考图2a)发展至占用面积更小的环形栅极结构(GAA，Gate All Around)排布(参考图2b)；同时，DRAM中的电容尺寸也随之调整，从六边形最密堆积(参考图2c)演变成四边形堆积(参考图2d)；其中，电容的半径也变得更小，从杯状结构退回到柱状结构。
为了增大电容的尺寸，即增加电容器电极与介质层间的表面积，以提高存储器的存储容量，一方面可以增加电容高度，然而电容高度的增加会造成更高的深宽比(Aspect Ratio)，这种大的深宽比结构会增大工艺难度，反而限制电容的高度；另一方面可以采用多个电容堆叠的方式，然而，在实现电容的堆叠的过程中，多个电容之间的对准较为困难。
鉴于此，为解决上述问题中的一个或多个，本公开实施例提供了一种半导体结构的制作方法，以增大电容高度的同时，降低工艺难度，提高存储器的存储容量。图3为本公开实施例提供的半导体结构的制作方法的流程示意图。如图3所示，本公开实施例提供的半导体结构的制作方法包括以下步骤：
S100：提供半导体层；
S200：在所述半导体层中形成多个晶体管，每个所述晶体管均包括沿第一方向延伸的半导体主体及覆盖所述半导体主体的至少一个侧面的栅极结构；所述第一方向为所述半导体层的厚度方向；
S300：在每一所述半导体主体暴露的顶面均形成导电柱；
S400：形成覆盖所述导电柱的存储结构。
应当理解，图3中所示的步骤并非排他的，也可以在所示操作中的任何步骤之前、之后或之间执行其他步骤；图3中所示的各步骤可以根据实际需求进行顺序调整。图4a至图4d为本公开实施例提供的一种半导体结构的制作过程的剖面示意图。下面结合图3、图4a至图4d，对本公开实施例提供的半导体结构的制作方法进行详细地说明。
在步骤S100中，参考图4a，提供半导体层30。
所述半导体层的材料可以包括硅(Si)、锗(Ge)、锗化硅(SiGe)等；在一些具体实施例中，所述半导体层还可以为绝缘体上硅(SOI，Silicon-On-Insulator)或者绝缘体上锗(GOI，Germanium-On-Insulator)。
在一些实施例中，所述方法还包括：提供衬底；在所述衬底上形成半导体层。
这里，所述衬底可以包括多种半导体材料，例如硅、锗化硅、锗、砷化嫁、磷化锢等。在一些具体示例中，所述衬底的材料包括硅，所述半导体层包括锗化硅。
在一些实施例中，所述半导体层可以通过物理气相沉积(PVD，Physical Vapor Deposition)工艺、化学气相沉积(CVD，Chemical Vapor Deposition)工艺、原子层沉积(ALD，Atomic Layer Deposition)等工艺形成。
在一些实施例中，参考图4a，所述方法还包括：在形成多个晶体管之前，在所述半导体层中形成多条位线301。
这里，位线301配置为在晶体管302导通时，对所述晶体管302执行读取或写入操作。
所述位线301的材料包括但不限于金属钨。
所述位线301可以通过PVD、CVD或ALD等工艺形成。
在步骤S200中，在半导体层30中形成多个晶体管302。
这里，晶体管302与位线301直接接触。
在一些实施例中，晶体管的类型包括以下之一：
柱型栅极晶体管；
半环绕型栅极晶体管；
全环绕型栅极晶体管。
其中，柱型栅极晶体管中，栅极以柱状形式形成在沟道区的一侧；半环绕型栅极晶体管中，栅极半包围沟道区；全环绕型栅极晶体管中，栅极全包围沟道区。
本公开实施例中的晶体管类型可以包括上述多种类型，但不限于此。为了描述的清楚、简洁，以下实施例中以全环绕型栅极晶体管为例进行说明。但需要说明的是，以下实施例中关于晶体管类型的描述仅配置为说明本公开，并不用来限制本公开的范围。
在一些实施例中，在所述半导体层30中形成多个晶体管302，包括：
从所述半导体层30的表面沿第一方向刻蚀所述半导体层30，形成晶体管的半导体主体(图4a中未标示出)。
这里，在所述半导体主体沿所述第一方向上相对的两端分别形成晶体管的源极(S，Source)3021和漏极(D，Drain)3022。半导体主体中源极和漏极之间的区域为沟道区3023。
所述第一方向为所述半导体主体延伸的方向，所述第一方向也是垂直于所述半导体层30的方向。在一些具体示例中，所述第一方向可以是图4a中所示的Z轴方向。
在一些实施例中，源极和漏极分别为沟道区在Z轴方向上相对设置的两端，且源极和漏极可以互换位置。本公开实施例中，以漏极位于半导体主体的底部与位线连接为例进行说明；换言之，本公开实施例中，所述位线301与多个晶体管302中的半导体主体的底面(即漏极3022)直接接触。其中，半导体主体的顶面(即源极3021)暴露。
在一些实施例中，源极3021和漏极3022可以通过掺杂或扩散工艺形成，还可以是其他合适的方法。
示例性的，通过离子注入工艺实现掺杂，形成源极3021和漏极3022。
示例性的，可以先形成靠近位线301一端的漏极3022，再形成远离位线301一端的源极3021。
本公开实施例中，所述方法还包括：在所述半导体主体的侧面形成环绕型晶体管的栅极结构3024。
需要说明的是，这里的栅极结构3024包括栅极(G，Gate)3024a和栅氧化层(Gate oxide layer) 3024b；其中，栅氧化层3024b位于栅极3024a与沟道区3023之间，配置为电隔离沟道区3023和栅极3024a，减小晶体管的热载流子效应。
这里，栅极3024a的材料可以包括金属或多晶硅(Poly)等。栅氧化层3024b的材料可以包括但不限于氧化硅。
在一些实施例中，栅极3024a的形成方法包括但不限于PVD、CVD或ALD等。栅氧化层3024b的形成方法包括但不限于原位氧化。
需要说明的是，不同类型的晶体管，栅极3024a的位置不同；换言之，栅极3024a可以位于沟道区3023的一侧；也可以是位于沟道区3023的相对两侧；还可以是位于沟道区3023的周围。具体位置可以根据晶体管的类型而定；而在全环绕型栅极晶体管中，栅极3024a位于沟道区3023的周围。
本公开实施例中，所述方法还包括，在半导体层中的多个晶体管302之间的空隙处形成绝缘层303。
所述绝缘层303可以配置为电隔离多个晶体管302；还可以配置为起支撑作用。
这里，所述绝缘层303的材料包括但不限于氮化硅(SiN)。
形成所述绝缘层的方法包括但不限于PVD、CVD或ALD工艺等。
在步骤S300中，参考图4b，在每一所述半导体主体暴露的顶面均形成导电柱304。
在一些实施例中，导电柱304的材料可以是其他可沿着第一方向单向生长的导电材料。
示例性的，导电柱304的材料包括锗化硅。
在一些实施例中，所述导电柱304可以通过外延生长工艺形成。
这里，外延生长是指在半导体主体暴露的顶面上生长一层有一定要求的、与半导体主体晶向相同的材料层。
可以理解的是，本公开实施例中，通过外延生长工艺形成多个导电柱的过程中，可以实现导电柱与源极的自对准；即降低或避免导电柱304与半导体主体的顶面(即源极)的对准困难问题。
本公开实施例中，参考图4b，沿第二方向排布的多个导电柱之间存在间隙305。
这里，第二方向与第一方向垂直，且与所述半导体层的表面垂直。示例性的，第二方向可以是图4b中所示的X轴方向。
需要说明的是，在一些实施例中，所述半导体层30中形成的多个晶体管302可以分别沿第二方向和第三方向(这里，所述第三方向与第一方向和第二方向均垂直)呈阵列排布，此时，对应地，多个导电柱304分别沿所述第二方向和第三方向呈阵列排布。
在步骤S400中，参考图4c，在间隙305中形成覆盖所述导电柱的存储结构306。
这里，所述存储结构306配置为存储数据。示例性的，所述存储结构306包括电容。
在一些实施例中，形成所述存储结构306包括：
通过选择性沉积工艺，形成覆盖所述导电柱的下电极导电层3061；
通过选择性沉积工艺，形成覆盖所述下电极导电层表面的介质层3062；
形成覆盖所述介质层3062及所述绝缘层303顶面的上电极导电层3063。
这里，下电极导电层3061配置为作为电容的下电极；介质层3062配置为作为电容的电介质；上电极导电层3063配置为作为电容的上电极。
这里，选择性沉积工艺是指有选择性地将下电极导电层沉积在导电柱的表面；以及有选择性的将介质层沉积在下电极导电层的表面。
在一些实施例中，所述导电柱304的材料与所述下电极导电层3061或上电极导电层3063的材料可以相同，也可以不同。在一些具体实施例中，下电极导电层3061和上电极导电层3063的材料均可以包括但不限于氮化钛(TiN)。
所述介质层3062的材料包括高介电常数(High-K)材料，高介电常数材料一般指介电常数 高于3.9的材料，且通常显著高于该值。在一些具体示例中，所述介质层3062的材料可以包括但不限于氧化铪(HfO 2)。
需要说明的是，本公开实施例中，通过选择性沉积工艺形成下电极导电层3061的过程中，可以使得配置为形成下电极导电层3061的材料仅在所述导电柱304的表面生长，或形成在其他被选择的材料上，而不形成在绝缘层303的顶面，参考图4c。同样，通过选择性沉积工艺形成介质层3062的过程中，可以使得配置为形成介质层3062的材料仅形成在下电极导电层3061的表面，而不形成在绝缘层303的顶面，参考图4c。这样，一方面避免了在较高深宽比的间隙中形成下电极导电层3061和介质层3062，降低了工艺难度，提高了工艺窗口；另一方面，还可以避免采用其他工艺形成下电极导电层、介质层和上电极导电层的过程中出现的空洞问题；进而提高了半导体结构的可靠性。
另外，本公开实施例采用外延生长工艺形成导电柱304以及采用选择性沉积工艺形成存储结构306，还可以避免利用光罩技术在半导体层中形成刻蚀孔(配置为形成存储结构)的过程中，出现的多次重叠光刻问题。
需要说明的是，覆盖所述介质层3062及位于绝缘层303顶面上的上电极导电层3063是连成一个整体的，如此，可以增大上电极导电层3063的表面积，进而提高存储结构的存储容量。
在一些实施例中，形成上电极导电层3063的方法包括但不限于PVD、CVD、或ALD等工艺。可以理解的是，上电极导电层3063并不需要采用选择性沉积工艺。
在一些实施例中，参考图4d，所述上电极导电层3063可以直接将相邻的两个介质层3062之间的间隙填满。
在一些实施例中，形成上电极导电层3063后，在上电极导电层3063的间隙中，填充导电材料层307。在一些具体示例中，所述导电材料层307的材料可以包括但不限于锗化硅。
可以理解的是，通过沉积工艺直接将相邻的两个相邻介质层3062之间的间隙填满，以形成上电极导电层3063可能较为困难，容易形成空洞等，而通过在上电极导电层3063上方的间隙中形成导电材料层307，可以降低工艺难度，形成质量较好的上电极导电层3063。这里，导电材料层307还配置为提升半导体结构的稳固性。
本公开上述实施例中，可以通过外延生长工艺，仅在与半导体主体直接接触的位置处形成导电柱，降低晶体管与导电柱的对准难度，增大工艺窗口，提高半导体结构的可靠性；同时，通过选择性沉积工艺，可以在具有较大深宽比的间隙中形成存储结构，增大工艺窗口，降低工艺难度，提高半导体结构的可靠性。
可以理解的是，导电柱的高度决定了存储结构的尺寸和存储容量；基于此，在本公开的一些实施例中，为了提高存储结构的存储容量，增大导电柱的高度，提出了另一种半导体结构及其制作方法。
在另一些实施例中，每一所述导电柱包括沿所述第一方向堆叠设置的N个子导电柱，N为大于或者等于1的正整数；相应地，所述存储结构包括沿所述第一方向堆叠设置的N个子存储结构；
形成所述导电柱和所述存储结构，包括：
在所述半导体主体上形成一个子导电柱和相应的一个子存储结构；
沿所述第一方向，依次形成(N-1)个子导电柱和相应的(N-1)个子存储结构。
这里，通过形成多个子导电柱，并将多个子导电柱之间堆叠设置形成导电柱，使得导电柱的总高度增加，进而增大存储结构的表面，提高存储器的存储容量。
换言之，通过外延生长工艺在所述半导体层上方(即源极的两侧端部中远离沟道区的一侧端部)形成堆叠设置的多个子导电柱，和多个覆盖在对应的所述子导电柱表面的子存储结构。
其中，子导电柱与子存储结构一一对应。
需要说明的是，本公开实施例中，可以在半导体层上方形成N个堆叠设置的子导电柱；而 为了降低形成子存储结构的工艺难度，在每形成一个子导电柱后，形成相应的子存储结构。
相应的，N个沿Z轴方向堆叠设置的子导电柱，对应N个沿Z轴方向堆叠设置的子存储结构。
需要说明的是，位于顶部的子存储结构(第N个子存储结构)与非顶部的子存储结构(第一至第N个子存储结构)不同。具体地，非顶部的子存储结构仅覆盖相应的子导电柱的侧壁，而顶部子存储结构覆盖相应的子导电柱的顶部和侧壁。
在一些实施例中，形成第一至第N个子导电柱以及与其对应的子存储结构后，在第N个子导电柱的顶部形成部分子存储结构，以使位于第N个子导电柱顶部的子存储结构与侧壁的存储结构连接，形成完整的第N个子存储结构。
在另一些实施例中，先形成第一至第N-1个子导电柱以及与其对应的第一至第N-1个子存储结构；接下来形成第N个子导电柱；然后再同时形成覆盖第N个子导电柱的顶部和侧壁的子存储结构。
可以理解的是，同时形成覆盖第N个子导电柱的侧壁和顶部的子存储结构，可以节省工艺流程，降低制造成本。
示例性的，形成导电柱和存储结构包括依次形成沿Z轴方向堆叠设置的(N-1)个子导电柱和相应的(N-1)个子存储结构；其中，在每形成一个子导电柱后，形成相应的子存储结构。
接下来，在第N-1个子导电柱上形成第N个子导电柱；以及形成覆盖第N个子导电柱顶部和侧壁的第N个子存储结构。
这里，在形成第N个子存储结构的过程中，可根据事实需求进行选择形成位于第N个子导电柱顶部的子存储结构的时序。
下面为了更清楚的理解本公开的立意，以每一所述导电柱包括三个子导电柱，每个存储结构包括三个子存储结构为例进行详细说明。
也就是说，所述N＝3，所述导电柱包括第一子导电柱，位于所述第一子导电柱上的第二子导电柱，以及位于所述第二子导电柱上的第三子导电柱。
相应地，所述存储结构包括覆盖所述第一子导电柱的第一子存储结构、覆盖所述第二子导电柱的第二子存储结构、覆盖所述第三子导电柱的第三子存储结构。
在一些实施例中，形成所述导电柱和所述存储结构，包括：
在每一所述半导体主体暴露的顶面上均形成第一子导电柱；
形成覆盖所述第一子导电柱的第一子存储结构；
在每一所述第一子导电柱暴露的顶面上均形成第二子导电柱；所述第一子导电柱与相应的所述第二子导电柱直接接触；
形成覆盖所述第二子导电柱的第二子存储结构；所述第一子存储结构与所述第二子存储结构直接接触；
在每一所述第二子导电柱暴露的顶面上均形成第三子导电柱；所述第三子导电柱与相应的所述第二子导电柱直接接触；
形成覆盖所述第三子导电柱的第三子存储结构；所述第三子存储结构与所述第二子存储结构直接接触。
这里，参考图5a，提供半导体层50，所述半导体层50与前述实施例中的半导体层30相同；
半导体层50包括多个晶体管502；所述晶体管502的一端(即半导体主体暴露的端面)与半导体层50的顶面基本齐平；前已述及，这里不再赘述。
本公开实施例中，通过外延生长，在每一所述半导体主体暴露的顶面上均形成第一子导电柱5041。
这里，多个第一子导电柱之间存在间隙505。
接下来，参考图5b，在所述间隙505中，形成覆盖所述第一子导电柱5041的第一子存储 结构5061。其中，所述第一子存储结构5061包括下电极导电层5061a、介质层5061b以及上电极导电层5061c。
具体地，在一些实施例中，所述形成覆盖所述第一子导电柱的第一子存储结构，包括：
通过选择性沉积工艺，形成覆盖每一所述第一子导电柱5041顶面和侧壁的多个下电极导电层5061a；
通过选择性沉积工艺，形成覆盖每一所述下电极导电层5061a的多个介质层5061b；相邻的两个所述介质层5061b之间形成第一间隙(图5b中未标示出)；
形成覆盖多个所述介质层5061b及多个所述第一间隙底部的上电极导电层5061c。
这里，通过选择性沉积工艺可以仅在第一子导电柱5041顶面和侧壁形成的下电极导电层5061a，而不在第一间隙底部形成下电极导电层5061a。
同样，通过选择性沉积工艺可以仅在下电极导电层5061a的侧壁形成介质层5061b。
如此，能够在深宽比较深的间隙505中形成下电极导电层5061a和介质层5061b，增大工艺窗口，降低工艺难度，提高器件的可靠性。
可以理解的是，上电极导电层5061c并不需要采用选择性沉积工艺。示例性的，形成所述上电极导电层5061c的方法包括但不限于PVD、CVD或ALD工艺等。
这里，覆盖所述介质层5061b及位于绝缘层顶面上的上电极导电层5061c是连成一个整体的，如此，能够增大子存储结构的存储容量。
接下来，所述方法还包括：
在形成有上电极导电层多个第一间隙中形成第一支撑层507。
这里，第一支撑层507包括第一导电材料层5071和位于第一导电材料层5071上方的第一介质材料层5072。
参考图5c，通过PVD或CVD等工艺在第一子存储结构5061之间的多个第一间隙中以及上电极导电层5061c的顶面形成第一导电材料层5071。
在一些实施例中，第一导电材料层5071与导电柱504的材料可以相同，也可以不同；实际情况可根据实际需求进行选择设置。示例性的，第一导电材料层5071的组成材料包括但不限于锗化硅。
参考图5d，对所述第一导电材料层5071进行刻蚀，以去除位于上电极导电层5061c的顶面的第一导电材料层5071，以及位于第一间隙中的部分第一导电材料层5071。
这里，第一间隙中剩余的第一导电材料层5071的顶面低于上电极导电层5061c的顶面。
参考图5e，在上电极导电层5061c的顶面和第一导电材料层5071的顶面形成第一介质材料层5072。
在一些具体示例中，所述第一介质材料层5072的材料包括但不限于氮化硅(SiN)。
形成第一介质材料层5072的方法包括但不限于PVD、CVD、或ALD工艺等。
需要说明的是，这里第一介质材料层采用氮化硅，可以使得后续工艺中，在通过外延生长形成第二子导电柱5042，第二子导电柱5042不形成在第一介质材料层(氮化硅)上以及在通过选择性沉积形成第二子存储结构中的下电极导电层和介质层时，第二子存储结构的下电极导电层和介质层不形成在第一介质材料层(氮化硅)上。
参考图5f，所述方法还包括：
去除所述第一子导电柱5041顶面的下电极导电层5061a、介质层5061b、上电极导电层5061c以及第一介质材料层5072，以暴露所述第一子导电柱5041的顶面；此时，第一间隙中剩余的所述第一介质材料层5072的顶面与所述第一子导电柱5041暴露的顶面基本齐平。
在一些实施例中，所述去除工艺包括但不限于化学机械研磨(CMP，Chemical Mechanical Polish)。
接下来，参考图5g，在每一所述第一子导电柱5041暴露的顶面上均形成第二子导电柱5042。
这里，所述第二子导电柱5042与所述第一子导电柱5041的材料相同，形成方法相同，前已述及，这里不再赘述。
接下来，参考图5h，形成覆盖所述第二子导电柱5042的第二子存储结构5062。其中，所述第二子存储结构5062包括下电极导电层5061a、介质层5061b以及上电极导电层5061c。
这里，下电极导电层5061a和上电极导电层5061c的材料均可以包括但不限于氮化钛。
具体地，在一些实施例中，所述形成覆盖所述第二子导电柱5042的第二子存储结构5062，包括：
通过选择性沉积工艺，形成覆盖每一所述第二子导电柱5042顶面和侧壁的多个下电极导电层5061a；所述第二子存储结构5062的下电极导电层5061a与所述第一子存储结构5061的下电极导电层5061a直接接触；
通过选择性沉积工艺，形成覆盖每一所述第二子导电柱5042的上电极导电层的多个介质层5061b；其中，所述第二子存储结构5062的介质层5061b与所述第一子存储结构5061的介质层5061b直接接触；且相邻的两个所述介质层之间形成第二间隙；
形成覆盖多个所述介质层及多个所述第二间隙底部的上电极导电层5061c；所述第二子存储结构5062的上电极导电层5061c与所述第一子存储结构5061的上电极导电层5061c直接接触。这里，需要说明的是，通过选择性沉积工艺，仅在第二子导电柱5042顶面和侧壁形成的下电极导电层5061a；以及仅在下电极导电层5061a的侧壁形成介质层5061b。这样，可以在较高深宽比的间隙中形成子存储结构；增大工艺窗口，降低工艺难度，提高半导体结构的可靠性。
接下来，在形成第二子存储结构5062后，为了增大半导体结构的稳固性，提高存储器器件的可靠性，在形成有上电极导电层的多个第二间隙中形成第二支撑层508。
这里，第二支撑层508包括第二导电材料层5081和位于所述第二导电材料层5081上方的第二介质材料层5082。
实际操作过程中，可以先形成第二导电材料层5081，再在所述第二导电材料层5081上方的第二介质材料层5082。
需要说明的是，第二支撑层508与第一支撑层507相同；其中，第二导电材料层5081与第一导电材料层5071相同；第二介质材料层5082与第一介质材料层5072相同；其材料及形成方法前已述及，这里不再赘述。
在一些实施例中，所述方法还包括：
去除所述第二子导电柱5042顶面的下电极导电层5061a、介质层5061b及上电极导电层5061c，以暴露所述第二子导电柱5042的顶面；其中，所述第二介质材料层5082的顶面与所述上电极导电层5061c暴露的顶面基本齐平。
接下来，参考图5h，在每一所述第二子导电柱5042暴露的顶面上均形成第三子导电柱5043。
这里，所述第三子导电柱5043与所述第一子导电柱5041、所述第二子导电柱5042的材料相同，形成方法相同，前已述及，这里不再赘述。
接下来，参考图5i，形成覆盖所述第三子导电柱5043的第三子存储结构5063。其中，所述第三子存储结构5063包括下电极导电层5061a、介质层5061b以及上电极导电层5061c。
在一些实施例中，形成覆盖所述第三子导电柱5043的第三子存储结构5063，包括：
通过选择性沉积工艺，形成覆盖每一所述第三子导电柱5043顶面和侧壁的多个下电极导电层5061a；所述第三子存储结构5063的下电极导电层5061a与所述第二子存储结构5062的下电极导电层5061a直接接触；
通过选择性沉积工艺，形成覆盖每一所述第三子导电柱5043的下电极导电层的多个介质层；所述第三子存储结构5063的介质层5061b与所述第二子存储结构5062的介质层5061b直接接触；其中，沿X轴方向相邻的两个第三子存储结构5063的介质层5061b之间形成第三间隙(图5f中未标出)；
形成覆盖多个所述第三子存储结构5063的介质层5061b及多个所述第三间隙底部的上电极导电层5061c；其中，位于所述第三子导电柱5043侧壁的所述第三子存储结构5063的下电极导电层5061a与所述第二子存储结构5062的下电极导电层5061a直接接触。
本公开的一些实施例中，所述方法还包括：
在形成有所述上电极导电层多个第三间隙中及所述上电极导电层的顶部形成第三导电材料层509。
这里，在第三间隙填充第三导电材料层509相较于采用其他材料填充第三间隙时，可以降低工艺难度；另外第三导电材料层509还可以配置为固定多个第三子存储结构，增强半导体结构的可靠性。
本公开实施例中，第一子存储结构、第二子存储结构、第三子存储结构中上、下电极导电层相互连接形成完整上、下电极层；
以及第一子存储结构、第二子存储结构、第三子存储结构中介质层相互连接形成完整介质层。
在一些实施例中，参考图6，为了增大存储结构的高度，增加半导体结构的存储容量，半导体结构中还可以在第三子导电柱上形成第四子导电柱、第五子导电柱等；相应的，形成覆盖第四子导电柱的第四子存储结构，以及形成覆盖第五子导电柱的第五子存储结构等。
本公开上述实施例中，可以通过外延生长工艺，仅在与半导体主体直接接触的位置处形成导电柱，降低晶体管与导电柱的对准难度，增大工艺窗口，提高半导体结构的可靠性；同时，通过选择性沉积工艺，可以在具有较大深宽比的间隙中形成存储结构，增大工艺窗口，降低工艺难度。并且，在另一些实施例中，通过依次形成多个直接接触的子导电柱，以及相应的子存储结构，使得半导体结构中的存储结构的尺寸可以随着导电柱的尺寸的增加而增加，进而可以根据实际需求设置存储结构的尺寸，提高存储结构的存储容量。
本公开实施例中还提供了一种半导体结构，所述半导体结构，包括：
多个晶体管，位于半导体层中；每个晶体管均包括沿第一方向延伸的半导体主体及覆盖所述半导体主体的至少一个侧面的栅极结构；所述第一方向为所述半导体层的厚度方向；
多个导电柱；每一导电柱位于相应的一个半导体主体的顶面上，且与所述相应的一个半导体主体直接接触；
存储结构，覆盖所述多个导电柱。
在一些实施例中，每一所述导电柱包括沿所述第一方向堆叠设置的N个子导电柱，N为大于或者等于1的正整数；相应地，所述存储结构包括沿所述第一方向堆叠设置的N个子存储结构。
在一些实施例中，所述N＝3，所述半导体结构包括：
位于每一所述半导体主体顶面上的第一子导电柱；覆盖所述第一子导电柱侧壁的第一子存储结构；
位于每一所述第一子导电柱顶面上的第二子导电柱；覆盖所述第二子导电柱侧壁的第二子存储结构；
位于每一所述第二子导电柱顶面上的第三子导电柱；覆盖所述第三子导电柱顶面和侧壁的第三子存储结构；
其中，所述第一子导电柱、第二子导电柱、所述第三子导电柱之间直接接触，所述第一子存储结构、第二子存储结构、第三子存储结构之间直接接触。
在一些实施例中第一子存储结构包括：覆盖每一所述第一子导电柱侧壁的多个下电极导电层，覆盖每一所述下电极导电层的多个介质层，覆盖多个所述介质层及相邻的两个所述介质层之间的半导体层的顶面的上电极导电层，位于所述上电极导电层中依次层叠设置的导电材料层和介质材料层；
第二子存储结构包括：覆盖每一所述第二子导电柱侧壁的多个下电极导电层，覆盖每一所述下电极导电层的多个介质层，覆盖多个所述介质层及所述介质材料层顶面的上电极导电层，位于所述上电极导电层中依次层叠设置的导电材料层和介质材料层；
第三子存储结构包括：覆盖每一所述第三子导电柱侧壁和顶面的多个上电极导电层，覆盖每一所述上电极导电层的多个介质层，覆盖多个所述介质层及所述介质材料层顶面的下电极导电层，位于所述下电极导电层中及顶面的导电材料层；
其中，第一、二、三子存储结构中上、下电极导电层相互连接形成完整上、下电极层；
第一、二、三子存储结构中介质层相互连接形成完整介质层。
在一些实施例中，所述晶体管还包括：分别在所述第一方向上设置在所述半导体主体的两个端部处的源极和漏极。
在一些实施例中，所述半导体结构还包括：多条位线；
每一所述位线与多个所述半导体主体的底面直接接触。
在一些实施例中，所述导电柱通过外延生长工艺形成；所述存储结构至少通过选择性沉积工艺形成。
本公开实施例还提供了一种存储器，所述存储器包括：如本公开上述多个实施例中任一项所述的半导体结构。
本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种半导体结构，包括：
    多个晶体管，位于半导体层中；每个晶体管均包括沿第一方向延伸的半导体主体及覆盖所述半导体主体的至少一个侧面的栅极结构；所述第一方向为所述半导体层的厚度方向；
    多个导电柱；每一导电柱位于相应的一个半导体主体的顶面上，且与所述相应的一个半导体主体直接接触；
    存储结构，覆盖所述多个导电柱。
  2. 根据权利要求1所述的半导体结构，其中，每一所述导电柱包括沿所述第一方向堆叠设置的N个子导电柱，N为大于或者等于1的正整数；相应地，所述存储结构包括沿所述第一方向堆叠设置的N个子存储结构。
  3. 根据权利要求2所述的半导体结构，其中，所述第一方向堆叠设置的三个子存储结构，所述半导体结构包括：
    位于每一所述半导体主体顶面上的第一子导电柱；覆盖所述第一子导电柱侧壁的第一子存储结构；
    位于每一所述第一子导电柱顶面上的第二子导电柱；覆盖所述第二子导电柱侧壁的第二子存储结构；
    位于每一所述第二子导电柱顶面上的第三子导电柱；覆盖所述第三子导电柱顶面和侧壁的第三子存储结构；
    其中，所述第一子导电柱、第二子导电柱、所述第三子导电柱之间直接接触，所述第一子存储结构、第二子存储结构、第三子存储结构之间直接接触。
  4. 根据权利要求3所述的半导体结构，其中，
    第一子存储结构包括：覆盖每一所述第一子导电柱侧壁的多个下电极导电层，覆盖每一所述下电极导电层的多个介质层，覆盖多个所述介质层及相邻的两个所述介质层之间的半导体层的顶面的上电极导电层，位于所述上电极导电层中依次层叠设置的导电材料层和介质材料层；
    第二子存储结构包括：覆盖每一所述第二子导电柱侧壁的多个下电极导电层，覆盖每一所述下电极导电层的多个介质层，覆盖多个所述介质层及所述介质材料层顶面的上电极导电层，位于所述上电极导电层中依次层叠设置的导电材料层和介质材料层；
    第三子存储结构包括：覆盖每一所述第三子导电柱侧壁和顶面的多个上电极导电层，覆盖每一所述上电极导电层的多个介质层，覆盖多个所述介质层及所述介质材料层顶面的下电极导电层，位于所述下电极导电层中及顶面的导电材料层；
    其中，第一、二、三子存储结构中上、下电极导电层相互连接形成完整上、下电极层；
    第一、二、三子存储结构中介质层相互连接形成完整介质层。
  5. 根据权利要求1所述的半导体结构，其中，所述晶体管还包括：分别在所述第一方向上设置在所述半导体主体的两个端部处的源极和漏极。
  6. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括：多条位线；
    每一所述位线与多个所述半导体主体的底面直接接触。
  7. 根据权利要求1所述的半导体结构，其中，所述导电柱通过外延生长工艺形成；所述存储结构至少通过选择性沉积工艺形成。
  8. 一种存储器，包括：如权利要求1至7中任一项所述的半导体结构。
  9. 一种半导体结构的制作方法，所述方法包括：
    提供半导体层；
    在所述半导体层中形成多个晶体管，每个所述晶体管均包括沿第一方向延伸的半导体主体 及覆盖所述半导体主体的至少一个侧面的栅极结构；所述第一方向为所述半导体层的厚度方向；
    在每一所述半导体主体暴露的顶面均形成导电柱；
    形成覆盖所述导电柱的存储结构。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，每一所述导电柱包括沿所述第一方向堆叠设置的N个子导电柱，N为大于或者等于1的正整数；相应地，所述存储结构包括沿所述第一方向堆叠设置的N个子存储结构；
    形成所述导电柱和所述存储结构，包括：
    在所述半导体主体上形成一个子导电柱和相应的一个子存储结构；
    沿所述第一方向，依次形成(N-1)个子导电柱和相应的(N-1)个子存储结构。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，所述第一方向堆叠设置的三个子存储结构，所述形成所述导电柱和所述存储结构，包括：
    在每一所述半导体主体暴露的顶面上均形成第一子导电柱；
    形成覆盖所述第一子导电柱的第一子存储结构；
    在每一所述第一子导电柱暴露的顶面上均形成第二子导电柱；所述第一子导电柱与相应的所述第二子导电柱直接接触；
    形成覆盖所述第二子导电柱的第二子存储结构；所述第一子存储结构与所述第二子存储结构直接接触；
    在每一所述第二子导电柱暴露的顶面上均形成第三子导电柱；所述第三子导电柱与相应的所述第二子导电柱直接接触；
    形成覆盖所述第三子导电柱的第三子存储结构；所述第三子存储结构与所述第二子存储结构直接接触。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，所述形成覆盖所述第一子导电柱的第一子存储结构，包括：
    通过选择性沉积工艺，形成覆盖每一所述第一子导电柱顶面和侧壁的多个下电极导电层；
    通过选择性沉积工艺，形成覆盖每一所述下电极导电层的多个介质层；相邻的两个所述介质层之间形成第一间隙；
    形成覆盖多个所述介质层及多个所述第一间隙底部的上电极导电层。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，所述方法还包括：
    在每一所述第一子导电柱暴露的顶面上均形成第二子导电柱之前，在形成有上电极导电层多个第一间隙中依次形成导电材料层和介质材料层；
    去除所述第一子导电柱顶面的下电极导电层、介质层及上电极导电层，以暴露所述第一子导电柱的顶面；其中，所述介质材料层的顶面与所述第一子导电柱暴露的顶面基本齐平。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，所述导电柱的材料与所述导电材料层的材料相同或不同。
  15. 根据权利要求13所述的半导体结构的制作方法，其中，形成覆盖所述第二子导电柱的第二子存储结构，包括：
    通过选择性沉积工艺，形成覆盖每一所述第二子导电柱顶面和侧壁的多个下电极导电层；
    通过选择性沉积工艺，形成覆盖每一所述上电极导电层的多个介质层；相邻的两个所述介质层之间形成第二间隙；
    形成覆盖多个所述介质层及多个所述第二间隙底部的上电极子导电层；所述第二子存储结构的上电极导电层与所述第一子存储结构的上电极导电层直接接触。
  16. 根据权利要求15所述的半导体结构的制作方法，其中，所述方法还包括：
    在每一所述第二子导电柱暴露的顶面上均形成第三子导电柱之前，在形成有上电极导电层多个第二间隙中依次形成导电材料层和介质材料层；
    去除所述第二子导电柱顶面的下电极导电层、介质层及上电极导电层，以暴露所述第二子导电柱的顶面；其中，所述介质材料层的顶面与所述上电极导电柱暴露的顶面基本齐平。
  17. 根据权利要求15所述的半导体结构的制作方法，其中，形成覆盖所述第三子导电柱的第三子存储结构，包括：
    通过选择性沉积工艺，形成覆盖每一所述第三子导电柱顶面和侧壁的多个下电极导电层；
    通过选择性沉积工艺，形成覆盖每一所述下电极导电层的多个介质层；相邻的两个所述介质层之间形成第三间隙；
    形成覆盖多个所述介质层及多个所述第三间隙底部的上电极导电层；
    所述方法还包括：
    在形成有所述上电极导电层多个第三间隙中及所述上电极导电层的顶部形成第三导电材料层；
    其中，第一、二、三子存储结构中上、下电极导电层相互连接形成完整上、下电极层；
    第一、二、三子存储结构中介质层相互连接形成完整介质层。
  18. 根据权利要求9所述的半导体结构的制作方法，其中，
    在所述半导体层中形成多个晶体管，包括：
    从所述半导体层的表面沿第一方向刻蚀所述半导体层，形成晶体管的半导体主体；
    在所述半导体主体的至少一个侧面形成晶体管的栅极结构；
    在所述半导体主体沿所述第一方向上相对的两端分别形成晶体管的源极和漏极。
  19. 根据权利要求9所述的半导体结构的制作方法，其中，所述方法还包括：
    在所述半导体层中形成多条位线；
    每一所述位线与多个所述半导体主体的底面直接接触。
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CN112951770A (zh) * 2021-04-15 2021-06-11 长鑫存储技术有限公司 存储器的制作方法及存储器

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