WO2023226081A1 - 半导体结构及其制作方法、存储器 - Google Patents

半导体结构及其制作方法、存储器 Download PDF

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Publication number
WO2023226081A1
WO2023226081A1 PCT/CN2022/097307 CN2022097307W WO2023226081A1 WO 2023226081 A1 WO2023226081 A1 WO 2023226081A1 CN 2022097307 W CN2022097307 W CN 2022097307W WO 2023226081 A1 WO2023226081 A1 WO 2023226081A1
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Prior art keywords
gate
layer
material layer
adjustment
gate structure
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PCT/CN2022/097307
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English (en)
French (fr)
Inventor
郗宁
卢经文
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长鑫存储技术有限公司
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Priority to US17/951,518 priority Critical patent/US20230015580A1/en
Publication of WO2023226081A1 publication Critical patent/WO2023226081A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure, a manufacturing method thereof, and a memory.
  • Transistors in semiconductor structures are widely used as switching devices or driving devices in electronic equipment.
  • transistors can be used in dynamic random access memory (DRAM) to control the capacitance in each memory cell.
  • DRAM dynamic random access memory
  • the basic memory cell structure of dynamic random access memory consists of a transistor and a storage capacitor. Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit (bit) is 1 or 0.
  • Embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a memory.
  • a semiconductor structure including:
  • the source and drain are both located in the substrate;
  • a gate dielectric layer located in the substrate and covering the sidewalls and bottom of the trench defined between the source and drain electrodes;
  • a gate adjustment layer located at least between the gate dielectric layer and the gate structure
  • the sidewall of the gate structure has a first control area covered by the gate adjustment layer, and the bottom surface of the gate structure has a second control area not covered by the gate adjustment layer;
  • the gate adjustment layer is made of polysilicon.
  • the area of the first control region accounts for 60% to 100% of the area of the sidewall of the gate structure.
  • the top edge of the first control region is not lower than the top edge of the sidewall of the gate structure.
  • the gate structure has a protrusion at the position of the second control area.
  • the gate adjustment layer is doped with impurities, and the doping type of the gate adjustment layer is different from the doping type of the source and drain.
  • the doping concentration range of the doping impurities of the gate adjustment layer is 10 19 to 10 20 ions/cm 3 .
  • the gate adjustment layer covers at least part of the sidewalls of the gate structure and does not cover the bottom surface of the gate structure.
  • the gate adjustment layer covers the sidewalls of the gate structure and covers the top surface and part of the bottom surface of the gate structure.
  • the contact interface between the gate adjustment layer and the top surface of the gate structure is a curved surface.
  • the material of the gate structure includes: tungsten and/or titanium nitride.
  • the gate structure includes: a gate electrode, and a first barrier layer covering the sidewalls and bottom of the gate electrode.
  • the gate structure further includes a second barrier layer located on top of the gate.
  • the semiconductor structure further includes: an insulating cap layer located in the trench and on the gate structure.
  • a memory including:
  • a memory cell coupled to one of the source and drain
  • a method of manufacturing a semiconductor structure including:
  • the substrate has a source electrode, a drain electrode, a trench between the source electrode and the drain electrode, and a gate dielectric layer covering the sidewalls and bottom of the trench;
  • the material of the gate structure includes metal or a metal compound
  • the sidewall of the gate structure has a first control area covered by the gate adjustment layer, and the bottom surface of the gate structure has a second control area not covered by the gate adjustment layer.
  • the area of the first control region accounts for 60% to 100% of the area of the sidewall of the gate structure.
  • the top edge of the first control region is not lower than the top edge of the sidewall of the gate structure.
  • the gate structure has a protrusion at the position of the second control area.
  • forming the gate adjustment layer includes:
  • the first gate adjustment material layer is subjected to a doping treatment with a doping type that is different from the source and drain doping types to obtain the gate adjustment layer.
  • forming a gate adjustment layer that at least partially covers the gate dielectric layer includes:
  • the second gate adjustment material layer covering the bottom and part of the sidewall of the gate dielectric layer is removed to form the gate adjustment layer.
  • the gate structure includes: a gate electrode and a first barrier layer; the method of forming the gate structure includes:
  • forming a gate adjustment layer that at least partially covers the gate dielectric layer includes:
  • the gate structure includes: a gate electrode, a first barrier layer and a second barrier layer; the method of forming the gate structure includes:
  • the method also includes:
  • An insulating capping layer is formed in the trench in which the gate structure is formed and on the gate structure.
  • Embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a memory.
  • the semiconductor structure includes: a source electrode and a drain electrode, both located in a substrate; a gate dielectric layer located in the substrate and covered by The sidewalls and bottom of the trench defined between the source electrode and the drain electrode; a gate electrode structure located in the trench; a material of the gate electrode structure including a metal or a metal compound; a gate adjustment layer, at least is located between the gate dielectric layer and the gate structure; wherein the sidewalls of the gate structure have a first control area covered by the gate adjustment layer, and the bottom surface of the gate structure has The second control area is not covered by the gate adjustment layer; the material of the gate adjustment layer includes polysilicon.
  • the sidewall of the gate structure has a first control region covered by the gate adjustment layer, thereby effectively improving the problem of gate-induced drain leakage, while the bottom surface of the gate structure has a first control region that is not covered by the gate adjustment layer.
  • the second area covered by the gate adjustment layer can improve the problem that the gate structure is completely wrapped by the gate adjustment layer, causing excessive resistance and thus reducing the current.
  • Figure 1 is a schematic diagram of a circuit connection of a semiconductor structure provided in an embodiment of the present disclosure
  • Figure 3a is a schematic diagram 1 of another semiconductor structure provided in an embodiment of the present disclosure.
  • Figure 3b is a second schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure.
  • Figure 3c is a schematic diagram three of another semiconductor structure provided in an embodiment of the present disclosure.
  • Figure 3d is a schematic diagram 4 of another semiconductor structure provided in an embodiment of the present disclosure.
  • Figure 4 is a schematic flow diagram of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure
  • 5a-5i are schematic process diagrams of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.
  • 6a to 6l are schematic process diagrams of another method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.
  • spatially relative terms such as “on”, “over”, “over”, “on”, “upper”, etc. may be used herein to describe the figures. The relationship of one element or feature to another element or feature.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • the term "layer" refers to a portion of material that includes a region having a thickness.
  • a layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure.
  • the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal plane at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along inclined surfaces.
  • a layer can include multiple sub-layers.
  • an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.
  • the terms "first”, “second”, etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
  • the semiconductor structure involved in the embodiments of the present disclosure is at least a portion that will be used in subsequent processes to form a final device structure.
  • the final device may include a memory, and the memory includes but is not limited to a dynamic random access memory. The following only takes the dynamic random access memory as an example for description.
  • the size of memory cells is getting smaller and smaller, and its array architecture has changed from 8F 2 to 6F 2 to 4F 2 ; in addition, based on the demand for ions and leakage current in dynamic random access memory , the memory architecture has changed from Planar Array Transistor to Recess Gate Array Transistor, then from Recess Gate Array Transistor to Buried Channel Array Transistor, and then from Buried Channel Array Transistor. channel array transistor to vertical channel array transistor (Vertical Channel Array Transistor).
  • dynamic random access memory is composed of multiple memory cell structures.
  • Each memory cell structure is mainly composed of a transistor and a It is composed of a memory unit (storage capacitor) controlled by a transistor, that is, the dynamic random access memory includes a transistor (T, Transistor) and a capacitor (C, Capacitor) (1T1C); its main principle of action is to use the capacitor
  • T, Transistor transistor
  • C, Capacitor capacitor
  • the amount of charge stored inside represents whether a binary bit (bit) is 1 or 0.
  • Figure 1 is a schematic circuit connection diagram using a 1T1C architecture provided in an embodiment of the present disclosure.
  • the drain of the transistor T is electrically connected to the bit line (BL, Bit Line), and the source of the transistor T is electrically connected to One of the electrode plates of the capacitor C is electrically connected, and the other electrode plate of the capacitor C can be connected to a reference voltage.
  • the reference voltage can be the ground voltage or other voltages.
  • the gate of the transistor T is connected to the word line (WL, Word Line). Connection; applying a voltage through the word line WL controls the transistor T to be turned on or off, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is turned on.
  • Figure 2 is a schematic structural diagram of a semiconductor structure provided in an embodiment of the disclosure; an embodiment of the disclosure provides a semiconductor structure, as shown in Figure 2, the semiconductor structure includes:
  • the source electrode 102 and the drain electrode 103 are both located in the substrate 101;
  • Gate dielectric layer 105 is located in the substrate 101 and covers the sidewalls and bottom of the trench defined between the source electrode 102 and the drain electrode 103;
  • the gate structure 107 is located in the trench; the material of the gate structure 107 includes metal or metal compounds.
  • the gate structure 107 with metal tungsten and metal compound titanium nitride has lower resistance and can reduce word line resistance.
  • the size of memories is getting smaller and smaller.
  • Gate-induced drain leakage has a huge adverse impact on the formation of buried array transistors, reducing the performance of the semiconductor structure.
  • the source electrode 102 and the drain electrode 103 are both located in the substrate 101;
  • Gate dielectric layer 105 is located in the substrate 101 and covers the sidewalls and bottom of the trench defined between the source electrode 102 and the drain electrode 103;
  • Gate structure 107 is located in the trench; the material of the gate structure 107 includes metal or metal compounds;
  • Gate adjustment layer 106 is located at least between the gate dielectric layer 105 and the gate structure 107;
  • the sidewalls of the gate structure 107 have a first control area covered by the gate adjustment layer 106 , and the bottom surface of the gate structure 107 has a second control area not covered by the gate adjustment layer 106 .
  • Control area The material of the gate adjustment layer 106 includes polysilicon.
  • the semiconductor structure may include a transistor.
  • the substrate 101 may include a single semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (such as a silicon germanium (SiGe) substrate). substrates, etc.), silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, etc.
  • the substrate is a silicon substrate.
  • the substrate 101 between the source electrode 102 and the drain electrode 103 constitutes a channel region, and the channel region provided in the embodiment of the present disclosure may be a U-shaped channel region.
  • the gate dielectric layer 105 can also be called a gate oxide layer and is used to electrically isolate the channel region and the gate structure 107 .
  • the material of the gate dielectric layer 105 may include but is not limited to silicon oxide.
  • the gate dielectric layer 105 can be used to induce different electric fields and apply them to the surface of the channel region, so that the minority carriers in the semiconductor structure are adsorbed to the surface of the channel region, accumulate and invert, thereby realizing source switching. 102 and drain 103.
  • the first control area refers to the portion of the sidewall of the gate structure 107 that is covered by the gate adjustment layer 106
  • the second control area refers to the bottom surface of the gate structure 107 that is not covered by the gate adjustment layer 106 part.
  • the embodiment of the present disclosure also provides a second control region on the basis of the first control region, so that the problem of gate-induced drain leakage can be effectively improved and the current can be controlled at an appropriate level. within the range.
  • the area of the first control region accounts for 60% to 100% of the area of the sidewalls of the gate structure 107 .
  • Figure 3b is a second structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • the area of the first control region accounts for 60% to 100% of the area of the sidewalls of the gate structure 107. It can be understood that the sidewalls of the gate structure 107 may be completely covered by the gate adjustment layer 106, or may be partially covered by the gate adjustment layer 106.
  • the polar adjustment layer 106 covers.
  • the area of the first control region accounts for 100% of the area of the sidewalls of the gate structure 107 , it means that the sidewalls of the gate structure 107 are entirely covered by the gate adjustment layer 106 .
  • the side walls of the gate structure 107 are completely covered by the gate adjustment layer 106 ; as shown in FIG. 3 b , the side walls of the gate structure 107 are partially covered by the gate adjustment layer 106 .
  • the choice can be made based on the requirements for both gate-induced drain leakage and resistance.
  • the first control region is provided around the gate structure 107. It can be understood that the drawings in the embodiments of the present disclosure only show cross-sectional views of the semiconductor structure, and the actual gate structure 107 is columnar. , when the first control region does not completely cover the sidewalls of the gate structure 107, if the first control region is not disposed around the gate structure 107, an opening will be formed, resulting in the problem of gate-induced drain leakage from the opening.
  • the top edge of the first control region is no lower than the top edge of the sidewall of the gate structure 107 .
  • the problem of gate-induced drain leakage is more likely to occur in the region of the gate structure 107 closer to the drain electrode 103 , that is, the problem of gate-induced drain leakage is more likely to occur near the top of the gate structure 107 .
  • the area in the gate structure 107 that is prone to gate-induced drain leakage is wrapped with the gate adjustment layer 106, which can effectively improve the problem of gate-induced drain leakage.
  • the top edge of the first control region is lower than the top edge of the sidewall of the gate structure 107 , it means that the topmost sidewall of the gate structure 107 is not covered by the gate adjustment layer 106 , and the top sidewall of the gate structure 107 The location of the gate-induced drain leakage problem is most likely to occur. Therefore, in the embodiment of the present disclosure, the top edge of the first control region is set equal to or higher than the top edge of the sidewall of the gate structure 107 , thereby effectively improving the gate structure 107 . The problem of pole-induced drain leakage.
  • FIG. 3c is a schematic diagram 3 of a semiconductor structure provided by an embodiment of the disclosure
  • FIG. 3d is a schematic diagram 4 of a semiconductor structure provided by an embodiment of the disclosure.
  • the gate adjustment layer 106 covers at least part of the sidewalls of the gate structure 107 and does not cover the bottom surface of the gate structure 107 .
  • the gate adjustment layer 106 not covering the bottom surface of the gate structure 107 can effectively increase the current and avoid excessive resistance.
  • the gate adjustment layer 106 covering the sidewalls, top surface and part of the bottom surface of the gate structure 107 can further improve the problem of gate-induced drain leakage. It can be understood that the gate adjustment layer 106 completely wraps the top of the gate structure 107, so that the current is less likely to leak out from the gate structure 107, and the bottom surface of the gate structure 107 is still partially unblocked. This is because the resistance of the gate adjustment layer 106 is larger than that of the gate structure 107. If the gate adjustment layer 106 also covers the entire bottom of the gate structure 107, the resistance will be too large. , the current becomes smaller, so here the gate adjustment layer 106 only covers part of the bottom surface of the gate structure 107 .
  • the contact interface between the gate adjustment layer 106 and the top surface of the gate structure 107 is a curved surface.
  • the contact interface between the gate adjustment layer 106 and the top surface of the gate structure 107 is set as a curved surface. Compared with a flat surface, the contact area between the gate structure and the gate adjustment layer with a curved top surface is larger. Large, thus making it possible to further improve the problem of gate-induced drain leakage.
  • the gate structure 107 has a protrusion at the position of the second control area.
  • the bottom portion of the gate structure 107 that is not covered by the gate adjustment layer 106 has a protruding structure. This is because the gate adjustment layer 106 under the gate structure 107 is removed and then filled with the gate structure 107
  • the protruding structure here increases the cross-sectional area of the gate, thereby reducing the resistance of the current flowing through the word line when passing through the gate. It can be understood that when the gate resistance decreases, the word line When the load on the word line is reduced, the number of transistors that can be controlled by the word line can also be increased or the turn-on voltage of the word line can be reduced to reduce the power consumption of the word line. Therefore, the protruding structure here can increase the word line current, thereby achieving Better control over transistors.
  • the gate adjustment layer 106 is doped with impurities, and the doping type of the gate adjustment layer 106 is different from the doping types of the source electrode 102 and the drain electrode 103 .
  • the doping type of the gate adjustment layer 106 is P type; when the source electrode 102 and the doping type When the doping type of the drain electrode 103 is P type, the doping type of the gate adjustment layer 106 is N type.
  • the doping concentration of the doping impurities of the gate adjustment layer 106 ranges from 10 19 to 10 20 ions/cm 3 .
  • doping the gate adjustment layer 106 can reduce the resistance of the gate adjustment layer 106 , and a doping concentration as large as possible can make the resistance smaller, thereby increasing the word line current.
  • the range of the doping impurity concentration of the gate adjustment layer 106 is only an exemplary description and is not used to limit the doping concentration of the doping impurities of the gate adjustment layer 106 in the embodiment of the present disclosure. .
  • the gate structure 107 includes: a gate electrode, and a first barrier layer 108 covering the sidewalls and bottom of the gate electrode.
  • the material of the first barrier layer 108 includes, but is not limited to, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride, silicon oxycarbide, silicon carbonitride or silicon oxynitride. one or several kinds.
  • the material of the first barrier layer 108 needs to have good barrier diffusion properties, good stability at high temperatures, be able to resist corrosion and oxidation, have good contact with both semiconductors and metals, have high conductivity but low ohmic contact resistance, so that It is ensured that the first barrier layer 108 can prevent the metal in the gate from diffusing into the gate dielectric layer 105 to avoid affecting the performance of the device.
  • the material of the gate electrode includes but is not limited to tungsten and titanium nitride.
  • the semiconductor structure further includes an insulating capping layer 110 located in the trench and on the gate structure 107 .
  • the insulating cap layer 110 is used to isolate the source electrode 102 and the drain electrode 103 .
  • the material of the insulating capping layer 110 includes but is not limited to silicon nitride.
  • the gate structure 107 further includes a second barrier layer 111 located on top of the gate.
  • the material of the second barrier layer 111 includes, but is not limited to, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride, silicon oxycarbide, silicon carbonitride or silicon oxynitride. one or more types.
  • the second barrier layer 111 can prevent the metal in the gate 109 from diffusing into the insulating cap layer 110 to avoid affecting the performance of the device.
  • Embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a memory.
  • the semiconductor structure includes: a source electrode 102 and a drain electrode 103, both located in the substrate 101; and a gate dielectric layer 105 located in the substrate 101.
  • the gate structure 107 is located in the trench; the material of the gate structure 107 includes metal or Metal compound; gate adjustment layer 106, located at least between the gate dielectric layer 105 and the gate structure 107; wherein the sidewalls of the gate structure 107 have a surface covered by the gate adjustment layer 106
  • the first control area, and the bottom surface of the gate structure 107 has a second control area not covered by the gate adjustment layer 106; the material of the gate adjustment layer 106 includes polysilicon.
  • a bit line coupled to the other of the source 102 and the drain 103 .
  • the memory includes: dynamic random access memory, ferroelectric memory, phase change memory, magnetic change memory, or resistive change memory.
  • the memory includes dynamic random access memory
  • the storage unit includes a storage capacitor
  • One end of the storage capacitor is connected to the source 102 in the semiconductor structure
  • the storage capacitor can take on various structures.
  • the storage capacitor includes a cup-shaped, cylindrical or pillar-shaped capacitor.
  • the storage capacitor may include a cup-shaped capacitor CUP, a cylindrical capacitor CYL, and a pillar-shaped capacitor PIL.
  • the cup-shaped capacitor CUP, the cylindrical capacitor CYL, and the pillar-shaped capacitor PIL all include a bottom electrode, a top electrode, and a dielectric layer located between the bottom electrode and the top electrode.
  • the bottom electrode is connected to the source electrode 102 in the semiconductor structure, and the top electrode of the cup-shaped capacitor CUP is connected to ground.
  • the cup-shaped capacitor CUP is used to store written data.
  • the cylindrical capacitor CYL can be used as the storage unit of the memory, which is beneficial to improving the integration of the memory.
  • the memory also includes: a resistor
  • FIG. 4 is a schematic flowchart of a semiconductor structure manufacturing method provided by an embodiment of the present disclosure. As shown in Figure 4, the manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:
  • Step 403 Form a gate structure in the trench where the gate adjustment layer is formed, and the material of the gate structure includes metal or a metal compound;
  • the sidewall of the gate structure has a first control area covered by the gate adjustment layer, and the bottom surface of the gate structure has a second control area not covered by the gate adjustment layer.
  • the area of the first control region accounts for 60% to 100% of the area of the sidewalls of the gate structure.
  • a top edge of the first control region is no lower than a top edge of a sidewall of the gate structure.
  • the gate structure has a protrusion at the location of the second control region.
  • forming the gate adjustment layer includes:
  • the first gate adjustment material layer is subjected to a doping treatment with a doping type that is different from the source and drain doping types to obtain the gate adjustment layer.
  • forming a gate adjustment layer that at least partially covers the gate dielectric layer includes:
  • the second gate adjustment material layer covering the bottom and part of the sidewall of the gate dielectric layer is removed to form the gate adjustment layer.
  • the gate structure includes: a gate electrode and a first barrier layer; the method of forming the gate structure includes:
  • forming a gate adjustment layer that at least partially covers the gate dielectric layer includes:
  • the third gate adjustment material layer and part of the fourth gate adjustment material layer covering part of the bottom of the gate dielectric layer are removed to form the gate adjustment layer.
  • the gate structure includes: a gate electrode, a first barrier layer and a second barrier layer; and the method of forming the gate structure includes:
  • a second barrier layer is formed on the remaining first barrier material layer and gate material layer in the trench to obtain a gate structure.
  • the method further includes:
  • An insulating capping layer is formed in the trench in which the gate structure is formed and on the gate structure.
  • 5a to 5i are schematic process diagrams of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure. It should be understood that the steps shown in Figure 4 are not exclusive, and other steps can also be performed before, after, or between any steps in the operations shown; the order of the steps shown in Figure 4 can be adjusted according to actual needs.
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIG. 4 and FIG. 5a to FIG. 5i.
  • Figures 5a to 5i are a complete schematic diagram of the implementation process of the manufacturing method of a semiconductor structure, and some unmarked parts in the drawings can be shared with each other.
  • step 401 the substrate 101 is mainly provided.
  • the substrate 101 has a source electrode 102, a drain electrode 103, and a trench 104 between the source electrode 102 and the drain electrode 103.
  • the substrate 101 may include a single semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (such as a silicon germanium (SiGe) substrate). substrates, etc.), silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, etc.
  • the substrate is a silicon substrate.
  • the substrate 101 can be formed by a physical vapor deposition (PVD, Physical Vapor Deposition) process, a chemical vapor deposition (CVD, Chemical Vapor Deposition) process, an atomic layer deposition (ALD, Atomic Layer Deposition) process, etc. .
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD Atomic Layer Deposition
  • a dry etching process may be used to etch the substrate 101, such as a plasma etching process or a reactive ion etching process, to form the trench 104 in the substrate 101.
  • a gate dielectric layer 105 is formed in the sidewalls and bottom of the trench 104.
  • the material of the gate dielectric layer 105 includes but is not limited to silicon oxide, and the method of forming the gate dielectric layer 105 includes but is not limited to PVD, CVD, ALD, etc.
  • step 402 the gate adjustment layer 106 is mainly formed.
  • a gate adjustment material layer 106 - 1 covering the sidewalls and bottom of the gate dielectric layer 105 is formed in the trench 104 in which the gate dielectric layer 105 is formed.
  • the material of the gate adjustment material layer 106-1 includes but is not limited to polysilicon, and the method of forming the gate adjustment material layer 106-1 includes but is not limited to low pressure chemical vapor deposition (LPCVD, Low Pressure Chemical Vapor Deposition). ), CVD, ALD, etc.
  • LPCVD low pressure chemical vapor deposition
  • CVD high pressure Chemical Vapor Deposition
  • ALD ALD
  • the gate material layer 109-1 is doped.
  • the doping method includes but is not limited to ion implantation and diffusion.
  • the P-type impurity source when the doping type of the gate adjustment layer 106 is P-type doping, the P-type impurity source may be boron (B), aluminum (Al), etc., and the P-type impurity source is not limited thereto; when the gate When the doping type of the adjustment layer 106 is N-type doping, the N-type impurity source may be phosphorus (P), arsenic (As), etc., and the N-type impurity source is not limited thereto.
  • the formed gate adjustment material layer 106-1 is partially removed.
  • the gate adjustment material layer 106 - 1 covering the bottom and part of the sidewalls of the gate dielectric layer 105 may be removed.
  • the gate adjustment material layer 106 - 1 covering the bottom of the gate dielectric layer 105 may be removed without removing the gate adjustment material layer 106 - 1 covering the sidewalls of the gate dielectric layer 105 .
  • What is shown in FIG. 5d is the case where the gate adjustment material layer 106-1 covering the bottom of the gate dielectric layer 105 is removed without removing the gate adjustment material layer 106-1 covering the sidewalls of the gate dielectric layer 105.
  • the method of removing part of the gate adjustment layer 106 includes, but is not limited to, a dry plasma etching process.
  • further cleaning may be performed with dilute hydrofluoric acid.
  • step 403 the gate structure 107 is mainly formed.
  • the material of the first barrier material layer 108-1 includes but is not limited to titanium nitride.
  • Methods of forming the first barrier material layer 108-1 include, but are not limited to, ALD.
  • a gate material layer 109-1 is formed in the trench 104 where the first barrier material layer 108-1 is formed and on the surface of the substrate 101.
  • the material of the gate material layer 109-1 includes but is not limited to tungsten and titanium nitride.
  • the method of forming the gate material layer 109-1 includes, but is not limited to, CVD.
  • the gate material layer 109-1 and the first barrier material layer 108-1 are planarized to expose out of the substrate 101 surface.
  • the method of planarizing the gate material layer 109-1 and the first barrier material layer 108-1 includes but is not limited to chemical mechanical polishing (CMP, Chemical Mechanical Polishing).
  • part of the first barrier material layer 108-1 and part of the gate material layer 109-1 in the trench 104 are removed to form the first barrier layer 108 and the gate electrode 109.
  • the first barrier layer 108 Together with the gate electrode 109, the gate structure 107 is formed.
  • the method of removing part of the gate material layer 109-1 and part of the first barrier material layer 108-1 includes but is not limited to a dry plasma etching process. After removing part of the first barrier material layer 108-1 and part of the gate material layer 109-1 in the trench 104, sulfuric acid or dilute hydrofluoric acid may be used for cleaning.
  • part of the gate adjustment material layer 106 - 1 in the trench 104 is removed, so that the top surface of the gate adjustment material layer 106 - 1 is in contact with the top surface of the first barrier layer 108 and the gate electrode 109 The top surface of the gate adjustment layer 106 is formed flat.
  • the method of removing part of the gate adjustment material layer 106-1 includes but is not limited to a wet etching process.
  • an insulating cap layer 110 is formed in the trench 104 where the gate structure 107 is formed and on the gate structure 107 .
  • the material of the insulating capping layer 110 includes but is not limited to silicon nitride.
  • Methods for forming the insulating capping layer 110 include, but are not limited to, LPCVD and CVD.
  • FIGS. 6a to 6l are schematic process diagrams of another method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure will be further described below with reference to FIGS. 6a to 6l.
  • FIGS. 6 a - 6 l are a complete schematic diagram of the implementation process of the manufacturing method of a semiconductor structure, and some unmarked parts in the drawings can be shared with each other.
  • Figure 6a is for providing the substrate 101
  • Figure 6b is for forming the gate dielectric layer 105.
  • the formation of this part is similar to the method in the previous embodiment, and will not be described again here.
  • Figure 6c shows the formation of the gate adjustment material layer 106-1. Specifically, the gate adjustment material layer 106-1 covering the sidewalls and bottom of the gate dielectric layer 105 is formed. After forming the gate adjustment material layer 106-1 covering the sidewalls and bottom of the gate dielectric layer 105, remove the gate adjustment material layer 106-1 at the bottom of the gate dielectric layer 105 and part of the sidewalls of the gate dielectric layer 105. Extremely tuned material layer 106-1.
  • part of the gate adjustment material layer 106-1 can be removed through a dry plasma etching process, and the amount of the gate adjustment material layer 106-1 removed can be adjusted by adjusting the process parameters of the dry plasma etching process. the goal of.
  • a first barrier material layer 108-1 and a gate electrode are formed on the sidewalls and bottom of the trench 104 where the gate adjustment material layer 106-1 is formed.
  • Material layer 109-1 While the gate dielectric layer 105, the gate adjustment material layer 106-1, the first barrier material layer 108-1, and the gate material layer 109-1 are formed in the trench 104, they are also formed sequentially on the surface of the substrate 101. Gate dielectric layer 105, gate adjustment material layer 106-1, first barrier material layer 108-1, gate material layer 109-1.
  • the gate material layer 109-1 includes but is not limited to tungsten and titanium nitride.
  • dry plasma etching can be used to remove the first barrier material layer 108-1 and the gate material layer 109-1 on the surface of the substrate 101, so that the gate electrode on the surface of the substrate 101 is exposed. Adjust material layer 106-1.
  • a dry plasma etching process is used to remove the gate adjustment material layer 106-1 on the surface of the substrate 101, so that the gate dielectric layer 105 on the surface of the substrate 101 is exposed.
  • a wet etching process is used to remove part of the first barrier material layer 108-1 and part of the gate material layer 109-1 in the trench 104, so that the remaining first barrier material layer 108- 1 and the top surface of the remaining gate material layer 109-1 is a curved surface.
  • a second barrier layer 111 is formed on the first barrier layer 108 and the gate electrode 109 in the trench 104.
  • the second barrier layer 111, the first barrier layer 108, and the gate electrode 109 together form a gate electrode. Structure107.
  • a gate adjustment material layer 106-1 is formed again in the trench 104 where the gate structure 107 is formed and on the gate structure 107.
  • gate adjustment material layer 106 - 1 covering the top of the gate structure 107 , the gate adjustment material layer 106 - 1 covering the side walls and bottom of the gate dielectric layer 105 , and the gate electrode.
  • the remaining gate adjustment material layer 106 - 1 on top of structure 107 collectively constitutes gate adjustment layer 106 .
  • an insulating cap layer 110 is formed in the trench 104 where the gate structure 107 is formed and on the gate structure 107 .
  • embodiments of the present disclosure also provide a method of manufacturing a memory.
  • a semiconductor structure is formed.
  • the method for forming the semiconductor structure has been described before and will not be described again.
  • Forming multiple memory cells may include the following steps: forming a memory cell contact hole on the source; filling the memory cell contact hole with a metal material to form a memory cell contact; forming a memory cell hole on the memory cell contact; Form a memory cell, such as a storage capacitor.
  • the memory cell formed is a magnetic tunnel junction.
  • Bit lines are formed by forming metal lines at preset bit line locations.
  • the metal lines include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.
  • the disclosed devices and methods can be implemented in a non-target manner.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the components shown or discussed are coupled to each other, or directly coupled.
  • the sidewall of the gate structure has a first control region covered by the gate adjustment layer, thereby effectively improving the problem of gate-induced drain leakage, while the bottom surface of the gate structure has a first control region that is not covered by the gate adjustment layer.
  • the second area covered by the gate adjustment layer can improve the problem that the gate structure is completely wrapped by the gate adjustment layer, causing excessive resistance and thus reducing the current.

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Abstract

本公开实施例提供了一种半导体结构及其制作方法、存储器，所述半导体结构包括：源极、漏极，均位于衬底中；栅极介质层，位于所述衬底中，且覆盖被限定在所述源极和漏极之间的沟槽的侧壁和底部；栅极结构，位于所述沟槽中；所述栅极结构的材料包括金属或金属化合物；栅极调整层，至少位于所述栅极介质层与所述栅极结构之间；其中，所述栅极结构的侧壁具有被所述栅极调整层覆盖的第一控制区域，以及所述栅极结构的底面具有未被所述栅极调整层覆盖的第二控制区域；所述栅极调整层的材料包括多晶硅。

Description

半导体结构及其制作方法、存储器
相关申请的交叉引用
本公开基于申请号为202210563800.9、申请日为2022年05月23日、发明名称为“半导体结构及其制作方法、存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法、存储器。
背景技术
半导体结构中的晶体管在电子设备中被广泛地用作开关器件或驱动装置。例如，晶体管可以用于动态随机存储器(DRAM，Dynamic Random Access Memory)中，用于控制每一存储单元中的电容。动态随机存取存储器的基本存储单元结构由一个晶体管和一个存储电容组成，其主要的作用原理是利用电容内存储电荷的多寡来代表一个二进制比特(bit)是l还是0。
然而，相关技术中的晶体管还存在诸多问题亟待改善。
发明内容
本公开实施例提供了一种半导体结构及其制作方法、存储器。
根据本公开实施例的第一方面，提供一种半导体结构，包括：
源极、漏极，均位于衬底中；
栅极介质层，位于所述衬底中，且覆盖被限定在所述源极和漏极之间的沟槽的侧壁和底部；
栅极结构，位于所述沟槽中；所述栅极结构的材料包括金属或金属化合物；
栅极调整层，至少位于所述栅极介质层与所述栅极结构之间；
其中，所述栅极结构的侧壁具有被所述栅极调整层覆盖的第一控制区域，以及所述栅极结构的底面具有未被所述栅极调整层覆盖的第二控制区域；所述栅极调整层的材料包括多晶硅。
上述方案中，所述第一控制区域的面积占所述栅极结构侧壁的面积的60％～100％。
上述方案中，所述第一控制区域的顶部边缘不低于所述栅极结构的侧壁的顶部边缘。
上述方案中，所述栅极结构在所述第二控制区域位置具有凸出部。
上述方案中，所述栅极调整层掺杂有杂质，所述栅极调整层的掺杂类型与所述源极和漏极的掺杂类型均不同。
上述方案中，所述栅极调整层的掺杂杂质的掺杂浓度范围为10 19～10 20ions/cm 3。
上述方案中，所述栅极调整层至少覆盖所述栅极结构的部分侧壁且未覆盖所述栅极结构的底面。
上述方案中，所述栅极调整层覆盖所述栅极结构的侧壁且覆盖所述栅极结构的顶面和部分底面。
上述方案中，所述栅极调整层与所述栅极结构顶面之间的接触界面为曲面。
上述方案中，所述栅极结构的材料包括：钨和/或氮化钛。
上述方案中，所述栅极结构包括：栅极，以及覆盖所述栅极侧壁及底部的第一阻挡层。
上述方案中，所述栅极结构还包括位于所述栅极顶部的第二阻挡层。
上述方案中，所述半导体结构还包括：位于所述沟槽中且位于所述栅极结构上的绝缘盖层。
根据本公开实施例的第二方面，提供一种存储器，包括：
如上述方案中任一项所述的半导体结构；
存储单元，所述存储单元与所述源极和漏极中的一个耦合；
位线，所述位线与所述源极和漏极中的另一个耦合。
根据本公开实施例的第三方面，提供一种半导体结构的制造方法，包括：
提供衬底；所述衬底中具有源极、漏极、位于所述源极和漏极之间的沟槽，以及覆盖所述沟槽侧壁和底部的栅极介质层；
形成至少部分覆盖所述栅极介质层的栅极调整层，所述栅极调整层的材料包括多晶硅；
在形成有栅极调整层的沟槽中形成栅极结构，所述栅极结构的材料包括金属或金属化合物；
其中，所述栅极结构的侧壁具有被所述栅极调整层覆盖的第一控制区域，以及所述栅极结构的底面具有未被所述栅极调整层覆盖的第二控制区域。
上述方案中，所述第一控制区域的面积占所述栅极结构侧壁的面积的60％～100％。
上述方案中，所述第一控制区域的顶部边缘不低于所述栅极结构的侧壁的顶部边缘。
上述方案中，所述栅极结构在所述第二控制区域位置具有凸出部。
上述方案中，形成所述栅极调整层，包括：
形成至少部分覆盖所述栅极介质层的第一栅极调整材料层；
对所述第一栅极调整材料层进行掺杂类型与所述源极和漏极的掺杂类型均不同的掺杂处理，得到所述栅极调整层。
上述方案中，所述形成至少部分覆盖所述栅极介质层的栅极调整层，包括：
形成覆盖所述栅极介质层侧壁及底部的第二栅极调整材料层；
去除覆盖所述栅极介质层的底部及部分侧壁的第二栅极调整材料层，形成所述栅极调整层。
上述方案中，所述栅极结构包括：栅极及第一阻挡层；所述形成栅极结构的方法，包括：
在形成有栅极调整层的沟槽的侧壁、底部及所述衬底表面形成第一阻挡材料层；
在形成有第一阻挡材料层的沟槽中及所述衬底表面形成栅极材料层；
对栅极材料层进行平坦化处理，以暴露出所述衬底表面；
去除沟槽中的部分第一阻挡材料层及部分栅极材料层，形成栅极结构。
上述方案中，所述形成至少部分覆盖所述栅极介质层的栅极调整层，包括：
形成覆盖所述栅极介质层侧壁及底部的第三栅极调整材料层；
在形成有第三栅极调整材料层的沟槽中形成栅极结构；
在形成有栅极结构的沟槽中且所述栅极结构上形成第四栅极调整材料层；
去除覆盖所述栅极介质层的部分底部的第三栅极调整材料层和部分第四栅极调整材料层，形成所述栅极调整层。
上述方案中，所述栅极结构包括：栅极、第一阻挡层及第二阻挡层；所述形成栅极 结构的方法，包括：
在形成有第三栅极调整材料层的沟槽的侧壁、底部及所述衬底表面形成第一阻挡材料层；
在形成有第一阻挡材料层的沟槽中及所述衬底表面形成栅极材料层；
利用干法刻蚀，去除衬底表面上的栅极材料层、第一阻挡材料层；
利用湿法刻蚀，去除沟槽中的部分第一阻挡材料层及部分栅极材料层；
在沟槽中剩余的第一阻挡材料层及栅极材料层上形成第二阻挡层，得到栅极结构。
上述方案中，所述方法还包括：
在形成有栅极结构的沟槽中且所述栅极结构上形成绝缘盖层。
本公开实施例提供了一种半导体结构及其制作方法、存储器，所述半导体结构包括：源极、漏极，均位于衬底中；栅极介质层，位于所述衬底中，且覆盖被限定在所述源极和漏极之间的沟槽的侧壁和底部；栅极结构，位于所述沟槽中；所述栅极结构的材料包括金属或金属化合物；栅极调整层，至少位于所述栅极介质层与所述栅极结构之间；其中，所述栅极结构的侧壁具有被所述栅极调整层覆盖的第一控制区域，以及所述栅极结构的底面具有未被所述栅极调整层覆盖的第二控制区域；所述栅极调整层的材料包括多晶硅。本公开实施例中，在栅极结构的侧壁具有被栅极调整层覆盖的第一控制区域，从而使得能有效改善栅极诱导漏极泄露的问题，而在栅极结构的底面具有未被栅极调整层覆盖的第二区域，可以改善栅极结构被栅极调整层全部包裹住而使得电阻过大，进而使电流减小的问题，通过第一控制区域和第二控制区域的共同设置能在改善栅极诱导漏极泄露的问题的同时使半导体结构具有相对较小的电阻，从而可以有效提高半导体结构的性能。
附图说明
图1为本公开实施例中提供的一种半导体结构的电路连接示意图；
图2为本公开实施例中提供的一种半导体结构的示意图；
图3a为本公开实施例中提供的另一种半导体结构的示意图一；
图3b为本公开实施例中提供的另一种半导体结构的示意图二；
图3c为本公开实施例中提供的另一种半导体结构的示意图三；
图3d为本公开实施例中提供的另一种半导体结构的示意图四；
图4为本公开实施例中提供的一种半导体结构的制造方法的实现流程示意图；
图5a-图5i为本公开实施例中提供的一种半导体结构的制造方法的工艺过程示意图；
图6a-图6l为本公开实施例中提供的另一种半导体结构的制造方法的工艺过程示意图。
具体实施方式
为使本公开实施例的技术方案和优点更加清楚，下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻的理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
可以理解的是，本公开中的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读，以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义，而且还包括在某物“上”且其间有居间特征或层的含义。
此外，为了便于描述，可以在本文中使用诸如“在……上”、“在……之上”、“在……上方”、“上”“上部”等的空间相对术语来描述如图所示的一个元件或特征与另一个元件或特征的关系。除了在附图中所描绘的取向之外，空间相对术语旨在涵盖设备在使用或操作中的不同取向。装置可以以其它方式定向(旋转90度或处于其它取向)并且同样可以相应地解释本文使用的空间相对描述词。
在本公开实施例中，术语“衬底”是指在其上添加后续材料层的材料。衬底本身可以被图案化。被添加在衬底顶部的材料可以被图案化或者可以保持未被图案化。此外，衬底可以包括多种半导体材料，例如硅、硅锗、锗、砷化嫁、磷化锢等。替代地，衬底可以由非导电材料制成，例如玻璃、塑料或蓝宝石晶圆。
在本公开实施例中，术语“层”是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构厚度的均质或非均质连续结构的区域。例如，层可位于连续结构的顶表面和底表面之间，或者层可在连续结构顶表面和底表面处的任何水平面对之间。层可以水平、垂直和/或沿倾斜表面延伸。层可以包括多个子层。例如，互连层可包括一个或多个导体和接触子层(其中形成互连线和/或过孔触点)、以及一个或多个电介质子层。
在本公开实施例中，术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本公开实施例涉及的半导体结构是将被用于后续制程以形成最终的器件结构的至少一部分。这里，所述最终的器件可以包括存储器，所述存储器包括但不限于动态随机存取存储器，以下仅以动态随机存取存储器为例进行说明。
随着动态随机存取存储器技术的发展，存储单元的尺寸越来越小，其阵列架构由8F 2到6F 2再到4F 2；另外，基于动态随机存取存储器中对离子和漏电流的需求，存储器的架构从平面阵列晶体管(Planar Array Transistor)到凹栅阵列晶体管(Recess Gate Array Transistor)，又从凹栅阵列晶体管到掩埋式沟道阵列晶体管(Buried Channel Array Transistor)，再从掩埋式沟道阵列晶体管到垂直沟道阵列晶体管(Vertical Channel Array Transistor)。
实际应用中，不论是平面晶体管、凹栅阵列晶体管、掩埋式晶体管还是垂直栅极晶体管，动态随机存取存储器均由多个存储单元结构构成，每一个存储单元结构主要是由一个晶体管与一个由晶体管所操控的存储单元(存储电容)构成，即动态随机存取存储器包括1个晶体管(T，Transistor)和1个电容(C，Capacitor)(1T1C)的架构；其主要的作用原理是利用电容内存储电荷的多寡来代表一个二进制比特(bit)是l还是0。
图1为本公开实施例中提供的一种采用1T1C的架构的电路连接示意图，如图1所示，晶体管T的漏极与位线(BL，Bit Line)电连接，晶体管T的源极与电容C的其中一个电极板电连接，电容C的另外一个电极板可以连接参考电压，所述参考电压可以是地电压也可以是其他电压，晶体管T的栅极与字线(WL，Word Line)连接；通过字线WL施加电压控制晶体管T导通或截止，位线BL用于在晶体管T导通时，对所述晶体管T执行读取或写入操作。
图2为本公开实施例中提供的一种半导体结构的结构示意图；本公开实施例提供了一种半导体结构，如图2所示，所述半导体结构包括：
源极102、漏极103，均位于衬底101中；
栅极介质层105，位于所述衬底101中，且覆盖被限定在所述源极102和漏极103之间的沟槽的侧壁和底部；
栅极结构107，位于所述沟槽中；所述栅极结构107的材料包括金属或金属化合物。
研究发现，在采用如上所述的晶体管结构时，具有金属钨、金属化合物氮化钛的栅极结构107，具有较低的电阻，可以降低字线电阻。但随着半导体工艺的发展，存储器的尺寸越来越小，栅极诱导漏极泄漏对掩埋式阵列晶体管的形成产生巨大的不良影响，使得半导体结构的性能降低。
基于上述问题中的一个或多个，本公开实施例提供了一种半导体结构及其制作方法、存储器。
图3a为本公开实施例提供的一种半导体结构的结构示意图一，如图3a所示，所述半导体结构包括：
源极102、漏极103，均位于衬底101中；
栅极介质层105，位于所述衬底101中，且覆盖被限定在所述源极102和漏极103之间的沟槽的侧壁和底部；
栅极结构107，位于所述沟槽中；所述栅极结构107的材料包括金属或金属化合物；
栅极调整层106，至少位于所述栅极介质层105与所述栅极结构107之间；
其中，所述栅极结构107的侧壁具有被所述栅极调整层106覆盖的第一控制区域，以及所述栅极结构107的底面具有未被所述栅极调整层106覆盖的第二控制区域；所述栅极调整层106的材料包括多晶硅。
这里，实际应用中，所述半导体结构可以包括晶体管。
在一些具体示例中，所述衬底101可以包括单质半导体材料衬底(例如为硅(Si)衬底、锗(Ge)衬底等)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)、绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底等。优选地，所述衬底为硅衬底。
这里，源极102和漏极103之间的衬底101构成沟道区，本公开实施例中提供的沟道区可以为U型沟道区。
这里，栅极介质层105又可以称为栅极氧化层(Gate oxide layer)，用于电隔离沟道区和栅极结构107。这里，栅极介质层105的材料可以包括但不限于氧化硅。
具体地，栅极介质层105可以用于感应出不同的电场并施加在沟道区表面，以使半导体结构中的少数载流子被吸附到沟道区表面积累并反型，从而实现源极102与漏极103之间的导通。
这里，第一控制区域指的是栅极结构107的侧壁中被栅极调整层106所覆盖的部分，第二控制区域指的是栅极结构107的底面中未被栅极调整层106覆盖的部分。
可以理解的是，栅极结构107的侧壁具有被栅极调整层106覆盖的第一区域，也就是说，栅极调整层106取代一部分栅极结构107，在栅极结构107容易发生栅极诱导漏极泄露问题的区域，用材料为多晶硅的栅极调整层106将栅极结构107包裹住，而多晶硅在靠近漏极103的位置处的漏电会比金属或金属化合物小一些，从而可以有效改善栅极诱导漏极泄漏的问题。但多晶硅的电阻比金属及金属化合物的电阻要大，若栅极结构107的侧壁和底面均被栅极调整层106覆盖，将会使电阻过大，从而使电流减小，为了平衡电流和栅极诱导漏极泄露的问题，本公开实施例在设置第一控制区域的基础上还设置有第二控制区域，使得既能有效改善栅极诱导漏极泄露问题，又能使得电流在合适的范围内。
在一些实施例中，所述第一控制区域的面积占所述栅极结构107侧壁的面积的60％～100％。
图3b为本公开实施例提供的一种半导体结构的结构示意图二。
这里，第一控制区域的面积占栅极结构107侧壁的面积的60％～100％，可以理解为，栅极结构107的侧壁可以全部被栅极调整层106覆盖，也可以部分被栅极调整层106覆盖。当第一控制区域的面积占栅极结构107侧壁的面积的100％时，代表栅极结构107的侧壁全部被栅极调整层106覆盖。如图3a示出的是，栅极结构107的侧壁被栅极调整层106全部覆盖；图3b示出的是，栅极结构107的侧壁被栅极调整层106部分覆盖。当栅极结构107的侧壁全部被栅极调整层106覆盖时，对栅极诱导漏极泄露问题的改善效果越好。当栅极结构107的侧壁被栅极调整层106覆盖的越少时，对栅极诱导漏极泄露问题的改善效果越差，但电阻会越小。在实际应用中，可以根据对栅极诱导漏极泄露和电阻两者的需求进行选择。
需要强调的是，第一控制区域是环绕栅极结构107设置的，可以理解的是，本公开实施例中的附图仅示出了半导体结构的截面图，实际的栅极结构107是柱状的，当第一控制区域未全部覆盖栅极结构107的侧壁时，若第一控制区域不环绕栅极结构107设置，形成开口，导致从开口处出现栅极诱导漏极泄露的问题。
在一些实施例中，所述第一控制区域的顶部边缘不低于所述栅极结构107的侧壁的顶部边缘。
可以理解的是，在栅极结构107越靠近漏极103的区域越容易发生栅极诱导漏极泄露的问题，也即在靠近栅极结构107的顶部位置易发生栅极诱导漏极泄露的问题。本公开实施例中，将栅极结构107中易发生栅极诱导漏极泄露的区域用栅极调整层106包裹住，这样能有效改善栅极诱导漏极泄露的问题。若第一控制区域的顶部边缘低于栅极结构107的侧壁的顶部边缘，则代表栅极结构107的最顶部侧壁未被栅极调整层106覆盖，而栅极结构107的顶部侧壁的位置是最容易发生栅极诱导漏极泄露问题的，因此，本公开实施例将第一控制区域的顶部边缘设置的等于或高于栅极结构107的侧壁的顶部边缘，从而有效改善栅极诱导漏极泄露的问题。
图3c为本公开实施例提供的一种半导体结构的结构示意图三；图3d为本公开实施例提供的一种半导体结构的结构示意图四。
对于栅极调整层106具体覆盖的区域，本公开实施例提出以下几种不同的方案。且以下方案仅为示例性的示范，并不用于限制本公开中栅极调整层106所覆盖的区域。
在一些实施例中，如图3b所示，所述栅极调整层106至少覆盖所述栅极结构107的部分侧壁且未覆盖所述栅极结构107的底面。
可以理解的是，栅极调整层106未覆盖栅极结构107的底面可以有效提高电流，避免电阻过大。
在一些实施例中，如图3c所示，所述栅极调整层106覆盖所述栅极结构107的侧壁且覆盖所述栅极结构107的顶面和部分底面。
这里，所述栅极调整层106覆盖栅极结构107的侧壁、顶面和部分底面可以进一步改善栅极诱导漏极泄露的问题。可以理解的是，栅极调整层106将栅极结构107的顶部整体包裹住，这样使得电流更不容易从栅极结构107向外泄露出去，而栅极结构107的底面还有部分未被栅极调整层106覆盖住，这是由于栅极调整层106的电阻相对于栅极结构107来说较大，若栅极调整层106将栅极结构107的整个底部也覆盖住将使得电阻过大，电流变小，因此，这里栅极调整层106只覆盖了栅极结构107的部分底面。
在一些实施例中，如图3c以及图3d所示，所述栅极调整层106与所述栅极结构107顶面之间的接触界面为曲面。
可以理解的是，这里栅极调整层106与栅极结构107的顶面之间的接触界面设置成曲面，相对于平面来说，顶部为曲面的栅极结构与栅极调整层的接触面积更大，从而使 得可以进一步改善栅极诱导漏极泄露的问题。
在一些实施例中，如图3a、图3b、图3c所示，所述栅极结构107在所述第二控制区域位置具有凸出部。
可以理解的是，栅极结构107底部未被栅极调整层106覆盖的部分具有一个凸出结构，这是由于栅极结构107下方的栅极调整层106被去除后再填充栅极结构107的材料形成的，这里的凸出结构使得栅极的横截面积增大，从而使得通过字线的电流在经过栅极时的电阻减小，可以理解的是，当栅极电阻减小，字线上的负载降低，字线可控制的晶体管数量也能随之增加亦或降低字线的开启电压从而降低字线的功耗，因此，这里的凸出结构可以实现字线电流的提升，从而实现对晶体管更好的控制效果。
在一些实施例中，所述栅极调整层106掺杂有杂质，所述栅极调整层106的掺杂类型与所述源极102和漏极103的掺杂类型均不同。
在一些具体示例中，当所述源极102和所述漏极103的掺杂类型为N型时，所述栅极调整层106的掺杂类型为P型；当所述源极102和所述漏极103的掺杂类型为P型时，所述栅极调整层106的掺杂类型为N型。
在一些实施例中，所述栅极调整层106的掺杂杂质的掺杂浓度范围为10 19～10 20ions/cm 3。
可以理解的是，对栅极调整层106进行掺杂处理可以使得栅极调整层106的电阻减小，尽量大的掺杂浓度可以使得电阻更小，从而使得字线电流提高。
需要说明的是，上述栅极调整层106的掺杂杂质的掺杂浓度的范围仅为示例性的说明，并不用于限制本公开实施例中栅极调整层106的掺杂杂质的掺杂浓度。
在一些实施例中，所述栅极结构107的材料包括：钨和/或氮化钛。
在一些实施例中，如图3a-图3d所示，所述栅极结构107包括：栅极，以及覆盖所述栅极侧壁及底部的第一阻挡层108。
在一些具体示例中，所述第一阻挡层108的材料包括但不限于钛、钽、钨、氮化钛、氮化钽、氮化钨、碳氧化硅、碳氮硅或碳氮氧化硅中的一种或几种。第一阻挡层108的材料需要具有好的阻挡扩散特性，且在高温下稳定性好，能够抗腐蚀与氧化，与半导体和金属均接触良好，具有高电导率但欧姆接触电阻很低，这样可以确保第一阻挡层108能够阻止栅极中的金属向栅极介质层105中扩散，以避免影响器件的性能。
在一些具体示例中，栅极的材料包括但不限于钨、氮化钛。
在一些实施例中，如图3a-图3d所示，所述半导体结构还包括：位于所述沟槽中且位于所述栅极结构107上的绝缘盖层110。
这里，所述绝缘盖层110用于隔离源极102和漏极103。
在一些具体示例中，所述绝缘盖层110的材料包括但不限于氮化硅。
在一些实施例中，如图3c、图3d所示，所述栅极结构107还包括位于所述栅极顶部的第二阻挡层111。
在一些具体示例中，所述第二阻挡层111的材料包括但不限于钛、钽、钨、氮化钛、氮化钽、氮化钨、碳氧化硅、碳氮硅或碳氮氧化硅中的一种或几种。第二阻挡层111能够阻挡栅极109中的金属向绝缘盖层110中扩散，以避免影响器件的性能。
本公开实施例提供了一种半导体结构及其制作方法、存储器，所述半导体结构包括：源极102、漏极103，均位于衬底101中；栅极介质层105，位于所述衬底101中，且覆盖被限定在所述源极102和漏极103之间的沟槽的侧壁和底部；栅极结构107，位于所述沟槽中；所述栅极结构107的材料包括金属或金属化合物；栅极调整层106，至少位于所述栅极介质层105与所述栅极结构107之间；其中，所述栅极结构107的侧壁具有被所述栅极调整层106覆盖的第一控制区域，以及所述栅极结构107的底面具有未被所 述栅极调整层106覆盖的第二控制区域；所述栅极调整层106的材料包括多晶硅。本公开实施例中，在栅极结构107的侧壁具有被栅极调整层106覆盖的第一控制区域，从而使得能有效改善栅极诱导漏极泄露的问题，而在栅极结构107的底面具有未被栅极调整层106覆盖的第二区域，可以改善栅极结构107被栅极调整层106全部包裹住而使得电阻过大，进而使电流减小的问题，通过第一控制区域和第二控制区域的共同设置能在改善栅极诱导漏极泄露的问题的同时使半导体结构具有相对较小的电阻，从而可以有效提高存储器的性能。
基于上述半导体结构，本公开实施例还提供了一种存储器，所述存储器包括：
如上述实施例中所述的半导体结构；
存储单元，所述存储单元与所述源极102和漏极103中的一个耦合；
位线，所述位线与所述源极102和漏极103中的另一个耦合。
在一些实施例中，所述存储器包括：动态随机存取存储器、铁电存储器、相变存储器、磁变存储器或者阻变存储器。
在一些实施例中，所述存储器包括动态随机存取存储器，所述存储单元包括存储电容；
所述存储电容的一端与所述半导体结构中的源极102连接；
所述位线与所述半导体结构的漏极103连接。
实际应用中，所述存储电容可以呈现多种结构。在一些实施例中，所述存储电容包括杯形、圆筒形或者支柱形电容。
示例性地，所述存储电容可以包括杯形电容CUP、圆筒形电容CYL、支柱形电容PIL。其中，杯形电容CUP、圆筒形电容CYL、支柱形电容PIL均包括底电极、顶电极以及位于底电极和顶电极之间的电介质层。
需要说明的是，底电极与所述半导体结构中源极102连接，所述杯形电容CUP的顶电极接地，所述杯形电容CUP用于存储写入的数据。
需要说明的是，在杯形电容CUP、圆筒形电容CYL、支柱形PIL中所述底电极的面积相等的情况下，圆筒形电容CYL的顶电极的面积最大，圆筒形电容CYL和支柱形PIL的顶电极的面积次之。基于此，实际应用中，可以采用圆筒形电容CYL作为存储器的存储单元，有利于提高存储器的集成度。
本公开实施例中，只是示例性地列举了一些常见的存储器，本公开的保护范围不限于此，任何包含本公开实施例提供的半导体结构的存储器均属于本公开的保护范围。
实际应用中，所述存储器还包括：电阻；
所述电阻连接于所述位线和半导体结构的源极102之间，或者，所述电阻连接于所述位线和半导体结构的漏极103之间，所述电阻用于通过所述位线提供的位线电压调节存储单元中所存储的数据的状态。
图4为本公开实施例提供的一种半导体结构制造方法的流程示意图。如图4所示，本公开实施例提供的半导体结构的制造方法包括以下步骤：
步骤401：提供衬底；所述衬底中具有源极、漏极、位于所述源极和漏极之间的沟槽，以及覆盖所述沟槽侧壁和底部的栅极介质层；
步骤402：形成至少部分覆盖所述栅极介质层的栅极调整层，所述栅极调整层的材料包括多晶硅；
步骤403：在形成有栅极调整层的沟槽中形成栅极结构，所述栅极结构的材料包括金属或金属化合物；
其中，所述栅极结构的侧壁具有被所述栅极调整层覆盖的第一控制区域，以及所述栅极结构的底面具有未被所述栅极调整层覆盖的第二控制区域。
在一些实施例中，所述第一控制区域的面积占所述栅极结构侧壁的面积的60％～100％。
在一些实施例中，所述第一控制区域的顶部边缘不低于所述栅极结构的侧壁的顶部边缘。
在一些实施例中，所述栅极结构在所述第二控制区域位置具有凸出部。
在一些实施例中，形成所述栅极调整层，包括：
形成至少部分覆盖所述栅极介质层的第一栅极调整材料层；
对所述第一栅极调整材料层进行掺杂类型与所述源极和漏极的掺杂类型均不同的掺杂处理，得到所述栅极调整层。
在一些实施例中，所述形成至少部分覆盖所述栅极介质层的栅极调整层，包括：
形成覆盖所述栅极介质层侧壁及底部的第二栅极调整材料层；
去除覆盖所述栅极介质层的底部及部分侧壁的第二栅极调整材料层，形成所述栅极调整层。
在一些实施例中，所述栅极结构包括：栅极及第一阻挡层；所述形成栅极结构的方法，包括：
在形成有栅极调整层的沟槽的侧壁、底部及所述衬底表面形成第一阻挡材料层；
在形成有第一阻挡材料层的沟槽中及所述衬底表面形成栅极材料层；
对栅极材料层进行平坦化处理，以暴露出所述衬底表面；
去除沟槽中的部分第一阻挡材料层及部分栅极材料层，形成栅极结构。
在一些实施例中，所述形成至少部分覆盖所述栅极介质层的栅极调整层，包括：
形成覆盖所述栅极介质层侧壁及底部的第三栅极调整材料层；
在形成有第三栅极调整材料层的沟槽中形成栅极结构；
在形成有栅极结构的沟槽中且所述栅极结构上形成第四栅极调整材料层；
去除覆盖所述栅极介质层的部分底部的第三栅极调整材料层和部分第四栅极调整材料层，形成所述栅极调整层。
在一些实施例中，所述栅极结构包括：栅极、第一阻挡层及第二阻挡层；所述形成栅极结构的方法，包括：
在形成有第三栅极调整材料层的沟槽的侧壁、底部及所述衬底表面形成第一阻挡材料层；
在形成有第一阻挡材料层的沟槽中及所述衬底表面形成栅极材料层；
利用干法刻蚀，去除衬底表面上的栅极材料层、第一阻挡材料层；
利用湿法刻蚀，去除沟槽中的部分第一阻挡材料层及部分栅极材料层；
在沟槽中剩余的第一阻挡材料层及栅极材料层上形成第二阻挡层，得到栅极结构。
在一些实施例中，所述方法还包括：
在形成有栅极结构的沟槽中且所述栅极结构上形成绝缘盖层。
图5a至图5i为本公开实施例中提供的一种半导体结构的制作方法的工艺过程示意图。应当理解，图4中所示的步骤并非排他的，也可以在所示操作中的任何步骤之前、之后或之间执行其他步骤；图4中所示的各步骤可以根据实际需求进行顺序调整。下面结合图4、图5a至图5i，对本公开实施例提供的半导体结构的制造方法进行详细地说明。
需要说明的是，图5a-图5i为一个完整的反映半导体结构的制造方法的实现过程示意图，对于部分附图中未做标记的部分可以相互共用。
首先，如图5a所示，在步骤401中，主要是提供衬底101。
其中，所述衬底101中具有源极102、漏极103、位于所述源极102和漏极103之间的沟槽104。
在一些具体示例中，所述衬底101可以包括单质半导体材料衬底(例如为硅(Si)衬底、锗(Ge)衬底等)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)、绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底等。优选地，所述衬底为硅衬底。
在一些具体示例中，所述衬底101可以通过物理气相沉积(PVD，Physical Vapor Deposition)工艺、化学气相沉积(CVD，Chemical Vapor Deposition)工艺、原子层沉积(ALD，Atomic Layer Deposition)等工艺形成。
在一些具体示例中，可以采用干法刻蚀工艺对衬底101进行刻蚀，例如，等离子体刻蚀工艺或者反应离子刻蚀工艺，从而在衬底101中形成沟槽104。
接下来，如图5b所示，在沟槽104的侧壁和底部中形成栅极介质层105。在一些具体示例中，栅极介质层105的材料包括但不限于氧化硅，形成栅极介质层105的方法包括但不限于PVD，CVD，ALD等。
在步骤402中，主要是形成栅极调整层106。
如图5c所示，在形成有栅极介质层105的沟槽104中形成覆盖栅极介质层105侧壁和底部的栅极调整材料层106-1。
在一些具体示例中，栅极调整材料层106-1的材料包括但不限于多晶硅，形成栅极调整材料层106-1的方法包括但不限于低压化学气相沉积法(LPCVD，Low Pressure Chemical Vapor Deposition)，CVD，ALD等。在形成栅极调整材料层106-1后对栅极材料层109-1进行掺杂处理，掺杂的方法包括但不限于离子注入、扩散。示例性的，当栅极调整层106的掺杂类型为P型掺杂时，P型杂质源可以是硼(B)、铝(Al)等，且P型杂质源不限于此；当栅极调整层106的掺杂类型为N型掺杂时，N型杂质源可以是磷(P)、砷(As)等，且N型杂质源不限于此。
接下来，如图5d所示，对形成的栅极调整材料层106-1进行部分去除。在一些具体示例中，可以是去除覆盖栅极介质层105的底部和部分侧壁的栅极调整材料层106-1。在另一些具体示例中，可以是去除覆盖栅极介质层105的底部的栅极调整材料层106-1，而不去除覆盖栅极介质层105的侧壁的栅极调整材料层106-1。图5d中示出的是去除覆盖栅极介质层105的底部的栅极调整材料层106-1，而不去除覆盖栅极介质层105的侧壁的栅极调整材料层106-1的情况。
在一些具体示例中去除部分栅极调整层106的方法包括但不限于干法等离子体刻蚀工艺。
在一些具体示例中，可以通过在等离子体干法刻蚀工艺中对工艺参数进行调整实现选择性的去除栅极调整材料层106-1的多少。
在一些具体示例中，在利用等离子体干法刻蚀工艺去除部分栅极调整材料层106-1后，可用稀释的氢氟酸进行进一步的清洗。
在步骤403中，主要是形成栅极结构107。
如图5e所示，在形成有栅极调整层106的沟槽104中形成第一阻挡材料层108-1。具体的，可以是在形成有栅极调整层106的沟槽104的侧壁、底部及所述衬底101表面形成第一阻挡材料层108-1。
这里，第一阻挡材料层108-1的材料包括但不限于氮化钛。形成第一阻挡材料层108-1的方法包括但不限于ALD。
接下来，如图5f所示，在形成有第一阻挡材料层108-1的沟槽104中及所述衬底101表面形成栅极材料层109-1。
这里，栅极材料层109-1的材料包括但不限于钨、氮化钛。形成栅极材料层109-1的方法包括但不限于CVD。
在一些具体示例中，在形成栅极材料层109-1和第一阻挡材料层108-1之后，对栅 极材料层109-1以及第一阻挡材料层108-1进行平坦化处理，以暴露出所述衬底101表面。在一些具体示例中，对栅极材料层109-1以及第一阻挡材料层108-1进行平坦化处理的方法包括但不限于化学机械研磨(CMP，Chemical Mechanical Polishing)。
接下来，如图5g所示，去除沟槽104中的部分第一阻挡材料层108-1及部分栅极材料层109-1，形成第一阻挡层108和栅极109，第一阻挡层108和栅极109共同构成栅极结构107。
在一些具体示例中，去除部分栅极材料层109-1及部分第一阻挡材料层108-1的方法包括但不限于干法等离子体刻蚀工艺。在去除沟槽104中的部分第一阻挡材料层108-1及部分栅极材料层109-1后还可利用硫酸或稀释的氢氟酸进行清洗。
接下来，如图5h所示，去除沟槽104中的部分栅极调整材料层106-1，使得栅极调整材料层106-1的顶面与第一阻挡层108的顶面及栅极109的顶面平齐，从而形成栅极调整层106。
在一些具体示例中，所述去除部分栅极调整材料层106-1的方法包括但不限于湿法刻蚀工艺。
接下来，如图5i所示，在形成有栅极结构107的沟槽104中且所述栅极结构107上形成绝缘盖层110。在一些具体示例中，所述绝缘盖层110的材料包括但不限于氮化硅。形成绝缘盖层110的方法包括但不限于LPCVD、CVD。
图6a至图6l为本公开实施例中提供的另一种半导体结构的制作方法的工艺过程示意图。下面结合图6a至图6l，对本公开实施例提供的半导体结构的制造方法进行进一步地说明。
需要说明的是，图6a-图6l为一个完整的反映半导体结构的制造方法的实现过程示意图，对于部分附图中未做标记的部分可以相互共用。
图6a为提供衬底101、图6b为形成栅极介质层105，这部分的形成与上一实施例中的方法类似，这里不再赘述。
图6c为形成栅极调整材料层106-1，具体的，形成覆盖栅极介质层105侧壁及底部的栅极调整材料层106-1。在形成覆盖栅极介质层105侧壁及底部的栅极调整材料层106-1后，去除栅极介质层105底部的栅极调整材料层106-1以及栅极介质层105侧壁的部分栅极调整材料层106-1。
这里，可以通过干法等离子体刻蚀工艺去除部分栅极调整材料层106-1，并且可通过调节干法等离子体刻蚀工艺的工艺参数，达到调整去除栅极调整材料层106-1的多少的目的。
如图6d所示，在形成栅极调整材料层106-1之后，在形成有栅极调整材料层106-1的沟槽104的侧壁及底面形成第一阻挡材料层108-1及栅极材料层109-1。在沟槽104中形成栅极介质层105、栅极调整材料层106-1、第一阻挡材料层108-1、栅极材料层109-1的同时，在衬底101表面也也会依次形成栅极介质层105、栅极调整材料层106-1、第一阻挡材料层108-1、栅极材料层109-1。
这里，所述栅极材料层109-1包括但不限于钨、氮化钛。
如图6e所示，可以利用干法等离子体刻蚀，去除衬底101表面上的第一阻挡材料层108-1和栅极材料层109-1，使得暴露出衬底101表面上的栅极调整材料层106-1。
接下来，如图6f所示，利用干法等离子体刻蚀工艺去除衬底101表面上的栅极调整材料层106-1，使得暴露出衬底101表面上的栅极介质层105。
接下来，如图6g所示，利用湿法刻蚀工艺去除沟槽104中的部分第一阻挡材料层108-1和部分栅极材料层109-1，使得剩余的第一阻挡材料层108-1和剩余的栅极材料层109-1的顶面为曲面。
接下来，如图6h所示，利用干法等离子体刻蚀工艺进一步去除剩余的部分第一阻挡材料层108-1和剩余的部分栅极材料层109-1，形成第一阻挡层108和栅极109，第一阻挡层108和栅极109的顶面为曲面。
接下来，如图6i所示，在沟槽104中第一阻挡层108和栅极109上形成第二阻挡层111，第二阻挡层111、第一阻挡层108、栅极109共同构成栅极结构107。
接下来，如图6j所示，在形成有栅极结构107的沟槽104中且所述栅极结构107上再次形成栅极调整材料层106-1。
接下来，如图6k所示，去除覆盖栅极结构107顶部的部分栅极调整材料层106-1，覆盖栅极介质层105侧壁及底面的栅极调整材料层106-1、覆盖栅极结构107顶部的剩余的栅极调整材料层106-1共同构成栅极调整层106。
接下来，如图6l所示，在形成有栅极结构107的沟槽104中且所述栅极结构107上形成绝缘盖层110。
需要说明的是，本公开实施例中提供的半导体结构的示意图仅为示例性的示范，在不相冲突的情况下可以相互组合。本公开实施例中提供的半导体结构的制造方法的流程图仅为示例性的示范，在不相冲突的情况下也可以相互组合。
另外，本公开实施例还提供一种存储器的制造方法。
首先形成半导体结构，关于半导体结构的形成方法前已述及不再赘述。
形成多个存储单元可以包括以下步骤：在源极上形成存储单元接触孔；在存储单元接触孔中填充金属材料，形成存储单元接触；在存储单元接触上形成存储单元孔；在存储单元孔中形成存储单元，例如形成存储电容。在另一实施例中，形成的存储单元为磁隧道结。
通过在预设位线位置形成金属线来形成位线。所述金属线包括但不限于钨(W)、钴(Co)、铜(Cu)、铝(Al)、多晶硅、掺杂硅、硅化物或其任何组合。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例中，在栅极结构的侧壁具有被栅极调整层覆盖的第一控制区域，从而使得能有效改善栅极诱导漏极泄露的问题，而在栅极结构的底面具有未被栅极调整层覆盖的第二区域，可以改善栅极结构被栅极调整层全部包裹住而使得电阻过大，进而使电流减小的问题，通过第一控制区域和第二控制区域的共同设置能在改善栅极诱导漏极泄露的问题的同时使半导体结构具有相对较小的电阻，从而可以有效提高半导体结构的性能。

Claims (24)

  1. 一种半导体结构，包括：
    源极、漏极，均位于衬底中；
    栅极介质层，位于所述衬底中，且覆盖被限定在所述源极和漏极之间的沟槽的侧壁和底部；
    栅极结构，位于所述沟槽中；所述栅极结构的材料包括金属或金属化合物；
    栅极调整层，至少位于所述栅极介质层与所述栅极结构之间；
    其中，所述栅极结构的侧壁具有被所述栅极调整层覆盖的第一控制区域，以及所述栅极结构的底面具有未被所述栅极调整层覆盖的第二控制区域；所述栅极调整层的材料包括多晶硅。
  2. 根据权利要求1所述的半导体结构，其中，所述第一控制区域的面积占所述栅极结构侧壁的面积的60％～100％。
  3. 根据权利要求1所述的半导体结构，其中，所述第一控制区域的顶部边缘不低于所述栅极结构的侧壁的顶部边缘。
  4. 根据权利要求1所述的半导体结构，其中，所述栅极结构在所述第二控制区域位置具有凸出部。
  5. 根据权利要求1所述的半导体结构，其中，所述栅极调整层掺杂有杂质，所述栅极调整层的掺杂类型与所述源极和漏极的掺杂类型均不同。
  6. 根据权利要求5所述的半导体结构，其中，所述栅极调整层的掺杂杂质的掺杂浓度范围为10 19～10 20ions/cm 3。
  7. 根据权利要求1所述的半导体结构，其中，所述栅极调整层至少覆盖所述栅极结构的部分侧壁且未覆盖所述栅极结构的底面。
  8. 根据权利要求1所述的半导体结构，其中，所述栅极调整层覆盖所述栅极结构的侧壁且覆盖所述栅极结构的顶面和部分底面。
  9. 根据权利要求8所述的半导体结构，其中，所述栅极调整层与所述栅极结构顶面之间的接触界面为曲面。
  10. 根据权利要求1所述的半导体结构，其中，所述栅极结构的材料包括：钨和/或氮化钛。
  11. 根据权利要求1所述的半导体结构，其中，所述栅极结构包括：栅极，以及覆盖所述栅极侧壁及底部的第一阻挡层。
  12. 根据权利要求11所述的半导体结构，其中，所述栅极结构还包括位于所述栅极顶部的第二阻挡层。
  13. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括：位于所述沟槽中且位于所述栅极结构上的绝缘盖层。
  14. 一种存储器，包括：
    如权利要求1-13任一项所述的半导体结构；
    存储单元，所述存储单元与所述源极和漏极中的一个耦合；
    位线，所述位线与所述源极和漏极中的另一个耦合。
  15. 一种半导体结构的制造方法，包括：
    提供衬底；所述衬底中具有源极、漏极、位于所述源极和漏极之间的沟槽，以及覆盖所述沟槽侧壁和底部的栅极介质层；
    形成至少部分覆盖所述栅极介质层的栅极调整层，所述栅极调整层的材料包括多晶 硅；
    在形成有栅极调整层的沟槽中形成栅极结构，所述栅极结构的材料包括金属或金属化合物；
    其中，所述栅极结构的侧壁具有被所述栅极调整层覆盖的第一控制区域，以及所述栅极结构的底面具有未被所述栅极调整层覆盖的第二控制区域。
  16. 根据权利要求15所述的方法，其中，所述第一控制区域的面积占所述栅极结构侧壁的面积的60％～100％。
  17. 根据权利要求15所述的方法，其中，所述第一控制区域的顶部边缘不低于所述栅极结构的侧壁的顶部边缘。
  18. 根据权利要求15所述的方法，其中，所述栅极结构在所述第二控制区域位置具有凸出部。
  19. 根据权利要求15所述的方法，其中，形成所述栅极调整层，包括：
    形成至少部分覆盖所述栅极介质层的第一栅极调整材料层；
    对所述第一栅极调整材料层进行掺杂类型与所述源极和漏极的掺杂类型均不同的掺杂处理，得到所述栅极调整层。
  20. 根据权利要求15所述的方法，其中，所述形成至少部分覆盖所述栅极介质层的栅极调整层，包括：
    形成覆盖所述栅极介质层侧壁及底部的第二栅极调整材料层；
    去除覆盖所述栅极介质层的底部及部分侧壁的第二栅极调整材料层，形成所述栅极调整层。
  21. 根据权利要求20所述的方法，其中，所述栅极结构包括：栅极及第一阻挡层；所述形成栅极结构的方法，包括：
    在形成有栅极调整层的沟槽的侧壁、底部及所述衬底表面形成第一阻挡材料层；
    在形成有第一阻挡材料层的沟槽中及所述衬底表面形成栅极材料层；
    对栅极材料层进行平坦化处理，以暴露出所述衬底表面；
    去除沟槽中的部分第一阻挡材料层及部分栅极材料层，形成栅极结构。
  22. 根据权利要求15所述的方法，其中，所述形成至少部分覆盖所述栅极介质层的栅极调整层，包括：
    形成覆盖所述栅极介质层侧壁及底部的第三栅极调整材料层；
    在形成有第三栅极调整材料层的沟槽中形成栅极结构；
    在形成有栅极结构的沟槽中且所述栅极结构上形成第四栅极调整材料层；
    去除覆盖所述栅极介质层的部分底部的第三栅极调整材料层和部分第四栅极调整材料层，形成所述栅极调整层。
  23. 根据权利要求22所述的方法，其中，所述栅极结构包括：栅极、第一阻挡层及第二阻挡层；所述形成栅极结构的方法，包括：
    在形成有第三栅极调整材料层的沟槽的侧壁、底部及所述衬底表面形成第一阻挡材料层；
    在形成有第一阻挡材料层的沟槽中及所述衬底表面形成栅极材料层；
    利用干法刻蚀，去除衬底表面上的栅极材料层、第一阻挡材料层；
    利用湿法刻蚀，去除沟槽中的部分第一阻挡材料层及部分栅极材料层；
    在沟槽中剩余的第一阻挡材料层及栅极材料层上形成第二阻挡层，得到栅极结构。
  24. 根据权利要求21或23所述的方法，其中，所述方法还包括：
    在形成有栅极结构的沟槽中且所述栅极结构上形成绝缘盖层。
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CN112447717A (zh) * 2019-08-27 2021-03-05 长鑫存储技术有限公司 半导体器件及其制造方法
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