WO2023245758A1 - 半导体结构及其制作方法、存储器 - Google Patents

半导体结构及其制作方法、存储器 Download PDF

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Publication number
WO2023245758A1
WO2023245758A1 PCT/CN2022/105112 CN2022105112W WO2023245758A1 WO 2023245758 A1 WO2023245758 A1 WO 2023245758A1 CN 2022105112 W CN2022105112 W CN 2022105112W WO 2023245758 A1 WO2023245758 A1 WO 2023245758A1
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Prior art keywords
semiconductor
pillars
pillar
layer
support
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PCT/CN2022/105112
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English (en)
French (fr)
Inventor
邵光速
肖德元
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长鑫存储技术有限公司
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Priority to US17/949,987 priority Critical patent/US20230016905A1/en
Publication of WO2023245758A1 publication Critical patent/WO2023245758A1/zh

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure, a manufacturing method thereof, and a memory.
  • the memory array architecture of dynamic random access memory is an array composed of memory cells (i.e., 1T1C memory cells) including a transistor and a capacitor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a memory.
  • a semiconductor structure including:
  • the plurality of first semiconductor pillars are arranged in an array along a first direction and a second direction; both the first direction and the second direction are perpendicular to the extension direction of the first semiconductor pillar, and the first The direction intersects the second direction;
  • the first support layer covers top sidewalls of the plurality of first semiconductor pillars
  • Each second semiconductor pillar is located on a corresponding first semiconductor pillar; the storage structure at least surrounds sidewalls of the plurality of first semiconductor pillars and the plurality of second semiconductor pillars.
  • the first support layer includes: a plurality of first support columns and a plurality of second support columns; wherein,
  • Each first support pillar is located between the tops of two first semiconductor pillars adjacent along the first direction
  • each second support pillar is located between the tops of two first semiconductor pillars adjacent along the second direction. between the tops, and the first support layer covers part of the top sidewalls of the first semiconductor pillars.
  • the storage structure includes:
  • each first electrode covers at least a portion of the sidewall of one of the first semiconductor pillars that is not covered by the first support layer, and covers a corresponding portion of the second semiconductor pillar. side wall;
  • each dielectric layer covers at least one side wall of the first electrode, one side wall of the first support pillar, and one side wall of the second support pillar;
  • the second electrode is located in the gaps between the plurality of first semiconductor pillars and the plurality of second semiconductor pillars and covers the plurality of dielectric layers.
  • the semiconductor structure further includes:
  • each of the first semiconductor pillars is located on the top surface of a corresponding one of the oxidation pillars;
  • a sacrificial layer located in the gaps between the plurality of oxidation pillars
  • the dielectric layer also covers the top surface of the sacrificial layer.
  • the semiconductor structure further includes:
  • a plurality of transistors the channel structure of each transistor is located on the upper part of the second semiconductor pillar, and the extending direction of the channel structure is perpendicular to the plane of the first direction and the second direction;
  • the transistors include:
  • a memory including: one or more semiconductor structures as described in any of the above aspects of the disclosure.
  • a method for manufacturing a semiconductor structure including:
  • a first semiconductor substrate is provided, a first active layer is formed on the first semiconductor substrate, the first active layer includes a plurality of first semiconductor pillars arranged in an array along the first direction and the second direction;
  • the first direction and the second direction are both perpendicular to the extension direction of the first semiconductor pillar, and the first direction and the second direction intersect;
  • the second active layer includes a plurality of second semiconductor pillars; each of the second semiconductor pillars is located on top of a corresponding first semiconductor pillar. noodle;
  • Storage structures are formed on sidewalls of the plurality of first semiconductor pillars and the plurality of second semiconductor pillars.
  • the method further includes: before forming the first support layer, forming a first insulating layer in the gaps between the plurality of first semiconductor pillars;
  • Forming the first support layer includes:
  • first support pillar and the second support pillar together constitute the first support layer, and each first support pillar is located between the tops of two first semiconductor pillars adjacent along the first direction.
  • each of the second support pillars is located between the tops of two adjacent first semiconductor pillars along the second direction, and the first support layer covers part of the top sidewalls of the first semiconductor pillars.
  • forming the second semiconductor substrate includes:
  • the second semiconductor substrate is formed on the first semiconductor pillar using an epitaxial growth process.
  • the method also includes:
  • Forming the second support layer includes:
  • the third support pillar and the fourth support pillar together constitute the second support layer, and each third support pillar is located between the tops of two second semiconductor pillars adjacent along the first direction. , each of the fourth support pillars is located between the tops of two adjacent second semiconductor pillars along the second direction, and the second support layer covers part of the top sidewalls of the second semiconductor pillars.
  • forming the storage structure includes:
  • a dielectric layer and a second electrode are formed sequentially in the second filling area.
  • the first oxide layer located on the sidewall at the top of the second semiconductor pillar is removed to form a third filling region, and the first oxide layer is formed in the third filling region.
  • the sacrificial material is used to form a third support layer on top of the second semiconductor pillar.
  • the conductive material is formed in the third groove and the fourth groove to form a fourth support layer on top of the second semiconductor pillar.
  • forming the first active layer includes:
  • a plurality of first trenches spaced apart along a first direction and a plurality of second trenches spaced apart along a second direction are formed in the first semiconductor substrate; wherein the first trenches and the first trenches are spaced apart along the second direction.
  • the second trench divides the first semiconductor substrate into a plurality of first semiconductor pillars;
  • each first trench and/or the second trench is enlarged so that the formed first semiconductor pillar includes a first part and a second part located on the first part;
  • the maximum diameter width is smaller than the minimum diameter width of the second portion.
  • the first part is completely oxidized into oxidized columns; while a sacrificial material is formed in the gaps of the first oxide layer, the sacrificial material is also formed in the oxidation layer. in the gap between the pillars; and when the sacrificial material between the first electrodes is removed, the sacrificial material between the oxidation pillars is retained to form a sacrificial layer, and the oxidation pillars and the sacrificial layer form a bottom support layer.
  • the method also includes:
  • a gate structure is formed on at least one side of part of the upper sidewall.
  • Embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a memory.
  • the manufacturing method of the semiconductor structure includes: providing a first semiconductor substrate, forming a first active layer on the first semiconductor substrate, and the first active layer is formed on the first semiconductor substrate.
  • An active layer includes a plurality of first semiconductor pillars arranged in an array along a first direction and a second direction; both the first direction and the second direction are perpendicular to the extension direction of the first semiconductor pillar, and The first direction and the second direction intersect; a first support layer is formed on top of the first active layer; a second semiconductor substrate is formed on the first active layer and the first support layer ;Remove part of the second semiconductor base to form a second active layer, the second active layer includes a plurality of second semiconductor pillars; Each of the second semiconductor pillars is located on a corresponding one of the first semiconductor pillars.
  • a first semiconductor pillar is first formed on the first semiconductor substrate, and a first support layer is formed on the top of the first semiconductor pillar, and then a second semiconductor pillar is formed on the first semiconductor pillar, and the first semiconductor pillar is formed on the top of the first semiconductor pillar.
  • a second support layer is formed on the top of the two semiconductor pillars, so that a storage structure with a larger storage capacity can be formed in the gap between the higher semiconductor pillars.
  • the first support layer and the second support layer can support the first semiconductor pillar and the second support layer.
  • the second semiconductor pillar plays a supporting role, so that a higher-height semiconductor pillar can be formed without collapsing, so that a high-capacity and high-strength semiconductor structure can be obtained.
  • Figure 1 is a schematic circuit connection diagram of a DRAM transistor provided in an embodiment of the present disclosure
  • Figure 2 is a schematic flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • 3-30 are schematic cross-sectional views of a manufacturing process of a semiconductor structure provided by embodiments of the present disclosure.
  • spatially relative terms such as “on”, “over”, “over”, “on”, “upper”, etc. may be used herein to describe the figures. The relationship of one element or feature to another element or feature.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • the term "substrate” refers to a material on which subsequent layers of material are added.
  • the substrate itself can be patterned.
  • the material added on top of the substrate can be patterned or can remain unpatterned.
  • the substrate may include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, arsenide, indium phosphide, and the like.
  • the substrate may be made of non-conductive material, such as glass, plastic or sapphire wafers.
  • the term "layer" refers to a portion of material that includes a region having a thickness.
  • a layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure.
  • the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal plane at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along inclined surfaces.
  • a layer can include multiple sub-layers.
  • an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.
  • the terms "first”, “second”, etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
  • the semiconductor structure involved in the embodiments of the present disclosure is at least a portion that will be used in subsequent processes to form a final device structure.
  • the final device may include a memory, and the memory includes but is not limited to a dynamic random access memory. The following only takes the dynamic random access memory as an example for description.
  • the size of memory cells is getting smaller and smaller, and its array architecture has changed from 8F 2 to 6F 2 to 4F 2 ; in addition, based on the demand for ions and leakage current in dynamic random access memory , the memory architecture has changed from Planar Array Transistor to Recess Gate Array Transistor, then from Recess Gate Array Transistor to Buried Channel Array Transistor, and then from Buried Channel Array Transistor. channel array transistor to vertical channel array transistor (Vertical Channel Array Transistor).
  • the dynamic random access memory is composed of multiple memory cell structures, and each memory cell structure is mainly composed of a
  • the transistor is composed of a storage unit (storage capacitor) controlled by the transistor, that is, the dynamic random access memory includes a transistor (T, Transistor) and a capacitor (C, Capacitor) (1T1C) structure; its main function
  • the principle is to use the amount of charge stored in the capacitor to represent whether a binary bit (bit) is 1 or 0.
  • Figure 1 is a schematic circuit connection diagram using a 1T1C architecture provided in an embodiment of the present disclosure; as shown in Figure 1, the drain of the transistor T is electrically connected to the bit line (BL, Bit Line), and the source of the transistor T is electrically connected to One of the electrode plates of the capacitor C is electrically connected, and the other electrode plate of the capacitor C can be connected to a reference voltage.
  • the reference voltage can be the ground voltage or other voltages.
  • the gate of the transistor T is connected to the word line (WL, Word Line). Connection; applying a voltage through the word line WL controls the transistor T to be turned on or off, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is turned on.
  • FIG. 2 is a schematic flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. As shown in Figure 2, the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:
  • S100 Provide a first semiconductor substrate, and form a first active layer on the first semiconductor substrate.
  • the first active layer includes a plurality of first semiconductor pillars arranged in an array along the first direction and the second direction. ;
  • the first direction and the second direction are both perpendicular to the extension direction of the first semiconductor pillar, and the first direction and the second direction intersect;
  • S300 Form a second semiconductor substrate on the first active layer and the first support layer;
  • the second active layer includes a plurality of second semiconductor pillars; each of the second semiconductor pillars is located on a corresponding first semiconductor pillar. the top surface;
  • S500 Form a second support layer on top of the second active layer
  • S600 Form memory structures on the sidewalls of the plurality of first semiconductor pillars and the plurality of second semiconductor pillars.
  • FIG. 3 to FIG. 30 are schematic cross-sectional views of a manufacturing process of a semiconductor structure provided by embodiments of the present disclosure. It should be noted that FIG. 3 to FIG. 30 are a complete schematic diagram of the implementation process of the manufacturing method of a semiconductor structure, and some unmarked parts in the drawings can be shared with each other. The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIG. 2, FIG. 3 to FIG. 30.
  • step S100 a first active layer composed of a plurality of first semiconductor pillars 102 is mainly formed on the first semiconductor substrate 101.
  • forming the first active layer includes:
  • a plurality of first trenches 118 spaced apart along a first direction and a plurality of second trenches 119 spaced apart along a second direction are formed in the first semiconductor substrate 101; wherein, the first trenches The groove 118 and the second trench 119 divide the first semiconductor substrate 101 into a plurality of the first semiconductor pillars 102;
  • each first trench 118 and/or the second trench 119 is enlarged, so that the formed first semiconductor pillar 102 includes a first portion 102-1 and a portion located on the first portion 102-1.
  • the first semiconductor substrate 101 includes but is not limited to a substrate.
  • the substrate may include a single substance semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), Composite semiconductor material substrates (such as silicon germanium (SiGe) substrates, etc.), silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, etc.
  • the substrate is a silicon substrate.
  • the formation process of the first semiconductor pillar 102 will be described in detail below with reference to FIGS. 3-6 .
  • a first etching is performed on the surface of the first semiconductor substrate 101 to form a plurality of first trenches 118 spaced apart along the first direction in the first semiconductor substrate 101 .
  • each first groove 118 extends along the second direction.
  • the first direction is parallel to the surface of the first semiconductor substrate 101 ; the second direction intersects the first direction and is parallel to the surface of the first semiconductor substrate 101 .
  • the third direction is the extension direction of the first semiconductor pillar 102 , and the third direction is perpendicular to the surface of the first semiconductor substrate 101 .
  • intersection of the first direction and the second direction can be understood to mean that the angle between the first direction and the second direction is 0-90 degrees.
  • the first direction and the second direction are perpendicular to each other as an example.
  • the first direction is the X-axis direction shown in Figure 3;
  • the second direction is the Y-axis direction shown in Figure 3;
  • the third direction is the Z-axis direction shown in Figure 3 direction.
  • the description of directions in the following embodiments is only used to illustrate the present disclosure and is not used to limit the scope of the present disclosure.
  • the first trench 118 includes, but is not limited to, a Shallow Trench Isolation (STI) structure.
  • STI Shallow Trench Isolation
  • the method of forming the first trench 118 includes, but is not limited to, a dry plasma etching process.
  • a first insulating layer 106 is formed in the first trench 118; wherein, the top surface of the first insulating layer 106 is substantially flush with the top surface of the first semiconductor substrate 101; here, the The first insulating layer 106 is used for supporting.
  • substantially flush mentioned in this disclosure can be understood as “roughly flush”; it can be understood that during the manufacturing process of the memory, misalignment or non-flush caused by process errors are also included in “substantially flush”. within the range.
  • the constituent material of the first insulating layer 106 includes but is not limited to silicon oxide (SiO 2 ).
  • the method of forming the first insulating layer 106 includes but is not limited to PVD, CVD, ALD and other processes.
  • a second etching is performed on the first semiconductor substrate 101 on which the first insulating layer 106 is formed to form a plurality of second trenches 119 in the first semiconductor substrate 101 ; wherein, a plurality of second trenches 119 are formed in the first semiconductor substrate 101 .
  • the two grooves 119 are spaced apart along the second direction, and each second groove 119 extends along the first direction; that is, the first groove 118 and the second groove 119 intersect.
  • the first groove 118 and the second groove 119 are perpendicular to each other.
  • a plurality of the first grooves 118 are arranged at intervals along the X-axis direction; and each of the first grooves 118 extends along the Y-axis direction; and a plurality of the second grooves 119 are arranged along the Y-axis direction. They are arranged at intervals in the axial direction; and each of the second grooves 119 extends along the X-axis direction.
  • the method of forming the second trench 119 includes, but is not limited to, a dry plasma etching process.
  • the second trench 119 includes, but is not limited to, a shallow trench isolation (STI) structure.
  • STI shallow trench isolation
  • first trench 118 and the second trench 119 divide the first semiconductor substrate 101 into a plurality of first semiconductor pillars 102 arranged in an array along the first direction and the second direction.
  • a grid-shaped mask layer can also be formed on the surface of the first semiconductor substrate 101, and the grid-shaped mask layer is used as a mask to etch the first semiconductor substrate 101, while forming The first trench 118 and the second trench 119 are used to form a plurality of first semiconductor pillars 102 arranged in an array along the first direction and the second direction in the first semiconductor substrate 101 .
  • each first trench 118 and/or the second trench 119 is enlarged; here, the enlarging process can be understood as enlarging the first trench 118
  • the bottom is etched along the first direction; and/or the bottom of the second trench 119 is etched along the second direction, so that the bottom of the first trench 118 and/or the second trench 119 is etched along the
  • the diameter width in the first direction is greater than the diameter width of the top of the corresponding groove along the first direction;
  • the diameter width of the bottom of the first groove 118 and/or the second groove 119 along the second direction is greater than the diameter width of the top of the corresponding groove along the second direction.
  • the etching process used may include a wet etching process, a dry etching process, etc.
  • the etchant is passed into the bottom of the first trench 118 and/or the second trench 119, and the first trench is increased through anisotropic etching of the etchant.
  • the diameter width of the bottom of the groove 118 and/or the second groove 119 along the X-axis direction; and/or the diameter width of the bottom of the first groove 118 and/or the second groove 119 along the Y-axis direction is increased.
  • lateral etching is performed by controlling plasma to form a trench structure with an enlarged diameter and width at the bottom of the first trench 118 and/or the second trench 119 .
  • the etching process causes a plurality of second trenches located on the first semiconductor substrate 101 to The bottom area of one semiconductor pillar 102 is etched, and the size of the bottom area of the first semiconductor pillar 102 is reduced.
  • the first semiconductor pillar 102 includes a first part 102-1 and a second part 102-2 located on the first part 102-1; here, the second part 102-2 of the first semiconductor pillar 102 is located on above the first portion 102 - 1 of the first semiconductor pillar 102 .
  • the maximum diameter width of the first portion 102-1 of the first semiconductor pillar 102 along the X-axis direction is smaller than the second portion of the first semiconductor pillar 102. 102-2The minimum diameter along the X-axis direction.
  • the maximum diameter width of the first portion 102-1 of the first semiconductor pillar 102 along the Y-axis direction is smaller than the second portion of the first semiconductor pillar 102.
  • 102-2 The minimum diameter along the Y-axis direction.
  • the maximum diameter width of the first portion 102-1 of the first semiconductor pillar 102 along the X-axis direction is smaller than that of the first semiconductor pillar 102.
  • the minimum diameter width of the second portion 102-2 of the pillar 102 along the X-axis direction; and the maximum diameter width of the first portion 102-1 of the first semiconductor pillar 102 along the Y-axis direction is smaller than the The minimum diameter width of the second part 102-2 along the Y-axis direction.
  • both the first trench 118 and the second trench 119 are enlarged so that the size of the first portion 102-1 of the first semiconductor pillar 102 is reduced.
  • the maximum diameter width of the first portion 102-1 can be understood as the diameter width at the contact position between the first portion 102-1 of the first semiconductor pillar 102 and the second portion 102-2 of the first semiconductor pillar 102 in FIG. 5;
  • the minimum diameter width of the second part 102-2 can be understood as the smallest area in the second part 102-2 of the first semiconductor pillar 102; referring to FIG. 5, the upper and lower parts of the second part 102-2 of the first semiconductor pillar 102 have the same size, that is, the minimum diameter width and the maximum diameter width of the second portion 102-2 of the first semiconductor pillar 102 are the same.
  • a first insulating layer 106 is formed in the second trench 119; the top surface of the first insulating layer 106 is substantially flush with the top surface of the first semiconductor substrate 101.
  • the first insulating material is used for supporting.
  • first trench 118 and the second trench 119 and filling the first trench 118 and the second trench 119 with the first insulating material to form the first insulating layer 106 can be selected according to the actual situation. . In other specific embodiments, the first trench 118 and the second trench 119 may be formed first, and then the first insulating layer 106 may be formed in the first trench 118 and the second trench 119 .
  • step S200 as shown in FIGS. 7 to 10, the first support layer 109 is mainly formed on the top of the first active layer.
  • the method further includes: before forming the first support layer 109, forming a first insulating layer 106 in the gaps of the plurality of first semiconductor pillars 102 (as shown in FIG. 6);
  • Forming the first support layer 109 includes:
  • a first support column 109-1 is formed in the first groove 107;
  • a second support column 109-2 is formed in the second groove 108;
  • first support column 109-1 and the second support column 109-2 together constitute the first support layer 109, and each first support column 109-1 is located adjacent along the first direction. Between the tops of the two first semiconductor pillars 102, each second support pillar 109-2 is located between the tops of the two adjacent first semiconductor pillars 102 along the second direction, and the first support layer 109 covers part of the top sidewall of the first semiconductor pillar 102 .
  • first insulating layer 106 on the top of the first semiconductor pillar 102 is removed to form a plurality of first grooves 107 .
  • Each of the first grooves 107 is located between the tops of two adjacent first semiconductor pillars 102 along the second direction.
  • the plurality of first grooves 107 are arranged at intervals along the X-axis direction, and each first groove 107 extends along the Y-axis direction.
  • the method of removing part of the first insulating layer 106 on top of the first semiconductor pillar 102 includes, but is not limited to, a dry etching process and a wet etching process.
  • a first support post 109 - 1 is formed in the first groove 107 .
  • the method of forming the first support pillar 109-1 includes but is not limited to PVD, CVD, ALD and other processes.
  • the material of the first support pillar 109-1 includes but is not limited to silicon nitride.
  • part of the first insulating layer 106 on the top of the first semiconductor pillar 102 is removed to form a plurality of second grooves 108 .
  • Each of the second grooves 108 is located between the tops of two adjacent first semiconductor pillars 102 along the first direction.
  • the plurality of second grooves 108 are arranged at intervals along the Y-axis direction, and each second groove 108 extends along the X-axis direction.
  • a second support post 109 - 2 is formed in the second groove 108 .
  • the method of forming the second support pillar 109-2 includes but is not limited to PVD, CVD, ALD and other processes.
  • first support pillar 109-1 and the second support pillar 109-2 may be made of the same or different materials.
  • the first support layer 109 is also planarized, so that the first support layer 109 is in contact with the first semiconductor.
  • the top surface of column 102 is flush.
  • the planarization process includes but is not limited to chemical mechanical polishing (CMP, Chemical Mechanical Polishing).
  • the first support pillars 109-1 and the second support pillars 109-2 formed together constitute the first support layer 109.
  • the first support layer 109 has a mesh structure, and the first support layer 109 Cover part of the top sidewall of the first semiconductor pillar 102 .
  • a grid-shaped mask layer may also be formed on the first semiconductor pillar 102 , and the grid-shaped mask layer may be used as a mask to etch the first insulating layer 106 while forming a third A groove 107 and a second groove 108, and while the first support post 109-1 is formed in the first groove 107, the second support post 109-2 is formed in the second groove 108.
  • the first support layer 109 covers part of the top sidewall of the first semiconductor pillar 102. It can be understood that the first support pillar 109-1 covers part of the top sidewall of the first semiconductor pillar 102, and/or, the second The support pillar 109 - 2 covers part of the top sidewall of the first semiconductor pillar 102 . That is to say, at least part of the first support layer 109 covers part of the top sidewall of the first semiconductor pillar 102 . The first support layer 109 must cover the top sidewall of the first semiconductor pillar 102 , but cannot completely cover the top of the first semiconductor pillar 102 . side walls.
  • the first support layer 109 can only support the first semiconductor pillar 102 by covering the top sidewall of the first semiconductor pillar 102 .
  • the first support layer 109 covers the top of the first semiconductor pillar 102 The more sidewalls there are, the better the support effect is; secondly, if the first support layer 109 completely covers the sidewalls of the first semiconductor pillar 102, when the memory structure 105 is formed in the subsequent process, the material of the first electrode will be It can only be filled into the gap of the second semiconductor pillar 104 but cannot be filled downward into the gap of the first semiconductor pillar 102 .
  • the aspect ratio of the first semiconductor pillar 102 continues to increase, and the risk of collapse may easily occur during the formation of the first semiconductor pillar 102 .
  • at least part of the first support layer 109 covers part of the top sidewall of the first semiconductor pillar 102, so that the plurality of first semiconductor pillars 102 are connected to each other, so that the first semiconductor pillar 102 can be removed in the subsequent process.
  • the insulating layer 106 can support the first semiconductor pillar 102 so that the first semiconductor pillar 102 with a large aspect ratio is less likely to collapse.
  • the above describes the process of forming the first semiconductor pillars 102 on the first semiconductor substrate 101.
  • the storage capacity of the memory structure formed in the gaps between the semiconductor pillars of a certain height may not be enough, and the height of the semiconductor pillars needs to be further increased. , thereby forming a larger-capacity storage structure in the gap of the elevated semiconductor.
  • the elevated semiconductor pillar is more likely to collapse.
  • embodiments of the present disclosure also propose the following technical solutions.
  • step S300 the second semiconductor substrate 103 is mainly formed.
  • forming the second semiconductor substrate 103 includes:
  • the second semiconductor substrate 103 is formed on the first semiconductor pillar 102 , the remaining first support layer 109 and the remaining first insulating layer 106 .
  • the first insulating layer 106 on the top of the first semiconductor pillar 102 is removed to expose part of the sidewall on the top of the first semiconductor pillar 102 .
  • the method of removing the first insulating layer 106 on top of the first semiconductor pillar 102 includes, but is not limited to, a dry etching process and a wet etching process.
  • a second semiconductor substrate 103 is formed on the first semiconductor pillar 102 and the first support layer 109 .
  • the method of forming the second semiconductor substrate 103 includes, but is not limited to, an epitaxial growth process.
  • the purpose of removing the first insulating layer 106 on the top of the first semiconductor pillar 102 and exposing part of the sidewalls on the top of the first semiconductor pillar 102 is mainly to make it easier to use epitaxial growth to form the second semiconductor layer 106 .
  • the material of the first semiconductor substrate 101 may include elemental semiconductor materials (such as silicon, germanium, etc.), composite semiconductor materials (such as silicon germanium, etc.), and the like.
  • the material of the second semiconductor substrate 103 and the material of the first semiconductor substrate 101 may be the same or different.
  • step S400 a second active layer composed of a plurality of second semiconductor pillars 104 is mainly formed.
  • each second semiconductor pillar 104 is located on the top surface of a corresponding first semiconductor pillar 102 .
  • a second insulating layer 110 is formed in the gap of the second semiconductor pillar 104 .
  • the material of the second insulating layer 110 includes but is not limited to silicon oxide.
  • the materials of the second insulating layer 110 and the first insulating layer 106 are the same or different.
  • the process of forming the second semiconductor pillar 104 on the first semiconductor pillar 102 is similar to the process of forming the first semiconductor pillar 102 in the previous embodiment, and will not be described again here.
  • step S500 as shown in FIG. 14, the second support layer 114 is mainly formed.
  • the method further includes:
  • Forming the second support layer 114 includes:
  • the third support column 114-1 and the fourth support column 114-2 together constitute the second support layer 114, and each third support column 114-1 is located adjacent along the first direction. Between the tops of the two second semiconductor pillars 104, each fourth support pillar 114-2 is located between the tops of the two second semiconductor pillars 104 adjacent along the second direction, and the second support layer 114 covers part of the top sidewall of the second semiconductor pillar 104 .
  • the material of the second support layer 114 includes but is not limited to silicon nitride.
  • the material of the second support layer 114 is the same as or different from the material of the first support layer 109 .
  • the process of forming the second support layer 114 on top of the second active layer is similar to the process of forming the first support layer 109 on top of the first active layer in the previous embodiment, and will not be described again here.
  • the second support layer 114 here plays a supporting role for the second semiconductor pillar 104, so that the second semiconductor pillar 104 is not easy to collapse after the first insulating layer 106 and the second insulating layer 110 are removed in the subsequent process. .
  • step S600 as shown in Figures 15 to 27, the storage structure 105 is mainly formed.
  • forming the storage structure 105 includes:
  • the dielectric layer 105-2 and the second electrode 105-3 are sequentially formed in the second filling area.
  • the first portion 102 - 1 is completely oxidized into oxide pillars 122 ; while forming the sacrificial material 117 in the gaps of the first oxide layer 115 , the sacrificial material 117 is also formed in the gap between the oxidation pillars 122; and when the sacrificial material 117 between the first electrodes 105-1 is removed, the sacrificial material 117 between the oxidation pillars 122 is retained.
  • the material 117 forms a sacrificial layer 123, and the oxidation pillars 122 and the sacrificial layer 123 form a bottom support layer.
  • the first oxide layer 115 on the sidewall on top of the second semiconductor pillar 104 is removed to form a third filling region.
  • the sacrificial material 117 is formed in the filling area to form a third support layer 120 on top of the second semiconductor pillar 104 .
  • the conductive material is formed in the third groove and the fourth groove while forming the first electrode 105-1 to form on top of the second semiconductor pillar 104
  • the fourth support layer 121 is formed.
  • the remaining first insulating layer 106 and the remaining second insulating layer 110 are completely removed.
  • methods for completely removing the remaining first insulating layer 106 and the remaining second insulating layer 110 include, but are not limited to, dry etching processes and wet etching processes.
  • the exposed surfaces of the first semiconductor pillar 102 and the second semiconductor pillar 104 are oxidized through an oxidation process, such as a thermal oxidation process, so that the first portion 102 - 1 of the first semiconductor pillar 102 is completely is oxidized into the oxide pillar 122, and the exposed surface of the second portion 102-2 of the first semiconductor pillar 102 and the exposed surface of the second semiconductor pillar 104 are oxidized into the first oxide layer 115.
  • the first semiconductor substrate The surface of 101 is also oxidized to form a second oxide layer 116.
  • the second oxide layer 116 and the oxide pillar 122 formed here enable the capacitor formed in the subsequent process to be isolated from the bottom first semiconductor substrate 101, thereby improving the leakage problem at the bottom of the capacitor.
  • the first oxide layer 115, the second oxide layer 116, and the oxidation pillar 122 are made of the same material.
  • the constituent materials of the first oxide layer 115, the second oxide layer 116, and the oxide pillars 122 include but are not limited to silicon oxide.
  • the materials of the first oxide layer 115 , the second oxide layer 116 , and the oxidation pillars 122 are the same as or different from the materials of the first insulating layer 106 .
  • the materials of the first oxide layer 115 , the second oxide layer 116 , and the oxidation pillars 122 are the same as or different from the materials of the second insulating layer 110 .
  • FIG. 17 , FIG. 19 , FIG. 23 , and FIG. 25 individually show cross-sectional schematic views of the top of the first semiconductor pillar 102 .
  • the first support layer 109 and the second support layer 114 cover, so there are only uncovered portions of the sidewalls of the first semiconductor pillar 102 and portions of the second semiconductor pillar 104 on the top of the first semiconductor pillar 102 and the top of the second semiconductor pillar 104
  • the sidewalls are oxidized into the first oxide layer 115 .
  • the first portion 102 - 1 of the first semiconductor pillar 102 is smaller in size and is easy to be completely oxidized. Moreover, when the first portion 102-1 of the first semiconductor pillar 102 is oxidized, only the surface of the second portion 102-2 of the first semiconductor pillar 102 is oxidized.
  • a sacrificial material 117 is formed in the gaps of the first oxide layer 115 and the gaps of the oxidation pillars 122 .
  • methods of forming the sacrificial material 117 include, but are not limited to, PVD, CVD, and ALD.
  • the material of the sacrificial material 117 formed includes but is not limited to polysilicon and carbon.
  • the selection of the material of the sacrificial material 117 firstly, it is necessary to consider that the sacrificial material 117 has a certain etching selectivity ratio relative to the first oxide layer 115, so that when the first oxide layer 115 is removed in the subsequent process, the etching selectivity can be retained.
  • Sacrificial material 117 Secondly, it is necessary to consider that the sacrificial material 117 has a certain etching selectivity ratio relative to the material of the first electrode 105-1 formed in the subsequent process, so that when the sacrificial material 117 is removed to form the sacrificial layer 123 in the subsequent process , to reduce the impact on the formed first electrode 105-1; thirdly, the sacrificial material 117 needs to be easily removed in subsequent processes.
  • the first oxide layer 115 on the sidewall at the top of the second semiconductor pillar 104 is removed to form a third filling region, and a sacrificial material 117 is formed in the third filling region to form the second filling region.
  • a third support layer 120 is formed on the top of the semiconductor pillar 104.
  • the second support layer 120 may be a sacrificial material in the dotted box as shown in Figure 20. Specifically, it may be surrounding the second semiconductor pillar as shown in Figure 20. Sacrificial material for the four corner areas.
  • the method of removing the first oxide layer 115 on the sidewall at the top of the second semiconductor pillar 104 includes, but is not limited to, a dry etching process and a wet etching process.
  • methods of forming the sacrificial material 117 in the third filling region include, but are not limited to, PVD, CVD, and ALD.
  • the first oxide layer 115 on the sidewall at the top of the second semiconductor pillar 104 is not removed.
  • the first oxide layer 115 on the sidewall at the top of the second semiconductor pillar 104 is not removed first to form the third support layer 120, but the entire first oxide layer 115 is directly removed together, then in the aforementioned
  • the top of the second semiconductor pillar 104 will be separated from the formed sacrificial material 117, and in subsequent processes
  • the plurality of second semiconductor pillars 104 will lose their support, and there is a risk of collapse. Therefore, forming the third support layer 120 first as a top support can further improve the collapse problem.
  • the second support layer 114 is removed, and the third groove 112 and the fourth groove 113 are formed.
  • the method of removing the second support layer 114 includes but is not limited to a dry etching process and a wet etching process.
  • First packed area 127 of column 104 The area where the top of the first semiconductor pillar shown in FIG. 23 surrounds the four corners of the first semiconductor pillar is also part of the first filling area 127 .
  • methods for removing the remaining first oxide layer 115 include, but are not limited to, dry etching processes and wet etching processes.
  • conductive material is filled in the first filling region 127 to form the first electrode 105 - 1 .
  • the conductive material may be filled in the third groove 112, the fourth groove 113, the gap of the first semiconductor pillar 102, and the gap of the part of the second semiconductor pillar 104 except the top.
  • the conductive material filled in the third groove 112 and the fourth groove 113 forms the fourth support layer 121 .
  • the conductive material filled in the gap of the first semiconductor pillar 102 and the gap of the portion of the second semiconductor pillar 104 except the top forms the first electrode 105-1.
  • the first filling region 127 shown in FIG. 25 surrounding the four corners of the first semiconductor pillar at the top is also formed with the first electrode 105-1.
  • the formation of the fourth support layer 121 here can play a supporting role and improve the problem that the first semiconductor pillar 102 and the second semiconductor pillar 104 lose support and collapse after the sacrificial material 117 is removed in the subsequent process.
  • the first electrode 105-1 is used as a lower electrode of the capacitor.
  • the constituent materials of the first electrode 105-1 may include, but are not limited to, ruthenium (Ru), ruthenium oxide (RuO), and titanium nitride (TiN).
  • methods of forming the first electrode 105-1 include, but are not limited to, PVD, CVD, and ALD.
  • the first filling region 127 is formed after the first oxide layer 115 is removed. At this time, the first filling region 127 surrounds the first semiconductor pillar 102 and the second semiconductor pillar 104. The filling region 127 is directly filled with the material forming the first electrode 105-1, thereby forming the first electrode 105-1, and the plurality of formed first electrodes 105-1 are separated from each other.
  • the traditional method is to directly deposit the material of the first electrode 105-1 in the first trench 118 and the second trench 119 in the gap of the first semiconductor pillar 102 to form multiple first electrodes 105-1, so that multiple first electrodes 105-1 are formed.
  • the bottoms of the first electrodes 105-1 cannot be separated from each other, so that the first electrodes 105-1 interfere with each other.
  • the first electrodes 105-1 formed by the solution of the embodiment of the present disclosure can be separated from each other, thereby improving the mutual interference problem between the plurality of first electrodes 105-1.
  • the sacrificial material 117 between the first electrodes 105 - 1 is removed to form a second filling region 128 .
  • the sacrificial material 117 between the first electrodes 105-1 is removed, the sacrificial material 117 between the oxidation pillars 122 is retained to form a sacrificial layer 123, and the oxidation pillars 122 and the sacrificial layer 123 form a bottom support. layer.
  • the sacrificial material 117 between the first electrodes 105-1 is removed, the sacrificial material 117 between the fourth support layers 121 is also removed at the same time.
  • methods for removing the sacrificial material 117 include, but are not limited to, wet etching processes and dry etching processes.
  • the etching time can be controlled to only etch between the first electrodes 105-1 and the fourth support layer 121.
  • the sacrificial material 117 is retained in the gap between the oxidized pillars 122 .
  • the dielectric layer 105-2 and the second electrode 105-3 are sequentially formed in the second filling region 128.
  • the dielectric layer 105-2 is used as a dielectric of the capacitor.
  • the constituent materials of the dielectric layer 105-2 include high-k materials.
  • High-k materials generally refer to materials with a dielectric constant higher than 3.9, and are usually significantly higher than this value.
  • the material of the dielectric layer 105-2 may include, but is not limited to, aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO), hafnium oxide (HfO 2 ), strontium titanate (SrTiO 3 ), etc. .
  • the constituent materials of the second electrode 105-3 may include but are not limited to ruthenium, ruthenium oxide, and titanium nitride.
  • the method of forming the second electrode 105-3 includes but is not limited to PVD, CVD and other processes.
  • the semiconductor pillar is formed in two steps, that is, the first semiconductor pillar 102 is formed first, and then the second semiconductor pillar 104 is formed, and then the first semiconductor pillar 102 and the second semiconductor pillar 104 are formed.
  • the memory structure 105 is formed in the gap between the first semiconductor pillar 102 and the second semiconductor, which can improve the collapse problem caused by the high semiconductor pillars formed at one time.
  • the semiconductor pillar is formed in two times.
  • the semiconductor pillar can also be formed in three or more times.
  • the specific number of times of formation can be selected from the balance between saving process time and improving the collapse problem area.
  • the method further includes: before forming the second semiconductor substrate 103, forming a third semiconductor substrate on the first semiconductor pillar 102 and the first support layer 109;
  • the third active layer includes a plurality of third semiconductor pillars; each of the third semiconductor pillars is located on a corresponding first semiconductor pillar 102 the top surface;
  • a memory structure 105 is formed on the sidewalls of the plurality of first semiconductor pillars 102 and the plurality of second semiconductor pillars 104, including:
  • a memory structure 105 is formed on the sidewalls of the plurality of first semiconductor pillars 102, the plurality of second semiconductor pillars 104, and the plurality of third semiconductor pillars.
  • a transistor is formed on the upper sidewall of the second semiconductor pillar 104, and a bit line electrically connected to one of the source and drain electrodes of the transistor is formed.
  • the capacitance in the semiconductor structure is connected to the source electrode and the drain electrode in the transistor. of another electrical connection.
  • the method further includes:
  • a gate structure 124 is formed on at least one side of a portion of the upper sidewall.
  • the fourth support layer 121 and part of the memory structure 105 located above the second semiconductor pillar 104 are removed to expose the upper sidewall of the second semiconductor pillar 104 .
  • methods for removing the fourth support layer 121 and part of the memory structure 105 located above the second semiconductor pillar 104 include, but are not limited to, dry etching processes and wet etching processes.
  • a third insulating layer 111 is formed between the second semiconductor pillars 104 with exposed sidewalls.
  • the height of the third insulating layer 111 in the third direction is lower than the height of the second semiconductor pillar 104 in the third direction.
  • a gate oxide layer 125 (Gate oxide layer) and a gate 126 (G, Gate) are formed on the exposed sidewalls of the second semiconductor pillar 104 .
  • the shape of the gate 126 is different; for example, in a columnar gate transistor, the gate 126 is formed in a columnar form on one side of the channel region; in a semi-surround gate transistor, the gate 126 has a columnar shape.
  • the gate electrode 126 semi-surrounds the channel area; in a fully surround (GAA, Gate All Around) gate transistor, the gate electrode 126 fully surrounds the channel area.
  • the transistor types in the embodiments of the present disclosure may include the above-mentioned types, but are not limited thereto.
  • the type of the transistor is a full surround gate transistor.
  • the gate structure 124 here includes a gate electrode 126 and a gate oxide layer; the gate oxide layer is located between the gate electrode 126 and the channel region, and is used to electrically isolate the channel region and the gate electrode 126, reducing Hot carrier effect in transistors.
  • the material of the gate 126 may include metal or polysilicon (Poly), or the like.
  • the material of the gate oxide layer may include, but is not limited to, silicon oxide.
  • the formation method of the gate 126 includes but is not limited to PVD, CVD, ALD, etc.
  • the formation method of the gate oxide layer includes but is not limited to in-situ oxidation.
  • the method further includes forming a source electrode and a drain electrode respectively at two opposite ends in the third direction on the upper part of the second semiconductor pillar 104 .
  • Methods for forming the source and drain electrodes include but are not limited to doping processes and diffusion processes.
  • the positions of the source electrode and the drain electrode located at the two opposite ends of the upper part of the second semiconductor pillar 104 can be interchanged; the actual situation can be selected and set according to actual needs.
  • the method further includes:
  • a plurality of bit lines are formed on the second semiconductor pillar 104; the plurality of bit lines are in electrical contact with the top of the second semiconductor pillar 104.
  • the memory in the above embodiment is a transistor on capacitor (TOC) structure.
  • the structure also includes: a plurality of bit lines located on the transistor and the second semiconductor pillar 104. Top electrical contact.
  • bit line BL is used to perform a read or write operation on the transistor when the transistor is turned on.
  • bit line BL above the transistor and using the bit line BL as a metal bit line (Metal BL) can reduce resistance and process difficulty; it is more consistent with the circuit design scheme of the memory.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which includes: providing a first semiconductor substrate 101, forming a first active layer on the first semiconductor substrate 101, the first active layer including: A plurality of first semiconductor pillars 102 are arranged in an array in a direction and a second direction; the first direction and the second direction are both perpendicular to the extension direction of the first semiconductor pillar 102, and the first direction and The second directions intersect; form a first support layer 109 on top of the first active layer; form a second semiconductor substrate 103 on the first active layer and the first support layer 109; remove portions
  • the second semiconductor substrate 103 forms a second active layer, and the second active layer includes a plurality of second semiconductor pillars 104; each of the second semiconductor pillars 104 is located on a corresponding first semiconductor pillar 102.
  • a first semiconductor pillar is first formed on the first semiconductor substrate, and a first support layer is formed on the top of the first semiconductor pillar, and then a second semiconductor pillar is formed on the first semiconductor pillar, and the first semiconductor pillar is formed on the top of the first semiconductor pillar.
  • a second support layer is formed on the top of the two semiconductor pillars, so that a storage structure with a larger storage capacity can be formed in the gap between the higher semiconductor pillars.
  • the first support layer and the second support layer can support the first semiconductor pillar and the second support layer.
  • the second semiconductor pillar plays a supporting role, so that a higher-height semiconductor pillar can be formed without collapsing, so that a high-capacity and high-strength semiconductor structure can be obtained.
  • an embodiment of the disclosure further provides a semiconductor structure, including:
  • the plurality of first semiconductor pillars are arranged in an array along a first direction and a second direction; both the first direction and the second direction are perpendicular to the extension direction of the first semiconductor pillar, and the first The direction intersects the second direction;
  • the first support layer covers top sidewalls of the plurality of first semiconductor pillars
  • Each second semiconductor pillar is located on a corresponding first semiconductor pillar; the storage structure at least surrounds sidewalls of the plurality of first semiconductor pillars and the plurality of second semiconductor pillars.
  • the first support layer includes: a plurality of first support columns and a plurality of second support columns; wherein,
  • Each first support pillar is located between the tops of two first semiconductor pillars adjacent along the first direction
  • each second support pillar is located between the tops of two first semiconductor pillars adjacent along the second direction. between the tops, and the first support layer covers part of the top sidewalls of the first semiconductor pillars.
  • the storage structure includes:
  • each first electrode covers at least a portion of the sidewall of one of the first semiconductor pillars that is not covered by the first support layer, and covers a corresponding portion of the second semiconductor pillar. side wall;
  • each dielectric layer covers at least one side wall of the first electrode, one side wall of the first support pillar, and one side wall of the second support pillar;
  • the second electrode is located in the gaps between the plurality of first semiconductor pillars and the plurality of second semiconductor pillars and covers the plurality of dielectric layers.
  • the semiconductor structure further includes:
  • each of the first semiconductor pillars is located on the top surface of a corresponding one of the oxidation pillars;
  • a sacrificial layer located in the gaps between the plurality of oxidation pillars
  • the dielectric layer also covers the top surface of the sacrificial layer.
  • the semiconductor structure further includes:
  • a plurality of transistors the channel structure of each transistor is located on the upper part of the second semiconductor pillar, and the extending direction of the channel structure is perpendicular to the plane of the first direction and the second direction;
  • the transistors include:
  • the semiconductor structure further includes: a plurality of third semiconductor pillars and a fifth support layer; wherein,
  • Each of the third semiconductor pillars is located on a corresponding first semiconductor pillar, and each of the second semiconductor pillars is located on a corresponding third semiconductor pillar;
  • the fifth support layer covers the top sidewall of the third semiconductor pillar
  • the memory structure also surrounds sidewalls of the plurality of third semiconductor pillars.
  • an embodiment of the present disclosure further provides a memory, including: one or more semiconductor structures as described in any of the above embodiments of the present disclosure.
  • the disclosed devices and methods can be implemented in a non-target manner.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the components shown or discussed are coupled to each other, or directly coupled.
  • a first semiconductor pillar is first formed on the first semiconductor substrate, and a first support layer is formed on the top of the first semiconductor pillar, and then a second semiconductor pillar is formed on the first semiconductor pillar, and the first semiconductor pillar is formed on the top of the first semiconductor pillar.
  • a second support layer is formed on the top of the two semiconductor pillars, so that a storage structure with a larger storage capacity can be formed in the gap between the higher semiconductor pillars.
  • the first support layer and the second support layer can support the first semiconductor pillar and the second support layer.
  • the second semiconductor pillar plays a supporting role, so that a higher-height semiconductor pillar can be formed without collapsing, so that a high-capacity and high-strength semiconductor structure can be obtained.

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Abstract

本公开实施例公开了一种半导体结构及其制作方法、存储器,其中,所述半导体结构包括:多个第一半导体柱、多个第二半导体柱、第一支撑层及存储结构;其中,所述多个第一半导体柱沿第一方向和第二方向呈阵列排布;所述第一方向和所述第二方向均与所述第一半导体柱的延伸方向垂直,且所述第一方向和所述第二方向相交;所述第一支撑层覆盖所述多个第一半导体柱的顶部侧壁;每一所述第二半导体柱位于相应的一个所述第一半导体柱上;所述存储结构至少围绕所述多个第一半导体柱和所述多个第二半导体柱的侧壁。

Description

半导体结构及其制作方法、存储器
相关申请的交叉引用
本公开基于申请号为202210709198.5、申请日为2022年06月21日、发明名称为“半导体结构及其制作方法、存储器”的中国专利申请提出,并要求该中国专利申请的优先权,该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域,具体地,涉及一种半导体结构及其制作方法、存储器。
背景技术
动态随机存取存储器(DRAM,Dynamic Random Access Memory)的存储阵列架构是由包括一个晶体管和一个电容器的存储单元(即1T1C的存储单元)组成的阵列。晶体管的栅极与字线相连,漏极与位线相连,源极与电容器相连。
随着动态随机存取存储器的尺寸不断缩小,电容器的尺寸也随之缩小。如何保证动态随机存取存储器中电容器的性能,成为亟待解决的问题。
发明内容
有鉴于此,本公开实施例提出一种半导体结构及其制作方法、存储器。
根据本公开的一个方面,提供了一种半导体结构,包括:
多个第一半导体柱、多个第二半导体柱、第一支撑层及存储结构;其中,
所述多个第一半导体柱沿第一方向和第二方向呈阵列排布;所述第一方向和所述第二方向均与所述第一半导体柱的延伸方向垂直,且所述第一方向和所述第二方向相交;
所述第一支撑层覆盖所述多个第一半导体柱的顶部侧壁;
每一所述第二半导体柱位于相应的一个所述第一半导体柱上;所述存储结构至少围绕所述多个第一半导体柱和所述多个第二半导体柱的侧壁。
上述方案中,所述第一支撑层包括:多个第一支撑柱和多个第二支撑柱;其中,
每个所述第一支撑柱位于沿第一方向相邻的两个第一半导体柱的顶部之间,每个所述第二支撑柱位于沿第二方向相邻的两个第一半导体柱的顶部之间,且所述第一支撑层覆盖所述第一半导体柱的部分顶部侧壁。
上述方案中,所述存储结构包括:
多个第一电极;每一所述第一电极至少覆盖一个所述第一半导体柱的侧壁中未被所述第一支撑层覆盖的部分,且覆盖相应的一个所述第二半导体柱的侧壁;
多个介质层;每一所述介质层至少覆盖一个所述第一电极的侧壁、一个所述第一支撑柱的侧壁和一个所述第二支撑柱的侧壁;
第二电极,位于多个第一半导体柱和多个第二半导体柱的间隙中且覆盖所述多个介质层。
上述方案中,所述半导体结构还包括:
多个氧化柱,每一所述第一半导体柱均位于相应的一个所述氧化柱的顶面上;
牺牲层,位于多个所述氧化柱的间隙中;
所述介质层还覆盖所述牺牲层的顶面。
上述方案中,所述半导体结构还包括:
多个晶体管;每一晶体管的沟道结构位于所述第二半导体柱的上部,所述沟道结构的延伸方向垂直于所述第一方向和第二方向所在平面;
所述晶体管包括:
至少围绕部分所述第二半导体柱的上部侧壁的栅极结构,以及分别设置在所述第二半导体柱的上部,且位于所述沟道结构两端的源极和漏极。
根据本公开的另一个方面,提供了一种存储器,包括:一个或多个如本公开上述方案中任一方案所述的半导体结构。
根据本公开的再一个方面,提供了一种半导体结构的制作方法,所述方法包括:
提供第一半导体基底,在所述第一半导体基底上形成第一有源层,所述第一有源层包括沿第一方向和第二方向呈阵列排布的多个第一半导体柱;所述第一方向和所述第二方向均与所述第一半导体柱的延 伸方向垂直,且所述第一方向和所述第二方向相交;
在所述第一有源层的顶部形成第一支撑层;
在所述第一有源层和所述第一支撑层上形成第二半导体基底;
去除部分所述第二半导体基底形成第二有源层,所述第二有源层包括多个第二半导体柱;每个所述第二半导体柱位于相应的一个所述第一半导体柱的顶面;
在所述第二有源层的顶部形成第二支撑层;
在多个所述第一半导体柱和多个所述第二半导体柱的侧壁形成存储结构。
上述方案中,所述方法还包括:在形成所述第一支撑层之前,在所述多个第一半导体柱的间隙中形成第一绝缘层;
形成所述第一支撑层,包括:
去除部分所述第一绝缘层,形成多个第一凹槽;
在所述第一凹槽中形成第一支撑柱;
去除部分所述第一绝缘层,形成多个第二凹槽;
在所述第二凹槽中形成第二支撑柱;
其中,所述第一支撑柱和所述第二支撑柱共同构成所述第一支撑层,每个所述第一支撑柱位于沿第一方向相邻的两个第一半导体柱的顶部之间,每个所述第二支撑柱位于沿第二方向相邻的两个第一半导体柱的顶部之间,且所述第一支撑层覆盖所述第一半导体柱的部分顶部侧壁。
上述方案中,形成所述第二半导体基底,包括:
去除部分所述第一绝缘层以及部分所述第一支撑层,暴露所述第一半导体柱顶部的部分侧壁;
利用外延生长工艺,在所述第一半导体柱上形成所述第二半导体基底。
上述方案中,所述方法还包括:
在形成所述第二支撑层之前,在所述多个第二半导体柱的间隙中形成第二绝缘层;
形成所述第二支撑层,包括:
去除部分所述第二绝缘层,形成多个第三凹槽;
在所述第三凹槽中形成第三支撑柱;
去除部分所述第二绝缘层,形成多个第四凹槽;
在所述第四凹槽中形成第四支撑柱;
其中,所述第三支撑柱和所述第四支撑柱共同构成所述第二支撑层,每个所述第三支撑柱位于沿第一方向相邻的两个第二半导体柱的顶部之间,每个所述第四支撑柱位于沿第二方向相邻的两个第二半导体柱的顶部之间,且所述第二支撑层覆盖所述第二半导体柱的部分顶部侧壁。
上述方案中,形成所述存储结构,包括:
完全去除剩余的所述第一绝缘层以及剩余的所述第二绝缘层;
对所述第一半导体柱和所述第二半导体柱暴露的表面进行氧化处理,形成第一氧化层;
在所述第一氧化层的间隙中形成牺牲材料;
去除所述第二支撑层以及所述第一氧化层,形成围绕所述第一半导体柱和所述第二半导体柱的第一填充区域;
在所述第一填充区域中填充导电材料形成第一电极;
去除所述第一电极之间的所述牺牲材料,形成第二填充区域;
在所述第二填充区域中依次形成介质层和第二电极。
上述方案中,在去除所述第二支撑层之前,去除位于所述第二半导体柱顶部的侧壁的所述第一氧化层,形成第三填充区域,在所述第三填充区域中形成所述牺牲材料,以在所述第二半导体柱顶部形成第三支撑层。
上述方案中,在形成所述第一电极的同时,在所述第三凹槽和所述第四凹槽中形成所述导电材料,以在所述第二半导体柱顶部形成第四支撑层。
上述方案中,形成所述第一有源层,包括:
在所述第一半导体基底中形成多条沿第一方向间隔排布的第一沟槽,以及多条沿第二方向间隔排布的第二沟槽;其中,所述第一沟槽和所述第二沟槽将所述第一半导体基底分割成多个所述第一半导体柱;
对每一所述第一沟槽和/或所述第二沟槽底部进行扩大处理,使得形成的第一半导体柱包括第一部分和位于所述第一部分上的第二部分;所述第一部分的最大径宽小于所述第二部分的最小径宽。
上述方案中,在形成所述第一氧化层的同时,所述第一部分被全部氧化成氧化柱;在所述第一氧化层的间隙中形成牺牲材料的同时,所述牺牲材料还形成在氧化柱的间隙中;且在去除所述第一电极之间的所述牺牲材料时,保留位于所述氧化柱之间的所述牺牲材料形成牺牲层,所述氧化柱和所述牺牲层形成底部支撑层。
上述方案中,所述方法还包括:
去除所述第四支撑层以及位于所述第二半导体柱上部的部分存储结构,暴露出所述第二半导体柱的 上部侧壁;
在部分所述上部侧壁的至少一侧形成栅极结构。
本公开实施例提供了一种半导体结构及其制作方法、存储器,所述半导体结构的制作方法包括:提供第一半导体基底,在所述第一半导体基底上形成第一有源层,所述第一有源层包括沿第一方向和第二方向呈阵列排布的多个第一半导体柱;所述第一方向和所述第二方向均与所述第一半导体柱的延伸方向垂直,且所述第一方向和所述第二方向相交;在所述第一有源层的顶部形成第一支撑层;在所述第一有源层和所述第一支撑层上形成第二半导体基底;去除部分所述第二半导体基底形成第二有源层,所述第二有源层包括多个第二半导体柱;每个所述第二半导体柱位于相应的一个所述第一半导体柱的顶面;在所述第二有源层的顶部形成第二支撑层;在多个所述第一半导体柱和多个所述第二半导体柱的侧壁形成存储结构。本公开实施例中,通过先在第一半导体基底上形成第一半导体柱,并在第一半导体柱的顶部形成第一支撑层,再在第一半导体柱上形成第二半导体柱,并在第二半导体柱的顶部形成第二支撑层,这样使得能在高度较高的半导体柱的间隙中形成存储容量较大的存储结构,同时第一支撑层和第二支撑层能够对第一半导体柱和第二半导体柱起到支撑作用,使得在能够形成高度较高的半导体柱的同时不会坍塌,从而可以得到高容量、高强度的半导体结构。
附图说明
图1为本公开实施例中提供的一种DRAM晶体管的电路连接示意图;
图2为本公开实施例提供的半导体结构的制造方法的流程示意图;
图3-图30为本公开实施例提供的一种半导体结构的制造过程的剖面示意图。
具体实施方式
为使本公开实施例的技术方案和优点更加清楚,下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法,然而应当理解,可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反,提供这些实施方式是为了能够更透彻的理解本公开,并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书,本公开的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本公开实施例的目的。
可以理解的是,本公开中的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读,以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义,而且还包括在某物“上”且其间有居间特征或层的含义。
此外,为了便于描述,可以在本文中使用诸如“在……上”、“在……之上”、“在……上方”、“上”“上部”等的空间相对术语来描述如图所示的一个元件或特征与另一个元件或特征的关系。除了在附图中所描绘的取向之外,空间相对术语旨在涵盖设备在使用或操作中的不同取向。装置可以以其它方式定向(旋转90度或处于其它取向)并且同样可以相应地解释本文使用的空间相对描述词。
在本公开实施例中,术语“衬底”是指在其上添加后续材料层的材料。衬底本身可以被图案化。被添加在衬底顶部的材料可以被图案化或者可以保持未被图案化。此外,衬底可以包括多种半导体材料,例如硅、硅锗、锗、砷化嫁、磷化锢等。替代地,衬底可以由非导电材料制成,例如玻璃、塑料或蓝宝石晶圆。
在本公开实施例中,术语“层”是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸,或者可以具有小于下方或上方结构范围的范围。此外,层可以是厚度小于连续结构厚度的均质或非均质连续结构的区域。例如,层可位于连续结构的顶表面和底表面之间,或者层可在连续结构顶表面和底表面处的任何水平面对之间。层可以水平、垂直和/或沿倾斜表面延伸。层可以包括多个子层。例如,互连层可包括一个或多个导体和接触子层(其中形成互连线和/或过孔触点)、以及一个或多个电介质子层。
在本公开实施例中,术语“第一”、“第二”等是用于区别类似的对象,而不必用于描述特定的顺序或先后次序。
本公开实施例涉及的半导体结构是将被用于后续制程以形成最终的器件结构的至少一部分。这里,所述最终的器件可以包括存储器,所述存储器包括但不限于动态随机存取存储器,以下仅以动态随机存取存储器为例进行说明。
但需要说明的是,以下实施例关于动态随机存取存储器的描述仅用来说明本公开,并不用来限制本公开的范围。
随着动态随机存取存储器技术的发展,存储单元的尺寸越来越小,其阵列架构由8F 2到6F 2再到4F 2;另外,基于动态随机存取存储器中对离子和漏电流的需求,存储器的架构从平面阵列晶体管(Planar Array  Transistor)到凹栅阵列晶体管(Recess Gate Array Transistor),又从凹栅阵列晶体管到掩埋式沟道阵列晶体管(Buried Channel Array Transistor),再从掩埋式沟道阵列晶体管到垂直沟道阵列晶体管(Vertical Channel Array Transistor)。
本公开的一些实施例中,不论是平面晶体管、凹栅阵列晶体管、掩埋式晶体管还是垂直栅极晶体管,动态随机存取存储器均由多个存储单元结构构成,每一个存储单元结构主要是由一个晶体管与一个由晶体管所操控的存储单元(存储电容)构成,即动态随机存取存储器包括1个晶体管(T,Transistor)和1个电容(C,Capacitor)(1T1C)的架构;其主要的作用原理是利用电容内存储电荷的多寡来代表一个二进制比特(bit)是l还是0。
图1为本公开实施例中提供的一种采用1T1C的架构的电路连接示意图;如图1所示,晶体管T的漏极与位线(BL,Bit Line)电连接,晶体管T的源极与电容C的其中一个电极板电连接,电容C的另外一个电极板可以连接参考电压,所述参考电压可以是地电压也可以是其他电压,晶体管T的栅极与字线(WL,Word Line)连接;通过字线WL施加电压控制晶体管T导通或截止,位线BL用于在晶体管T导通时,对所述晶体管T执行读取或写入操作。
然而,随着存储器的发展,动态随机存取存储器的尺寸在不断缩小,存储器的存储容量不断提高,进而使得形成电容的工艺难度越来越大,存在坍塌的风险。
基于此,为解决上述问题中的一个或多个,本公开实施例提供了一种半导体结构的制作方法,可以改善坍塌问题。图2为本公开实施例提供的半导体结构的制作方法的流程示意图。如图2所示,本公开实施例提供的半导体结构的制作方法包括以下步骤:
S100:提供第一半导体基底,在所述第一半导体基底上形成第一有源层,所述第一有源层包括沿第一方向和第二方向呈阵列排布的多个第一半导体柱;所述第一方向和所述第二方向均与所述第一半导体柱的延伸方向垂直,且所述第一方向和所述第二方向相交;
S200:在所述第一有源层的顶部形成第一支撑层;
S300:在所述第一有源层和所述第一支撑层上形成第二半导体基底;
S400:去除部分所述第二半导体基底形成第二有源层,所述第二有源层包括多个第二半导体柱;每个所述第二半导体柱位于相应的一个所述第一半导体柱的顶面;
S500:在所述第二有源层的顶部形成第二支撑层;
S600:在多个所述第一半导体柱和多个所述第二半导体柱的侧壁形成存储结构。
应当理解,图2中所示的步骤并非排他的,也可以在所示操作中的任何步骤之前、之后或之间执行其他步骤;图2中所示的各步骤可以根据实际需求进行顺序调整。图3至图30为本公开实施例提供的一种半导体结构的制作过程的剖面示意图。需要说明的是,图3至图30为一个完整的反映半导体结构的制造方法的实现过程示意图,对于部分附图中未做标记的部分可以相互共用。下面结合图2、图3至图30,对本公开实施例提供的半导体结构的制作方法进行详细地说明。
在步骤S100中,主要是在第一半导体基底101上形成由多个第一半导体柱102构成的第一有源层。
在一些实施例中,形成所述第一有源层,包括:
在所述第一半导体基底101中形成多条沿第一方向间隔排布的第一沟槽118,以及多条沿第二方向间隔排布的第二沟槽119;其中,所述第一沟槽118和所述第二沟槽119将所述第一半导体基底101分割成多个所述第一半导体柱102;
对每一所述第一沟槽118和/或所述第二沟槽119底部进行扩大处理,使得形成的第一半导体柱102包括第一部分102-1和位于所述第一部分102-1上的第二部分102-2;所述第一部分102-1的最大径宽小于所述第二部分102-2的最小径宽。
在一些具体示例中,所述第一半导体基底101包括但不限于衬底,所述衬底可以包括单质半导体材料衬底(例如为硅(Si)衬底、锗(Ge)衬底等)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)、绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底等。优选地,所述衬底为硅衬底。
下面结合图3-图6对第一半导体柱102的形成过程进行详细说明。
如图3所示,对第一半导体基底101的表面进行第一刻蚀,在第一半导体基底101中形成沿第一方向间隔排布的多个第一沟槽118。这里,每一所述第一沟槽118沿第二方向延伸。
这里,所述第一方向与第一半导体基底101的表面平行;所述第二方向与所述第一方向相交,且与所述第一半导体基底101的表面平行。第三方向为第一半导体柱102的延伸方向,且所述第三方向垂直于所述第一半导体基底101的表面。
这里,第一方向与第二方向相交,可以理解为,第一方向与第二方向之间的夹角为0-90度。
为了清楚的描述本公开,以下实施例中以第一方向与第二方向垂直为例进行说明。示例性的,所述第一方向为图3中示出的X轴方向;所述第二方向为图3中示出的Y轴方向;所述第三方向为图3中示出的Z轴方向。但需要说明的是,以下实施例中关于方向的描述仅用于说明本公开,并不用来限制本公开的范围。
在一些具体示例中,所述第一沟槽118包括但不限于浅槽隔离(STI,Shallow Trench Isolation)结构。
在一些具体示例中,形成第一沟槽118的方法包括但不限于干法等离子体刻蚀工艺。
如图4所示,在所述第一沟槽118中形成第一绝缘层106;其中,所述第一绝缘层106的顶面与第一半导体基底101的顶面基本齐平;这里,所述第一绝缘层106用于起支撑作用。
需要说明的是,本公开中涉及的基本齐平可以理解为大致平齐;可以理解的是,在存储器的制造过程中,由于工艺误差导致的未对齐或未平齐也包括在基本齐平的范围内。
在一些具体示例中,所述第一绝缘层106的组成材料包括但不限于氧化硅(SiO 2)。
在一些具体示例中,形成第一绝缘层106的方法包括但不限于PVD、CVD、ALD等工艺。
如图5所示,对形成有第一绝缘层106的第一半导体基底101进行第二刻蚀,以在所述第一半导体基底101中形成多个第二沟槽119;其中,多个第二沟槽119沿第二方向间隔排布,且每个所述第二沟槽119沿第一方向延伸;也就是说,所述第一沟槽118和所述第二沟槽119相交。
在一些具体示例中,在第一方向与第二方向垂直时,所述第一沟槽118和所述第二沟槽119互相垂直。
在一些具体示例中,多个所述第一沟槽118沿X轴方向间隔排布;且每个所述第一沟槽118沿Y轴方向延伸;多个所述第二沟槽119沿Y轴方向间隔排布;且每个所述第二沟槽119沿X轴方向延伸。
在一些具体示例中,形成第二沟槽119的方法包括但不限于干法等离子体刻蚀工艺。
在一些具体示例中,所述第二沟槽119包括但不限于浅槽隔离(STI)结构。
这里,第一沟槽118和第二沟槽119将所述第一半导体基底101分割成多个沿第一方向和第二方向呈阵列排布的第一半导体柱102。
在一些具体示例中,还可以在第一半导体基底101的表面上形成网格状的掩膜层,将该网格状的掩膜层作为掩膜对第一半导体基底101进行刻蚀,同时形成第一沟槽118和第二沟槽119,以在第一半导体基底101中形成多个沿第一方向和第二方向呈阵列排布的第一半导体柱102。
接下来,如图5所示,对每一所述第一沟槽118和/或所述第二沟槽119底部进行扩大处理;这里,所述扩大处理可以理解为对第一沟槽118的底部进行沿第一方向的刻蚀;和/或,对第二沟槽119的底部进行沿第二方向的刻蚀,使得第一沟槽118和/或第二沟槽119的底部沿所述第一方向的径宽大于相应沟槽的顶部沿所述第一方向的径宽;
和/或,
第一沟槽118和/或第二沟槽119的底部沿所述第二方向的径宽大于相应沟槽的顶部沿所述第二方向的径宽。
在一些具体示例中,所采用的刻蚀工艺可以包括湿法刻蚀工艺、干法刻蚀工艺等。
示例性的,所述湿法刻蚀工艺中,将刻蚀剂通入第一沟槽118和/或第二沟槽119的底部,通过刻蚀剂的各向异性刻蚀,增大第一沟槽118和/或第二沟槽119的底部沿X轴方向的径宽;和/或,增大第一沟槽118和/或第二沟槽119的底部沿Y轴方向的径宽。
示例性的,所述干法刻蚀工艺中,通过控制等离子体进行横向刻蚀,以在第一沟槽118和/或第二沟槽119的底部形成径宽扩大的沟槽结构。
本公开实施例中,在对每一所述第一沟槽118和/或所述第二沟槽119底部进行扩大处理的过程后,刻蚀工艺使得位于第一半导体基底101上的多个第一半导体柱102的底部区域被刻蚀,第一半导体柱102的底部区域尺寸减小。
换言之,所述第一半导体柱102包括第一部分102-1和位于所述第一部分102-1上的第二部分102-2;这里,所述第一半导体柱102的第二部分102-2位于所述第一半导体柱102的第一部分102-1之上。
示例性的,在仅对第一沟槽118进行扩大处理时,所述第一半导体柱102的第一部分102-1沿X轴方向的最大径宽小于所述第一半导体柱102的第二部分102-2沿X轴方向的最小径宽。
示例性的,在仅对第二沟槽119进行扩大处理时,所述第一半导体柱102的第一部分102-1沿Y轴方向的最大径宽小于所述第一半导体柱102的第二部分102-2沿Y轴方向的最小径宽。
示例性的,在对第一沟槽118和第二沟槽119均进行扩大处理时,所述第一半导体柱102的第一部分102-1沿X轴方向的最大径宽小于所述第一半导体柱102的第二部分102-2沿X轴方向的最小径宽;以及所述第一半导体柱102的第一部分102-1沿Y轴方向的最大径宽小于所述第一半导体柱102的第二部分102-2沿Y轴方向的最小径宽。
优选地,对第一沟槽118和第二沟槽119均进行扩大处理,使得所述第一半导体柱102的第一部分102-1的尺寸减小。
示例性的,第一部分102-1的最大径宽可以理解为图5中第一半导体柱102的第一部分102-1与第一半导体柱102的第二部分102-2接触位置处的径宽;第二部分102-2的最小径宽可以理解为 第一半导体柱102的第二部分102-2中尺寸最小的区域;参考图5,第一半导体柱102的第二部分102-2的上下部分的尺寸相同,即第一半导体柱102的第二部分102-2的最小径宽和最大径宽相同。
接下来,如图6所示,在第二沟槽119中形成第一绝缘层106;所述第一绝缘层106的顶面与所述第一半导体基底101的顶面基本齐平。所述第一绝缘材料用于起支撑作用。
需要说明的是,形成第一沟槽118、第二沟槽119以及在第一沟槽118、第二沟槽119中填充第一绝缘材料形成第一绝缘层106的顺序可以根据实际情况进行选择。在另一些具体实施例中,可以先形成第一沟槽118和第二沟槽119后,再在第一沟槽118和第二沟槽119中形成第一绝缘层106。
在步骤S200中,如图7至图10所示,主要是在第一有源层的顶部形成第一支撑层109。
在一些实施例中,所述方法还包括:在形成所述第一支撑层109之前,在所述多个第一半导体柱102的间隙中形成第一绝缘层106(如图6示出);
形成所述第一支撑层109,包括:
去除部分所述第一绝缘层106,形成多个第一凹槽107;
在所述第一凹槽107中形成第一支撑柱109-1;
去除部分所述第一绝缘层106,形成多个第二凹槽108;
在所述第二凹槽108中形成第二支撑柱109-2;
其中,所述第一支撑柱109-1和所述第二支撑柱109-2共同构成所述第一支撑层109,每个所述第一支撑柱109-1位于沿第一方向相邻的两个第一半导体柱102的顶部之间,每个所述第二支撑柱109-2位于沿第二方向相邻的两个第一半导体柱102的顶部之间,且所述第一支撑层109覆盖所述第一半导体柱102的部分顶部侧壁。
如图7所示,去除第一半导体柱102顶部的部分第一绝缘层106,形成多个第一凹槽107。每个所述第一凹槽107位于沿第二方向相邻的两个第一半导体柱102的顶部之间。所述多个第一凹槽107沿X轴方向间隔排布,且每一个第一凹槽107沿Y轴方向延伸。
在一些具体示例中,去除第一半导体柱102顶部的部分第一绝缘层106的方法包括但不限于干法刻蚀工艺、湿法刻蚀工艺。
接下来,如图8所示,在第一凹槽107中形成第一支撑柱109-1。
在一些具体示例中,形成第一支撑柱109-1的方法包括但不限于PVD、CVD、ALD等工艺。
这里,所述第一支撑柱109-1的材料包括但不限于氮化硅。
接下来,如图9所示,去除第一半导体柱102顶部的部分第一绝缘层106,形成多个第二凹槽108。每个所述第二凹槽108位于沿第一方向相邻的两个第一半导体柱102的顶部之间。所述多个第二凹槽108沿Y轴方向间隔排布,且每一个第二凹槽108沿X轴方向延伸。
接下来,如图10所示,在第二凹槽108中形成第二支撑柱109-2。
在一些具体示例中,形成第二支撑柱109-2的方法包括但不限于PVD、CVD、ALD等工艺。
这里,所述第一支撑柱109-1与第二支撑柱109-2的可以材料相同或不同。
在一些具体示例中,在第一凹槽107和第二凹槽108中形成第一支撑层109后,还包括对第一支撑层109进行平坦化处理,使得第一支撑层109与第一半导体柱102的顶面齐平。
在一些具体示例中,所述平坦化处理工艺包括但不限于化学机械抛光技术(CMP,Chemical Mechanical Polishing)。
这里,形成的第一支撑柱109-1和第二支撑柱109-2共同构成第一支撑层109,如图10所示,第一支撑层109为网状的结构,且第一支撑层109覆盖所述第一半导体柱102的部分顶部侧壁。
在另一些具体示例中,还可以在第一半导体柱102上形成网格状的掩膜层,将该网格状的掩膜层作为掩膜对第一绝缘层106进行刻蚀,同时形成第一凹槽107和第二凹槽108,并在第一凹槽107中形成第一支撑柱109-1的同时,在第二凹槽108中形成第二支撑柱109-2。
这里,第一支撑层109覆盖所述第一半导体柱102的部分顶部侧壁,可以理解为,第一支撑柱109-1覆盖第一半导体柱102的部分顶部侧壁,和/或,第二支撑柱109-2覆盖第一半导体柱102的部分顶部侧壁。也就是说,至少部分第一支撑层109覆盖第一半导体柱102的部分顶部侧壁,第一支撑层109既要覆盖第一半导体柱102顶部侧壁,又不能完全覆盖第一半导体柱102顶部侧壁。可以理解的是,第一方面,第一支撑层109只有覆盖第一半导体柱102的顶部侧壁,才能对第一半导体柱102起到支撑作用,第一支撑层109覆盖第一半导体柱102顶部侧壁的部分越多,支撑效果越好;第二方面,第一支撑层109若完全覆盖第一半导体柱102的侧壁,则在后续工艺制程中形成存储结构105时,第一电极的材料只能填充到第二半导体柱104的间隙中,而无法向下填充到第一半导体柱102的间隙中。
可以理解的是,随着目前对存储器密度要求的不断提升,第一半导体柱102的深宽比不断增大,在形成第一半导体柱102的过程中容易出现坍塌的风险。本公开实施例中,至少部分第一支撑层109覆盖所述第一半导体柱102的部分顶部侧壁,这样使得多个第一半导体柱102彼此连接 起来,从而在后续工艺制程中在去除第一绝缘层106时,可以对第一半导体柱102起到支撑作用,使得深宽比较大的第一半导体柱102不易坍塌。
以上介绍了在第一半导体基底101上形成第一半导体柱102的过程,实际应用中,在一定高度的半导体柱的间隙中形成的存储结构的存储容量可能不够,需要进一步加高半导体柱的高度,从而在加高的半导体的间隙中形成更大容量的存储结构,然而加高半导体柱更容易出现坍塌,为了进一步解决上述坍塌问题,本公开实施例还提出了以下技术方案。
在步骤S300中,主要是形成第二半导体基底103。
在一些实施例中,形成所述第二半导体基底103,包括:
去除部分所述第一支撑层109及部分所述第一绝缘层106,暴露所述第一半导体柱102顶部的部分侧壁;
利用外延生长工艺,在所述第一半导体柱102、剩余的所述第一支撑层109和剩余的第一绝缘层106上形成所述第二半导体基底103。
如图11所示,去除第一半导体柱102顶部的第一绝缘层106,暴露出第一半导体柱102顶部的部分侧壁。
在一些实施例中,去除第一半导体柱102顶部的第一绝缘层106的方法包括但不限于干法刻蚀工艺、湿法刻蚀工艺。
接下来,如图12所示,在第一半导体柱102以及第一支撑层109上形成第二半导体基底103。
在一些具体示例中,形成第二半导体基底103的方法包括但不限于外延生长工艺。
可以理解的是,上述实施例中去除第一半导体柱102顶部的第一绝缘层106,暴露出第一半导体柱102顶部的部分侧壁的目的主要是使得能更方便的利用外延生长形成第二半导体基底103。
在一些具体示例中,第一半导体基底101的材料可以包括单质半导体材料(例如为硅、锗等)、复合半导体材料(例如为锗硅等)等。第二半导体基底103的材料与第一半导体基底101的材料可以相同,也可以不同。
在步骤S400中,主要是形成由多个第二半导体柱104构成的第二有源层。
如图13所示,形成多个第二半导体柱104,每个所述第二半导体柱104位于相应的一个所述第一半导体柱102的顶面。并在第二半导体柱104的间隙中形成第二绝缘层110。
这里,第二绝缘层110的材质包括但不限于氧化硅。第二绝缘层110与第一绝缘层106的材质相同或不同。
这里,在第一半导体柱102上形成第二半导体柱104的过程与前述实施例中形成第一半导体柱102的过程类似,这里不再赘述。
在步骤S500中,如图14所示,主要是形成第二支撑层114。
在一些实施例中,所述方法还包括:
在形成所述第二支撑层114之前,在所述多个第二半导体柱104的间隙中形成第二绝缘层110;
形成所述第二支撑层114,包括:
去除部分所述第二绝缘层110,形成多个第三凹槽;
在所述第三凹槽中形成第三支撑柱114-1;
去除部分所述第二绝缘层110,形成多个第四凹槽;
在所述第四凹槽中形成第四支撑柱114-2;
其中,所述第三支撑柱114-1和所述第四支撑柱114-2共同构成所述第二支撑层114,每个所述第三支撑柱114-1位于沿第一方向相邻的两个第二半导体柱104的顶部之间,每个所述第四支撑柱114-2位于沿第二方向相邻的两个第二半导体柱104的顶部之间,且所述第二支撑层114覆盖所述第二半导体柱104的部分顶部侧壁。
这里,第二支撑层114的材质包括但不限于氮化硅。第二支撑层114的材质与第一支撑层109的材质相同或不同。
这里,在第二有源层的顶部形成第二支撑层114的过程与前述实施例中在第一有源层的顶部形成第一支撑层109的过程类似,这里不再赘述。
可以理解的是,这里的第二支撑层114对第二半导体柱104起到支撑作用,使得在后续工艺中在去除第一绝缘层106和第二绝缘层110后,第二半导体柱104不易坍塌。
在步骤S600中,如图15-图27所示,主要是形成存储结构105。
在一些实施例中,形成所述存储结构105,包括:
完全去除剩余的所述第一绝缘层106以及剩余的所述第二绝缘层110;
对所述第一半导体柱102和所述第二半导体柱104暴露的表面进行氧化处理,形成第一氧化层115;
在所述第一氧化层115的间隙中形成牺牲材料117;
去除所述第二支撑层114以及所述第一氧化层115,形成围绕所述第一半导体柱102和所述第二半导体柱104的第一填充区域;
在所述第一填充区域中填充导电材料形成第一电极105-1;
去除所述第一电极105-1之间的所述牺牲材料117,形成第二填充区域;
在所述第二填充区域中依次形成介质层105-2和第二电极105-3。
在一些实施例中,在形成所述第一氧化层115的同时,所述第一部分102-1被全部氧化成氧化柱122;在所述第一氧化层115的间隙中形成牺牲材料117的同时,所述牺牲材料117还形成在氧化柱122的间隙中;且在去除所述第一电极105-1之间的所述牺牲材料117时,保留位于所述氧化柱122之间的所述牺牲材料117形成牺牲层123,所述氧化柱122和所述牺牲层123形成底部支撑层。
在一些实施例中,在去除所述第二支撑层114之前,去除位于所述第二半导体柱104顶部的侧壁的所述第一氧化层115,形成第三填充区域,在所述第三填充区域中形成所述牺牲材料117,以在所述第二半导体柱104顶部形成第三支撑层120。
在一些实施例中,在形成所述第一电极105-1的同时,在所述第三凹槽和所述第四凹槽中形成所述导电材料,以在所述第二半导体柱104顶部形成第四支撑层121。
如图15所示,完全去除剩余的第一绝缘层106和剩余的第二绝缘层110。
在一些具体示例中,完全去除剩余的第一绝缘层106和剩余的第二绝缘层110的方法包括但不限于干法刻蚀工艺、湿法刻蚀工艺。
接下来,如图16所示,通过氧化工艺,如热氧化工艺对所述第一半导体柱102及第二半导体柱104暴露的表面进行氧化,使得第一半导体柱102的第一部分102-1全部被氧化成氧化柱122,暴露出的第一半导体柱102的第二部分102-2的表面以及暴露出的第二半导体柱104的表面被氧化成第一氧化层115,同时,第一半导体基底101的表面也被氧化形成第二氧化层116。
可以理解的是,这里形成的第二氧化层116以及氧化柱122使得后续工艺中形成的电容能够与底部第一半导体基底101隔离,从而使得改善电容底部的漏电问题。
这里,第一氧化层115、第二氧化层116、氧化柱122的材料相同。示例性的,第一氧化层115、第二氧化层116、氧化柱122的组成材料包括但不限于氧化硅。
在一些具体示例中,这里第一氧化层115、第二氧化层116、氧化柱122的材料与所述第一绝缘层106的材料相同或不同。第一氧化层115、第二氧化层116、氧化柱122的材料与所述第二绝缘层110的材料相同或不同。
为了更清楚的示出第一半导体柱102的顶部在工艺过程中的变化,图17、图19、图23、图25单独示出了第一半导体柱102顶部的截面示意图。
如图16以及图17所示,在对第一半导体柱102以及第二半导体柱104进行氧化处理的过程中,由于第一半导体柱102的顶部以及第二半导体柱104的顶部有部分侧壁被第一支撑层109和第二支撑层114覆盖,因此在第一半导体柱102的顶部以及第二半导体柱104的顶部只有未被覆盖的部分第一半导体柱102侧壁和部分第二半导体柱104侧壁被氧化成了第一氧化层115。
需要说明的是,前述实施例中通过对第一沟槽118和/或第二沟槽119进行扩大处理后,第一半导体柱102的第一部分102-1和尺寸较小,易于被完全氧化。而且在第一半导体柱102的第一部分102-1被氧化时,所述第一半导体柱102的第二部分102-2仅表面被氧化。
接下来,如图18以及图19所示,在所述第一氧化层115的间隙中以及氧化柱122的间隙中形成牺牲材料117。
在一些具体示例中,形成牺牲材料117的方法包括但不限于PVD、CVD、ALD。
在一些具体示例中,形成的牺牲材料117的材质包括但不限于多晶硅、碳。
这里,对于牺牲材料117的材质的选择,第一方面,需要考虑牺牲材料117相对于第一氧化层115具有一定的刻蚀选择比,使得在后续工艺中去除第一氧化层115时,可以保留牺牲材料117;第二方面,需要考虑牺牲材料117相对于后续工艺中形成的第一电极105-1的材料具有一定的刻蚀选择比,使得后续工艺中在去除牺牲材料117形成牺牲层123时,减小对已形成的第一电极105-1的影响;第三方面,牺牲材料117需要能在后续工艺中较方便去除。
接下来,如图20所示,去除位于第二半导体柱104顶部的侧壁的第一氧化层115,形成第三填充区域,在第三填充区域中形成牺牲材料117,以在所述第二半导体柱104顶部形成第三支撑层120,第二支撑层120具体可以是如图20所示出的虚线框中的牺牲材料,具体的可以是如图20中示出的围绕第二半导体柱的四个角的区域的牺牲材料。
在一些具体示例中,去除位于第二半导体柱104顶部的侧壁的第一氧化层115的方法包括但不限于干法刻蚀工艺、湿法刻蚀工艺。
在一些具体示例中,在第三填充区域中形成牺牲材料117的方法包括但不限于PVD、CVD、ALD。
需要说明的是,去除位于第二半导体柱104顶部的侧壁的第一氧化层115时,第一半导体柱102顶部的侧壁的第一氧化层115未被去除。
可以理解的是,若这里不先去除位于第二半导体柱104顶部的侧壁的第一氧化层115形成第三支撑层120,而是直接将全部的第一氧化层115一起去除,则在前述实施例中在第二半导体柱104的间隙中 形成的牺牲材料117在第一氧化层115被全部去除后,第二半导体柱104顶部将会与所形成的牺牲材料117分离,并且在后续工艺中第二支撑层114被去除后,多个第二半导体柱104将会失去支撑,存在坍塌的风险。因此,这里先形成第三支撑层120作为顶部支撑可以进一步改善坍塌问题。
接下来,如图21所示,去除第二支撑层114,形成第三凹槽112以及第四凹槽113。
这里,去除第二支撑层114的方法包括但不限于干法刻蚀工艺、湿法刻蚀工艺。
接下来,如图22以及图23所示,去除第一半导体柱102以及第二半导体柱104的间隙中剩余的第一氧化层115。
这里,去除所述第二支撑层114以及第一半导体柱102以及第二半导体柱104的间隙中剩余的第一氧化层115后,形成了围绕所述第一半导体柱102和所述第二半导体柱104的第一填充区域127。在图23中示出的第一半导体柱的顶部包围第一半导体柱的四个角的区域也为第一填充区域127的一部分。
在一些具体示例中,去除剩余的第一氧化层115的方法包括但不限于干法刻蚀工艺、湿法刻蚀工艺。
接下来,如图24以及图25所示,在第一填充区域127中填充导电材料形成第一电极105-1。具体的,可以是在第三凹槽112、第四凹槽113、第一半导体柱102的间隙以及第二半导体柱104除顶部以外的部分的间隙中填充导电材料。填充在第三凹槽112和第四凹槽113中的导电材料形成第四支撑层121。填充在第一半导体柱102的间隙以及第二半导体柱104除顶部以外的部分的间隙中的导电材料形成第一电极105-1。图25中示出的在第一半导体柱的顶部包围第一半导体柱的四个角的第一填充区域127也形成有第一电极105-1。
可以理解的是,这里形成第四支撑层121可以起到支撑作用,改善后续工艺制程中去除牺牲材料117后第一半导体柱102和第二半导体柱104失去支撑,从而产生坍塌的问题。
这里,第一电极105-1用于作为电容的下电极。
在一些具体示例中,所述第一电极105-1的组成材料可以包括但不限于钌(Ru)、氧化钌(RuO)、氮化钛(TiN)。
在一些具体示例中,形成第一电极105-1的方法包括但不限于PVD、CVD、ALD。
可以理解的是,本公开实施例中,在去除第一氧化层115后形成第一填充区域127,此时的第一填充区域127环绕第一半导体柱102以及第二半导体柱104,在第一填充区域127中直接填充形成第一电极105-1的材料,从而形成第一电极105-1,形成的多个第一电极105-1是彼此分开的。传统的方法是,在第一半导体柱102的间隙中的第一沟槽118和第二沟槽119中直接沉积第一电极105-1的材料形成多个第一电极105-1,这样使得多个第一电极105-1底部无法彼此分开,从而使得第一电极105-1之间相互干扰。而本公开实施例的方案形成的第一电极105-1能彼此分开,从而可以改善多个第一电极105-1之间的彼此干扰问题。
接下来,如图26所示,去除第一电极105-1之间的牺牲材料117,形成第二填充区域128。在去除所述第一电极105-1之间的所述牺牲材料117时,保留位于氧化柱122之间的牺牲材料117形成牺牲层123,所述氧化柱122和所述牺牲层123形成底部支撑层。并且在去除第一电极105-1之间的所述牺牲材料117时,第四支撑层121之间的牺牲材料117也同时被去除。
在一些具体示例中,去除牺牲材料117的方法包括但不限于湿蚀工艺、干法刻蚀工艺。示例性的,在利用刻蚀工艺去除第一电极105-1之间的牺牲材料117时,可以通过控制刻蚀时间达到只刻蚀第一电极105-1之间以及第四支撑层121之间的牺牲材料117,而氧化柱122间隙中的牺牲材料117被保留的目的。
接下来,如图27所示,在第二填充区域128中依次形成介质层105-2和第二电极105-3。
这里,介质层105-2用于作为电容的电介质。
这里,所述介质层105-2的组成材料包括高介电常数(High-K)材料,高介电常数材料一般指介电常数高于3.9的材料,且通常显著高于该值。在一些具体示例中,所述介质层105-2的材料可以包括但不限于氧化铝(Al 2O 3)、氧化锆(ZrO)、氧化铪(HfO 2)、钛酸锶(SrTiO 3)等。
在一些具体实施例中,所述第二电极105-3的组成材料可以包括但不限于钌、氧化钌、氮化钛。
这里,形成第二电极105-3的方法包括但不限于PVD、CVD等工艺。
可以理解的是,本公开实施例中,将半导体柱分两次形成,即先形成第一半导体柱102,再形成第二半导体柱104,并在形成第一半导体柱102和第二半导体柱104之后,再在第一半导体柱102和第二半导体的间隙中形成存储结构105,这样可以改善一次形成的半导体柱较高而出现的坍塌问题。
以上介绍了将半导体柱分两次形成,在一些具体示例中,还可以将半导体柱分三次或者更多次形成。实际应用中,具体进行几次形成,可以从平衡节省工艺时间和改善坍塌问题区进行选择。
在一些实施例中,所述方法还包括:在形成第二半导体基底103之前,在所述第一半导体柱102和所述第一支撑层109上形成第三半导体基底;
去除部分所述第三半导体基底,形成第三有源层,所述第三有源层包括多个第三半导体柱;每个所述第三半导体柱位于相应的一个所述第一半导体柱102的顶面;
在所述第三有源层的顶部形成第五支撑层,所述第五支撑层覆盖所述第三半导体柱的顶部侧壁;
在多个所述第一半导体柱102和多个所述第二半导体柱104的侧壁形成存储结构105,包括:
在多个所述第一半导体柱102、多个第二半导体柱104及多个第三半导体柱的侧壁形成存储结构105。
接下来,在第二半导体柱104的上部侧壁形成晶体管,并形成与晶体管的源极和漏极中的一个电连接的位线,半导体结构中的电容与晶体管中的源极和漏极中的另一个电连接。
在一些实施例中,所述方法还包括:
去除所述第四支撑层121以及位于所述第二半导体柱104上部的部分存储结构105,暴露出所述第二半导体柱104的上部侧壁;
在部分所述上部侧壁的至少一侧形成栅极结构124。
如图27所示,去除第四支撑层121以及位于所述第二半导体柱104上部的部分存储结构105,暴露出第二半导体柱104的上部侧壁。
在一些具体示例中,除第四支撑层121以及位于所述第二半导体柱104上部的部分存储结构105的方法包括但不限于干法刻蚀工艺、湿法刻蚀工艺。
如图28所示,在暴露了侧壁的第二半导体柱104之间形成第三绝缘层111。所述第三绝缘层111在第三方向的高度低于所述第二半导体柱104在第三方向的高度。
如图29以及图30所示,在第二半导体柱104被暴露的侧壁形成栅极氧化层125(Gate oxide layer)以及栅极126(G,Gate)。
这里,不同类型的晶体管中,栅极126的形状不同;示例性的,柱型栅极晶体管中,栅极126以柱状形式形成在沟道区的一侧;半环绕型栅极晶体管中,栅极126半包围沟道区;全环绕型(GAA,Gate All Around)栅极晶体管中,栅极126全包围沟道区。
本公开实施例中的晶体管类型可以包括上述多种类型,但不限于此。优选地,所述晶体管的类型为全环绕型栅极晶体管。
需要说明的是,这里的栅极结构124包括栅极126和栅氧化层;其中,栅氧化层位于栅极126与沟道区之间,用于电隔离沟道区和栅极126,减小晶体管的热载流子效应。
这里,栅极126的材料可以包括金属或多晶硅(Poly)等。栅氧化层的材料可以包括但不限于氧化硅。
在一些具体示例中,栅极126的形成方法包括但不限于PVD、CVD、ALD等。栅氧化层的形成方法包括但不限于原位氧化。
在一些具体示例中,所述方法还包括在第二半导体柱104上部形成在第三方向相对的两端分别形成源极和漏极。形成源极、漏极的方法包括但不限于掺杂工艺和扩散工艺等。
需要说明的是,位于第二半导体柱104上部相对的两端的源极和漏极的位置可以互换;实际情况可以根据实际需求进行选择设置。
在一些实施例中,所述方法还包括:
在所述第二半导体柱104上形成多条位线;所述多条位线与所述第二半导体柱104的顶部电接触。
可以理解的是,上述实施例中的存储器为晶体管-电容(TOC,Transistor on Capacitor)结构,所述结构还包括:多条位线,位于所述晶体管上,与所述第二半导体柱104的顶部电接触。
可以理解的是,位线BL用于在晶体管导通时,对所述晶体管执行读取或写入操作。
这里,将位线BL设置在晶体管的上方,并将位线BL作为金属位线(Metal BL),可以减少电阻,降低工艺难度;与存储器的电路设计方案更匹配。
本公开实施例提供了一种半导体结构的制作方法,包括:提供第一半导体基底101,在所述第一半导体基底101上形成第一有源层,所述第一有源层包括沿第一方向和第二方向呈阵列排布的多个第一半导体柱102;所述第一方向和所述第二方向均与所述第一半导体柱102的延伸方向垂直,且所述第一方向和所述第二方向相交;在所述第一有源层的顶部形成第一支撑层109;在所述第一有源层和所述第一支撑层109上形成第二半导体基底103;去除部分所述第二半导体基底103形成第二有源层,所述第二有源层包括多个第二半导体柱104;每个所述第二半导体柱104位于相应的一个所述第一半导体柱102的顶面;在所述第二有源层的顶部形成第二支撑层114;在多个所述第一半导体柱102和多个所述第二半导体柱104的侧壁形成存储结构105。本公开实施例中,通过先在第一半导体基底上形成第一半导体柱,并在第一半导体柱的顶部形成第一支撑层,再在第一半导体柱上形成第二半导体柱,并在第二半导体柱的顶部形成第二支撑层,这样使得能在高度较高的半导体柱的间隙中形成存储容量较大的存储结构,同时第一支撑层和第二支撑层能够对第一半导体柱和第二半导体柱起到支撑作用,使得在能够形成高度较高的半导体柱的同时不会坍塌,从而可以得到高容量、高强度的半导体结构。
根据本公开的另一方面,本公开实施例又提供了一种半导体结构,包括:
多个第一半导体柱、多个第二半导体柱、第一支撑层及存储结构;其中,
所述多个第一半导体柱沿第一方向和第二方向呈阵列排布;所述第一方向和所述第二方向均与所述第一半导体柱的延伸方向垂直,且所述第一方向和所述第二方向相交;
所述第一支撑层覆盖所述多个第一半导体柱的顶部侧壁;
每一所述第二半导体柱位于相应的一个所述第一半导体柱上;所述存储结构至少围绕所述多个第一半导体柱和所述多个第二半导体柱的侧壁。
在一些实施例中,所述第一支撑层包括:多个第一支撑柱和多个第二支撑柱;其中,
每个所述第一支撑柱位于沿第一方向相邻的两个第一半导体柱的顶部之间,每个所述第二支撑柱位于沿第二方向相邻的两个第一半导体柱的顶部之间,且所述第一支撑层覆盖所述第一半导体柱的部分顶部侧壁。
在一些实施例中,所述存储结构包括:
多个第一电极;每一所述第一电极至少覆盖一个所述第一半导体柱的侧壁中未被所述第一支撑层覆盖的部分,且覆盖相应的一个所述第二半导体柱的侧壁;
多个介质层;每一所述介质层至少覆盖一个所述第一电极的侧壁、一个所述第一支撑柱的侧壁和一个所述第二支撑柱的侧壁;
第二电极,位于多个第一半导体柱和多个第二半导体柱的间隙中且覆盖所述多个介质层。
在一些实施例中,所述半导体结构还包括:
多个氧化柱,每一所述第一半导体柱均位于相应的一个所述氧化柱的顶面上;
牺牲层,位于多个所述氧化柱的间隙中;
所述介质层还覆盖所述牺牲层的顶面。
在一些实施例中,所述半导体结构还包括:
多个晶体管;每一晶体管的沟道结构位于所述第二半导体柱的上部,所述沟道结构的延伸方向垂直于所述第一方向和第二方向所在平面;
所述晶体管包括:
至少围绕部分所述第二半导体柱的上部侧壁的栅极结构,以及分别设置在所述第二半导体柱的上部,且位于所述沟道结构两端的源极和漏极。
在一些实施例中,所述半导体结构还包括:多个第三半导体柱和第五支撑层;其中,
每一所述第三半导体柱位于相应的一所述第一半导体柱上,每一所述第二半导体柱位于相应的一所述第三半导体柱上;
所述第五支撑层覆盖所述第三半导体柱的顶部侧壁;
所述存储结构还环绕所述多个第三半导体柱的侧壁。
根据本公开的再一方面,本公开实施例还提供了一种存储器,包括:一个或多个如本公开上述实施例中任一实施例所述的半导体结构。
上述实施例中提供的半导体结构及存储器在方法侧已详细介绍,这里不再赘述。
在本公开所提供的几个实施例中,应该理解到,所揭露的设备和方法,可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的,例如,所述单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,如:多个单元或组件可以结合,或可以集成到另一个系统,或一些特征可以忽略,或不执行。另外,所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
本公开所提供的几个方法或设备实施例中所揭露的特征,在不冲突的情况下可以任意组合,得到新的方法实施例或设备实施例。
本公开的具体实施方式,但本公开的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本公开揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本公开的保护范围之内。因此,本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例中,通过先在第一半导体基底上形成第一半导体柱,并在第一半导体柱的顶部形成第一支撑层,再在第一半导体柱上形成第二半导体柱,并在第二半导体柱的顶部形成第二支撑层,这样使得能在高度较高的半导体柱的间隙中形成存储容量较大的存储结构,同时第一支撑层和第二支撑层能够对第一半导体柱和第二半导体柱起到支撑作用,使得在能够形成高度较高的半导体柱的同时不会坍塌,从而可以得到高容量、高强度的半导体结构。

Claims (16)

  1. 一种半导体结构,包括:多个第一半导体柱、多个第二半导体柱、第一支撑层及存储结构;其中,
    所述多个第一半导体柱沿第一方向和第二方向呈阵列排布;所述第一方向和所述第二方向均与所述第一半导体柱的延伸方向垂直,且所述第一方向和所述第二方向相交;
    所述第一支撑层覆盖所述多个第一半导体柱的顶部侧壁;
    每一所述第二半导体柱位于相应的一个所述第一半导体柱上;所述存储结构至少围绕所述多个第一半导体柱和所述多个第二半导体柱的侧壁。
  2. 根据权利要求1所述的半导体结构,其中,所述第一支撑层包括:多个第一支撑柱和多个第二支撑柱;其中,
    每个所述第一支撑柱位于沿第一方向相邻的两个第一半导体柱的顶部之间,每个所述第二支撑柱位于沿第二方向相邻的两个第一半导体柱的顶部之间,且所述第一支撑层覆盖所述第一半导体柱的部分顶部侧壁。
  3. 根据权利要求2所述的半导体结构,其中,所述存储结构包括:
    多个第一电极;每一所述第一电极至少覆盖一个所述第一半导体柱的侧壁中未被所述第一支撑层覆盖的部分,且覆盖相应的一个所述第二半导体柱的侧壁;
    多个介质层;每一所述介质层至少覆盖一个所述第一电极的侧壁、一个所述第一支撑柱的侧壁和一个所述第二支撑柱的侧壁;
    第二电极,位于多个第一半导体柱和多个第二半导体柱的间隙中且覆盖所述多个介质层。
  4. 根据权利要求3所述的半导体结构,其中,所述半导体结构还包括:
    多个氧化柱,每一所述第一半导体柱均位于相应的一个所述氧化柱的顶面上;
    牺牲层,位于多个所述氧化柱的间隙中;
    所述介质层还覆盖所述牺牲层的顶面。
  5. 根据权利要求1所述的半导体结构,其中,所述半导体结构还包括:
    多个晶体管;每一晶体管的沟道结构位于所述第二半导体柱的上部,所述沟道结构的延伸方向垂直于所述第一方向和第二方向所在平面;
    所述晶体管包括:
    至少围绕部分所述第二半导体柱的上部侧壁的栅极结构,以及分别设置在所述第二半导体柱的上部,且位于所述沟道结构两端的源极和漏极。
  6. 一种存储器,包括:至少一个如权利要求1至5中任一项所述的半导体结构。
  7. 一种半导体结构的制作方法,所述方法包括:
    提供第一半导体基底,在所述第一半导体基底上形成第一有源层,所述第一有源层包括沿第一方向和第二方向呈阵列排布的多个第一半导体柱;所述第一方向和所述第二方向均与所述第一半导体柱的延伸方向垂直,且所述第一方向和所述第二方向相交;
    在所述第一有源层的顶部形成第一支撑层;
    在所述第一有源层和所述第一支撑层上形成第二半导体基底;
    去除部分所述第二半导体基底形成第二有源层,所述第二有源层包括多个第二半导体柱;每个所述第二半导体柱位于相应的一个所述第一半导体柱的顶面;
    在所述第二有源层的顶部形成第二支撑层;
    在多个所述第一半导体柱和多个所述第二半导体柱的侧壁形成存储结构。
  8. 根据权利要求7所述的半导体结构的制作方法,其中,所述方法还包括:在形成所述第一支撑层之前,在所述多个第一半导体柱的间隙中形成第一绝缘层;
    形成所述第一支撑层,包括:
    去除部分所述第一绝缘层,形成多个第一凹槽;
    在所述第一凹槽中形成第一支撑柱;
    去除部分所述第一绝缘层,形成多个第二凹槽;
    在所述第二凹槽中形成第二支撑柱;
    其中,所述第一支撑柱和所述第二支撑柱共同构成所述第一支撑层,每个所述第一支撑柱位于沿第一方向相邻的两个第一半导体柱的顶部之间,每个所述第二支撑柱位于沿第二方向相邻的两个第一半导体柱的顶部之间,且所述第一支撑层覆盖所述第一半导体柱的部分顶部侧壁。
  9. 根据权利要求8所述的半导体结构的制作方法,其中,形成所述第二半导体基底,包括:
    去除部分所述第一支撑层以及部分所述第一绝缘层,暴露所述第一半导体柱顶部的部分侧壁;
    利用外延生长工艺,在所述第一半导体柱上形成所述第二半导体基底。
  10. 根据权利要求8所述的半导体结构的制作方法,其中,所述方法还包括:
    在形成所述第二支撑层之前,在所述多个第二半导体柱的间隙中形成第二绝缘层;
    形成所述第二支撑层,包括:
    去除部分所述第二绝缘层,形成多个第三凹槽;
    在所述第三凹槽中形成第三支撑柱;
    去除部分所述第二绝缘层,形成多个第四凹槽;
    在所述第四凹槽中形成第四支撑柱;
    其中,所述第三支撑柱和所述第四支撑柱共同构成所述第二支撑层,每个所述第三支撑柱位于沿第一方向相邻的两个第二半导体柱的顶部之间,每个所述第四支撑柱位于沿第二方向相邻的两个第二半导体柱的顶部之间,且所述第二支撑层覆盖所述第二半导体柱的部分顶部侧壁。
  11. 根据权利要求10所述的半导体结构的制作方法,其中,形成所述存储结构,包括:
    完全去除剩余的所述第一绝缘层以及剩余的所述第二绝缘层;
    对所述第一半导体柱和所述第二半导体柱暴露的表面进行氧化处理,形成第一氧化层;
    在所述第一氧化层的间隙中形成牺牲材料;
    去除所述第二支撑层以及所述第一氧化层,形成围绕所述第一半导体柱和所述第二半导体柱的第一填充区域;
    在所述第一填充区域中填充导电材料形成第一电极;
    去除所述第一电极之间的所述牺牲材料,形成第二填充区域;
    在所述第二填充区域中依次形成介质层和第二电极。
  12. 根据权利要求11所述的半导体结构的制作方法,其中,
    在去除所述第二支撑层之前,去除位于所述第二半导体柱顶部的侧壁的所述第一氧化层,形成第三填充区域,在所述第三填充区域中形成所述牺牲材料,以在所述第二半导体柱顶部形成第三支撑层。
  13. 根据权利要求11所述的半导体结构的制作方法,其中,在形成所述第一电极的同时,在所述第三凹槽和所述第四凹槽中形成所述导电材料,以在所述第二半导体柱顶部形成第四支撑层。
  14. 根据权利要求11所述的半导体结构的制作方法,其中,
    形成所述第一有源层,包括:
    在所述第一半导体基底中形成多条沿第一方向间隔排布的第一沟槽,以及多条沿第二方向间隔排布的第二沟槽;其中,所述第一沟槽和所述第二沟槽将所述第一半导体基底分割成多个所述第一半导体柱;
    对每一所述第一沟槽和/或所述第二沟槽底部进行扩大处理,使得形成的第一半导体柱包括第一部分和位于所述第一部分上的第二部分;所述第一部分的最大径宽小于所述第二部分的最小径宽。
  15. 根据权利要求14所述的半导体结构的制作方法,其中,在形成所述第一氧化层的同时,所述第一部分被全部氧化成氧化柱;在所述第一氧化层的间隙中形成牺牲材料的同时,所述牺牲材料还形成在氧化柱的间隙中;且在去除所述第一电极之间的所述牺牲材料时,保留位于所述氧化柱之间的所述牺牲材料形成牺牲层,所述氧化柱和所述牺牲层形成底部支撑层。
  16. 根据权利要求13所述的半导体结构的制作方法,其中,所述方法还包括:
    去除所述第四支撑层以及位于所述第二半导体柱上部的部分存储结构,暴露出所述第二半导体柱的上部侧壁;
    在部分所述上部侧壁的至少一侧形成栅极结构。
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