WO2023206738A1 - 电容器的制作方法、电容器以及存储器 - Google Patents

电容器的制作方法、电容器以及存储器 Download PDF

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Publication number
WO2023206738A1
WO2023206738A1 PCT/CN2022/098120 CN2022098120W WO2023206738A1 WO 2023206738 A1 WO2023206738 A1 WO 2023206738A1 CN 2022098120 W CN2022098120 W CN 2022098120W WO 2023206738 A1 WO2023206738 A1 WO 2023206738A1
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Prior art keywords
electrode
layer
capacitor
manufacturing
dielectric layer
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PCT/CN2022/098120
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English (en)
French (fr)
Inventor
杨蒙蒙
肖德元
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长鑫存储技术有限公司
长鑫集电(北京)存储技术有限公司
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Application filed by 长鑫存储技术有限公司, 长鑫集电(北京)存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP22782648.4A priority Critical patent/EP4290552A4/en
Priority to US17/822,815 priority patent/US20230354574A1/en
Publication of WO2023206738A1 publication Critical patent/WO2023206738A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present disclosure relates to a manufacturing method of a capacitor, a capacitor and a memory.
  • DRAM Dynamic Random Access Memory
  • the present disclosure provides a method for manufacturing a capacitor, a capacitor and a memory.
  • a first aspect of the present disclosure provides a method of manufacturing a capacitor.
  • the method of manufacturing a capacitor includes:
  • a first electrode is formed on the substrate, the first electrode extends in a first direction parallel to the substrate, and a size of the first electrode in the first direction is larger than that of the first electrode in a second direction. direction, as well as the size in the third direction, the first direction, the second direction and the third direction are perpendicular to each other;
  • a second electrode covering the dielectric layer is formed.
  • the manufacturing method of the capacitor also includes:
  • the dielectric layer covers the surfaces of the plurality of first electrodes and is located in the three-dimensional space to form a common dielectric layer;
  • the second electrode is coated on the surface of the dielectric layer and located in the three-dimensional space to form a common second electrode.
  • forming the first electrode on the substrate includes:
  • At least one epitaxial layer is formed on the substrate.
  • the epitaxial layer includes an overlapping arrangement of a single crystal silicon layer and a silicon-containing material layer.
  • the size of the single crystal silicon layer in the first direction is larger than that in the second direction.
  • a pattern area and a contact area are defined on the epitaxial layer, wherein the single crystal silicon layer at the contact area forms a source or drain area of a transistor;
  • the epitaxial layer is selectively etched downward to expose the substrate.
  • the remaining epitaxial layer at the pattern area defines the position of the first electrode and extends laterally. , wherein the remaining single crystal silicon layer reserves a gap for the first electrode;
  • the first electrode is formed in the gap.
  • a patterned first mask layer is formed on the epitaxial layer, and the epitaxial layer is etched downward using the patterned first mask layer as a mask until the substrate is exposed, so as to simultaneously define the The pattern area, the contact area, and the position of the first electrode.
  • forming the first electrode in the gap includes:
  • a first electrode material is deposited in the pattern area, the first electrode material fills the grooves and the gaps in the pattern area, and the first electrode material extends outside the pattern area and covers the contact the top surface of the area;
  • Maskless etching is used to remove the first electrode material in the groove and on the top surface of the contact area, and the first electrode material retained in the gap forms the first electrode.
  • the first electrode material is formed using an atomic layer deposition process and a chemical vapor deposition process.
  • the manufacturing method of the capacitor further includes: forming a support structure on the side wall of the first electrode; forming the support structure on the side wall of the first electrode, include:
  • a patterned second mask layer is formed on the surface of the support material, the patterned second mask layer covers the surface of the contact area, and the patterned second mask layer is also on the graphic area Form an array arrangement;
  • the support material at the height of the top surface is removed so that the support material is located on the side walls of the first electrode and the side walls of the contact area to form the support structure.
  • first lower electrodes when forming multiple first lower electrodes, it also includes:
  • a wet etching process or a vapor etching process is used to remove the remaining silicon-containing material layer in the epitaxial layer to form the three-dimensional space.
  • forming a dielectric layer covering the first electrode includes:
  • a dielectric layer is formed using an atomic layer deposition process, and the dielectric layer continuously covers the outer surface of the first electrode.
  • forming the second electrode layer covering the dielectric layer includes:
  • the second electrode layer is formed using an atomic layer deposition process, and the second electrode layer continuously covers the outer surface of the dielectric layer.
  • the first electrode has an aspect ratio between the first direction and the third direction, and the aspect ratio is greater than or equal to 35.
  • the capacitor is used to connect a wrap-around gate transistor, wherein the gate of the transistor is connected to the word line, one of the drain and the source is connected to the bit line, and the other of the drain and the source is connected to the word line.
  • the first electrode of the capacitor is connected, the first electrode extends along a first direction, the word line extends along the second direction, and the bit line extends along a third direction.
  • a second aspect of the present disclosure provides a capacitor including:
  • a first electrode is located on the substrate, the first electrode extends in a first direction parallel to the substrate, and the size of the first electrode in the first direction is larger than that of the first electrode in the second direction. , and the size in the third direction, the first direction, the second direction and the third direction are perpendicular to each other;
  • the second electrode is coated on the surface of the dielectric layer.
  • a plurality of first electrodes arranged at intervals along the second direction and/or along the third direction, with a three-dimensional space between adjacent first electrodes;
  • the dielectric layer covers the surfaces of the plurality of first electrodes and is located in the three-dimensional space to form a common dielectric layer;
  • the second electrode is coated on the surface of the dielectric layer and located in the three-dimensional space to form a common second electrode.
  • a third aspect of the present disclosure provides a memory including:
  • a wrap-around gate transistor the gate of the transistor is connected to the word line, one of the drain and the source is connected to the bit line, and the other of the drain and the source is connected to the capacitor, wherein the capacitor Extending along the first direction, the word line extends along the second direction, and the bit line extends along the third direction.
  • capacitor and memory of the present disclosure by arranging the first electrode in a first direction parallel to the substrate, and the size of the first electrode in the transverse direction is larger than its size in the longitudinal direction, so that the first electrode, The dielectric layer and the second electrode form a horizontally arranged capacitor, so that more capacitors can be arranged in a three-dimensional space, thereby increasing the storage capacity of the memory.
  • the capacitor structure provided by the present disclosure can be adapted to wrap-around gate transistors, which greatly expands the integration space of the memory.
  • FIG. 1 is a flow chart of a method of manufacturing a capacitor according to an exemplary embodiment.
  • FIG. 2 is a schematic diagram of a single-layer capacitor placed horizontally according to an exemplary embodiment.
  • FIG. 3 is a schematic diagram of multilayer capacitors arranged in a vertical direction according to an exemplary embodiment.
  • FIG. 4 is a top view of FIG. 2 .
  • FIG. 5 is a cross-sectional view of the epitaxial layer formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the A-A section in FIG. 4 .
  • FIG. 6 is a cross-sectional view of the epitaxial layer formed by the method for manufacturing a capacitor according to an exemplary embodiment, taken along the B-B section in FIG. 4 .
  • FIG. 7 is a top view of a first mask pattern formed in a method of manufacturing a capacitor according to an exemplary embodiment.
  • FIG. 8 is a cross-sectional view of the first mask layer formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the A-A section in FIG. 4 .
  • FIG. 9 is a cross-sectional view of the first mask pattern formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the B-B section in FIG. 4 .
  • FIG. 10 is a cross-sectional view of the groove formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the A-A section in FIG. 4 .
  • FIG. 11 is a cross-sectional view of the groove formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the B-B section in FIG. 4 .
  • FIG. 12 is a cross-sectional view of the gap formed in the manufacturing method of the capacitor according to an exemplary embodiment, taken along the A-A section in FIG. 4 .
  • FIG. 13 is a cross-sectional view of the gap formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the B-B section in FIG. 4 .
  • FIG. 14 is a cross-sectional view of the first electrode material formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the A-A section in FIG. 4 .
  • FIG. 15 is a cross-sectional view of the first electrode material formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the B-B section in FIG. 4 .
  • FIG. 16 is a cross-sectional view of the first electrode formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the A-A section in FIG. 4 .
  • FIG. 17 is a cross-sectional view of the first electrode formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the B-B section in FIG. 4 .
  • FIG. 18 is a top view of a second mask pattern formed in a method of manufacturing a capacitor according to an exemplary embodiment.
  • FIG. 19 is a cross-sectional view of the support material formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the A-A section in FIG. 4 .
  • FIG. 20 is a cross-sectional view of the support material and the second mask layer formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the B-B section in FIG. 4 .
  • FIG. 21 is a cross-sectional view of the A-A section in FIG. 4 after removing part of the support material in a method for manufacturing a capacitor according to an exemplary embodiment.
  • FIG. 22 is a cross-sectional view of the B-B section in FIG. 4 after removing part of the supporting material in a method for manufacturing a capacitor according to an exemplary embodiment.
  • FIG. 23 is a cross-sectional view of the A-A section in FIG. 4 after removing the silicon-containing material layer in the pattern area in a method for manufacturing a capacitor according to an exemplary embodiment.
  • FIG. 24 is a cross-sectional view of the B-B section in FIG. 4 after removing the silicon-containing material layer in the pattern area in a method for manufacturing a capacitor according to an exemplary embodiment.
  • FIG. 25 is a cross-sectional view of the support structure formed after removing the top height support material in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the A-A section in FIG. 4 .
  • FIG. 26 is a cross-sectional view of the support structure formed after removing the top surface height support material in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the B-B section in FIG. 4 .
  • FIG. 27 is a cross-sectional view of the dielectric layer formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the A-A section in FIG. 4 .
  • FIG. 28 is a cross-sectional view of the dielectric layer formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the B-B section in FIG. 4 .
  • FIG. 29 is a cross-sectional view of the second electrode formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the A-A section in FIG. 4 .
  • FIG. 30 is a cross-sectional view of the second electrode formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the B-B section in FIG. 4 .
  • FIG. 31 is a cross-sectional view of the external circuit formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the A-A section in FIG. 4 .
  • FIG. 32 is a cross-sectional view of the external circuit formed in the method of manufacturing a capacitor according to an exemplary embodiment, taken along the B-B section in FIG. 4 .
  • Support structure 120. Support structure; 130. Support material;
  • Second mask layer 141. Second mask pattern
  • Conductive layer 170. Array opening;
  • Exemplary embodiments of the present disclosure provide a method for manufacturing a semiconductor structure.
  • the method for manufacturing a semiconductor structure will be introduced below with reference to FIGS. 1 to 30 .
  • This embodiment does not limit the semiconductor structure.
  • the following introduction will take the semiconductor structure as a capacitor in a dynamic random access memory (DRAM) as an example.
  • DRAM dynamic random access memory
  • this embodiment is not limited to this.
  • the semiconductor structure in this embodiment can also be a capacitor in a dynamic random access memory (DRAM). other structures.
  • an exemplary embodiment of the present disclosure provides a method for manufacturing a capacitor, which includes the following steps:
  • Step S100 Provide a substrate.
  • Step S200 Form a first electrode on the substrate.
  • the first electrode extends in a first direction parallel to the substrate.
  • the size of the first electrode in the first direction is larger than the size of the first electrode in the second direction and in the third direction.
  • Dimensions: the first direction, the second direction and the third direction are perpendicular to each other.
  • Step S300 Form a dielectric layer covering the first electrode.
  • Step S400 Form a second electrode covering the dielectric layer.
  • the substrate 10 serves as a supporting component of the dynamic random access memory and is used to support other components provided on it.
  • the substrate 10 can be provided with a word line structure, a bit line structure, an isolation structure, an active District and other structures.
  • the substrate 10 may be made of a semiconductor material, and the semiconductor material may be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.
  • a direction parallel to the top surface of the substrate 10 is defined as the first direction X.
  • the first direction X may be the length direction of the first electrode 20; definition Let the direction parallel to the top surface of the substrate 10 and perpendicular to the first direction X be the second direction Y.
  • the second direction Y may be the width direction of the first electrode 20, and the second direction is also parallel to the top surface of the substrate 10;
  • the extending direction perpendicular to the top surface of the substrate 10 is defined as a third direction Z (the third direction Z may be a vertical direction), and the third direction Z may be the thickness direction of the first electrode 20 .
  • a first electrode 20 may be formed on the substrate 10 using a deposition process.
  • the material of the first electrode 20 may include, but is not limited to, polysilicon, metal tungsten, titanium nitride, etc.
  • the first electrode 20 extends along the first direction X parallel to the substrate 10 , which can define the capacitance length of a single capacitor.
  • the size of the first electrode 20 in the first direction The dimension on Y, the first direction X and the second direction Y are perpendicular to each other.
  • the size of the first electrode 20 in the first direction for example, 35 to 220, for example, 36:1 or 80:1 or 100:1 or 150:1 or 200:1.
  • the aspect ratio of the first electrode 20 is less than 35, the length of the first electrode 20 of the capacitor 10A If it is too small, the storage capacity of the capacitor is insufficient.
  • the aspect ratio of the first electrode is too high, for example, when it is greater than 220, the preparation of the capacitor 10A is difficult and the performance is unstable. Using parameter values within the above range can increase the storage capacity of the capacitor 10A and ensure the performance of the capacitor 10A is stable and reliable.
  • the first direction X and the third direction Z are perpendicular to each other.
  • the second direction Y and the third direction Z are also perpendicular to each other. perpendicular to each other.
  • the material of the dielectric layer 30 may include but is not limited to high-K materials.
  • the high-K material can be, for example, one or a combination of zirconium oxide (ZrOx), hafnium oxide (HfOx), zirconium titanium oxide (ZrTiOx), ruthenium oxide (RuOx), aluminum oxide (AlOx), that is to say,
  • the material of the dielectric layer may be one of the above materials, or a combination or mixture of the above materials.
  • the material of the dielectric layer 30 uses a high-K material, which is beneficial to improving the capacitance value of the subsequent unit area capacitor, increasing the charge storage capacity of the subsequently formed capacitor, and improving the performance of the semiconductor structure.
  • step S400 taking the example shown in FIG. 2 as an example, part of the second electrode 40 is coated on the outer surface of the dielectric layer 30 along the first direction X, and part of the second electrode 40 is disposed along the third direction Z.
  • the material of the second electrode 40 may include, but is not limited to, polysilicon, metal tungsten, titanium nitride, etc.
  • the deposition process in this embodiment and below may include but is not limited to an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, etc.
  • the length dimension of the first electrode is greater than the width dimension and thickness dimension of the first electrode, thereby forming a horizontally placed first electrode, so as to cooperate with the dielectric layer and the second electrode to form a horizontally placed first electrode.
  • capacitors so that more capacitors can be arranged in three-dimensional space, thereby increasing the storage capacity of the memory.
  • two capacitors 10A on the same horizontal line are arranged opposite each other, and are respectively connected to two oppositely arranged gate-all-around (GAA) transistors.
  • the source S or the drain D of the transistor 150 share the same bit line 152 and are on the same horizontal line, which can further improve the integration of the memory per unit area.
  • two opposite transistors 150 are provided in the active area 10B, where the active area 10B is located between two horizontally placed capacitors 10A.
  • this embodiment includes the method in the above embodiment, which will not be described again.
  • the difference from the above embodiment is that the process of forming the first electrode 20 on the substrate 10 includes:
  • a plurality of first electrodes 20 are formed at intervals along the second direction Y and/or along the third direction Z, and there is a three-dimensional space between two adjacent first electrodes 20 .
  • the dielectric layer 30 formed in step S300 of the above embodiment covers the surfaces of the plurality of first electrodes 20, and the dielectric layer 30 is located in a three-dimensional space, thereby forming a common dielectric layer 30.
  • the second electrode 40 formed in step S400 of the above embodiment is coated on the surface of the dielectric layer 30 and located in the three-dimensional space to form a common second electrode 40 .
  • the plurality of first electrodes 20 can be arranged in a rectangular array to form a three-dimensional structure.
  • the dielectric layer 30 and the second electrode 40 in the three-dimensional structure are both common, and the number of the dielectric layer 30 and the second electrode 40 is one. That is, the plurality of first electrodes 20 arranged in an array pass through one dielectric.
  • the electrical layer 30 is connected, and the outer surface of the dielectric layer 30 covers the second electrode 40.
  • the second electrode 40 is a whole. Taking the example shown in FIG. 3 as an example, part of the second electrode 40 is covered along the first direction X. On the outer surface of the dielectric layer 30, part of the second electrode 40 is arranged along the third direction Z. Thereby reducing the process difficulty and process cost of the capacitor.
  • a plurality of first electrodes are arranged in a rectangular array along the length direction and share a dielectric layer and a second electrode, thereby forming a three-dimensional structure capacitor.
  • the three-dimensional structure capacitor can be in its width. The expansion in the direction and thickness direction allows more horizontally placed capacitors to be arranged in the storage space per unit area, effectively improving the integration and storage capacity of the memory.
  • this embodiment is a further explanation of step S200 above.
  • At least one epitaxial layer 50 is formed on the substrate 10 using a deposition process.
  • the epitaxial layer 50 includes alternately arranged single crystal silicon layers 51 and silicon-containing material layers 52, wherein the size of the single crystal silicon layer 51 in the first direction X is larger than that of the single crystal silicon layer 51 in the second direction Y and the third direction Y. Dimensions in direction Z.
  • the material of the silicon-containing material layer 52 may include but is not limited to silicon germanium (SiGe), which has etching selectivity with the single crystal silicon layer 51 .
  • the number of epitaxial layers 50 may be one layer or multiple layers, such as two layers, three layers, four layers, etc.
  • a horizontally placed capacitor 10A may be formed, or a plurality of capacitors 10A spaced apart along the second direction Y may be formed.
  • a plurality of horizontally placed capacitors arranged along the second direction Y share a dielectric layer 30 and a second electrode 40, that is, a two-dimensional capacitor 10A arranged along the second direction Y can be formed.
  • a three-dimensional structure and horizontally placed capacitor can be formed.
  • multiple layers of first electrodes 20 can be provided at intervals along the third direction Z, thereby effectively increasing the capacitor unit. area storage capacity and integration.
  • a pattern area 60 and a contact area 70 are defined on the epitaxial layer 50 .
  • the single crystal silicon layer 51 at the contact region 70 can be used to form the source or drain region of the transistor, so as to facilitate the doping process of the source or drain region to form the source S or drain D of the transistor.
  • the source electrode S and the drain electrode D can be formed first, or the source electrode S and the drain electrode D can be formed at the same time as the capacitor 10A.
  • the epitaxial layer 50 is selectively etched downward in the pattern area 60 until the top surface of the substrate 10 is exposed.
  • the remaining epitaxial layer 50 in the pattern area 60 that has not been etched defines the position of the first electrode 20 , and the remaining epitaxial layer 50 in the pattern area 60 extends laterally, that is, along the first direction X.
  • the position of the single crystal silicon layer 51 in the remaining epitaxial layer 50 is the reserved position for the first electrode 20, that is, the pattern area
  • the original position of the single crystal silicon layer 51 is used to form the first electrode 20 .
  • an etching process is used to remove the single crystal silicon layer 51 in the remaining epitaxial layer 50 to form a gap 80 .
  • a deposition process is used to form the first electrode 20 in the gap 80 .
  • the number of columns of capacitors is defined in the third direction Z, for example, three epitaxial layers 50 are provided on the substrate, that is, in the third direction Z Z forms three layers of space for placing the capacitor 10A.
  • Etching is selectively performed in the second direction Y, and the number of rows of capacitors is defined in the second direction Y.
  • the remaining two epitaxial layers 50 arranged side by side in the pattern area 60 after etching are along the second direction.
  • Y intervals are provided, that is, two layers of space for placing the capacitor 10A are formed along the second direction Y. That is to say, at this time, as shown in FIGS. 16 and 17 , six first electrodes 20 arranged in an array can be formed.
  • the remaining epitaxial layer in the pattern area is used to define the formation position of the first electrode, and the single crystal silicon layer between any two adjacent silicon-containing material layers in the contact area is used to form the source area or Drain region, so that in the process of forming the first electrode, the first electrode is connected to the source or drain of the transistor.
  • the pattern area 60 and the contact area 70 may be formed using the following methods:
  • a first mask layer 90 is formed on the top surface of the epitaxial layer 50 using a deposition process.
  • the first mask layer 90 is patterned to form a first mask pattern 100 on the first mask layer 90 .
  • the epitaxial layer 50 is etched downward through an etching process until the top surface of the substrate 10 is exposed, thereby simultaneously defining the pattern area 60 and the contact area.
  • the formation positions of the region 70 and the first electrode 20 are as shown in FIG. 7 .
  • the first mask pattern on the first mask layer can be used to simultaneously define the formation positions of the pattern area, the contact area and the first electrode, which effectively reduces the difficulty of the manufacturing process of the capacitor and saves the cost of manufacturing the capacitor. cost.
  • a groove 61 is formed in the pattern area 60 .
  • the first electrode material 110 is deposited in the groove 61 of the pattern area 60 , and the first electrode material 110 fills the groove 61 and the gap 80 of the pattern area 60 .
  • the first electrode material 110 extends outside the pattern area 60 and covers the top surface of the epitaxial layer 50 located in the contact area 70 .
  • the first electrode material 110 may include but is not limited to polysilicon, metal tungsten, titanium nitride, etc.
  • a self-alignment process and a maskless etching process are used to remove the first electrode material 110 in the groove 61 and the top surface of the epitaxial layer 50 covering the contact area 70 .
  • the first electrode material 110 is retained in the gap 80 to form the first electrode 20 .
  • the first electrode material is used to fill the grooves and gaps, while the first electrode material also covers the top surface of the contact area, and then maskless etching is used to remove the first electrode material on the top surface of the groove and contact area.
  • the first electrode material remaining in the gap forms the first electrode.
  • the first electrode is realized through self-alignment process technology, which can avoid position deviation and ensure accurate removal of the first electrode material on the top surface of the groove and contact area, improving the performance and reliability of the capacitor.
  • the following methods may be used to form the first electrode 20 in the gap 80:
  • the first conductive material 110 is deposited in the groove 61 using a deposition process with reference to FIGS. 14 and 15 .
  • the first electrode material 110 fills the gap 80 between the groove 61 and the remaining silicon-containing material layer 52 in the pattern area 60 , wherein the first electrode material 110 extends outside the groove 61 and covers the epitaxial layer located in the contact area 70 50 tops.
  • the first electrode material 110 can be formed using an atomic layer deposition process and a chemical vapor deposition process.
  • an atomic layer deposition process is first used to deposit a layer of first electrode material 110 on the surface of groove 61 and gap 80 , for example, a chemical vapor deposition process is used to further deposit the first electrode material 110 , so that the first electrode material is completely filled. Groove 61 and gap 80.
  • the first electrode material 110 can be deposited on the surface of groove 61 and gap 80 through an atomic layer deposition process until the gap 80 is completely filled, and then chemical vapor phase is used. The deposition process fills the remaining part.
  • the atomic layer deposition process and the chemical vapor deposition process are used to form a larger length and a more uniform and dense first electrode 20, thereby effectively adapting to the high aspect ratio of the first electrode 20.
  • an atomic layer deposition process is used to deposit the first electrode material 110 on the top of the groove 61 to a predetermined height.
  • the predetermined height may be the height of the first silicon-containing material layer 52 in the groove 61 from bottom to top.
  • the chemical vapor deposition process is then used to continue to deposit the first electrode material 110 in the remaining grooves 61, and then the atomic layer deposition process is used to continue to deposit the first electrode material 110.
  • the atomic layer deposition process and the atomic layer deposition process are alternately used.
  • the chemical vapor deposition process is performed until the first electrode material 110 covers the top surface of the epitaxial layer 50 located in the contact region 70 .
  • the atomic layer deposition process has the characteristics of slow deposition speed, high density of the deposited film layer, and good step coverage. Using the atomic layer deposition process to form the first electrode material 110 can cover the bottom of the groove 61 or the gap 80 in a small space, avoid problems such as holes, effectively ensure the formation quality of the first electrode material 110, and thereby improve Performance and yield of the first electrode 20 .
  • a self-alignment process and a maskless etching process are used to remove the first electrode material layer 110 in the groove 61 and the epitaxial layer located in the contact area 70 .
  • the first electrode material 110 on the top surface of the layer 50 and the first electrode material 110 in the gap 80 are retained to form the first electrode 20 .
  • the first electrode material is formed using an atomic layer deposition process and a chemical vapor deposition process. While ensuring the formation quality of the first electrode material, it can also effectively increase the aspect ratio of the first electrode, thereby increasing the storage capacity of the capacitor. and integration.
  • the manufacturing method of the capacitor further includes: forming a support structure 120 on the side wall of the first electrode 20 .
  • the support structure 120 can be formed by the following methods:
  • a support material 130 is deposited in the groove 61 of the pattern area 60 using a deposition process.
  • the support material 130 extends outside the groove 61 and covers the top surface of the contact area 70 . It should be noted that in the step of forming the first electrode 20 , the groove formed in the pattern area 60 after the first electrode material 110 is removed is consistent with the structure of the groove 61 formed in the previous step.
  • a deposition process is used to form a patterned second mask layer 140 on the surface of the support material 130 .
  • the edge of the patterned second mask layer 140 also covers the surface of the support material 130 located in the contact area 70 , and at the same time, the patterned second mask layer 140 also forms an array arrangement on the pattern area 60 .
  • the patterned second mask layer 140 forms a second mask pattern 141 with a middle opening and closed edge positions on the support material 130 , and a plurality of mask pillars 142 arranged in an array are formed on the pattern area 60 .
  • the projected area of the second mask pattern 141 on the substrate 10 is larger than the projected area of the contact area 70 on the substrate 10 , wherein the outer edge of the second mask pattern 141 is flush with the outer edge of the contact area 70 , so that in the contact area
  • the sidewalls of the epitaxial layer 50 that are retained within 70 form the support material 130, which is subsequently used to form the support structure 120 (refer to FIG. 25).
  • the same number of mask pillars 142 as the number of rows of the first electrodes 20 are provided to support the first electrodes 20 in each row. For example, with reference to the embodiments of FIGS. 1, 6 and 17, it is in the Two rows of first electrodes 20 are arranged in the two directions Y.
  • two corresponding mask pillars 142 can be arranged directly above the first electrodes 20, wherein, in the second direction Y, the mask pillars 142 are on the substrate.
  • the projected width on 10 is larger than the width of the first electrode 20 to facilitate the subsequent formation of support structures 120 on both sides of the first electrode 20 and improve the structural stability of multiple first electrodes 20 arranged vertically.
  • the support material 130 is etched downward using the patterned second mask layer 140 as a mask to expose the epitaxial layer 50 , thereby forming an array opening 170 on the pattern area 60 .
  • the support material 130 is etched downward along the array opening 170 until the top surface of the substrate 10 is exposed.
  • a wet etching process is used to remove the remaining silicon-containing material layer 52 in the epitaxial layer 50 at the pattern area 60 .
  • the wet etching process can cleanly remove the remaining silicon-containing material layer 52 without causing damage to the first electrode 20 and the remaining supporting material 130, thereby ensuring the performance of the capacitor.
  • a vapor etching process is used to remove the remaining silicon-containing material layer 52 in the epitaxial layer 50 at the pattern area 60 .
  • HCl vapor can be used as the etching steam, and the etching time is 5 to 60 seconds, thereby quickly removing the silicon-containing material layer 52 .
  • an etching process is used to remove the support material 130 at the top surface, exposing the top surface of the contact area 70 , and opening the top of the support material 130 located on both sides of the first electrode 20 , so that the support material 130 remaining on the sidewalls of the first electrode 20 and the sidewalls of the contact area 70 jointly form the support structure 120 .
  • a three-dimensional space is formed between the multiple layers of first electrodes 20 .
  • a support structure is used to provide side wall support and protection for multiple first electrodes 20 located in the same column (that is, arranged along the same vertical direction), so that more first electrodes can be arranged in the vertical direction. It increases the possibility of capacitor expansion in the vertical direction, effectively improving the integration of capacitors per unit space area.
  • this embodiment is a further explanation of step S300 above.
  • Dielectric layer 30 is formed using an atomic layer deposition process.
  • the formed dielectric layer 30 continuously covers the outer surface of the first electrode 20 .
  • the dielectric layer 30 covers the outer surface of one first electrode 20 , and at the same time, the dielectric layer 30 also covers the outer surface of the support structure 120 .
  • the dielectric layer 30 continuously covers the outer surfaces of the multiple first electrodes 20 and the outer surface of the support structure 120, thereby forming a common Dielectric layer 30.
  • the dielectric layer is formed using an atomic layer deposition process.
  • the atomic layer deposition process has the characteristics of slow deposition speed, high density of the deposited film layer, and good step coverage.
  • the dielectric layer formed by the atomic layer deposition process can cover the outer surface of the first electrode and the support structure in a small space, avoiding occupying a large space, effectively ensuring the formation quality of the dielectric layer, and thereby improving the capacitor performance and yield.
  • this embodiment is a further explanation of step S400 above.
  • the second electrode 40 is formed using an atomic layer deposition process.
  • the formed second electrode 40 is continuously coated on the outer surface of the dielectric layer 30 and is shared by a plurality of horizontally arranged capacitors 10A.
  • the second electrode is formed using an atomic layer deposition process.
  • the atomic layer deposition process has the characteristics of slow deposition speed, high density of the deposited film layer, and good step coverage.
  • the second electrode formed by the atomic layer deposition process can cover the outer surface of the dielectric layer in a small space, avoid occupying a large space, effectively ensure the formation quality of the second electrode, and thereby improve the performance and quality of the capacitor. Rate.
  • the first electrode 20 in the capacitor 10A formed using the above-mentioned capacitor manufacturing method has an aspect ratio between the first direction X and the third direction Z.
  • the preset aspect ratio The ratio is greater than or equal to 35.
  • the first electrode 20 with an aspect ratio greater than or equal to 35 can effectively increase the storage capacity of the horizontally arranged capacitor 10A.
  • a plurality of first electrodes 20 arranged in a rectangular array can be arranged.
  • One electrode 20 shares a dielectric layer 30 and a second electrode 40, thereby effectively improving the integration level of the capacitor while reducing the manufacturing process difficulty of the capacitor.
  • a memory structure including horizontally arranged capacitors is shown, in which the schematic diagram of the support structure is omitted.
  • the capacitors arranged horizontally are used to connect the gate-all-around (GAA) transistor 150 .
  • the gate of the transistor 150 is connected to the word line 151
  • the drain D of the transistor 150 is connected to the bit line 152
  • the source S is connected to the first electrode 20 of the capacitor 10A; or, the source S of the transistor 150 is connected to the bit line 152, and its source S is connected to the bit line 152.
  • the drain D is connected to the first electrode 20 of the capacitor 10A.
  • the first electrode 20 extends along the first direction X
  • the word line 151 extends along the second direction Y
  • the bit line 152 extends along the third direction Z.
  • the structure of the memory in the embodiment of the present disclosure is based on the capacitor 10A and the GAA transistor 150, which can further save space. Furthermore, when forming a three-dimensional structure, the space is expanded upward again, which greatly contributes to improving the high integration level of DRAM. s help.
  • two capacitors 10A on the same horizontal line are arranged opposite each other, and the two capacitors 10A are arranged horizontally.
  • the two capacitors 10A are respectively connected to the sources S of two oppositely arranged transistors 150. Or the drain D, the two transistors 150 can share a bit line 152 and be on the same horizontal line to improve the integration of the memory per unit area.
  • two capacitors 10A arranged horizontally and on the same horizontal line are arranged opposite each other, and are respectively connected to the source S or drain D of two oppositely arranged transistors 150 on the same horizontal line.
  • the two transistors 150 Sharing a bit line 152.
  • a plurality of bit lines 152 are arranged at intervals, and are respectively connected to a plurality of columns of spaced-apart transistors 150, thereby forming a three-dimensional structure of memory, increasing the possibility of expansion of the memory in the vertical direction. , which improves the integration of memory per unit space area.
  • an exemplary embodiment of the present disclosure provides a capacitor 10A, including a substrate 10 , a first electrode 20 , a dielectric layer 30 and a second electrode 40 .
  • the first electrode 20 is disposed on the substrate 10 , and the first electrode 10 extends along the first direction X parallel to the substrate 10 .
  • the size of the first electrode 20 in the first direction X is larger than the size of the first electrode 20 in the second direction Y.
  • the first direction X and the second direction Y are perpendicular to each other.
  • the size of the first electrode 20 in the first direction X is also larger than the size of the first electrode 20 in the third direction Z.
  • the first direction X and the third direction Z are perpendicular to each other.
  • the second direction Y and the third direction Z Also perpendicular to each other.
  • the dielectric layer 30 covers the surface of the first electrode 20 .
  • the second electrode 40 covers the surface of the dielectric layer 30 .
  • the first electrode, the dielectric layer and the second electrode form a capacitor, wherein the length dimension of the first electrode is greater than the width dimension and thickness dimension of the first electrode, thereby forming a horizontally placed capacitor, so as to facilitate More capacitors can be arranged in the three-dimensional space, thereby increasing the storage capacity of the memory.
  • the capacitor 10A has a three-dimensional structure, and the three-dimensional structure capacitor 10A includes a plurality of first electrodes 20 , a dielectric layer 30 and a second electrode 40 .
  • the plurality of first electrodes 20 are arranged at intervals, and there is a three-dimensional space between adjacent first electrodes 20 .
  • the plurality of first electrodes 20 may be arranged at intervals along the second direction Y.
  • the plurality of first electrodes 20 may be arranged at intervals along the third direction Z.
  • the plurality of first electrodes 20 are arranged in a rectangular array at intervals along the second direction Y and the third direction Z.
  • the dielectric layer 30 is located in the three-dimensional space and covers the surfaces of the plurality of first electrodes 20 to form a dielectric layer 30 common to the plurality of first electrodes 20 .
  • the second electrode 40 is located in the three-dimensional space and covers the surfaces of the plurality of dielectric layers 30 to form the second electrode 40 shared by the plurality of first electrodes 20 .
  • a plurality of first electrodes are arranged in a rectangular array along the length direction and share a dielectric layer and a second electrode, thereby forming a three-dimensional structure capacitor.
  • the three-dimensional structure capacitor can be used in the second The expansion in the first and third directions allows more horizontally placed capacitors to be arranged in the storage space per unit area, effectively improving the integration and storage capacity of the final memory.
  • a buffer layer 190 is provided on the surface of the second electrode 40 of the capacitor 10A, and an isolation layer is provided on the buffer layer 190 Material 180.
  • the material of the buffer layer 190 may include but is not limited to polysilicon.
  • the capacitor 10A or the three-dimensional structure capacitor 10A of this embodiment also includes an external circuit 160 .
  • the external circuit 160 is used to electrically connect the capacitor 10A to the control circuit in the peripheral circuit area of the memory.
  • the external circuit 160 includes a contact layer 161 and a conductive layer 162.
  • the contact layer 161 half-wrapped the conductive layer 162.
  • the contact layer 161 is embedded in the isolation material 180 , and the bottom of the contact layer 161 extends into the buffer layer 190 and is connected to the buffer layer 190 . Wherein, the contact layer 161 is spaced apart from the second electrode 40 .
  • an exemplary embodiment of the present disclosure provides a memory.
  • the memory includes the capacitor 10A and the wraparound gate transistor 150 in the above embodiment.
  • the structure of the memory in the embodiment of the present disclosure is based on the capacitor 10A and the GAA transistor 150, which can further save space. Furthermore, when forming a three-dimensional structure, the space is expanded upward again, which greatly contributes to improving the high integration level of DRAM. s help.
  • the gate of the transistor 150 is connected to the word line 151, one of the drain D and the source S of the transistor 150 is connected to the bit line 152, and the other of the source S and drain D of the transistor 150 is used to connect the capacitor.
  • 10A first electrode 20 The first electrode 20 extends along the first direction X, the word line 151 extends along the second direction Y, and the bit line 152 extends along the third direction Z.
  • two opposite transistors 150 arranged horizontally and on the same horizontal line share a bit line 152 , and a horizontally arranged capacitor 10A is connected to the outer connection of each transistor 150 .
  • a plurality of word lines 151 are arranged at intervals, and are respectively connected to a plurality of columns of spaced-apart transistors 150, thus forming a three-dimensional structure memory, which increases the possibility of expansion of the memory in the vertical direction. The integration of memory per unit space area is improved.
  • the first electrode extends in a first direction parallel to the substrate, and the lateral size of the first electrode is larger than its vertical size, so that the first electrode, dielectric
  • the layer and the second electrode form a horizontally arranged capacitor, so that more capacitors can be arranged in a three-dimensional space, thereby increasing the storage capacity of the memory.

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Abstract

本公开公布了一种电容器的制作方法、电容器以及存储器，涉及半导体技术领域。该电容器的制作方法包括：提供基底；于基底上形成第一电极，第一电极沿平行于基底的第一方向延伸，第一电极在第一方向上的尺寸大于第一电极在第二方向上，以及在第三方向上的尺寸，第一方向、第二方向以及第三方向之间两两相互垂直；形成包覆第一电极的介电层；形成包覆介电层的第二电极。

Description

电容器的制作方法、电容器以及存储器
本公开基于申请号为202210462602.3，申请日为2022年04月29日，申请名称为“电容器的制作方法、电容器以及存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及一种电容器的制作方法、电容器以及存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管。随着半导体技术的发展，半导体器件的尺寸越来越小，对半导体制造技术的要求也在不断提高。
而现有的存储器的存储密度在横向扩展已经遇到瓶颈，因此，如何提高存储器的存储密度和性能是亟需解决的技术问题。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种电容器的制作方法、电容器以及存储器。
本公开的第一方面提供了一种电容器的制作方法，所述电容器的制作方法包括：
提供基底；
于所述基底上形成第一电极，所述第一电极沿平行于所述基底的第一方向延伸，所述第一电极在所述第一方向上的尺寸大于所述第一电极在第二方向上，以及在第三方向上的尺寸，所述第一方向、所述第二方向以及所述第三方向之间两两相互垂直；
形成包覆所述第一电极的介电层；
形成包覆所述介电层的第二电极。
其中，所述电容器的制作方法还包括：
形成沿所述第二方向和/或沿所述第三方向间隔排列的多个第一电极，相邻所述第一电极之间具有立体空间；
所述介电层包覆在多个所述第一电极的表面以及位于所述立体空间内，形成共用的介电层；
所述第二电极包覆在所述介电层的表面以及位于所述立体空间内，形成共用的第二电极。
其中，于所述基底上形成第一电极，包括：
于所述基底上形成至少一层外延层，所述外延层包括交叠布置的单晶硅层和含硅材料层，所述单晶硅层在所述第一方向尺寸均大于在第二方向上和在第三方向上的尺寸；
于所述外延层上定义出图形区和接触区，其中，所述接触区处的所述单晶硅层形成晶体管的源或漏区；
在所述图形区处，选择性地向下刻蚀所述外延层，至暴露所述基底，所述图形区处剩余的所述外延层定义出所述第一电极的位置，并沿横向延伸，其中，剩余的所述单晶硅层为所述第一电极预留间隙；
在所述图形区处，去除剩余的所述外延层中所述单晶硅层，形成所述间隙；
在所述间隙中形成所述第一电极。
其中，于外延层形成图案化的第一掩膜层，并以所述图案化的第一掩膜层为掩膜向下刻蚀所述外延层，至暴露所述基底，以同步定义出所述图形区、所述接触区，以及所述第一电极的位置。
其中，在所述间隙中形成所述第一电极，包括：
于所述图形区内沉积第一电极材料，所述第一电极材料填充满所述图形区的凹槽和所述间隙，所述第一电极材料延伸至所述图形区外并覆盖所述接触区的顶面；
利用无掩膜刻蚀去除所述凹槽内和所述接触区顶面的所述第一电极材料，于所述间隙中被保留下来的所述第一电极材料形成所述第一电极。
其中，使用原子层沉积工艺和化学气相沉积工艺共同形成所述第一电极材料。
其中，在所述间隙中形成第一电极之后，所述电容器的制作方法还包括：于所述第一电极的侧壁形成支撑结构；于所述第一电极的侧壁形成所述支撑结构，包括：
于所述图形区内沉积支撑材料，所述支撑材料延伸至所述图形区外并覆盖所述接触区的顶面；
于所述支撑材料表面形成图案化的第二掩膜层，所述图案化的第二掩膜层覆盖所述接触区的表面，且图案化的第二掩膜层还在所述图形区上形成阵列排布；
于所述图案化的所述第二掩膜层为掩膜向下刻蚀所述支撑材料，至暴露所述外延层，以在所述图形区上形成阵列开口；
沿所述阵列开口，继续向下刻蚀所述支撑材料，直至暴露所述基底；
去除顶面高度的支撑材料，以使所述支撑材料位于所述第一电极的侧壁和所述接触区的侧壁，形成所述支撑结构。
其中，在形成多个第一下电极时，还包括：
在所述图形区处，采用湿法刻蚀工艺或蒸汽刻蚀工艺去除剩余的所述外延层中所述含硅材料层，以形成所述立体空间。
其中，形成包覆所述第一电极的介电层，包括：
利用原子层沉积工艺形成介电层，所述介电层连续包覆在所述第一电极的外表面。
其中，形成包覆所述介电层的第二电极层，包括：
利用原子层沉积工艺形成所述第二电极层，所述第二电极层连续包覆所述介电层的外表面。
其中，所述第一电极在第一方向和在所述第三方向之间具有横纵比，所述横纵比大于等于35。
其中，所述电容器用于连接环绕式栅极型晶体管，其中，所述晶体管的栅极连接字线，漏极和源极之一连接位线，所述漏极和所述源极之另一连接所述电容器的所述第一电极，所述第一电极沿第一方向延伸，所述字线沿所述第二方向延伸，所述位线沿第三方向延伸。
本公开的第二方面提供了一种电容器，包括：
基底；
第一电极，位于所述基底上，所述第一电极沿平行于基底的第一方向延伸，所述第一电极在所述第一方向上的尺寸大于所述第一电极在第二方向上，以及在第三方向上的尺寸，所述第一方向、所述第二方向以及所述第三方向之间两两相互垂直；
介电层，包覆在所述第一电极的表面；
第二电极，包覆在所述介电层的表面。
其中，其包括：
沿第二方向和/或沿第三方向间隔排列的多个第一电极，相邻所述第一电极之间具有立体空间；
所述介电层包覆在多个所述第一电极的表面以及位于所述立体空间内，形成共用的介电层；
所述第二电极包覆在所述介电层的表面以及位于所述立体空间内，形成共用的第二电极。
本公开的第三方面提供了一种存储器，包括：
上述第二方面的电容器；
环绕式栅极型晶体管，所述晶体管的栅极连接字线，漏极和源极之一连接位线，所述漏极和所述源极之另一连接所述电容器，其中，所述电容器沿第一方向延伸，所述字线沿所述第二方向延伸，所述位线沿第三方向延伸。
本公开的电容器的制作方法、电容器以及存储器中，通过将第一电极沿平行于基底的第一方向设置，并且第一电极沿横向方向的尺寸大于其沿纵向方向的尺寸，使得第一电极、介电层和第二电极形成一种水平设置的电容器，从而可以在立体空间内布置更多的电容器，进而提高存储器的存储容量。此外，本公开提供的电容器结构可以适应环绕式栅极型晶体管，极大地拓展了存储器的集成空间。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的电容器的制作方法的流程图。
图2是根据一示例性实施例示出的单层电容器水平放置的示意图。
图3是根据一示例性实施例示出的多层电容器沿竖向方向排布的示意图。
图4是图2的俯视图。
图5是根据一示例性实施例示出的电容器的制作方法中形成的外延层在图4中A-A截面的截面图。
图6是根据一示例性实施例示出的电容器的制作方法形成的外延层在图4中B-B截面的截面图。
图7是根据一示例性实施例示出的电容器的制作方法中形成的第一掩膜图案的俯视图。
图8是根据一示例性实施例示出的电容器的制作方法中形成的第一掩膜层在图4中A-A截面的截面图。
图9是根据一示例性实施例示出的电容器的制作方法中形成的第一掩膜图案在图4中B-B截面的截面图。
图10是根据一示例性实施例示出的电容器的制作方法中形成的凹槽在图4中A-A截面的截面图。
图11是根据一示例性实施例示出的电容器的制作方法中形成的凹槽在图4中B-B截面的截面图。
图12是根据一示例性实施例示出的电容器的制作方法中形成的间隙在图4中A-A截面的截面图。
图13是根据一示例性实施例示出的电容器的制作方法中形成的间隙在图4中B-B截面的截面图。
图14是根据一示例性实施例示出的电容器的制作方法中形成的第一电极材料在图4中A-A截面的截面图。
图15是根据一示例性实施例示出的电容器的制作方法中形成的第一电极材料在图4中B-B截面的截面图。
图16是根据一示例性实施例示出的电容器的制作方法中形成的第一电极在图4中A-A截面的截面图。
图17是根据一示例性实施例示出的电容器的制作方法中形成的第一电极在图4中B-B截面的截面图。
图18是根据一示例性实施例示出的电容器的制作方法中形成的第二掩膜图案的俯视图。
图19是根据一示例性实施例示出的电容器的制作方法中形成的支撑材料在图4中A-A截面的截面图。
图20是根据一示例性实施例示出的电容器的制作方法中形成的支撑材料和第二掩膜层在图4中B-B截面的截面图。
图21是根据一示例性实施例示出的电容器的制作方法中去除部分支撑材料后在图4中A-A截面的截面图。
图22是根据一示例性实施例示出的电容器的制作方法中去除部分支撑材料后在图4中B-B截面的截面图。
图23是根据一示例性实施例示出的电容器的制作方法中去除图形区含硅材料层后在图4中A-A截面的截面图。
图24是根据一示例性实施例示出的电容器的制作方法中去除图形区含硅材料层后在图4中B-B截面的截面图。
图25是根据一示例性实施例示出的电容器的制作方法中去除顶面高度支撑材料后形成的支撑结构在图4中A-A截面的截面图。
图26是根据一示例性实施例示出的电容器的制作方法中去除顶面高度支撑材料后形成的支撑结构在图4中B-B截面的截面图。
图27是根据一示例性实施例示出的电容器的制作方法中形成的介电层在图4中A-A截面的截面图。
图28是根据一示例性实施例示出的电容器的制作方法中形成的介电层在图4中B-B截面的截面图。
图29是根据一示例性实施例示出的电容器的制作方法中形成的第二电极在图4中A-A截面的截面图。
图30是根据一示例性实施例示出的电容器的制作方法中形成的第二电极在图4中B-B截面的截面图。
图31是根据一示例性实施例示出的电容器的制作方法中形成的外接电路在图4中A-A截面的截面图。
图32是根据一示例性实施例示出的电容器的制作方法中形成的外接电路在图4中B-B截面的截面图。
附图标记：
10、基底；20、第一电极；
30、介电层；40、第二电极；
50、外延层；51、单晶硅层；
52、含硅材料层；60、图形区；
61、凹槽；70、接触区；
80、间隙；90、第一掩膜层；
100、第一掩膜图案；110、第一电极材料；
120、支撑结构；130、支撑材料；
140、第二掩膜层；141、第二掩膜图案；
142、掩膜柱；150、晶体管；
151、字线；152、位线；
160、外接电路；161、接触层；
162、导电层；170、阵列开口；
180、隔离材料；190、缓冲层；
10A、电容器；10B、有源区；
S、源极；D、漏极。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开示例性的实施例中提供了一种半导体结构的制作方法，下面结合图1至图30对半导体结构的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)中的电容器为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图1所示，本公开一示例性的实施例提供了一种电容器的制作方法，包括如下的步骤：
步骤S100：提供基底。
步骤S200：于基底上形成第一电极，第一电极沿平行于基底的第一方向延伸，第一电极在第一方向上的尺寸大于第一电极在第二方向上，以及在第三方向上的尺寸，第一方向、第二方向以及第三方向之间两两相互垂直。
步骤S300：形成包覆第一电极的介电层。
步骤S400：形成包覆介电层的第二电极。
其中，在步骤S100中，基底10作为动态随机存储器的支撑部件，用于支撑设在其上的其他部件，比如，在基底10中可以设置有字线结构、位线结构、隔离结构、有源区等结构。其中，基底10可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。
在步骤S200中，以图2中示出的方向为例，定义以平行于基底10的顶面的一个方向为第一方向X，该第一方向X可以是第一电极20的长度方向；定义以平行于基底10的顶面且垂直于第一方向X的方向为第二方向Y，该第二方向Y可以是第一电极20的宽度方向，第二方向也平行于基底10的顶面；定义以垂直于基底10的顶面的延伸方向为第三方向Z(第三方向Z可以为竖向方向)，该第三方向Z可以是第一 电极20的厚度方向。
参照图2所示，在步骤S200中，可以利用沉积工艺在基底10上形成第一电极20。第一电极20的材料可以包括但不限于多晶硅、金属钨或氮化钛等。其中，第一电极20沿平行于基底10的第一方向X延伸设置，其可以定义出单个电容中电容长度，第一电极20在第一方向X上的尺寸大于第一电极20在第二方向Y上的尺寸，第一方向X与第二方向Y相互垂直。第一电极20在第一方向X上的尺寸也大于第一电极20在第三方向Z上的尺寸，也即，第一电极20具有高的横纵比，例如可以大于或等于35，进一步地，例如为35～220，例如为36：1或者80：1或者100：1或者150：1或者200：1，当第一电极20横纵比小于35时，电容器10A的第一电极20的长度偏小，电容器的存储容量不足，当第一电极横纵比过高时，例如大于220时，电容器10A的制备难度大，性能不稳定。采用上述范围内的参数值，可以提高电容器10A的存储容量，保证电容器10A的性能稳定可靠，其中，第一方向X与第三方向Z相互垂直，同时，第二方向Y与第三方向Z也相互垂直。
在步骤S300中，介电层30的材料可以包括但不限于高K材料。其中，高K材料例如可以为氧化锆(ZrOx)、氧化铪(HfOx)、氧化钛锆(ZrTiOx)、氧化钌(RuOx)、氧化铝(AlOx)中的一种或其组合，也就是说，介电层的材质可以为上述材料的一种，也可以是上述材料的组合物或混合物。在一个示例中，介电层30的材料使用高K材料，有利于提高后续单位面积的电容器的电容值，增加后续形成的电容器的电荷存储量，提高半导体结构的性能。
在步骤S400中，以图2所示为例，部分第二电极40沿第一方向X包覆在介电层30的外表面，部分第二电极40沿第三方向Z设置。其中，第二电极40的材料可以包括但不限于多晶硅、金属钨或氮化钛等。
需要说明的是，本实施例以及下文中的沉积工艺可以包括但不限于原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺等。
在本实施例中，第一电极的长度尺寸大于第一电极的宽度尺寸以及厚度尺寸，从而形成一种水平放置的第一电极，以便于配合介电层和第二电极形成一种水平放置的电容器，从而可以在立体空间内布置更多的电容器，进而提高存储器的存储容量。
参照图2和图4所示，电容器10A水平放置时，处于同一水平线上的两个电容器10A相对设置，并分别连接两个相对设置的环绕式栅极(Gate-All-Around，GAA)型晶体管150的源极S或漏极D，两个晶体管150共用同一条位线152并处于同一水平线上，可以进一步地提高单位面积的存储器的集成度。需要说明的是，在图4中，两个相对设置的晶体管150设置在有源区10B中，其中，有源区10B位于两个水平放置的电容器10A之间。
根据一个示例性实施例，如图3所示，本实施例包括上述实施例中的方法，在此不再赘述。与上述实施例的不同在于，在基底10上形成第一电极20的过程中，包括：
形成沿第二方向Y和/或沿第三方向Z间隔排列的多个第一电极20，相邻的两个第一电极20之间具有立体空间。其中，上述实施例步骤S300中形成的介电层30包覆在多个第一电极20的表面，且介电层30位于立体空间内，从而形成共用的介电层30。而在上述实施例步骤S400中形成的第二电极40包覆在介电层30的表面，并位于立体空间内，形成共用的第二电极40。
也就是说，多个第一电极20可以呈矩形阵列排布，形成三维结构。该三维结构中的介电层30和第二电极40均为共用的，且介电层30和第二电极40的个数均为一个，即阵列排布的多个第一电极20通过一个介电层30连接，介电层30的外表面包 覆第二电极40，第二电极40为一个整体，其中，以图3所示为例，部分第二电极40沿第一方向X包覆在介电层30的外表面，部分第二电极40沿第三方向Z设置。从而降低电容器的制程工艺难度和工艺成本。
在本实施例中，多个第一电极沿长度方向呈矩形阵列排布，并共用一个介电层和一个第二电极，从而形成一种三维结构的电容器，该三维结构的电容器可以在其宽度方向和厚度方向上进行扩展，使得在单位面积的存储空间布置更多水平放置的电容器，有效提高了存储器的集成度和存储容量。
根据一个示例性实施例，如图5和图6所示，本实施例是对上文中步骤S200的进一步说明。
利用沉积工艺于基底10上形成至少一层外延层50。外延层50包括交替布置的单晶硅层51和含硅材料层52，其中，单晶硅层51在第一方向X上的尺寸均大于单晶硅层51在第二方向Y上和第三方向Z上的尺寸。含硅材料层52的材料可以包括但不限于锗化硅(SiGe)，其与单晶硅层51之间具有刻蚀选择性。外延层50的层数可以为一层，也可以为多层，例如两层、三层、四层等。
在一个示例中，当外延层50为一层时，此时，可以形成一个水平放置的电容器10A，或者，形成多个沿第二方向Y间隔设置的电容器10A。水平放置的多个沿第二方向Y设置的电容器共用一个介电层30和一个第二电极40，即可以形成沿第二方向Y设置的二维结构的电容器10A。
在另一个示例中，外延层50为多层时，可以形成三维结构的且水平放置的电容器，此时，沿第三方向Z可以设置多层间隔设置的第一电极20，从而有效提高电容器单位面积的存储容量和集成度。
待外延层50形成之后，参照图7至图11所示，于外延层50上定义出图形区60和接触区70。其中，接触区70处的单晶硅层51可以用于形成晶体管的源区或漏区，以便于对源区或漏区进行掺杂处理，形成晶体管的源极S或漏极D，当然在一些工艺中，可以先形成源极S和漏极D，或者也可以制作电容器10A的同时，制作源极S和漏极D。
参照图11所示，在图形区60中选择性地向下刻蚀外延层50，直至暴露出基底10的顶面。图形区60内没有被刻蚀的剩余的外延层50定义出第一电极20的位置，且图形区60内剩余的外延层50沿横向也就是沿第一方向X延伸。该步骤中，图形区60内没有被刻蚀的剩余的外延层50中，剩余的外延层50中的单晶硅层51所在的位置为第一电极20的预留位置，即，将图形区60内剩余外延层50中沿上下方向相邻的两层含硅材料层52之间的单晶硅层51去除之后，原来单晶硅层51所处的位置用于形成第一电极20。
参照图12和图13所示，利用刻蚀处理工艺去除剩余的外延层50中的单晶硅层51，形成间隙80。然后，利用沉积工艺在间隙80内形成第一电极20。
如图16和图17所示，在一个实施例中，通过第三方向Z上定义出电容的列数，例如沿第三方向Z，在基底上设置三层外延层50，即在第三方向Z形成三层用于放置电容器10A的空间。在第二方向Y上选择性地进行刻蚀，在第二方向Y上定义出电容的行数，例如，刻蚀后在图形区60内剩余的并排设置的两个外延层50沿第二方向Y间隔设置，即沿第二方向Y形成两层用于放置电容器10A的空间。也就是说，此时，在图16和图17中，可以形成呈阵列排布的六个第一电极20。
本实施例中，利用图形区中剩余的外延层定义第一电极的形成位置，而接触区中任意相邻的两层含硅材料层之间的单晶硅层用于形成晶体管的源区或漏区，从而 在形成第一电极的过程中，实现第一电极与晶体管的源极或漏极连接。
在一些实施例中，参照图7和图9，图形区60和接触区70的形成可以采用以下方法：
继续参考图8和图9，利用沉积工艺于外延层50的顶面上形成第一掩膜层90。图形化第一掩膜层90，以在第一掩膜层90上形成第一掩膜图案100。以具有第一掩膜图案100的第一掩膜层90为掩膜，通过刻蚀处理工艺向下刻蚀外延层50，直至暴露出基底10的顶面，从而同步定义出图形区60、接触区70和第一电极20的形成位置，如图7所示。
本实施例中，利用第一掩膜层上的第一掩膜图案，可以同步定义出图形区、接触区和第一电极的形成位置，有效降低了电容器的制程工艺难度，节省了电容器的制作成本。
继续参照图12和图13，待第一电极20的形成位置确定，并在图形区60内形成间隙80之后，图形区60中形成有凹槽61。而后，参照图14和图15，于图形区60的凹槽61内沉积第一电极材料110，第一电极材料110填充满图形区60的凹槽61和间隙80。第一电极材料110延伸至图形区60外并覆盖位于接触区70中的外延层50的顶面。其中，第一电极材料110可以包括但不限于多晶硅、金属钨或氮化钛等。
而后，如图16和图17所示，利用自对准工艺和无掩模刻蚀工艺去除凹槽61内的第一电极材料110，以及覆盖在接触区70中的外延层50的顶面的第一电极材料110，间隙80中的第一电极材料110被保留下来，形成第一电极20。
本实施例中，使用第一电极材料填充凹槽和间隙，同时第一电极材料还覆盖接触区的顶面，而后利用无掩模刻蚀去除凹槽和接触区顶面的第一电极材料，剩余在间隙内的第一电极材料形成第一电极。第一电极通过自对准工艺技术实现，可以避免发生位置偏移，保证准确去除凹槽和接触区顶面的第一电极材料，提升了电容器的性能和可靠度。
在一些实施例中，如图14至图17所示，在间隙80内形成第一电极20可以采用以下方法：
首先，参照图14和图15利用沉积工艺在凹槽61内沉积第一导电材料110。第一电极材料110填充满凹槽61和图形区60内剩余含硅材料层52之间的间隙80，其中，第一电极材料110延伸至凹槽61外并覆盖位于接触区70中的外延层50的顶面。
其中，第一电极材料110可以利用原子层沉工艺和化学气相沉积工艺共同形成。
在一个示例中，首先利用原子层沉积工艺在凹槽61和间隙80的表面沉积一层第一电极材料110，例如使用化学气相沉积工艺继续沉积第一电极材料110，使得第一电极材料完全充满凹槽61和间隙80，当然，在一些实施例中，可以通过原子层沉积工艺在凹槽61和间隙80的表面沉积第一电极材料110，直至将间隙80完全填充满之后，再使用化学气相沉积工艺填充剩余的部分，本公开实施里中使用原子层沉积工艺和化学气相沉积工艺能形成更大长度以及更加均匀致密的第一电极20，从而有效适应第一电极20的高横纵比。
在另一个示例中，利用原子层沉积工艺在凹槽61的顶部沉积第一电极材料110至预定高度，该预定高度可以是凹槽61内由下至上方向的第一层含硅材料层52的顶面，而后，利用化学气相沉积工艺于剩余凹槽61内继续沉积第一电极材料110，之后，再利用原子层沉积工艺继续沉积第一电极材料110，然后，依次交替使用原子层沉积工艺和化学气相沉积工艺，直至第一电极材料110覆盖位于接触区70内的外延层50的顶面。
原子层沉积工艺具有沉积速度慢、沉积形成的膜层致密性高以及阶梯覆盖率好的特点。利用原子层沉积工艺形成第一电极材料110能够在空间较小的条件下对凹槽61的底部或间隙80进行覆盖，避免出现孔洞等问题，有效保证第一电极材料110的形成质量，进而提高第一电极20的性能和良率。
参照图16和图17所示，待第一电极材料110形成之后，利用自对准工艺和无掩模刻蚀工艺去除凹槽61内的第一电极材料层110和位于接触区70内的外延层50顶面的第一电极材料110，间隙80中的第一电极材料110被保留下来，形成第一电极20。
本实施例中，利用原子层沉积工艺和化学气相沉积工艺共同形成第一电极材料，在保证第一电极材料形成质量的同时，也能有效提高第一电极横纵比，从而提升电容器的存储容量和集成度。
在一些实施例中，如图18至图26所示，待间隙80内形成第一电极20之后，该电容器的制作方法还包括：于第一电极20的侧壁形成支撑结构120。
其中，支撑结构120的形成可以采用以下方法：
参照图19和图20所示，利用沉积工艺在图形区60的凹槽61内沉积支撑材料130，支撑材料130延伸至凹槽61外并覆盖接触区70的顶面。需要说明的是，第一电极20形成步骤中，第一电极材料110去除之后在图形区60内形成的凹槽与上一步骤中所形成的凹槽61的结构一致。
而后，参考图18和图19，利用沉积工艺在支撑材料130表面形成图案化的第二掩膜层140。图形化的第二掩膜层140的边缘还覆盖位于接触区70中的支撑材料130的表面，同时，图案化的第二掩膜层140还在图形区60上形成阵列排布。其中，图案化的第二掩膜层140在支撑材料130上形成中间开口而边缘位置封闭的第二掩膜图案141，以及在图形区60上形成有多个阵列排布的掩膜柱142。第二掩膜图案141在基底10上的投影面积大于接触区70在基底10上的投影面积，其中，第二掩膜图案141的外边缘与接触区70的外边缘平齐，以在接触区70内被保留下来的外延层50的侧壁形成支撑材料130，后续用于形成支撑结构120(参照图25)。沿第二方向Y，至少设置与第一电极20行数数量相同的掩膜柱142，支撑每一行的第一电极20，例如，参考图1、6和图17的实施例中，其在第二方向Y上设置两行第一电极20，此时可以在第一电极20的正上方位置，设置相应地两个掩膜柱142，其中，在第二方向Y上，掩膜柱142在基底10上的投影宽度大于第一电极20的宽度，以便于后续在第一电极20的两侧形成支撑结构120，提高沿竖向排布的多个第一电极20的结构稳定性。
然后，参照图21所示，以图案化的第二掩膜层140为掩膜向下刻蚀支撑材料130，至暴露外延层50，从而在图形区60上形成阵列开口170。
如图22所示，沿阵列开口170，继续向下刻蚀支撑材料130，直至暴露基底10的顶面。
参照图23和图24所示，待基底10的顶面暴露之后，在图形区60处，采用湿法刻蚀工艺去除剩余的外延层50中的含硅材料层52。其中，湿法刻蚀工艺能够在干净去除剩余含硅材料层52的同时，不会对第一电极20和剩余的支撑材料130造成损坏，从而保证电容器的性能。
或者，待基底10的顶面暴露之后，在图形区60处，采用蒸汽刻蚀工艺去除剩余的外延层50中的含硅材料层52。其中，蒸汽刻蚀工艺中，刻蚀蒸汽可以采用HCl蒸汽，刻蚀时间为5至60秒，从而快速去除含硅材料层52。
最后，参照图25和图26所示，利用刻蚀处理工艺去除顶面高度的支撑材料130，暴露出接触区70的顶面，以及将位于第一电极20两侧的支撑材料130的顶部打开，从而使保留在第一电极20的侧壁、以及保留在接触区70的侧壁上的支撑材料130共同形成支撑结构120。
其中，待剩余的含硅材料层52去除之后，且在形成支撑结构120后，多层第一电极20之间形成立体空间。
本实施例中，利用支撑结构对位于同一列(即沿同一竖向方向排布)的多个第一电极20进行侧壁支撑保护，从而能够在竖向方向上布置更多的第一电极，增加电容器在竖向方向扩展的可能性，有效提高了单位空间面积的电容器的集成度。
根据一个示例性实施例，如图27和图28所示，本实施例是对上文中步骤S300的进一步说明。
利用原子层沉积工艺形成介电层30。所形成的介电层30连续包覆在第一电极20的外表面。当第一电极20的个数为一个时，该介电层30包覆在一个第一电极20的外表面，同时，介电层30还包覆在支撑结构120的外表面。而当第一电极20的个数为多个，且呈矩形阵列排布时，介电层30连续包覆在多个第一电极20的外表面以及支撑结构120的外表面，从而形成共用的介电层30。
本实施例中，介电层利用原子层沉积工艺形成，原子层沉积工艺具有沉积速度慢、沉积形成的膜层致密性高以及阶梯覆盖率好的特点。利用原子层沉积工艺形成得介电层能够在空间较小的条件下对第一电极和支撑结构的外表面进行覆盖，避免占据较大的空间，有效保证介电层的形成质量，进而提高电容器的性能和良率。
根据一个示例性实施例，如图29和图30所示，本实施例是对上文中步骤S400的进一步说明。
利用原子层沉积工艺形成第二电极40。所形成的第二电极40连续包覆在介电层30的外表面上，并被多个水平设置的电容器10A所共用。
本实施例中，第二电极利用原子层沉积工艺形成，原子层沉积工艺具有沉积速度慢、沉积形成的膜层致密性高以及阶梯覆盖率好的特点。利用原子层沉积工艺形成的第二电极能够在空间较小的条件下对介电层的外表面进行覆盖，避免占据较大的空间，有效保证第二电极的形成质量，进而提高电容器的性能和良率。
在一些实施例中，参照图27，利用上述电容器的制作方法所形成的电容器10A中的第一电极20在第一方向X和第三方向Z之间具有横纵比，该预设的横纵比大于或等于35。其中，横纵比大于或等于35的第一电极20可以有效增加水平布置的电容器10A的存储容量，同时，沿第二方向Y和第三方向Z，可以布置呈矩形阵列排布的多个第一电极20，并共用一个介电层30和共用一个第二电极40，从而在降低电容器的制程工艺难度的同时，有效提高了电容器的集成度。
在一些实施例中，如图2和图3所示，示出了包含水平布置电容器的存储器结构，当中均省略了支撑结构的示意图。本实施例中水平布置的电容器用于连接环绕式栅极(Gate-All-Around，GAA)型晶体管150。其中，晶体管150的栅极连接字线151，晶体管150的漏极D连接位线152，其源极S连接电容器10A的第一电极20；或者，晶体管150的源极S连接位线152，其漏极D连接电容器10A的第一电极20。第一电极20沿第一方向X延伸，字线151沿第二方向Y延伸，位线152沿第三方向Z延伸。本公开的实施例中存储器基于电容器10A和GAA型晶体管150的结构，可进一步节省空间，进一步地，在形成三维结构时，又再次向上进行了空间拓展，对提高DRAM的高集成度有极大的帮助。
在本实施例中，如图2所示，处于同一水平线上的两个电容器10A相对设置，两个电容器10A沿水平布置，上述两个电容器10A分别连接两个相对设置的晶体管150的源极S或漏极D，两个晶体管150可以共用一条位线152并处于同一水平线上，以提高单位面积的存储器的集成度。
如图3所示，沿水平设置且处于同一水平线上的两个电容器10A相对设置，并分别连接处于同一水平线上的两个相对设置的晶体管150的源极S或漏极D，两个晶体管150共用一条位线152。沿第二方向Y，多条位线152间隔排布，并分别与多列间隔排布的晶体管150对应连接，从而可以构成一种三维结构的存储器，增加了存储器在竖向方向扩展的可能性，提高了单位空间面积的存储器的集成度。
如图2所示，本公开一示例性的实施例提供了一种电容器10A，包括基底10、第一电极20、介电层30和第二电极40。
其中，第一电极20设置于基底10上，第一电极10沿平行于基底10的第一方向X延伸。第一电极20在第一方向X上的尺寸大于第一电极20在第二方向Y上的尺寸，第一方向X与第二方向Y相互垂直。第一电极20在第一方向X上的尺寸也大于第一电极20在第三方向Z上的尺寸，第一方向X与第三方向Z相互垂直，同时，第二方向Y与第三方向Z也相互垂直。
介电层30包覆在第一电极20的表面。第二电极40包覆在介电层30的表面。
本实施例中，第一电极、介电层和第二电极形成电容器，其中，第一电极的长度尺寸均大于第一电极的宽度尺寸和厚度尺寸，从而形成一种水平放置的电容器，以便于可以在立体空间内布置更多的电容器，进而提高存储器的存储容量。
在一些实施例中，如图3所示，电容器10A呈三维结构，该三维结构的电容器10A包括多个第一电极20、介电层30和第二电极40。
多个第一电极20间隔排布，且相邻的第一电极20之间具有立体空间。其中，多个第一电极20可以沿第二方向Y间隔排布。或者，多个第一电极20可以沿第三方向Z间隔排布。又或者，多个第一电极20沿第二方向Y和第三方向Z呈矩形阵列间隔排布。
介电层30位于立体空间内，并包覆在多个第一电极20的表面，形成多个第一电极20共用的介电层30。
第二电极40位于立体空间内，并包覆在多个介电层30的表面，形成多个第一电极20共用的第二电极40。
在本实施例中，多个第一电极沿长度方向呈矩形阵列排布，并共用一个介电层和一个第二电极，从而形成一种三维结构的电容器，该三维结构的电容器可以在第二方向和第三方向上进行扩展，使得在单位面积的存储空间布置更多水平放置的电容器，有效提高了最终的存储器的集成度和存储容量。
在一些实施例中，如图31和图32所示，水平布置的电容器10A形成之后，在电容器10A的第二电极40的表面设置一层缓冲层190，并在缓冲层190上设置一层隔离材料180。其中，缓冲层190的材料可以包括但不限于多晶硅。
本实施例的电容器10A或者三维结构的电容器10A中还包括外接电路160。外接电路160用于实现电容器10A与存储器的外围电路区内的控制电路电连接。其中，外接电路160包括接触层161和导电层162，接触层161半包裹导电层162。其中，接触层161嵌设于隔离材料180中，且接触层161的底部伸入缓冲层190内部，并与缓冲层190连接。其中，接触层161与第二电极40间隔设置。
如图3所示，本公开一示例性的实施例提供了一种存储器。该存储器包括上文实施例中的电容器10A、以及环绕式栅极型晶体管150。本公开的实施例中存储器基于电 容器10A和GAA型晶体管150的结构，可进一步节省空间，进一步地，在形成三维结构时，又再次向上进行了空间拓展，对提高DRAM的高集成度有极大的帮助。
其中，晶体管150的栅极连接字线151，晶体管150的漏极D和源极S两者之一连接位线152，晶体管150的源极S和漏极D中两者另一用于连接电容器10A的第一电极20。第一电极20沿第一方向X延伸，字线151沿第二方向Y延伸，位线152沿第三方向Z延伸。
在本实施例中，参照图3所示，沿水平设置且处于同一水平线上的两个相对设置的晶体管150共用一条位线152，每个晶体管150的外侧连接均连接有一个水平设置的电容器10A。沿第二方向Y，多条字线151间隔排布，并分别与多列间隔排布的晶体管150对应连接，从而构成一种三维结构的存储器，增加了存储器在竖向方向扩展的可能性，提高了单位空间面积的存储器的集成度。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的电容器的制作方法、电容器以及存储器中，第一电极沿平行于基底的第一方向延伸，且第一电极的横向尺寸大于其竖向尺寸，使得第一电极、介电层和第二电极形成一种水平设置的电容器，从而可以在立体空间内布置更多的电容器，提高了存储器的存储容量。

Claims (15)

  1. 一种电容器的制作方法，包括：
    提供基底；
    于所述基底上形成第一电极，所述第一电极沿平行于所述基底的第一方向延伸，所述第一电极在所述第一方向上的尺寸大于所述第一电极在第二方向上，以及在第三方向上的尺寸，所述第一方向、所述第二方向以及所述第三方向之间两两相互垂直；
    形成包覆所述第一电极的介电层；
    形成包覆所述介电层的第二电极。
  2. 根据权利要求1所述的电容器的制作方法，其中，所述电容器的制作方法还包括：
    形成沿所述第二方向和/或沿所述第三方向间隔排列的多个第一电极，相邻所述第一电极之间具有立体空间；
    所述介电层包覆在多个所述第一电极的表面以及位于所述立体空间内，形成共用的介电层；
    所述第二电极包覆在所述介电层的表面以及位于所述立体空间内，形成共用的第二电极。
  3. 根据权利要求1或2所述的电容器的制作方法，其中，于所述基底上形成第一电极，包括：
    于所述基底上形成至少一层外延层，所述外延层包括交叠布置的单晶硅层和含硅材料层，所述单晶硅层在所述第一方向尺寸均大于在第二方向上和在第三方向上的尺寸；
    于所述外延层上定义出图形区和接触区，其中，所述接触区处的所述单晶硅层形成晶体管的源或漏区；
    在所述图形区处，选择性地向下刻蚀所述外延层，至暴露所述基底，所述图形区处剩余的所述外延层定义出所述第一电极的位置，并沿横向延伸，其中，剩余的所述单晶硅层为所述第一电极预留间隙；
    在所述图形区处，去除剩余的所述外延层中所述单晶硅层，形成所述间隙；
    在所述间隙中形成所述第一电极。
  4. 根据权利要求3所述的电容器的制作方法，其中，于外延层形成图案化的第一掩膜层，并以所述图案化的第一掩膜层为掩膜向下刻蚀所述外延层，至暴露所述基底，以同步定义出所述图形区、所述接触区，以及所述第一电极的位置。
  5. 根据权利要求3所述的电容器的制作方法，其中，在所述间隙中形成所述第一电极，包括：
    于所述图形区内沉积第一电极材料，所述第一电极材料填充满所述图形区的凹槽和所述间隙，所述第一电极材料延伸至所述图形区外并覆盖所述接触区的顶面；
    利用无掩膜刻蚀去除所述凹槽内和所述接触区顶面的所述第一电极材料，于所述间隙中被保留下来的所述第一电极材料形成所述第一电极。
  6. 根据权利要求5所述的电容器的制作方法，其中，使用原子层沉积工艺和化学气相沉积工艺共同形成所述第一电极材料。
  7. 根据权利要求3所述的电容器的制作方法，其中，在所述间隙中形成第一电极之后，所述电容器的制作方法还包括：于所述第一电极的侧壁形成支撑结构；于所述第一电极的侧壁形成所述支撑结构，包括：
    于所述图形区内沉积支撑材料，所述支撑材料延伸至所述图形区外并覆盖所述接触 区的顶面；
    于所述支撑材料表面形成图案化的第二掩膜层，所述图案化的第二掩膜层覆盖所述接触区的表面，且图案化的第二掩膜层还在所述图形区上形成阵列排布；
    于所述图案化的所述第二掩膜层为掩膜向下刻蚀所述支撑材料，至暴露所述外延层，以在所述图形区上形成阵列开口；
    沿所述阵列开口，继续向下刻蚀所述支撑材料，直至暴露所述基底；
    去除顶面高度的支撑材料，以使所述支撑材料位于所述第一电极的侧壁和所述接触区的侧壁，形成所述支撑结构。
  8. 根据权利要求3所述的电容器的制作方法，其中，在形成多个第一下电极时，还包括：
    在所述图形区处，采用湿法刻蚀工艺或蒸汽刻蚀工艺去除剩余的所述外延层中所述含硅材料层，以形成立体空间。
  9. 根据权利要求1或2所述的电容器的制作方法，其中，形成包覆所述第一电极的介电层，包括：
    利用原子层沉积工艺形成介电层，所述介电层连续包覆在所述第一电极的表面。
  10. 根据权利要求1或2所述的电容器的制作方法，其中，形成包覆所述介电层的第二电极层，包括：
    利用原子层沉积工艺形成所述第二电极层，所述第二电极层连续包覆所述介电层的外表面。
  11. 根据权利要求1所述的电容器的制作方法，其中，所述第一电极在第一方向和所述第三方向之间具有横纵比，所述横纵比大于等于35。
  12. 根据权利要求1或2所述的电容器的制作方法，其中，所述电容器用于连接环绕式栅极型晶体管，其中，所述晶体管的栅极连接字线，漏极和源极之一连接位线，所述漏极和所述源极之另一连接所述电容器的所述第一电极，所述第一电极沿第一方向延伸，所述字线沿所述第二方向延伸，所述位线沿第三方向延伸。
  13. 一种电容器，包括：
    基底；
    第一电极，位于所述基底上，所述第一电极沿平行于基底的第一方向延伸，所述第一电极在所述第一方向上的尺寸大于所述第一电极在第二方向上，以及在第三方向上的尺寸，所述第一方向、所述第二方向以及所述第三方向之间两两相互垂直；
    介电层，包覆在所述第一电极的表面；
    第二电极，包覆在所述介电层的表面。
  14. 根据权利要求13所述的电容器，其中，其包括：
    沿第二方向和/或沿第三方向间隔排列的多个第一电极，相邻所述第一电极之间具有立体空间；
    所述介电层包覆在多个所述第一电极的表面以及位于所述立体空间内，形成共用的介电层；
    所述第二电极包覆在所述介电层的表面以及位于所述立体空间内，形成共用的第二电极。
  15. 一种存储器，包括：
    权利要求13或14任一项所述的电容器；
    环绕式栅极型晶体管，所述晶体管的栅极连接字线，漏极和源极之一连接位线，所述漏极和所述源极之另一连接所述电容器，其中，所述电容器沿第一方向延伸，所述字 线沿所述第二方向延伸，所述位线沿第三方向延伸。
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