WO2021169797A1 - 半导体结构制备方法和半导体结构 - Google Patents

半导体结构制备方法和半导体结构 Download PDF

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Publication number
WO2021169797A1
WO2021169797A1 PCT/CN2021/076099 CN2021076099W WO2021169797A1 WO 2021169797 A1 WO2021169797 A1 WO 2021169797A1 CN 2021076099 W CN2021076099 W CN 2021076099W WO 2021169797 A1 WO2021169797 A1 WO 2021169797A1
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Prior art keywords
dielectric layer
electrode
groove
layer
semiconductor structure
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PCT/CN2021/076099
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English (en)
French (fr)
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鲍锡飞
储瑶瑶
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长鑫存储技术有限公司
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Priority to US17/446,454 priority Critical patent/US11855131B2/en
Publication of WO2021169797A1 publication Critical patent/WO2021169797A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H10B12/373—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate the capacitor extending under or around the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments

Definitions

  • the embodiments of the present application relate to the field of semiconductor technology, and in particular, to a method for preparing a semiconductor structure and a semiconductor structure.
  • a dynamic random access memory (DRAM) cell includes a capacitor for storing charge and a transistor for accessing the capacitor.
  • DRAM stores data by the charge on the capacitor, so it is necessary to recharge the capacitor regularly every few milliseconds. The larger the capacitance of the capacitor, the longer the data stored in the DRAM can be maintained. Therefore, the aspect ratio of the dynamic random access memory capacitor in the prior art is relatively high.
  • the purpose of some embodiments of the present application is to provide a method for preparing a semiconductor structure and a semiconductor structure, which can effectively avoid defects caused by the connection of the first electrodes in adjacent grooves.
  • some embodiments of this application provide a method for preparing a semiconductor structure, including: providing a substrate; forming a groove on the substrate; forming a first dielectric layer on the sidewall of the groove; A first electrode is formed on the bottom of the groove and the inner surface of the first dielectric layer; a second dielectric layer is formed on the surface of the first electrode; and a second electrode is formed on the surface of the second dielectric layer.
  • the sidewall of the groove has a recessed area, and the first dielectric layer covers the recessed area. In this way, it is beneficial to avoid a short circuit caused by contact between adjacent electrodes due to the existence of the recessed area.
  • the first dielectric layer formed in the recessed area on the sidewall of the groove directly contacts the first dielectric layer on the sidewall of the adjacent groove.
  • the material of the first dielectric layer includes a high-K material. In this way, it is beneficial to increase the electrode isolation effect between adjacent grooves.
  • the high-K material includes any element of Zr, Hf, Nb, Al, or O or any combination thereof.
  • the substrate includes a support layer and a sacrificial layer, the support layer is located above the sacrificial layer; after forming a second dielectric layer on the surface of the first electrode, before forming a second electrode on the surface of the second dielectric layer , Further comprising: etching the support layer to form at least a portion of the sacrificial opening; etching through the opening to remove the sacrificial layer to form a space area exposing the outer surface of the first dielectric layer; in the space The second electrode is formed in the region.
  • the etching of the support layer to form an opening that exposes at least a part of the sacrificial layer further includes: the opening exposing the first electrode; After exiting the space area on the outer surface of the first dielectric layer and before forming the second electrode on the surface of the second dielectric layer, the method further includes: depositing a third dielectric layer on the exposed first electrode. In this way, it is beneficial to prevent the first electrode and the second electrode from contacting and causing a short circuit, thereby improving the yield of the semiconductor structure.
  • Some embodiments of the present application also provide a semiconductor structure, including: a substrate with a groove; a first dielectric layer, the first dielectric layer is located on the sidewall of the groove; a first electrode, the first electrode is located on the sidewall of the groove; The bottom of the groove and the inner surface of the first dielectric layer; the second dielectric layer, the second dielectric layer is located on the surface of the first electrode; the second electrode, the second electrode is located on the surface of the second dielectric layer .
  • the substrate includes a support layer
  • the groove penetrates the support layer to form a side surface of the support layer
  • the first dielectric layer directly contacts the side surface of the support layer
  • the second electrode is also located on the outer surface of the first dielectric layer.
  • the material of the first dielectric layer includes a high-K material.
  • the high-K material contains any element of Zr, Hf, Nb, Al, or O or any combination thereof.
  • the semiconductor structure further includes a third dielectric layer, which is located between the top of the first electrode and the second electrode, and is directly connected to the first electrode and the second electrode. touch.
  • the material of the third dielectric layer includes a high-K material.
  • the sidewall of the groove has a recessed area; the first dielectric layer covers the recessed area.
  • first dielectric layer on the recessed area of the sidewall of the groove is in direct contact with the first dielectric layer on the sidewall of the adjacent groove.
  • some embodiments of the present application first deposit the first dielectric layer before preparing the first electrode in the groove, and then sequentially form the first electrode and the second dielectric layer in the groove, and in the groove and
  • the second electrode is formed on the upper surface of the substrate, and a first dielectric layer is deposited in advance to ensure the isolation effect between adjacent first electrodes, and avoid the recessed area of the first electrode in two adjacent grooves when the first electrode is deposited The existence of the contact occurs, thereby ensuring the effectiveness of the semiconductor structure.
  • 1 to 8 are schematic structural diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present application;
  • 9 to 12 are schematic structural diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present application.
  • 13 to 16 are schematic structural diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present application.
  • Some embodiments of this application provide a method for preparing a semiconductor structure, including: providing a substrate; forming a groove on the substrate; forming a first dielectric layer on the sidewall of the groove; and on the bottom of the groove and the inner surface of the first dielectric layer Forming a first electrode; forming a second dielectric layer on the surface of the first electrode; forming a second electrode on the surface of the second dielectric layer.
  • 1 to 8 are schematic diagrams of cross-sectional structures corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the application.
  • a base 11 is provided.
  • the base 11 includes a substrate 111 and an intermediate dielectric layer 113 on the substrate 111; the substrate 111 is provided with a conductive structure 112.
  • the intermediate dielectric layer 113 is used to define a pattern, where the intermediate dielectric layer 113 may be formed by a deposition process such as an atomic layer deposition process or a chemical vapor deposition process.
  • the conductive structure 112 is used to connect with each subsequent capacitor to store data. It should be noted that the substrate 111 may also be formed with word lines, bit lines, transistors, and isolation trenches.
  • a groove 12 is formed on the substrate 11.
  • the groove 12 is a cylindrical hole; in other embodiments, the groove may also have other shapes, which is not limited in this embodiment.
  • the groove 12 can be obtained by etching the intermediate dielectric layer 113 by using multiple patterned photolithography and etching processes to improve the accuracy of photolithography and etching.
  • the side wall of the groove 12 has a recessed area 13, and the recessed area 13 is recessed in a direction away from the central axis of the groove 12.
  • a first dielectric layer 14 is formed on the sidewall of the groove 12.
  • the first dielectric film 141 is formed on the bottom and sidewalls of the groove 12 and the upper surface of the intermediate dielectric layer 113 by a method such as chemical vapor deposition or atomic layer deposition; And the first dielectric film 141 on the top of the intermediate dielectric layer 113 to form the first dielectric layer 14.
  • the recessed area 13 penetrates the intermediate dielectric layer 113, so that the first dielectric layer 14 formed on the recessed area 13 on the side wall of the groove 12 directly contacts the first dielectric layer 14 on the side wall of the adjacent groove 12 .
  • the material of the first dielectric layer 14 includes a high-K material, which helps to ensure the isolation effect of the first dielectric layer 14 and avoids the subsequent formation of the first electrodes located in two adjacent grooves 12 from being connected.
  • the material of the first dielectric layer 14 includes any element of Zr, Hf, Nb, Al, or O or any combination thereof.
  • the first dielectric layer 14 is any one or any combination of ZrO, AlO, ZrNbO, ZrHfO, ZrAlO.
  • the thickness of the first dielectric layer 14 ranges from 2 to 10 nm, for example, 4 mm, 6 mm, or 8 mm. It should be noted that in practical applications, the thickness of the first dielectric layer 14 is determined according to the diameter of the groove 12 and the thicknesses of the first electrode, the second dielectric layer, and the second electrode to be formed later. The electrodes, the second dielectric layer, and the second electrode reserve enough deposition space, and the thickness of the first dielectric layer 14 must be sufficient to isolate the first electrodes in two adjacent grooves 12. Preferably, the thickness of the first dielectric layer 14 is greater than the thickness of the second dielectric layer and the thickness of the second electrode, so that the first dielectric layer 14 has sufficient supporting capacity to prevent collapse.
  • a first electrode 15 is formed on the bottom of the groove 12 and the inner surface of the first dielectric layer 14.
  • the first electrode film 151 may be deposited by a deposition process such as an atomic layer deposition process, a physical vapor deposition process, or a plasma deposition process.
  • the first electrode film 151 is located at the bottom and sidewalls of the groove 12 and the intermediate dielectric layer 113 Top; dry etching or wet etching is used to remove the first electrode film 151 located on the top of the intermediate dielectric layer 113 to form the first electrode 15.
  • the material of the first electrode 15 includes any one or any combination of metal materials such as titanium nitride, tantalum nitride, copper, or tungsten.
  • using a low-power dry etching process to etch the first electrode film 151 can improve the etching accuracy of the first electrode 15.
  • a second dielectric layer 16 is formed on the surface of the first electrode 15.
  • a chemical vapor deposition process or an atomic layer deposition process is used to deposit the second dielectric layer 16 on the surface of the first electrode 15 and the top surface of the substrate 11; in other embodiments, the second dielectric layer may also cover the first electrode surface.
  • the material of the second dielectric layer 16 includes a high-K material.
  • the material of the second dielectric layer 16 may be the same as or different from the material of the first dielectric layer 14, which is not limited in this embodiment.
  • a second electrode 17 is formed on the surface of the second dielectric layer 16.
  • the second electrode 17 covers the surface of the second dielectric layer 16 and fills the entire groove 12; in other embodiments, the second electrode covers the surface of the second dielectric layer.
  • the material of the second electrode 17 includes a compound formed by one or two of metal nitride and metal silicide, such as titanium nitride, titanium silicide, nickel silicide, and silicon nitride. Titanium (TiSi x N y ) or other conductive materials.
  • the material of the second electrode 17 may also be a conductive semiconductor material, such as polysilicon, silicon germanium and the like.
  • the first electrodes 15 in adjacent grooves 12 are isolated, so as to prevent the first electrode 15 from being adjacent to each other due to the existence of the recessed area 13 when the first electrode 15 is deposited.
  • the first electrodes 15 in the two grooves 12 are connected to ensure the effectiveness of the capacitor.
  • Another embodiment of the present application also provides a method for fabricating a semiconductor structure.
  • the technical solution provided in this embodiment is substantially the same as the previous embodiment.
  • the main improvement is that the second electrode is located on the opposite side of the first dielectric layer to the first electrode. The other side.
  • 9 to 12 are schematic structural diagrams corresponding to each step of the semiconductor structure manufacturing method provided by another embodiment of the present application.
  • the same or corresponding parts as the previous embodiment please refer to the description of the previous embodiment, and will not be repeated here. .
  • the intermediate dielectric layer 213 includes a support layer and a sacrificial layer.
  • the intermediate dielectric layer 213 includes a first support layer 221 at the top, a second support layer 222 at the middle, and a third support layer at the bottom.
  • the number and positions of the support layer and the sacrificial layer are not limited, and the number of the support layer and the sacrificial layer can be appropriately increased, thereby increasing the height of the capacitor and further increasing the capacitance value of the capacitor.
  • the number of supporting layers can also be appropriately reduced, for example, including a first supporting layer and a second supporting layer.
  • the materials of the first support layer 221, the second support layer 222, and the third support layer 223 are silicon nitride
  • the materials of the first sacrificial layer 231 and the second sacrificial layer 232 are silicon oxide, BPSG, PSG, Any one or any combination of BSG and TEOS.
  • the support layer is etched to form an opening 261 exposing at least part of the sacrificial layer; the sacrificial layer is etched and removed through the opening 261 to form a space area 28 exposing the outer surface of the first dielectric layer 24.
  • FIG. 10 is a top view of the semiconductor structure corresponding to this step. As shown in FIG. The top view is circular; in other embodiments, the opening may also have other shapes.
  • the second dielectric layer 26 is deposited on the top of the substrate 21, that is, the top surface of the first support layer 221. Before the support layer is etched, the part on the top of the first support layer 221 needs to be etched and removed. The second dielectric layer 26 is then etched to the first supporting layer 221 to form an opening 261.
  • the first support layer 221 is etched first to expose part of the first sacrificial layer 231, the first sacrificial layer 231 is removed by acid washing to expose the second support layer 222; then the second support layer 222 is etched to expose part of the second sacrificial layer 232.
  • the second sacrificial layer 232 is removed by pickling.
  • the shape of the opening 261 can be defined by a multiple patterned photolithography process, and the second dielectric layer 26 and the first support layer 221 can be etched by a dry etching process.
  • a second electrode 27 is formed on the surface of the second dielectric layer 26.
  • the space area 28 exposing the outer surface of the first dielectric layer 24 is formed by removing the sacrificial layer by etching, and the second electrode 27 is filled in the space area 28 and the groove 22, so that the second electrode 27 surrounds the first dielectric layer 24.
  • the inner and outer sides of the electrode 25 are thus beneficial to increase the capacitance value of the capacitor.
  • Another embodiment of the present application also provides a method for fabricating a semiconductor structure.
  • the technical solution provided in this embodiment is substantially the same as the previous embodiment.
  • the main difference is that the support layer is etched to form an opening that exposes at least a portion of the sacrificial layer.
  • a first electrode, and a third dielectric layer is deposited on the exposed first electrode.
  • FIG. 13 is a top view of the structure of the semiconductor structure corresponding to this embodiment
  • FIG. 14 is a schematic view of the corresponding cross-sectional structure.
  • the opening 361 and the groove 32 have a common part.
  • the part located on the top of the first electrode 35 is etched away.
  • the second dielectric layer 36 exposes the top surface of the first electrode 35.
  • a third dielectric layer 39 is deposited on top of the exposed first electrode 35. In this way, when the second electrode 37 is subsequently deposited, the first electrode 35 and the second electrode 37 can be prevented from contacting, thereby ensuring the effectiveness of the capacitance.
  • the third dielectric layer 39 includes a high-K material, such as any element of Zr, Hf, Nb, Al, or O, or any combination thereof. In this way, it is beneficial to further improve the isolation effect of the third dielectric layer 39.
  • the opening 361 exposes part of the top surface of the first electrode 35. Therefore, the exposed top surface of the first electrode 35 is formed to cover the exposed top surface of the first electrode 35 before the second electrode 37 is deposited to prevent the first electrode 35 from contacting the second electrode 37. , So as to ensure the effectiveness of the capacitor.
  • FIG. 16 is a schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the application.
  • the semiconductor structure includes: a substrate 31 having a groove 32; a first dielectric layer 34, the first dielectric layer 34 is located on the sidewall of the groove 32; a first electrode 35, a first electrode 35 Located at the bottom of the groove 32 and the inner surface of the first dielectric layer 34; the second dielectric layer 36, the second dielectric layer 36 is located on the surface of the first electrode 35; the second electrode 37, the second electrode 37 is located on the surface of the second dielectric layer 36.
  • the base 31 includes a substrate 311 and an intermediate dielectric layer (not labeled); the substrate 311 is provided with a conductive structure 312; the groove 32 penetrates the intermediate dielectric layer and exposes the conductive structure 312.
  • the substrate 31 is used to carry the formed storage capacitors, and the intermediate dielectric layer is used to isolate the respective capacitors.
  • the intermediate dielectric layer specifically includes a plurality of support layers 314 connected to the first dielectric layer 34; the groove 32 penetrates the support layer 314 to form a side surface of the support layer, and the first dielectric layer 34 directly contacts the side surface of the support layer 314.
  • the support layer 314 arranged in the intermediate dielectric layer can ensure the stability of the intermediate dielectric layer.
  • the support layer 314 can be located at any position or multiple positions of the top, bottom, or middle of the intermediate dielectric layer, and the position of the support layer 314 and The number is unlimited.
  • the sidewall of the groove 32 has a recessed area 33; the first dielectric layer 34 covers the recessed area 33.
  • the first dielectric layer 34 on the recessed area 33 on the sidewall of the groove 32 is in direct contact with the first dielectric layer 34 on the recessed area 33 on the sidewall of the adjacent groove 32; in other embodiments, the sidewall of the groove There is a gap between the first dielectric layer on the recessed area and the first dielectric layer on the recessed area adjacent to the sidewall of the groove.
  • the material of the first dielectric layer 34 includes a high-K material, and the high-K material includes any element of Zr, Hf, Nb, Al, or O, or any combination thereof. In this way, it is beneficial to improve the isolation effect between adjacent grooves 32.
  • the second electrode 37 is also located on the outer surface of the first dielectric layer 34.
  • the first electrode 35 is located on the inner surface of the first dielectric layer 34
  • the second electrode 37 is located on the outer surface of the first dielectric layer 34. In this way, the second electrode 37 can be distributed around the two sides of the first electrode 35, thereby increasing the capacitance value of the capacitor.
  • the semiconductor structure further includes a third dielectric layer 39.
  • the third dielectric layer 39 is located between the top of the first electrode 35 and the second electrode 37, and is in direct contact with the first electrode 35 and the second electrode 37.
  • the third dielectric layer 39 includes a high-K material.
  • the adjacent first electrodes 35 are separated by the first dielectric layer 34, and the second electrode 37 surrounds the entire inside and outside of the first electrode 35, which can prevent the adjacent first electrodes 35 from being connected to the first electrode 35.
  • the connection with the second electrode 37 causes the capacitance to fail, and at the same time, the capacitance value of the capacitor can be increased.

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Abstract

本申请部分实施例公开了一种半导体结构制备方法和半导体结构。本申请中，半导体结构制备方法包括：提供基底(11)并刻蚀基底(11)形成凹槽(12)；在凹槽(12)侧壁形成第一介质层(14)；在凹槽(12)底部和第一介质层(14)内表面形成第一电极(15)；在第一电极(15)表面形成第二介质层(16)；在第二介质层(16)表面形成第二电极(17)。

Description

半导体结构制备方法和半导体结构
交叉引用
本申请要求于2020年2月24日递交的名称为“半导体结构制备方法和半导体结构”、申请号为202010110965.1的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体技术领域，特别涉及一种半导体结构制备方法和半导体结构。
背景技术
动态随机存取存储器(DRAM)单元包括用于存储电荷的电容器和存取电容器的晶体管。DRAM以电容器上的电荷存储数据，所以需要在每几个毫秒的间隔即将电容器作规则性的再充电，而电容器的电容越大，储存在DRAM中的数据也可被维持得越久。因此，现有技术中动态随机存取存储器电容的深宽比都较高。
然而由于动态随机存取存储器电容孔深宽比的不断提高导致电容孔的形貌控制越来越困难，相邻的电容孔在沉积第一电极时易产生缺陷，从而降低良率。
申请内容
本申请部分实施方式的目的在于提供一种半导体结构制备方法和半导体结构，能够有效避免相邻凹槽内的第一电极连接而产生缺陷。
为解决上述技术问题，本申请部分的实施例提供了一种半导体结构制备方法，包括：提供基底；在所述基底上形成凹槽；在所述凹槽侧壁形成第一介质层；在所述凹槽底部和所述第一介质层内表面形成第一电极；在所述第一电 极表面形成第二介质层；在所述第二介质层表面形成第二电极。
另外，所述凹槽侧壁具有凹陷区域，所述第一介质层覆盖所述凹陷区域。如此，有利于避免因凹陷区域的存在导致相邻电极产生接触导致短路。
另外，在所述凹槽侧壁上的凹陷区域形成的所述第一介质层与其邻近凹槽侧壁上的所述第一介质层直接接触。
另外，所述第一介质层的材料包含高K材料。如此，有利于增加相邻凹槽之间的电极隔离效果。
另外，所述高K材料包括Zr、Hf、Nb、Al或O中的任一元素或其任意组合。
另外，所述基底包括支撑层和牺牲层，所述支撑层位于所述牺牲层上方；在所述第一电极表面形成第二介质层之后，在所述第二介质层表面形成第二电极之前，还包括：刻蚀所述支撑层形成至少暴露部分所述牺牲的开口；通过所述开口刻蚀去除所述牺牲层形成暴露出所述第一介质层外表面的空间区域；在所述空间区域内形成所述第二电极。
另外，所述刻蚀所述支撑层形成至少暴露部分所述牺牲层的开口还包括：所述开口暴露出所述第一电极；在所述通过所述开口刻蚀去除所述牺牲层形成暴露出所述第一介质层外表面的空间区域后，且在所述第二介质层表面形成第二电极之前，还包括：在暴露的所述第一电极上沉积第三介质层。如此，有利于避免第一电极与第二电极接触而发生短路，进而提高半导体结构的良率。
本申请部分实施例还提供了一种半导体结构，包括：基底，所述基底具有凹槽；第一介质层，所述第一介质层位于凹槽侧壁；第一电极，第一电极位于所述凹槽底部和所述第一介质层内表面；第二介质层，所述第二介质层位于所述第一电极表面；第二电极，所述第二电极位于所述第二介质层表面。
另外，所述基底包括支撑层，所述凹槽贯穿所述支撑层形成支撑层侧面，所述第一介质层与所述支撑层侧面直接接触。
另外，所述第二电极还位于所述第一介质层的外表面。
另外，第一介质层的材料包含高K材料。
另外，所述高K材料包含Zr、Hf、Nb、Al或O中的任一元素或其任意 组合。
另外，所述半导体结构还包括第三介质层，所述第三介质层位于所述第一电极的顶部和所述第二电极之间，并与所述第一电极和所述第二电极直接接触。
另外，所述第三介质层的材料包含高K材料。
另外，所述凹槽侧壁具有凹陷区域；所述第一介质层覆盖所述凹陷区域。
另外，所述凹槽侧壁凹陷区域上的所述第一介质层与其邻近凹槽侧壁上的所述第一介质层直接接触。
本申请部分实施例相对于现有技术而言，在凹槽内制备第一电极之前先沉积第一介质层，然后依次在凹槽内形成第一电极和第二介质层以及在凹槽内和基底上表面形成第二电极，通过预先沉积一层第一介质层，保证相邻第一电极之间的隔离效果，避免在沉积第一电极时相邻两个凹槽内第一电极因凹陷区域的存在而发生接触，从而保证半导体结构的有效性。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1至图8是本申请一实施例提供的半导体结构的制造方法各步骤对应的结构示意图；
图9至图12是本申请又一实施例提供的半导体结构的制造方法各步骤对应的结构示意图；
图13至图16是本申请另一实施例提供的半导体结构的制造方法各步骤对应的结构示意图。
具体实施方式
本申请部分实施例提供了一种半导体结构制备方法，包括：提供基底； 在所述基底上形成凹槽；在凹槽侧壁形成第一介质层；在凹槽底部和第一介质层内表面形成第一电极；在第一电极表面形成第二介质层；在第二介质层表面形成第二电极。通过在沉积第一电极之前预先沉积一层第一介质层，使相邻第一电极被隔离，避免在沉积第一电极时相邻两个凹槽内的第一电极因凹陷区域的存在而发生接触，进而保证半导体结构的有效性。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1至图8为本申请一实施例提供的一种半导体结构的制作方法各步骤对应的剖面结构示意图。
参考图1，提供基底11，基底11包括衬底111和位于衬底111上的中间介质层113；衬底111内设有导电结构112。中间介质层113用于定义图案，其中，中间介质层113可以采用原子层沉积工艺、化学气相沉积工艺等沉积工艺形成。
本实施例中，导电结构112用于与每一后续形成的电容连接，起到存储数据的作用。需要说明的是，衬底111内部还可以形成有字线、位线、晶体管和隔离槽等结构。
参考图2，在基底11上形成凹槽12。
本实施例中，凹槽12为圆柱孔；在其他实施例中，凹槽也可以为其他形状，本实施例不做限制。此外，凹槽12可采用多重图形化光刻和刻蚀工艺对中间介质层113进行刻蚀得到，以提高光刻和刻蚀精度。
本实施例中，凹槽12侧壁具有凹陷区域13，凹陷区域13朝向远离凹槽12中心轴线的方向凹陷。
参考图3至图4，在凹槽12侧壁形成第一介质层14。
在一些实施例中，通过化学气相沉积或原子层沉积等方法在凹槽12底部和侧壁以及中间介质层113上表面形成第一介质膜141；采用干法刻蚀工艺去除 位于凹槽12底部以及中间介质层113顶部的第一介质膜141，以形成第一介质层14。
需要说明的是，采用高功率的干法刻蚀工艺对第一介质膜141进行刻蚀以形成第一介质层14，有利于提高第一介质层14的刻蚀精度。
本实施例中，凹陷区域13贯穿中间介质层113，如此，在凹槽12侧壁上的凹陷区域13形成的第一介质层14与其邻近凹槽12侧壁上的第一介质层14直接接触。
本实施例中，第一介质层14的材料包含高K材料，如此，有利于保证第一介质层14的隔离效果，避免后续形成的位于相邻两个凹槽12内的第一电极相连。在一些实施例中，第一介质层14的材料包含Zr、Hf、Nb、Al或O中的任一元素或其任意组合。具体的，第一介质层14为ZrO，AlO，ZrNbO，ZrHfO，ZrAlO中的任一种或其任一组合。
此外，本实施例中，第一介质层14的厚度范围为2～10nm，例如为4mm、6mm或8mm。需要说明的是，在实际应用中，第一介质层14的厚度根据凹槽12的直径以及后续形成的第一电极、第二介质层和第二电极的厚度决定，既要保证给后续第一电极、第二介质层和第二电极预留足够的沉积空间，又要保证第一介质层14的厚度足以隔离两个相邻凹槽12内的第一电极。优选的，第一介质层14的厚度大于第二介质层的厚度和第二电极的厚度，以使得第一介质层14有足够的支撑能力防止倒塌。
参考图5至图6，在凹槽12底部和第一介质层14内表面形成第一电极15。
在一些实施例中，可采用原子层沉积工艺、物理气相沉积工艺或等离子体沉积工艺等沉积工艺沉积第一电极膜151，第一电极膜151位于凹槽12底部和侧壁以及中间介质层113顶部；采用干法刻蚀或湿法刻蚀去除位于中间介质层113顶部的第一电极膜151，以形成第一电极15。
本实施例中，第一电极15的材料包括氮化钛、氮化钽、铜或钨等金属材料中的任一种或任意组合。此外，采用低功率的干法刻蚀工艺对第一电极膜151进行刻蚀，可提高第一电极15的刻蚀精度。
参考图7，在第一电极15表面形成第二介质层16。
本实施例中，采用化学气相沉积工艺或原子层沉积工艺等方法在第一电极15表面以及基底11顶部表面沉积第二介质层16；其他实施例中，第二介质层也可以覆盖第一电极表面。
本实施例中，第二介质层16的材料包含高K材料。第二介质层16的材料可以与第一介质层14的材料相同也可以不同，本实施例不做限制。
参考图8，在第二介质层16表面形成第二电极17。
在一些实施例中，本实施例中，第二电极17覆盖第二介质层16表面且填充整个凹槽12；在其他实施例中，第二电极覆盖第二介质层表面。其中，第二电极17的材料包括金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛、硅化钛(Titanium Silicide)、硅化镍(Titanium Silicide)、硅氮化钛(TiSi xN y)或者其他导电材料。第二电极17的材料也可以为导电的半导体材料，如多晶硅，锗硅等。
上述半导体结构制备方法中，通过预先沉积一层第一介质层14，使相邻凹槽12内的第一电极15被隔离，避免在沉积第一电极15时因为凹陷区域13的存在导致相邻两个凹槽12内的第一电极15相连接，进而保证电容的有效性。
本申请又一实施例还提供一种半导体结构制备方法，本实施例提供的技术方案与上一实施例大体相同，主要改进之处在于：第二电极位于第一介质层与第一电极相对的另一侧。
图9至图12是本申请又一实施例提供的半导体结构制备方法各步骤对应的结构示意图，与前一实施例相同或者相应的部分，可参考前一实施例的说明，在此不再赘述。
本实施例中，中间介质层213包括支撑层和牺牲层，在一些实施例中，中间介质层213包括位于顶部的第一支撑层221、位于中间的第二支撑层222、位于底部的第三支撑层223，以及位于第一支撑层221和第二支撑层222之间的第一牺牲层231、位于第二支撑层222和第三支撑层223之间的第二牺牲层232。通过在中间介质层213顶部、中间和底部各设置一支撑层，在中间介质层213较厚的情况下，刻蚀形成具有较大深宽比的凹槽22时，也能确保后续形成的第 一介质层24不会塌陷。
在其他实施例中，支撑层和牺牲层的数量和位置不受限制，可以适当增加支撑层和牺牲层的层数，从而提高电容器的高度，进一步提高电容器的电容值。也可以适当减少支撑层的层数，例如包括第一支撑层和第二支撑层。
本实施例中，第一支撑层221、第二支撑层222以及第三支撑层223的材料为氮化硅，第一牺牲层231和第二牺牲层232的材料为氧化硅、BPSG、PSG、BSG和TEOS中的任一种或其任意组合。
参考图10至图11，刻蚀支撑层形成至少暴露部分牺牲层的开口261；通过开口261刻蚀去除牺牲层形成暴露出第一介质层24外表面的空间区域28。
在一些实施例中，图10为本步骤对应的半导体结构俯视结构图，如图10所示，本实施例中，开口261位于各个凹槽22之间，与凹槽22没有公共部分，开口261俯视图为圆形；在其他实施例中，开口也可以为其他形状。
需要说明的是，本实施例中，基底21顶部，即第一支撑层221顶部表面沉积有第二介质层26，在刻蚀支撑层之前，需先刻蚀去除位于第一支撑层221顶部的部分第二介质层26，再刻蚀第一支撑层221形成开口261。
本实施例中，先刻蚀第一支撑层221暴露部分第一牺牲层231，酸洗去除第一牺牲层231暴露出第二支撑层222；再刻蚀第二支撑层222暴露部分第二牺牲层232，酸洗去除第二牺牲层232。其中，可以通过多重图形化光刻工艺定义出开口261的形状，并可采用干法刻蚀工艺刻蚀第二介质层26和第一支撑层221。
参考图12，在第二介质层26表面形成第二电极27。
本实施例中，通过刻蚀去除牺牲层形成暴露出第一介质层24外表面的空间区域28，并在空间区域28和凹槽22内填充第二电极27，使得第二电极27环绕第一电极25内外两侧，如此，有利于增加电容器的电容值。
本申请另一实施例还提供一种半导体结构制备方法，本实施例提供的技术方案与上一实施例大体相同，主要不同之处在于：刻蚀支撑层形成至少暴露部分牺牲层的开口暴露出第一电极，并在暴露的第一电极上沉积第三介质层。
图13为本实施例对应的半导体结构俯视结构图，图14为对应的剖面结 构示意图。
在一些实施例中，如图13和图14所示，开口361与凹槽32有公共部分，刻蚀中间介质层313形成开口361的过程中，刻蚀掉了位于第一电极35顶部的部分第二介质层36，从而暴露出第一电极35顶部表面。
如图15和图16所示，在沉积第二电极37之前，在暴露出的第一电极35顶部沉积第三介质层39。如此，在后续沉积第二电极37时，能够避免第一电极35与第二电极37接触，从而保证电容的有效性。
其中，第三介质层39包含高K材料，例如为Zr、Hf、Nb、Al或O中的任一元素或其任意组合。如此，有利于进一步提高第三介质层39的隔离效果。
本实施例中，开口361暴露出第一电极35部分顶部表面，因此，在沉积第二电极37之前形成覆盖暴露出的第一电极35顶部表面，以避免第一电极35与第二电极37接触，从而保证电容的有效性。
相应的，本申请实施例还提供一种半导体结构，可以采用上述任一方法制作。图16为本申请一实施例提供的半导体结构的剖面结构示意图。
参考图16，本实施例中，半导体结构包括：基底31，基底31具有凹槽32；第一介质层34，第一介质层34位于凹槽32侧壁；第一电极35，第一电极35位于凹槽32底部和第一介质层34内表面；第二介质层36，第二介质层36位于第一电极35表面；第二电极37，第二电极37位于第二介质层36表面。
在一些实施例中，基底31包括衬底311和中间介质层(未标示)；衬底311内设有导电结构312；凹槽32贯穿中间介质层，并暴露出导电结构312。基底31用于承载形成的存储电容，中间介质层用于将各个电容相隔离。
本实施例中，中间介质层具体包括若干个与第一介质层34相连的支撑层314；凹槽32贯穿支撑层314形成支撑层侧面，第一介质层34与支撑层314侧面直接接触。设置在中间介质层内的支撑层314能够保证中间介质层的稳定性，支撑层314可以位于中间介质层的顶部、底部或中部中的任一位置或多个位置，且支撑层314的位置和数量不受限制。
本实施例中，凹槽32侧壁具有凹陷区域33；第一介质层34覆盖凹陷区域33。
本实施例中，凹槽32侧壁凹陷区域33上的第一介质层34与其邻近凹槽32侧壁凹陷区域33上的第一介质层34直接接触；在其他实施例中，凹槽侧壁凹陷区域上的第一介质层与其邻近凹槽侧壁凹陷区域上的第一介质层之间存在间距。
此外，本实施例中，第一介质层34的材料包含高K材料，高K材料包含Zr、Hf、Nb、Al或O中的任一元素或其任意组合。如此，有利于提高相邻凹槽32之间的隔离效果。
本实施例中，第二电极37还位于第一介质层34的外表面。在一些实施例中，第一电极35位于第一介质层34内表面，第二电极37位于第一介质层34外表面。如此，第二电极37能够环绕于第一电极35两侧分布，从而提高电容器的电容值。
本实施例中，半导体结构还包括第三介质层39，第三介质层39位于第一电极35的顶部与第二电极37之间，并与第一电极35和第二电极37直接接触。其中，第三介质层39包含高K材料。
本实施例中，通过第一介质层34将相邻的第一电极35隔离，并且第二电极37环绕整个第一电极35内外，既能够避免相邻第一电极35相连接和第一电极35与第二电极37相连接导致电容失效，同时也能够增加电容器的电容值。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (16)

  1. 一种半导体结构制备方法，包括：
    提供基底；
    在所述基底上形成凹槽；
    在所述凹槽侧壁形成第一介质层；
    在所述凹槽底部和所述第一介质层内表面形成第一电极；
    在所述第一电极表面形成第二介质层；
    在所述第二介质层表面形成第二电极。
  2. 根据权利要求1所述的方法，其中，所述凹槽侧壁具有凹陷区域，所述第一介质层覆盖所述凹陷区域。
  3. 根据权利要求2所述的方法，其中，在所述凹槽侧壁上的凹陷区域形成的所述第一介质层与其邻近凹槽侧壁上的所述第一介质层直接接触。
  4. 根据权利要求1所述的方法，其中，所述第一介质层的材料包含高K材料。
  5. 根据权利要求4所述的方法，其中，所述高K材料包含Zr、Hf、Nb、Al或O中的任一元素或其任意组合。
  6. 根据权利要求1所述的方法，其中，所述基底包括支撑层和牺牲层；
    在所述第一电极表面形成第二介质层之后，在所述第二介质层表面形成第二电极之前，还包括：刻蚀所述支撑层形成至少暴露部分所述牺牲层的开口；
    通过所述开口刻蚀去除所述牺牲层形成暴露出所述第一介质层外表面的空间区域；
    在所述空间区域内形成所述第二电极。
  7. 根据权利要求6所述的方法，其中，所述刻蚀所述支撑层形成至少暴露部分所述牺牲层的开口还包括：所述开口暴露出所述第一电极；
    在所述通过所述开口刻蚀去除所述牺牲层形成暴露出所述第一介质层外表面的空间区域之后，且在所述第二介质层表面形成第二电极之前，还包括：在暴露的所述第一电极上沉积第三介质层。
  8. 一种半导体结构，包括：
    基底，所述基底具有凹槽；
    第一介质层，所述第一介质层位于所述凹槽侧壁；
    第一电极，所述第一电极位于所述凹槽底部和所述第一介质层内表面；
    第二介质层，所述第二介质层位于所述第一电极表面；
    第二电极，所述第二电极位于所述第二介质层表面。
  9. 根据权利要求8所述的结构，其中，所述基底包括支撑层，所述凹槽贯穿所述支撑层形成支撑层侧面，所述第一介质层与所述支撑层侧面直接接触。
  10. 根据权利要求8所述的结构，其中，所述第二电极还位于所述第一介质层的外表面。
  11. 根据权利要求8所述的结构，其中，所述第一介质层的材料包含高K材料。
  12. 根据权利要求11所述的结构，其中，所述高K材料包含Zr、Hf、Nb、Al或O中的任一元素或其任意组合。
  13. 根据权利要求8所述的结构，其中，所述半导体结构还包括第三介质层，所述第三介质层位于所述第一电极的顶部和所述第二电极之间，并与所述第一电极和所述第二电极直接接触。
  14. 根据权利要求13所述的结构，其中，所述第三介质层的材料包含高K材料。
  15. 根据权利要求8所述的结构，其中，所述凹槽侧壁具有凹陷区域；所述第一介质层覆盖所述凹陷区域。
  16. 根据权利要求15所述的结构，其中，所述凹槽侧壁凹陷区域上的所述第一介质层与其邻近凹槽侧壁上的所述第一介质层直接接触。
PCT/CN2021/076099 2020-02-24 2021-02-08 半导体结构制备方法和半导体结构 WO2021169797A1 (zh)

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