WO2021169787A1 - 双面电容结构及其形成方法 - Google Patents

双面电容结构及其形成方法 Download PDF

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Publication number
WO2021169787A1
WO2021169787A1 PCT/CN2021/075945 CN2021075945W WO2021169787A1 WO 2021169787 A1 WO2021169787 A1 WO 2021169787A1 CN 2021075945 W CN2021075945 W CN 2021075945W WO 2021169787 A1 WO2021169787 A1 WO 2021169787A1
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layer
capacitor
substrate
electrode layer
electrode
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PCT/CN2021/075945
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English (en)
French (fr)
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陆勇
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长鑫存储技术有限公司
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Priority to US17/373,904 priority Critical patent/US11984472B2/en
Publication of WO2021169787A1 publication Critical patent/WO2021169787A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • This application relates to the field of semiconductor manufacturing technology, and in particular to a double-sided capacitor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • each memory cell includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the opening and closing of the transistor, so that the storage can be read through the bit line Data information in the capacitor, or write data information into the capacitor.
  • the capacitor can be increased or maintained to have a sufficiently high capacitance value.
  • increasing the height of the bottom electrode or reducing the thickness of the bottom electrode will result in a relatively high length and a thinner thickness of the bottom electrode, which will affect the performance reliability of the capacitor array area. For example, it may cause the lower electrode to collapse or overturn, causing the adjacent lower electrode to short-circuit.
  • the stability of the lower electrode can be increased.
  • the single-layer lateral support layer has its height limit, so that the capacitance value of the capacitor is limited by the electrode height, and the risk of electrode overturning and collapse of the sheet still exists.
  • the present application provides a double-sided capacitor structure and a method for forming the same, which are used to solve the problem of poor lateral stability in the capacitor array region, so as to improve the performance stability of the semiconductor device.
  • the present application provides a method for forming a double-sided capacitor structure, which includes the following steps:
  • a substrate includes a substrate, a capacitor contact located in the substrate, a laminated structure located on the surface of the substrate, and a capacitor hole penetrating the laminated structure and exposing the capacitor contact ,
  • the laminated structure includes a sacrificial layer and a supporting layer alternately stacked in a direction perpendicular to the substrate;
  • a second dielectric layer covering the surface of the second electrode layer and the top surface of the first conductive filling layer and a third electrode layer covering the surface of the second dielectric layer are formed to form a double-sided capacitor structure.
  • the specific steps of filling a conductive material in the capacitor hole include:
  • the conductive material located on the top surface of the laminated structure is removed.
  • the laminated structure includes a first supporting layer, a first sacrificial layer, a second supporting layer, a second sacrificial layer, and a third supporting layer sequentially stacked in a direction perpendicular to the substrate;
  • the specific steps of completely removing several sacrificial layers and/or supporting layers from the top surface of the laminated structure include:
  • the second sacrificial layer is removed.
  • the specific steps of forming a second dielectric layer covering the surface of the second electrode layer and the top surface of the first conductive filling layer, and a third electrode layer covering the surface of the second dielectric layer include:
  • the method further includes the following steps:
  • a second conductive material is deposited on the surface of the third electrode layer to form a second conductive filling layer.
  • the first conductive material and the second conductive material are both polysilicon materials.
  • the present application also provides a double-sided capacitor structure, including:
  • the base includes a substrate, a capacitor contact located in the substrate, a laminated structure located on the surface of the substrate, and a capacitor hole penetrating the laminated structure and exposing the capacitor contact, so
  • the laminated structure includes a sacrificial layer and a supporting layer alternately stacked in a direction perpendicular to the substrate, and the number of the supporting layer is at least two;
  • a first electrode layer covering the inner wall of the capacitor hole and extending out of the laminated structure in a direction perpendicular to the substrate;
  • a first dielectric layer covering the top surface and bottom surface of the first electrode layer and the sidewall surface of the first electrode layer facing the capacitor hole;
  • a second electrode layer covering the top surface and bottom surface of the first dielectric layer and the sidewall surface of the first dielectric layer facing the capacitor hole;
  • the first conductive filling layer is filled in the area surrounded by the second electrode layer;
  • a second dielectric layer covering the surface of the second electrode layer and the surface of the first conductive filling layer
  • the third electrode layer covers the surface of the second dielectric layer.
  • the top surface of the first conductive filling layer is flush with the top surface of the second electrode layer.
  • the second dielectric layer also covers the surface of the support layer on the top layer of the laminated structure.
  • the laminated structure includes a first supporting layer on the surface of the substrate, a first sacrificial layer covering the surface of the first supporting layer, and a second supporting layer covering the surface of the first sacrificial layer Floor;
  • the second dielectric layer covers the surface of the second support layer facing away from the first sacrificial layer.
  • it also includes:
  • the second conductive filling layer covers the surface of the third electrode layer.
  • the materials of the first conductive filling layer and the second conductive filling layer are both polysilicon materials.
  • the double-sided capacitor structure and its forming method provided by the present application on the one hand, fill the first conductive filling layer in the area surrounded by the second electrode layer in the capacitor hole, and perform the first electrode layer and the second electrode layer.
  • the support reducing or even avoiding the risk of electrode collapse and overturning; on the other hand, retaining at least two support layers and the sacrificial layer located between the remaining support layers, further enhance the lateral stability of the capacitor array area, and help To increase the overall height of the electrode layer, thereby further increasing the capacitance value of the capacitor.
  • Fig. 1 is a flowchart of a method for forming a double-sided capacitor structure in a specific embodiment of the present application
  • 2A-2I are schematic cross-sectional views of main processes in the process of forming a double-sided capacitor structure in the specific embodiment of the present application.
  • FIG. 1 is a flowchart of the method for forming a double-sided capacitor structure in a specific embodiment of the application. Schematic diagram of the main process cross-section in the process of the surface capacitor structure.
  • the double-sided capacitor structure described in this specific embodiment can be, but is not limited to, applied to a DRAM memory.
  • the method for forming a double-sided capacitor structure provided in this embodiment includes the following steps:
  • a base is provided.
  • the base includes a substrate, a capacitor contact 20 located in the substrate, a stacked structure 21 located on the surface of the substrate, and a stacked structure 21 penetrating through the stacked structure 21 and exposing the In the capacitor hole 22 of the capacitor contact 20, the laminated structure 21 includes a sacrificial layer and a supporting layer alternately stacked in a direction perpendicular to the substrate, as shown in FIG. 2A.
  • the substrate has a plurality of active regions arranged in an array, and the capacitor contacts 20 are located in the active region.
  • the material of the capacitor contact 20 can be, but is not limited to, tungsten.
  • a plurality of the sacrificial layers and the supporting layers are alternately stacked in a direction perpendicular to the substrate, and the number of layers of the sacrificial layers and the supporting layers alternately stacked can be selected by those skilled in the art according to actual needs.
  • the number of layers of the supporting layer in the stack structure is at least 3, and the number of layers of the sacrificial layer is at least 2, so as to enhance the lateral stability of the capacitor array region.
  • the material of the sacrificial layer may be, but not limited to, an oxide material, such as silicon dioxide; the material of the support layer may be, but not limited to, a nitride material, such as silicon nitride.
  • Step S12 sequentially forming a first electrode layer 23, a first dielectric layer 24, and a second electrode layer 25 stacked along the radial direction of the capacitor hole 22 on the inner wall of the capacitor hole 22, as shown in FIG. 2A and FIG. 2B Shown.
  • the capacitor hole 22 materials such as titanium nitride are deposited on the inner wall of the capacitor hole 22 and the top surface of the laminated structure 21 (that is, the laminated structure is away from the substrate).
  • the first electrode layer 23 is formed, as shown in FIG. 2A; then, a dielectric layer material with a high dielectric constant is deposited on the surface of the first electrode layer 23 to form the first dielectric layer 24; then , Depositing materials such as titanium nitride on the surface of the first dielectric layer 24 to form the second electrode layer 25, as shown in FIG. 2B.
  • Step S13 filling the capacitor hole 22 with a first conductive material to form a first conductive filling layer 26, as shown in FIG. 2C.
  • the specific steps of filling a conductive material in the capacitor hole 22 include:
  • the conductive material on the top surface of the laminated structure 21 is removed.
  • a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process may be used to deposit the first conductive material in the capacitor hole 22 to form the capacitor hole 22 (that is, the second electrode).
  • the layer 25 surrounds the capacitor hole 22) and covers the second electrode layer 25 on the surface of the laminated structure 21, as shown in FIG. 2C.
  • the first conductive material may be a metal material or a polysilicon material, and those skilled in the art can make a selection according to actual needs.
  • step S14 several sacrificial layers and/or supporting layers are completely removed from the top surface of the laminated structure 21, so that at least two supporting layers remain, as shown in FIG. 2G.
  • the laminated structure 21 includes a first supporting layer 211, a first sacrificial layer 212, a second supporting layer 213, a second sacrificial layer 214, and a third supporting layer 211, which are sequentially stacked in a direction perpendicular to the substrate.
  • the specific steps of completely removing several layers of sacrificial layers and/or supporting layers from the top surface of the laminated structure 21 include:
  • the second sacrificial layer 214 is removed.
  • the first supporting layer 211, the first sacrificial layer 212, the second supporting layer 213, the second sacrificial layer 214, and the third supporting layer 215 are directed to all directions along the substrate.
  • the directions of the stacked structure 21 are stacked one after another.
  • the second electrode layer 25 is used as an etching medium layer, and the first conductive filling layer 26 covering the surface of the second electrode layer 25 is removed, and only the first conductive filling layer 26 located on the surface of the second electrode layer 25 remains
  • the first conductive filling layer 26 in the capacitor hole 22 makes the top surface of the remaining first conductive filling layer 26 flush with the top surface of the second electrode layer 25, and the resulting structure is as shown in FIG. 2D Show.
  • a photoresist layer 27 is formed on the surface of the first conductive filling layer 26, and an opening 271 for exposing the second electrode layer 25 is formed between adjacent photoresist layers 27, as shown in FIG. 2E.
  • the second electrode layer 25, the first dielectric layer 24, and the first electrode layer 23 are sequentially etched from the opening 271 using a dry etching process or a wet etching process to expose the first electrode layer.
  • the third supporting layer 215 and the second sacrificial layer 214 are sequentially etched to expose the second supporting layer 213, as shown in FIG. 2F.
  • FIG. 2G After removing the photoresist layer 27, a structure as shown in FIG. 2G is obtained.
  • the above are just examples.
  • those skilled in the art can also form more than four layers of the sacrificial layer; during the etching process, those skilled in the art can also retain three or four layers of support according to actual needs.
  • Floor By properly setting the thickness of the third supporting layer 215 and the second sacrificial layer 214, the first electrode layer 23 can be extended after the third supporting layer 215 and the second sacrificial layer 214 are removed. The height of the second support layer 213 is shown.
  • the first electrode layer 23 and the first The lateral stability of the dielectric layer 24 and the second electrode layer 25 can effectively prevent the first electrode layer 23, the first dielectric layer 24 and the second electrode layer 25 from collapsing or overturning.
  • this step does not remove all the sacrificial layer and the supporting layer, at least two layers of the supporting layer and the sacrificial layer located between the two adjacent supporting layers are retained, which reduces the support.
  • the layer height limit limits the height of the first electrode layer 23, so that the height of the first electrode layer 23 can be further increased, thereby helping to further increase the capacitance value of the double-sided capacitor structure.
  • Step S15 forming a second dielectric layer 28 covering the surface of the second electrode layer 25 and the top surface of the first conductive filling layer 26, and a third electrode layer 29 covering the surface of the second dielectric layer 28, A double-sided capacitor structure is formed, as shown in Figure 2H.
  • a second dielectric layer 28 covering the surface of the second electrode layer 25 and the top surface of the first conductive filling layer 26, and a third electrode layer 29 covering the surface of the second dielectric layer 28 are formed
  • the specific steps include:
  • a second dielectric layer 28 covering the surface of the second electrode layer 25, the top surface of the first conductive filling layer 26, and the exposed surface of the second support layer 213 is formed, and the second dielectric layer 28 is covered and covered with the second dielectric layer 28.
  • the first conductive material and the second conductive material are both polysilicon materials.
  • the method further includes the following steps:
  • a second conductive material is deposited on the surface of the third electrode layer 29 to form a second conductive filling layer 30, as shown in FIG. 2I.
  • the first electrode layer 23, the first dielectric layer 24, and the second electrode layer 25 are perpendicular to the
  • the second supporting layer 213 extends from the direction of the substrate, thereby forming a gap exposing the second supporting layer 213 between adjacent capacitors.
  • a second conductive material is deposited on the surface of the third electrode layer 29, and the formed second conductive filling layer 30 fills the gaps and covers the surface of the third electrode layer 29 above the capacitor hole 22.
  • this specific embodiment also provides a double-sided capacitor structure.
  • the double-sided capacitor structure provided in this embodiment can be formed by the method shown in FIGS. 1 and 2A-2I. As shown in FIG. 2I, the double-sided capacitor structure provided by this embodiment includes:
  • the base includes a substrate, a capacitor contact 20 located in the substrate, a stacked structure 21 located on the surface of the substrate, and a layer penetrating through the stacked structure 21 and exposing the capacitor contact 20
  • Capacitor holes 22 the laminated structure 21 includes sacrificial layers and support layers alternately stacked in a direction perpendicular to the substrate, and the number of the support layers is at least two;
  • the first electrode layer 23 covers the inner wall of the capacitor hole 22 and extends from the laminated structure 21 in a direction perpendicular to the substrate;
  • the first dielectric layer 24 covers the top surface and the bottom surface of the first electrode layer 23 and the sidewall surface of the first electrode layer 23 facing the capacitor hole 22;
  • the second electrode layer 25 covers the top surface and the bottom surface of the first dielectric layer 24 and the sidewall surface of the first dielectric layer 24 facing the capacitor hole 22;
  • the first conductive filling layer 26 is filled in the area surrounded by the second electrode layer 25;
  • the second dielectric layer 28 covers the surface of the second electrode layer 25 and the surface of the first conductive filling layer 26;
  • the third electrode layer 29 covers the surface of the second dielectric layer 28.
  • the top surface of the first conductive filling layer 26 is flush with the top surface of the second electrode layer 25.
  • the second dielectric layer 28 also covers the surface of the support layer on the top layer of the laminated structure 21.
  • the laminated structure 21 includes a first supporting layer 211 on the surface of the substrate, a first sacrificial layer 212 covering the surface of the first supporting layer 211, and a first sacrificial layer 212 covering the first sacrificial layer 212
  • the second dielectric layer 28 covers the surface of the second support layer 213 away from the first sacrificial layer 212.
  • the material of the first supporting layer 211 and the second supporting layer 213 may be the same, for example, both are nitride materials; the material of the first sacrificial layer 212 may be an oxide material.
  • the thickness of the first sacrificial layer 212 is greater than the thickness of the first supporting layer 211 and the thickness of the second supporting layer 213.
  • the double-sided capacitor structure further includes:
  • the second conductive filling layer 30 covers the surface of the third electrode layer 29.
  • the material of the first conductive filling layer 26 may be the same as or different from the material of the second conductive filling layer 30.
  • the materials of the first conductive filling layer 26 and the second conductive filling layer 30 are both polysilicon materials.
  • the first electrode layer 23 extends beyond the height of the stacked structure 21 in a direction perpendicular to the substrate, which can be set by those skilled in the art according to actual needs, for example, it may be greater than, equal to, or less than the first electrode layer.
  • An electrode layer 23 extends to the height inside the laminated structure 21.
  • the double-sided capacitor structure and the method for forming the same provided in this embodiment, on the one hand, by filling the first conductive filling layer in the area surrounded by the second electrode layer in the capacitor hole, the first electrode layer and the second electrode
  • the layer is supported, reducing or even avoiding the risk of electrode collapse and overturning; on the other hand, retaining at least two supporting layers and the sacrificial layer located between the remaining supporting layers further enhances the lateral stability of the capacitor array area, and It helps to increase the overall height of the electrode layer, thereby further increasing the capacitance value of the capacitor.

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Abstract

本申请涉及一种双面电容结构及其形成方法。所述双面电容结构的形成方法包括：提供一基底，所述基底包括衬底、位于所述衬底内的电容触点、位于所述衬底表面的叠层结构、以及贯穿所述叠层结构并暴露所述电容触点的电容孔，所述叠层结构包括沿垂直于所述衬底的方向交替堆叠的牺牲层和支撑层；依次形成第一电极层、第一电介质层和第二电极层于所述电容孔的内壁；填充第一导电材料于所述电容孔内，形成第一导电填充层；完全去除若干层牺牲层和/或支撑层，使得至少残留两层支撑层；形成第二电介质层、以及覆盖与所述第二电介质层表面的第三电极层。本申请减少甚至是避免了电极坍塌和倾覆的风险，同时有助于增大电容器的电容值。

Description

双面电容结构及其形成方法
相关申请引用说明
本申请要求于2020年2月27日递交的中国专利申请号202010123241.0、申请名为“双面电容结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种双面电容结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体结构，其由多个存储单元构成，每个存储单元包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启与关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
随着半导体器件尺寸的微缩，其在衬底上的横向面积减小。通过增加下电极(bottom electrode)的高度或者是减小下电极的厚度，能够提高或者维持电容器具有足够高的电容值。但是，增加下电极的高度或者是减小下电极的厚度会导致下电极的长径比较高，厚度较薄，从而对电容阵列区域的性能可靠性造成影响。比如，会引起下电极的坍塌或者倾覆，导致相邻的下电极短路。
通过添加电极的横向连续支撑层，能够增加下电极的稳定性。但是，单层的横向支撑层有其高度极限，从而使得电容器的电容值受到电极高度的限制，电极倾覆和成片坍塌的风险依然存在。
因此，如何解决电容阵列区域横向不稳定的问题，减小下电极坍塌或者倾覆的风险，提高半导体器件的性能稳定性，是目前亟待解决的技术问题。
发明内容
本申请提供一种双面电容结构及其形成方法，用于解决电容阵列区域横向稳定性较差的问题，以提高半导体器件的性能稳定性。
为了解决上述问题，本申请提供了一种双面电容结构的形成方法，包括如下步骤：
提供一基底，所述基底包括衬底、位于所述衬底内的电容触点、位于所述衬底表面的叠层结构、以及贯穿所述叠层结构并暴露所述电容触点的电容孔，所述叠层结构包括沿垂直于所述衬底的方向交替堆叠的牺牲层和支撑层；
依次形成沿所述电容孔的径向方向叠置的第一电极层、第一电介质层和第二电极层于所述电容孔的内壁；
填充第一导电材料于所述电容孔内，形成第一导电填充层；
自所述叠层结构的顶面完全去除若干层牺牲层和/或支撑层，使得至少残留两层支撑层；
形成覆盖于所述第二电极层表面和所述第一导电填充层顶面的第二电介质层、以及覆盖与所述第二电介质层表面的第三电极层，形成双面电容结构。
可选的，填充导电材料于所述电容孔内的具体步骤包括：
沉积第一导电材料于所述电容孔内和位于所述叠层结构顶面；
去除位于所述叠层结构顶面的所述导电材料。
可选的，所述叠层结构包括沿垂直于所述衬底的方向依次叠置的第一支撑层、第一牺牲层、第二支撑层、第二牺牲层和第三支撑层；自所述叠层结构的顶面完全去除若干层牺牲层和/或支撑层的具体步骤包括：
去除覆盖于所述叠层结构顶面的所述第二电极层、所述第一电介质层和所述第一电极层，暴露所述第三支撑层；
去除所述第三支撑层，暴露所述第二牺牲层；
去除所述第二牺牲层。
可选的，形成覆盖于所述第二电极层表面和所述第一导电填充层顶面的第二电介质层、以及覆盖与所述第二电介质层表面的第三电极层的具体步骤包括：
形成覆盖于所述第二电极层表面、所述第一导电填充层顶面和暴露的所述第二支撑层表面的第二电介质层、以及覆盖与所述第二电介质层表面的第三电极层。
可选的，形成双面电容结构之后，还包括如下步骤：
沉积第二导电材料于所述第三电极层表面，形成第二导电填充层。
可选的，所述第一导电材料和所述第二导电材料均为多晶硅材料。
为了解决上述问题，本申请还提供了一种双面电容结构，包括：
基底，所述基底包括衬底、位于所述衬底内的电容触点、位于所述衬底表面的叠层结构、以及贯穿所述叠层结构并暴露所述电容触点的电容孔，所述叠层结构包括沿垂直于所述衬底的方向交替堆叠的牺牲层和支撑层，所述支撑层的数量至少为两层；
第一电极层，覆盖于所述电容孔内壁并沿垂直于所述衬底的方向延伸出所述叠层结构；
第一电介质层，覆盖于所述第一电极层的顶面、底面和所述第一电极层朝向所述电容孔的侧壁表面；
第二电极层，覆盖于所述第一电介质层的顶面、底面和所述第一电介质层朝向所述电容孔的侧壁表面；
第一导电填充层，填充于所述第二电极层围绕而成的区域内；
第二电介质层，覆盖所述第二电极层表面和所述第一导电填充层表面；
第三电极层，覆盖所述第二电介质层表面。
可选的，所述第一导电填充层的顶面与所述第二电极层的顶面平齐。
可选的，所述第二电介质层还覆盖位于所述叠层结构顶层的支撑层表面。
可选的，所述叠层结构包括位于所述衬底表面的第一支撑层、覆盖于所述第一支撑层表面的第一牺牲层和覆盖于所述第一牺牲层表面的第二支撑层；
所述第二电介质层覆盖所述第二支撑层背离所述第一牺牲层的表面。
可选的，还包括：
第二导电填充层，覆盖于所述第三电极层表面。
可选的，所述第一导电填充层和所述第二导电填充层的材料均为多晶硅材料。
本申请提供的双面电容结构及其形成方法，一方面，通过在电容孔内的第二电极层围绕而成的区域内填充第一导电填充层，对第一电极层和第二电极层进行了支撑，减少甚至是避免了电极坍塌和倾覆的风险；另一方面，保留至少两层支撑层以及位于残留的支撑层之间的牺牲层，进一步增强了电容阵列区域横向稳定性，而且有助于提高电极层的整体高度，从而进一步增大电容器的电容值。
附图说明
附图1是本申请具体实施方式中双面电容结构的形成方法流程图；
附图2A-2I是本申请具体实施方式在形成双面电容结构的过程中主要的工艺截面示意图。
具体实施方式
下面结合附图对本申请提供的双面电容结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种双面电容结构的形成方法，附图1是本申请具体实施方式中双面电容结构的形成方法流程图，附图2A-2I是本申请具体实施方式在形成双面电容结构的过程中主要的工艺截面示意图。本具体实施方式中所述的双面电容结构可以是但不限于应用于DRAM存储器中。如图1、图2A-图2I所示，本具体实施方式提供的双面电容结构的形成方法，包括如下步骤：
步骤S11，提供一基底，所述基底包括衬底、位于所述衬底内的电容触点20、位于所述衬底表面的叠层结构21、以及贯穿所述叠层结构21并暴露所述电容触点20的电容孔22，所述叠层结构21包括沿垂直于所述衬底的方向交替堆叠的牺牲层和支撑层，如图2A所示。
具体来说，所述衬底内部具有呈阵列排布的多个有源区，所述电容触点20位于所述有源区内。所述电容触点20的材料可以是但不限于钨。多个所述牺牲层和所述支撑层沿垂直于所述衬底的方向交替堆叠，所述牺牲层和所述支撑层交替堆叠的层数，本领域技术人员可以根据实际需要进行选择。在本具体实施方式中，所述堆叠结构中所述支撑层的层数至少为3层，所述牺牲层的层数至少为2层，以便于增强电容阵列区域的横向稳定性。所述牺牲层的材料可以是但不限于氧化物材料，例如二氧化硅；所述支撑层的材料可以是但不限于氮化物材料，例如氮化硅。
步骤S12，依次形成沿所述电容孔22的径向方向叠置的第一电极层23、第一电介质层24和第二电极层25于所述电容孔22的内壁，如图2A、图2B所示。
具体来说，在形成所述电容孔22之后，沉积氮化钛等材料于所述电容孔22的内壁和所述叠层结构21的顶面(即所述叠层结构背离所述衬底的表面)， 形成所述第一电极层23，如图2A所示；然后，沉积具有高介电常数的电介质层材料于所述第一电极层23表面，形成所述第一电介质层24；接着，沉积氮化钛等材料于所述第一电介质层24表面，形成所述第二电极层25，如图2B所示。
步骤S13，填充第一导电材料于所述电容孔22内，形成第一导电填充层26，如图2C所示。
可选的，填充导电材料于所述电容孔22内的具体步骤包括：
沉积第一导电材料于所述电容孔22内和位于所述叠层结构21顶面；
去除位于所述叠层结构21顶面的所述导电材料。
具体来说，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沉积所述第一导电材料于所述电容孔22内，形成填充满所述电容孔22(即所述第二电极层25在所述电容孔22内围绕而成的区域)并覆盖于所述叠层结构21表面的所述第二电极层25之上，如图2C所示。所述第一导电材料可以是金属材料，也可以是多晶硅材料，本领域技术人员可以根据实际需要进行选择。
步骤S14，自所述叠层结构21的顶面完全去除若干层牺牲层和/或支撑层，使得至少残留两层支撑层，如图2G所示。
可选的，所述叠层结构21包括沿垂直于所述衬底的方向依次叠置的第一支撑层211、第一牺牲层212、第二支撑层213、第二牺牲层214和第三支撑层215；自所述叠层结构21的顶面完全去除若干层牺牲层和/或支撑层的具体步骤包括：
去除覆盖于所述叠层结构21顶面的所述第二电极层25、所述第一电介质层24和所述第一电极层23，暴露所述第三支撑层215；
去除所述第三支撑层215，暴露所述第二牺牲层214；
去除所述第二牺牲层214。
举例来说，所述第一支撑层211、所述第一牺牲层212、所述第二支撑层213、所述第二牺牲层214和所述第三支撑层215沿所述衬底指向所述叠层结构21的方向依次叠置。在形成如图2C所示的结构之后，以所述第二电极层25为刻蚀介质层，去除覆盖于所述第二电极层25表面的所述第一导电填充层 26，仅保留位于所述电容孔22内的所述第一导电填充层26，使得残留的所述第一导电填充层26的顶面与所述第二电极层25的顶面平齐，得到的结构如图2D所示。之后，形成光阻层27于所述第一导电填充层26表面，相邻所述光阻层27之间具有暴露所述第二电极层25的开口271，如图2E所示。然后，采用干法刻蚀工艺或者湿法刻蚀工艺自所述开口271依次刻蚀所述第二电极层25、所述第一电介质层24和所述第一电极层23，暴露所述第三支撑层215。接着，依次刻蚀所述第三支撑层215和所述第二牺牲层214，暴露所述第二支撑层213，如图2F所示。去除所述光阻层27之后，得到如图2G所示的结构。以上仅是举例说明，在实际应用过程中，本领域技术人员也可以形成四层以上的所述牺牲层；在刻蚀过程中，本领域技术人员也可以根据实际需要保留三层或者四层支撑层。通过合理设置所述第三支撑层215和所述第二牺牲层214的厚度，可以灵活调整去除所述第三支撑层215和所述第二牺牲层214之后，所述第一电极层23延伸出所述第二支撑层213的高度。
在本步骤去除若干层牺牲层和/或支撑层的过程中，由于所述电容孔22内填充满所述第一导电填充层26，从而增强了所述第一电极层23、所述第一电介质层24和所述第二电极层25的横向稳定性，可以有效的避免所述第一电极层23、所述第一电介质层24和所述第二电极层25出现坍塌或者倾覆。同时，由于本步骤并没有去除所有的所述牺牲层和所述支撑层，保留了至少两层所述支撑层以及位于被保留的相邻的两层支撑层之间的牺牲层，降低了支撑层高度极限对所述第一电极层23高度的限制，使得所述第一电极层23的高度能够进一步提升，从而有助于进一步增大所述双面电容结构的电容值。
步骤S15，形成覆盖于所述第二电极层25表面和所述第一导电填充层26顶面的第二电介质层28、以及覆盖与所述第二电介质层28表面的第三电极层29，形成双面电容结构，如图2H所示。
可选的，形成覆盖于所述第二电极层25表面和所述第一导电填充层26顶面的第二电介质层28、以及覆盖与所述第二电介质层28表面的第三电极层29的具体步骤包括：
形成覆盖于所述第二电极层25表面、所述第一导电填充层26顶面和暴露的所述第二支撑层213表面的第二电介质层28、以及覆盖与所述第二电介质层 28表面的第三电极层29。
可选的，所述第一导电材料和所述第二导电材料均为多晶硅材料。
可选的，形成双面电容结构之后，还包括如下步骤：
沉积第二导电材料于所述第三电极层29表面，形成第二导电填充层30，如图2I所示。
具体来说，在去除所述第三支撑层215和所述第二牺牲层214之后，所述第一电极层23、所述第一电介质层24和所述第二电极层25沿垂直于所述衬底的方向延伸出所述第二支撑层213，从而在相邻电容器之间形成了暴露所述第二支撑层213的空隙。沉积第二导电材料于所述第三电极层29的表面，形成的所述第二导电填充层30填充满所述空隙并覆盖位于所述电容孔22上方的所述第三电极层29表面。
不仅如此，本具体实施方式还提供了一种双面电容结构。本具体实施方式提供的双面电容结构可以采用如图1、图2A-图2I所示的方法形成。如图2I所示，本具体实施方式提供的双面电容结构，包括：
基底，所述基底包括衬底、位于所述衬底内的电容触点20、位于所述衬底表面的叠层结构21、以及贯穿所述叠层结构21并暴露所述电容触点20的电容孔22，所述叠层结构21包括沿垂直于所述衬底的方向交替堆叠的牺牲层和支撑层，所述支撑层的数量至少为两层；
第一电极层23，覆盖于所述电容孔22内壁并沿垂直于所述衬底的方向延伸出所述叠层结构21；
第一电介质层24，覆盖于所述第一电极层23的顶面、底面和所述第一电极层23朝向所述电容孔22的侧壁表面；
第二电极层25，覆盖于所述第一电介质层24的顶面、底面和所述第一电介质层24朝向所述电容孔22的侧壁表面；
第一导电填充层26，填充于所述第二电极层25围绕而成的区域内；
第二电介质层28，覆盖所述第二电极层25表面和所述第一导电填充层26表面；
第三电极层29，覆盖所述第二电介质层28表面。
可选的，所述第一导电填充层26的顶面与所述第二电极层25的顶面平齐。
可选的，所述第二电介质层28还覆盖位于所述叠层结构21顶层的支撑层表面。
可选的，所述叠层结构21包括位于所述衬底表面的第一支撑层211、覆盖于所述第一支撑层211表面的第一牺牲层212和覆盖于所述第一牺牲层212表面的第二支撑层213；
所述第二电介质层28覆盖所述第二支撑层213背离所述第一牺牲层212的表面。
其中，所述第一支撑层211与所述第二支撑层213的材料可以相同，例如均为氮化物材料；所述第一牺牲层212的材料可以为氧化物材料。所述第一牺牲层212的厚度大于所述第一支撑层211的厚度、以及所述第二支撑层213的厚度。
可选的，所述双面电容结构还包括：
第二导电填充层30，覆盖于所述第三电极层29表面。
所述第一导电填充层26的材料可以与所述第二导电填充层30的材料相同，也可以不同。为了进一步简化双面电容结构的制造工序，可选的，所述第一导电填充层26和所述第二导电填充层30的材料均为多晶硅材料。
其中，所述第一电极层23沿垂直于所述衬底的方向延伸出所述叠层结构21的高度，本领域技术人员可以根据实际需要进行设置，例如可以大于、等于或者小于所述第一电极层23延伸至所述叠层结构21内部的高度。
本具体实施方式提供的双面电容结构及其形成方法，一方面，通过在电容孔内的第二电极层围绕而成的区域内填充第一导电填充层，对第一电极层和第二电极层进行了支撑，减少甚至是避免了电极坍塌和倾覆的风险；另一方面，保留至少两层支撑层以及位于残留的支撑层之间的牺牲层，进一步增强了电容阵列区域横向稳定性，而且有助于提高电极层的整体高度，从而进一步增大电容器的电容值。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (12)

  1. 一种双面电容结构的形成方法，包括：
    提供一基底，所述基底包括衬底、位于所述衬底内的电容触点、位于所述衬底表面的叠层结构、以及贯穿所述叠层结构并暴露所述电容触点的电容孔，所述叠层结构包括沿垂直于所述衬底的方向交替堆叠的牺牲层和支撑层；
    依次形成沿所述电容孔的径向方向叠置的第一电极层、第一电介质层和第二电极层于所述电容孔的内壁；
    填充第一导电材料于所述电容孔内，形成第一导电填充层；
    自所述叠层结构的顶面完全去除若干层牺牲层和/或支撑层，使得至少残留两层支撑层；
    形成覆盖于所述第二电极层表面和所述第一导电填充层顶面的第二电介质层、以及覆盖与所述第二电介质层表面的第三电极层，形成双面电容结构。
  2. 根据权利要求1所述的方法，其中，填充导电材料于所述电容孔内的具体步骤包括：
    沉积第一导电材料于所述电容孔内和位于所述叠层结构顶面；
    去除位于所述叠层结构顶面的所述导电材料。
  3. 根据权利要求1所述的方法，其中，所述叠层结构包括沿垂直于所述衬底的方向依次叠置的第一支撑层、第一牺牲层、第二支撑层、第二牺牲层和第三支撑层；自所述叠层结构的顶面完全去除若干层牺牲层和/或支撑层的具体步骤包括：
    去除覆盖于所述叠层结构顶面的所述第二电极层、所述第一电介质层和所述第一电极层，暴露所述第三支撑层；
    去除所述第三支撑层，暴露所述第二牺牲层；
    去除所述第二牺牲层。
  4. 根据权利要求3所述的方法，其中，形成覆盖于所述第二电极层表面和所述第一导电填充层顶面的第二电介质层、以及覆盖与所述第二电介质层表面的第三电极层的具体步骤包括：
    形成覆盖于所述第二电极层表面、所述第一导电填充层顶面和暴露的所述第二支撑层表面的第二电介质层、以及覆盖与所述第二电介质层表面的第三电极层。
  5. 根据权利要求4所述的方法，其中，形成双面电容结构之后，还包括如下步骤：
    沉积第二导电材料于所述第三电极层表面，形成第二导电填充层。
  6. 根据权利要求5所述的方法，其中，所述第一导电材料和所述第二导电材料均为多晶硅材料。
  7. 一种双面电容结构，包括：
    基底，所述基底包括衬底、位于所述衬底内的电容触点、位于所述衬底表面的叠层结构、以及贯穿所述叠层结构并暴露所述电容触点的电容孔，所述叠层结构包括沿垂直于所述衬底的方向交替堆叠的牺牲层和支撑层，所述支撑层的数量至少为两层；
    第一电极层，覆盖于所述电容孔内壁并沿垂直于所述衬底的方向延伸出所述叠层结构；
    第一电介质层，覆盖于所述第一电极层的顶面、底面和所述第一电极层朝向所述电容孔的侧壁表面；
    第二电极层，覆盖于所述第一电介质层的顶面、底面和所述第一电介质层朝向所述电容孔的侧壁表面；
    第一导电填充层，填充于所述第二电极层围绕而成的区域内；
    第二电介质层，覆盖所述第二电极层表面和所述第一导电填充层表面；
    第三电极层，覆盖所述第二电介质层表面。
  8. 根据权利要求7所述的结构，其中，所述第一导电填充层的顶面与所述第二电极层的顶面平齐。
  9. 根据权利要求8所述的结构，其中，所述第二电介质层还覆盖位于所述叠层结构顶层的支撑层表面。
  10. 根据权利要求9所述的结构，其中，所述叠层结构包括位于所述衬底表面的第一支撑层、覆盖于所述第一支撑层表面的第一牺牲层和覆盖于所述第 一牺牲层表面的第二支撑层；
    所述第二电介质层覆盖所述第二支撑层背离所述第一牺牲层的表面。
  11. 根据权利要求7所述的结构，还包括：
    第二导电填充层，覆盖于所述第三电极层表面。
  12. 根据权利要求11所述的结构，其中，所述第一导电填充层和所述第二导电填充层的材料均为多晶硅材料。
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