WO2021244466A1 - 双面电容结构及其形成方法 - Google Patents

双面电容结构及其形成方法 Download PDF

Info

Publication number
WO2021244466A1
WO2021244466A1 PCT/CN2021/097161 CN2021097161W WO2021244466A1 WO 2021244466 A1 WO2021244466 A1 WO 2021244466A1 CN 2021097161 W CN2021097161 W CN 2021097161W WO 2021244466 A1 WO2021244466 A1 WO 2021244466A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
capacitor
forming
double
sub
Prior art date
Application number
PCT/CN2021/097161
Other languages
English (en)
French (fr)
Inventor
陆勇
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/503,607 priority Critical patent/US11894419B2/en
Publication of WO2021244466A1 publication Critical patent/WO2021244466A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/88—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Definitions

  • This application relates to the field of semiconductor manufacturing technology, and in particular to a double-sided capacitor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor for storing charges and a transistor for accessing the capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the opening and closing of the transistor, so that the storage can be read through the bit line.
  • DRAM stores data in the form of the charge on the capacitor, so the capacitor needs to be recharged regularly every few milliseconds. The larger the capacitance value of the capacitor, the data stored in the DRAM can be maintained. The longer.
  • the present application provides a double-sided capacitor structure and a forming method thereof, which are used to solve the problem of poor stability of the existing double-sided capacitor structure, so as to improve the performance of the double-sided capacitor structure and increase the yield of DRAM.
  • the present application provides a method for forming a double-sided capacitor structure, which includes the following steps:
  • the stacked structure including a sacrificial layer and a supporting layer alternately stacked;
  • a dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the surface of the dielectric layer are formed, and the gap is filled with at least the dielectric layer.
  • the specific steps of forming a laminated structure on the substrate include:
  • a first supporting layer, a first sacrificial layer, a second supporting layer, a second sacrificial layer, and a third supporting layer are sequentially deposited on the substrate from bottom to top to form the laminated structure, and the laminated structure covers the Capacitor contacts.
  • the method before removing a part of the supporting layer on the top of the laminated structure, the method further includes the following steps:
  • a filling layer is formed on the surface of the first electrode layer, and the capacitor hole is filled.
  • the material of the filling layer is carbon or a carbon-containing organic material.
  • the specific step of forming the opening to expose the sacrificial layer includes:
  • the third supporting layer is etched to form at least one opening to expose the second sacrificial layer, and each of the openings partially overlaps with at least one of the capacitor holes.
  • the specific step of simultaneously removing the sacrificial layer and the auxiliary layer along the opening includes:
  • the specific steps of forming a dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the surface of the dielectric layer include:
  • a second electrode layer covering the surface of the first sub-dielectric layer and the surface of the second sub-dielectric layer is formed.
  • the second sub-dielectric layer is further formed in the gap and covers the surface of the first sub-dielectric layer, and the second electrode layer covers the surface of the second sub-dielectric layer.
  • the auxiliary layer has a single-layer structure; or,
  • the auxiliary layer is a multilayer structure stacked along the radial direction of the capacitor hole.
  • the auxiliary layer and the sacrificial layer are made of the same material.
  • the materials of the auxiliary layer and the sacrificial layer are both silicon dioxide.
  • the present application also provides a double-sided capacitor structure, including:
  • a substrate, the surface of the substrate has capacitive contacts
  • the top support layer and the middle support layer each have a number of capacitor openings, and on a plane parallel to the substrate, the projected area of the middle support layer is larger than the projected area of the top support layer;
  • the first electrode layer is in the shape of a hollow column with a top opening perpendicular to the surface of the substrate and penetrates the top support layer and the middle support layer through the capacitor openings.
  • the bottom of the first electrode layer is in contact with the capacitor Point connection
  • a dielectric layer covering the surface of the first electrode layer, the top support layer and the middle support layer;
  • the second electrode layer covers the surface of the dielectric layer.
  • the projections of the capacitor openings in the middle support layer and the top support layer on the substrate overlap.
  • the dielectric layer includes:
  • the second sub-dielectric layer covers at least the inner surface of the first electrode layer.
  • the second sub-dielectric layer further covers the surface of the first sub-dielectric layer, and the second electrode layer covers the surface of the second sub-dielectric layer.
  • the material of the first sub-dielectric layer and the material of the second sub-dielectric layer are the same.
  • the thickness of the first sub-dielectric layer and the thickness of the second sub-dielectric layer are the same.
  • it also includes:
  • the conductive layer covers the surface of the second electrode layer.
  • the auxiliary layer is formed before the sidewall of the capacitor hole, and then after opening the supporting layer on the top of the laminated structure, the auxiliary layer and the auxiliary layer are removed simultaneously by selecting a suitable etching reagent.
  • All the sacrificial layers in the laminated structure do not need to etch the other supporting layers in the laminated structure, so that the supporting layer located in the middle of the laminated structure can simultaneously perform on opposite sides of a double-sided capacitor Support, on the one hand, can improve the lateral stability of the double-sided capacitor structure, thereby improving the yield of DRAM; on the other hand, because it can reduce the etching steps of the support layer in the stacked structure, it helps to simplify the double-sided capacitor.
  • the formation process of the structure shortens the process time.
  • Fig. 1 is a flowchart of a method for forming a double-sided capacitor structure in a specific embodiment of the present application
  • Figures 2A-2L are schematic cross-sectional views of main processes in the process of forming a double-sided capacitor structure in a specific embodiment of the present application.
  • FIG. 1 is a flowchart of the method for forming a double-sided capacitor structure in a specific embodiment of the application.
  • the double-sided capacitor structure described in this specific embodiment can be, but is not limited to, applied to a DRAM memory.
  • the method for forming a double-sided capacitor structure provided by this embodiment includes the following steps:
  • step S11 a substrate is provided, and capacitor contacts 21 are formed on the surface of the substrate, as shown in FIG. 2A.
  • Step S12 forming a laminated structure 20 on the substrate and covering the capacitor contact 21.
  • Step S13 forming a capacitor hole 22 in a direction perpendicular to the substrate, penetrating the laminated structure 20 and exposing the capacitor contact 21.
  • the laminated structure 20 includes a sacrificial layer and a supporting layer alternately stacked, such as Shown in Figure 2A.
  • the specific steps of forming the laminated structure 20 on the substrate include:
  • a first supporting layer 201, a first sacrificial layer 202, a second supporting layer 203, a second sacrificial layer 204, and a third supporting layer 205 are sequentially deposited on the substrate from bottom to top to form the laminated structure 20, the The laminated structure 20 covers the capacitor contact 21, as shown in FIG. 2A.
  • the substrate has a plurality of active regions arranged in an array, and the capacitor contacts 21 are connected to the active regions.
  • the material of the substrate may be but not limited to silicon, and the material of the capacitor contact 21 may be but not limited to tungsten.
  • a plurality of the sacrificial layers and the supporting layers are alternately stacked in a direction perpendicular to the substrate, and the number of layers of the sacrificial layers and the supporting layers alternately stacked can be selected by those skilled in the art according to actual needs.
  • the number of layers of the supporting layer in the laminated structure 20 is at least 3, and the number of layers of the sacrificial layer is at least 2, so as to enhance the lateral stability of the capacitor array area.
  • the material of the sacrificial layer may be, but not limited to, an oxide material, such as silicon dioxide; the material of the support layer may be, but not limited to, a nitride material, such as silicon nitride.
  • the stacked structure 20 can be etched by a dry etching process to form all the layers that penetrate the stacked structure 20 and expose the capacitor contacts 21. ⁇ Capacitive hole 22.
  • step S14 an auxiliary layer 23 is formed to cover the sidewall of the capacitor hole 22, as shown in FIG. 2C.
  • a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process may be used to deposit and cover the inner wall of the capacitor hole 22 (including the sidewall and bottom of the capacitor hole 22).
  • the wall) and the auxiliary layer 23 on the surface of the third support layer 205 as shown in FIG. 2B.
  • the auxiliary layer 23 is etched back to remove the auxiliary layer 23 covering the surface of the third support layer 205 and the bottom wall of the capacitor hole 22, leaving only the side wall covering the capacitor hole 22
  • the auxiliary layer 23 is as shown in FIG. 2C.
  • the auxiliary layer 23 may be a single-layer structure, or may be a multi-layer structure stacked along the radial direction of the capacitor hole 22, and those skilled in the art can make a selection according to actual needs.
  • step S15 a first electrode layer 24 is formed to cover the surface of the auxiliary layer 23 and the exposed capacitor contact 21, as shown in FIG. 2D.
  • a conductive material such as titanium nitride is deposited on the surface of the auxiliary layer 23, the bottom wall of the capacitor hole 22 and the On the surface of the third support layer 205, the first electrode layer 24 as shown in FIG. 2D is formed.
  • Step S16 removing part of the supporting layer on the top of the laminated structure 20 to form an opening 26 to expose the sacrificial layer, as shown in FIG. 2F.
  • the method before removing a part of the supporting layer on the top of the laminated structure 20, the method further includes the following steps:
  • a filling layer 25 is formed on the surface of the first electrode layer 24 and the capacitor hole 22 is filled, as shown in FIG. 2E.
  • the filling layer 25 is deposited in the capacitor hole 22 so that the filling layer 25 fills the capacitor
  • the hole 22 prevents the first electrode layer 24 from overturning or collapsing during the subsequent etching process.
  • the material of the filling layer 25 may be, but is not limited to, carbon or carbon-containing organic materials.
  • the specific steps of forming the opening 26 to expose the sacrificial layer include:
  • the third support layer 205 is etched to form at least one opening 26 to expose the second sacrificial layer 204, and each of the openings 26 partially overlaps the at least one capacitor hole 22.
  • FIG. 2G shows a schematic top view when one of the openings 26 and three capacitor holes 22 partially overlap.
  • step S17 the sacrificial layer and the auxiliary layer 23 are simultaneously removed along the opening 26 to form a gap 28 between the support layer and the first electrode layer 24, as shown in FIG. 2H.
  • the specific steps of simultaneously removing the sacrificial layer and the auxiliary layer 23 along the opening 26 include:
  • a wet etching process is used to simultaneously remove the second sacrificial layer 204, the first sacrificial layer 202, and the auxiliary layer 23 along the opening 26 to form the void 28 in the first electrode layer 24 and the remaining ⁇ The laminated structure 20 between.
  • the second sacrificial layer 204, the first sacrificial layer 202, and the auxiliary layer 23 are simultaneously removed along the opening 26 in combination with a wet etching process.
  • the acid etchant should be able to etch the auxiliary layer 23, the first sacrificial layer 202, and the second sacrificial layer 204 at the same time, and not affect the first support layer 201 and the second support layer 203. , The remaining third support layer 205 and the first electrode layer 24 cause damage.
  • the auxiliary layer 23 is made of the same material as the sacrificial layer.
  • auxiliary layer 23 by setting the material of the auxiliary layer 23 to be the same as the material of the first sacrificial layer 202 and the second sacrificial layer 204, for example, both are silicon dioxide, it is possible to simplify and remove the auxiliary layer at the same time.
  • Those skilled in the art can also set the material of the auxiliary layer 23 to be different from the material of the sacrificial layer according to actual needs, and subsequently remove the auxiliary layer 23 and the sacrificial layer at the same time by selecting a suitable etching reagent.
  • the etching selection ratio between the auxiliary layer 23 and the sacrificial layer should be Less than 3.
  • the auxiliary layer 23 and the first sacrificial layer can be removed after the second sacrificial layer 204 is removed.
  • the second support layer 203 does not need to be etched again, which not only ensures the lateral length of the second support layer 203, but also enables the second support layer 203 to be effective in the subsequent formation of the double-sided capacitor structure.
  • the opposite sides of the DRAM are supported, which greatly improves the stability of the double-sided capacitor structure, improves the performance of the capacitor, and improves the yield of the DRAM.
  • Step S18 forming a dielectric layer covering the surface of the first electrode layer 24 and a second electrode layer 30 covering the surface of the dielectric layer, the gap 28 is filled with at least the dielectric layer, as shown in FIG. 2K Show.
  • the specific steps of forming the dielectric layer covering the surface of the first electrode layer 24 and the second electrode layer 30 covering the surface of the dielectric layer include:
  • a first sub-dielectric layer 291 covering the surface of the first electrode layer 24 is formed in the gap 28, as shown in FIG. 2I;
  • At least a second sub-dielectric layer 292 covering the surface of the first electrode layer 24 is formed in the capacitor hole 22;
  • a second electrode layer 30 covering the surface of the first sub-dielectric layer 291 and the surface of the second sub-dielectric layer 292 is formed, as shown in FIG. 2K.
  • the outer surface of the first electrode layer 24 (that is, the first electrode layer 24)
  • a dielectric material with a high dielectric constant is deposited away from the surface of the capacitor hole 22 to form the first sub-dielectric layer 291, as shown in FIG. 2I.
  • the filling layer 25 filled inside the capacitor hole 22 is removed to expose the capacitor hole 22, as shown in FIG. 2J.
  • the filling layer 25 can be removed by an ashing process.
  • a dielectric material with a high dielectric constant is deposited again on the inner surface of the first electrode layer 24 (that is, the surface of the first electrode layer 24 facing the capacitor hole 22) to form the second sub-dielectric layer 292.
  • the material of the first sub-dielectric layer 291 may be the same as the material of the second sub-dielectric layer 292.
  • the thickness of the first sub-dielectric layer 291 may also be the same as the thickness of the second sub-dielectric layer 292.
  • a conductive material such as titanium nitride is deposited on the surface of the first sub-dielectric layer 291 and the surface of the second sub-dielectric layer 292 to form the second electrode layer 30, as shown in FIG. 2K.
  • the second sub-dielectric layer 292 is further formed in the gap 28 and covers the surface of the first sub-dielectric layer 291, and the second electrode layer 30 covers the surface of the second sub-dielectric layer 292 .
  • those skilled in the art can also deposit a dielectric material with a high dielectric constant on the inner surface of the first electrode layer 24 (that is, the first electrode layer) after removing the filling layer 25 according to actual needs. 24 facing the surface of the capacitor hole 22) and the surface of the first sub-dielectric layer 291, so that the gap 28 is simultaneously filled with the first sub-dielectric layer 291 and the second sub-dielectric layer 292. Then, a conductive material such as titanium nitride is deposited on the surface of the second sub-dielectric layer 292 to form the second electrode layer 30.
  • a conductive material such as doped polysilicon is deposited on the surface of the second electrode layer 30 to cover the second electrode layer 30 and fill the capacitor holes 22 and adjacent capacitor holes.
  • the conductive layer 31 in the gap area between 22 is as shown in FIG. 2L.
  • the width of the gap 28 (that is, the thickness of the auxiliary layer 23) is less than or equal to the thickness of the first sub-dielectric layer 291, so that the first sub-dielectric layer 291 fills the gap. 28.
  • the thickness of the auxiliary layer 23 can also adjust the thickness of the auxiliary layer 23 according to actual needs, so that the width of the void 28 formed is less than or equal to the sum of the thicknesses of the first sub-dielectric layer 291 and the second electrode layer 30 , So that the first sub-dielectric layer 291 and the second electrode layer 30 fill the gap 28 together.
  • auxiliary layer 23 can also adjust the thickness of the auxiliary layer 23 according to actual needs, so that the width of the void 28 formed is greater than the sum of the thicknesses of the first sub-dielectric layer 291 and the second electrode layer 30, so that Most of the first sub-dielectric layer 291, the second electrode layer 30 and a part of the conductive layer 31 fill the gap 28 together.
  • this specific embodiment also provides a double-sided capacitor structure.
  • the double-sided capacitor structure provided in this specific embodiment can be formed by the method shown in Figs. 1 and 2A-2L.
  • a schematic diagram of the double-sided capacitor structure provided in this specific embodiment please refer to Figs. 2A-2L.
  • the double-sided capacitor structure provided in this embodiment includes:
  • a substrate, the surface of the substrate has a capacitive contact 21;
  • the top support layer and the middle support layer each have a number of capacitor openings, and on a plane parallel to the substrate, the projected area of the middle support layer is larger than the projected area of the top support layer;
  • the first electrode layer 24 is in the form of a hollow column with a top opening perpendicular to the surface of the substrate and penetrates the top support layer and the middle support layer through the capacitor openings.
  • the bottom of the first electrode layer 24 is connected to the Capacitor contact 21 is connected;
  • the second electrode layer 30 covers the surface of the dielectric layer.
  • the top support layer in this specific embodiment is the third support layer 205
  • the intermediate support layer is the second Two supporting layers 203
  • the double-sided capacitor structure further includes a bottom supporting layer (that is, the first supporting layer 201) located below the intermediate supporting layer.
  • the first electrode layer 24, the dielectric layer and the second electrode layer 30 together constitute a capacitor.
  • the top support layer has a capacitor opening that penetrates the top support layer in a direction perpendicular to the substrate
  • the middle support layer also has a capacitor opening that penetrates the middle support layer in a direction perpendicular to the substrate .
  • That the projected area of the intermediate support layer is greater than the projected area of the top support layer means that the intermediate support layer is larger than the top support layer at least in the lateral extension length.
  • the projection of the middle support layer completely covers the projection of the top support layer.
  • At the edge of the capacitor there will be a side wall of the support layer (including the top support layer and the intermediate support layer) surrounding the entire capacitor, and the capacitor and the top support layer and the intermediate support layer Are connected and stand vertically on the substrate, so as to achieve stable support for the capacitor.
  • the projections of the capacitor openings in the middle support layer and the top support layer on the substrate overlap.
  • the capacitance openings in the middle support layer are aligned with the capacitance openings in the top support layer, and the size of the capacitance openings in the middle support layer is the same as the capacitance openings in the top support layer.
  • the sizes of the holes are equal to better support the capacitor.
  • the double-sided capacitor structure further includes:
  • the conductive layer 31 covers the surface of the second electrode layer 30.
  • the auxiliary layer is formed first on the sidewall of the capacitor hole, and after the supporting layer on the top of the laminated structure is opened, the auxiliary layer is simultaneously removed by selecting a suitable etching reagent. Layer and all the sacrificial layers in the laminated structure, so that there is no need to etch other supporting layers in the laminated structure, so that the supporting layer located in the middle of the laminated structure can simultaneously affect the opposite sides of a double-sided capacitor.
  • the formation process of the surface capacitor structure shortens the process time.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

本申请涉及一种双面电容结构及其形成方法。所述双面电容结构的形成方法包括如下步骤：提供基底；形成叠层结构于所述基底上；沿垂直于所述基底的方向形成电容孔贯穿所述叠层结构，所述叠层结构包括交替叠置的牺牲层和支撑层；形成辅助层覆盖于所述电容孔侧壁；形成第一电极层覆盖所述辅助层表面；去除所述叠层结构顶部的部分所述支撑层，以形成开口暴露所述牺牲层；沿所述开口同时去除所述牺牲层和所述辅助层，以形成空隙于所述支撑层和所述第一电极层之间；形成覆盖于所述第一电极层表面的电介质层、以及覆盖于所述电介质层表面的第二电极层，所述空隙内至少填充有所述电介质层。本申请能够提高双面电容结构的横向稳定性。

Description

双面电容结构及其形成方法
相关申请引用说明
本申请要求于2020年6月4日递交的中国专利申请号202010498454.1、申请名为“双面电容结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种双面电容结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体结构，其由多个存储单元构成，每个存储单元通常包括用于存储电荷的电容器和存取电容器的晶体管。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启与关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。DRAM以电容器上的电荷的形式存储数据，所以需要在每几个毫秒的时间间隔内即将电容器作规则性的再充电，而电容器的电容值越大，储存在DRAM中的数据也可被维持得越久。
由于DRAM中电容器深宽比的不断提高，电容孔在形成双面电容结构的过程中易发生剥离(peeling)现象，或者在后续制程中出现倾斜或弯曲，这都会导致DRAM良率的降低。
因此，如何增加双面电容结构的稳定性，改善双面电容结构的性能，提高DRAM的良率，是当前亟待解决的技术问题。
发明内容
本申请提供一种双面电容结构及其形成方法，用于解决现有的双面电容结构稳定性较差的问题，以改善双面电容结构的性能，提高DRAM的良率。
为了解决上述问题，本申请提供了一种双面电容结构的形成方法，包括如下步骤：
提供基底，所述基底表面形成有电容触点；
形成叠层结构于所述基底上，并覆盖所述电容触点；
沿垂直于所述基底的方向形成电容孔贯穿所述叠层结构，并暴露所述电容触点，所述叠层结构包括交替叠置的牺牲层和支撑层；
形成辅助层覆盖于所述电容孔侧壁；
形成第一电极层覆盖所述辅助层表面和被暴露出的所述电容触点；
去除所述叠层结构顶部的部分所述支撑层，以形成开口暴露所述牺牲层；
沿所述开口同时去除所述牺牲层和所述辅助层，以形成空隙于所述支撑层和所述第一电极层之间；
形成覆盖于所述第一电极层表面的电介质层、以及覆盖于所述电介质层表面的第二电极层，所述空隙内至少填充有所述电介质层。
可选的，所述形成叠层结构于所述基底上的具体步骤包括：
在所述基底上由下至上依次沉积第一支撑层、第一牺牲层、第二支撑层、第二牺牲层和第三支撑层，形成所述叠层结构，所述叠层结构覆盖所述电容触点。
可选的，所述去除所述叠层结构顶部的部分所述支撑层之前，还包括如下步骤：
形成填充层于所述第一电极层表面，并填充所述电容孔。
可选的，所述填充层的材料为碳或者含碳有机物材料。
可选的，所述形成开口暴露所述牺牲层的具体步骤包括：
刻蚀所述第三支撑层，形成至少一个开口暴露所述第二牺牲层，每个所述开口与至少一个所述电容孔部分交叠。
可选的，所述沿所述开口同时去除所述牺牲层和所述辅助层的具体步骤包括：
采用湿法刻蚀工艺沿所述开口同时去除所述第二牺牲层、所述第一牺牲层和所述辅助层，形成所述空隙于所述第一电极层和残留的所述叠层结构之间。
可选的，所述形成覆盖于所述第一电极层表面的电介质层、以及覆盖于所述电介质层表面的第二电极层的具体步骤包括：
于所述空隙中形成覆盖所述第一电极层表面的第一子电介质层；
去除所述填充层；
至少于所述电容孔内形成覆盖于所述第一电极层表面的第二子电介质层；
形成覆盖于所述第一子电介质层表面和所述第二子电介质层表面的第二电极层。
可选的，所述第二子电介质层还形成于所述空隙中，并覆盖所述第一子电介质层表面，所述第二电极层覆盖所述第二子电介质层表面。
可选的，所述辅助层为单层结构；或者，
所述辅助层为沿所述电容孔的径向方向叠置的多层结构。
可选的，所述辅助层与所述牺牲层的材料相同。
可选的，所述辅助层与所述牺牲层的材料均为二氧化硅。
为了解决上述问题，本申请还提供了一种双面电容结构，包括：
基底，所述基底表面具有电容触点；
顶层支撑层和中间支撑层，均具有若干电容开孔，且在平行于所述基底的平面上，所述中间支撑层的投影面积大于所述顶层支撑层的投影面积；
第一电极层，呈顶部开口的空心柱状垂直于所述基底表面且通过所述电容开孔贯穿所述顶层支撑层和所述中间支撑层，所述第一电极层的底部与所述电容触点连接；
电介质层，覆盖于所述第一电极层、所述顶层支撑层和所述中间支撑层表面；
第二电极层，覆盖于所述电介质层表面。
可选的，所述中间支撑层与所述顶层支撑层中的所述电容开孔在所述基底上的投影重叠。
可选的，所述电介质层包括：
第一子电介质层，覆盖于所述第一电极层的外表面；
第二子电介质层，至少覆盖于所述第一电极层的内表面。
可选的，所述第二子电介质层还覆盖于所述第一子电介质层表面，所述第二电极层覆盖于所述第二子电介质层表面。
可选的，所述第一子电介质层的材料和所述第二子电介质层的材料相同。
可选的，所述第一子电介质层的厚度和所述第二子电介质层的厚度相同。
可选的，还包括：
导电层，覆盖于所属第二电极层表面。
本申请提供的双面电容结构及其形成方法，先于电容孔的侧壁形成辅助层，后续在打开叠层结构顶部的支撑层之后，通过选择合适的刻蚀试剂同时去除所述辅助层和所述叠层结构中的所有牺牲层，从而无需对叠层结构中其他的支撑层再进行刻蚀，使得位于所述叠层结构中间的支撑层能够同时对一双面电容器的相对两侧进行支撑，一方面，能够提高双面电容结构的横向稳定性，从而改善DRAM的良率；另一方面，由于能够减少对叠层结构中支撑层的刻蚀步骤，从而有助于简化双面电容结构的形成工艺，缩短工艺制程时间。
附图说明
附图1是本申请具体实施方式中双面电容结构的形成方法流程图；
附图2A-2L是本申请具体实施方式在形成双面电容结构的过程中主要的工艺截面示意图。
具体实施方式
下面结合附图对本申请提供的双面电容结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种双面电容结构的形成方法，附图1是本申请具体实施方式中双面电容结构的形成方法流程图，附图2A-2L是本申请具体实施方式在形成双面电容结构的过程中主要的工艺截面示意图。本具体实施方式中所述的双面电容结构可以是但不限于应用于DRAM存储器中。如图1、图2A-图2L所示，本具体实施方式提供的双面电容结构的形成方法，包括如下步骤：
步骤S11，提供基底，所述基底表面形成有电容触点21，如图2A所示。
步骤S12，形成叠层结构20于所述基底上，并覆盖所述电容触点21。
步骤S13，沿垂直于所述基底的方向形成电容孔22贯穿所述叠层结构20，并暴露所述电容触点21，所述叠层结构20包括交替叠置的牺牲层和支撑层，如图2A所示。
可选的，所述形成叠层结构20于所述基底上的具体步骤包括：
在所述基底上由下至上依次沉积第一支撑层201、第一牺牲层202、第二支撑层203、第二牺牲层204和第三支撑层205，形成所述叠层结构20，所述叠层结构20覆盖所述电容触点21，如图2A所示。
具体来说，所述基底内部具有呈阵列排布的多个有源区，所述电容触点21 连接所述有源区。所述基底的材料可以是但不限于硅，所述电容触点21的材料可以是但不限于钨。多个所述牺牲层和所述支撑层沿垂直于所述基底的方向交替堆叠，所述牺牲层和所述支撑层交替堆叠的层数，本领域技术人员可以根据实际需要进行选择。在本具体实施方式中，所述叠层结构20中所述支撑层的层数至少为3层，所述牺牲层的层数至少为2层，以便于增强电容阵列区域的横向稳定性。所述牺牲层的材料可以是但不限于氧化物材料，例如二氧化硅；所述支撑层的材料可以是但不限于氮化物材料，例如氮化硅。
在形成交替堆叠的所述牺牲层和所述支撑层之后，可以采用干法刻蚀工艺刻蚀所述叠层结构20，形成贯穿所述叠层结构20并暴露所述电容触点21的所述电容孔22。
步骤S14，形成辅助层23覆盖于所述电容孔22侧壁，如图2C所示。
具体来说，在形成所述电容孔22之后，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沉积覆盖于所述电容孔22内壁(包括所述电容孔22的侧壁和底壁)和所述第三支撑层205表面的所述辅助层23，如图2B所示。之后，回刻蚀所述辅助层23，去除覆盖于所述第三支撑层205表面和所述电容孔22底壁上的所述辅助层23，仅保留覆盖于所述电容孔22侧壁上的所述辅助层23，如图2C所示。
在本具体实施方式中，所述辅助层23可以是单层结构，也可以是沿所述电容孔22的径向方向叠置的多层结构，本领域技术人员可以根据实际需要进行选择。
步骤S15，形成第一电极层24覆盖所述辅助层23表面和被暴露出的所述电容触点21，如图2D所示。
具体来说，在形成覆盖于所述电容孔22侧壁的所述辅助层23之后，沉积氮化钛等导电材料于所述辅助层23表面、所述电容孔22的底壁上和所述第三支撑层205表面，形成如图2D所示的第一电极层24。
步骤S16，去除所述叠层结构20顶部的部分所述支撑层，以形成开口26暴露所述牺牲层，如图2F所示。
可选的，所述去除所述叠层结构20顶部的部分所述支撑层之前，还包括如下步骤：
形成填充层25于所述第一电极层24表面，并填充所述电容孔22，如图2E所示。
具体来说，在对所述叠层结构20的所述第三支撑层205进行刻蚀之前，沉积所述填充层25于所述电容孔22内，使得所述填充层25填充满所述电容孔22，避免在后续刻蚀过程中，所述第一电极层24出现倾覆或者坍塌的现象。所述填充层25的材料可以是但不限于碳或者含碳有机物材料。
可选的，所述形成开口26暴露所述牺牲层的具体步骤包括：
刻蚀所述第三支撑层205，形成至少一个开口26暴露所述第二牺牲层204，每个所述开口26与至少一个所述电容孔22部分交叠。
具体来说，除去覆盖于所述第三支撑层205表面的所述第一电极层24之后，刻蚀部分的所述第三支撑层205，形成暴露所述第二牺牲层204的开口26。每个所述开口26可以与一个或者两个以上的电容孔22部分交叠，图2G中示出了一个所述开口26与三个所述电容孔22部分交叠时的俯视示意图。
步骤S17，沿所述开口26同时去除所述牺牲层和所述辅助层23，以形成空隙28于所述支撑层和所述第一电极层24之间，如图2H所示。
可选的，所述沿所述开口26同时去除所述牺牲层和所述辅助层23的具体步骤包括：
采用湿法刻蚀工艺沿所述开口26同时去除所述第二牺牲层204、所述第一牺牲层202和所述辅助层23，形成所述空隙28于所述第一电极层24和残留的所述叠层结构20之间。
具体来说，通过选择合适的酸性刻蚀剂，结合湿法刻蚀工艺沿所述开口26同时去除所述第二牺牲层204、所述第一牺牲层202和所述辅助层23。所述酸性刻蚀剂应能同时刻蚀所述辅助层23、所述第一牺牲层202和所述第二牺牲层204，且不对所述第一支撑层201、所述第二支撑层203、残留的所述第三支撑层205和所述第一电极层24造成损伤。
可选的，所述辅助层23与所述牺牲层的材料相同。
具体来说，通过将所述辅助层23的材料设置为与所述第一牺牲层202和所述第二牺牲层204的材料均相同，例如均为二氧化硅，可以简化同时除去所述辅助层23、所述第一牺牲层202和所述第二牺牲层204的步骤。
本领域技术人员也可以根据实际需要，将所述辅助层23的材料设置为与所述牺牲层的材料不同，后续通过选择合适的刻蚀试剂同时去除所述辅助层23和所述牺牲层。为了充分去除所述辅助层23和所述牺牲层，在所述辅助层23的材料与所述牺牲层的材料不同时，所述辅助层23与所述牺牲层之间的刻蚀选择比应小于3。
在本具体实施方式中，通过选择合适的所述辅助层23的材料以及刻蚀剂的种类，可以在去除所述第二牺牲层204之后，继续去除所述辅助层23和所述第一牺牲层202，而无需再次对所述第二支撑层203进行刻蚀，既确保了所述第二支撑层203的横向长度，又能使得所述第二支撑层203对后续形成的双面电容结构的相对两侧均进行支撑，从而极大的提高了双面电容结构的稳定性，改善了电容器的性能，提高了DRAM的良率。
步骤S18，形成覆盖于所述第一电极层24表面的电介质层、以及覆盖于所述电介质层表面的第二电极层30，所述空隙28内至少填充有所述电介质层，如图2K所示。
可选的，所述形成覆盖于所述第一电极层24表面的电介质层、以及覆盖于所述电介质层表面的第二电极层30的具体步骤包括：
于所述空隙28中形成覆盖所述第一电极层24表面的第一子电介质层291，如图2I所示；
去除所述填充层25，如图2J所示；
至少于所述电容孔22内形成覆盖于所述第一电极层24表面的第二子电介质层292；
形成覆盖于所述第一子电介质层291表面和所述第二子电介质层292表面的第二电极层30，如图2K所示。
具体来说，在去除所述第一牺牲层202、所述第二牺牲层204和所述辅助层23之后，先于所述第一电极层24的外表面(即所述第一电极层24背离所述电容孔22的表面)沉积具有高介电常数的电介质材料，形成所述第一子电介质层291，如图2I所示。之后，去除填充于所述电容孔22内部的所述填充层25，暴露所述电容孔22，如图2J所示。例如当所述填充层25的材料为碳时，可以采用灰化工艺去除所述填充层25。接着，再次沉积具有高介电常数的 电介质材料于所述第一电极层24的内表面(即所述第一电极层24朝向所述电容孔22的表面)，形成所述第二子电介质层292。在本具体实施方式中，所述第一子电介质层291的材料可以与所述第二子电介质层292的材料相同。所述第一子电介质层291的厚度也可以与所述第二子电介质层292的厚度相同。然后，沉积氮化钛等导电材料于所述第一子电介质层291表面和所述第二子电介质层292表面，形成所述第二电极层30，如图2K所示。
可选的，所述第二子电介质层292还形成于所述空隙28中，并覆盖所述第一子电介质层291表面，所述第二电极层30覆盖所述第二子电介质层292表面。
具体来说，本领域技术人员还可以根据实际需要在除去所述填充层25之后，沉积具有高介电常数的电介质材料于所述第一电极层24的内表面(即所述第一电极层24朝向所述电容孔22的表面)和所述第一子电介质层291表面，使得所述空隙28中同时填充有所述第一子电介质层291和所述第二子电介质层292。然后，沉积氮化钛等导电材料于所述第二子电介质层292表面，形成所述第二电极层30。
在形成所述第二电极层30之后，沉积掺杂多晶硅等导电材料于所述第二电极层30表面，形成覆盖所述第二电极层30并填充满所述电容孔22以及相邻电容孔22之间间隙区域的导电层31，如图2L所示。
本具体实施方式是以所述空隙28的宽度(即所述辅助层23的厚度)小于或者等于所述第一子电介质层291的厚度，使得所述第一子电介质层291填充满所述空隙28。本领域技术人员也可以根据实际需要调整所述辅助层23的厚度，使得形成的所述空隙28的宽度小于或者等于所述第一子电介质层291与所述第二电极层30的厚度之和，使得所述第一子电介质层291与所述第二电极层30共同填充满所述空隙28。本领域技术人员还可以根据实际需要调整所述辅助层23的厚度，使得形成的所述空隙28的宽度大于所述第一子电介质层291和所述第二电极层30的厚度之和，使得多数第一子电介质层291、所述第二电极层30和部分的所述导电层31共同填充满所述间隙28。
不仅如此，本具体实施方式还提供了一种双面电容结构。本具体实施方式提供的双面电容结构可以采用如图1、图2A-图2L所示的方法形成，本具体实 施方式提供的双面电容结构的示意图可以参见图2A-图2L。如图2A-图2L所示，本具体实施方式提供的双面电容结构，包括：
基底，所述基底表面具有电容触点21；
顶层支撑层和中间支撑层，均具有若干电容开孔，且在平行于所述基底的平面上，所述中间支撑层的投影面积大于所述顶层支撑层的投影面积；
第一电极层24，呈顶部开口的空心柱状垂直于所述基底表面且通过所述电容开孔贯穿所述顶层支撑层和所述中间支撑层，所述第一电极层24的底部与所述电容触点21连接；
电介质层，覆盖于所述第一电极层24、所述顶层支撑层和所述中间支撑层表面；
第二电极层30，覆盖于所述电介质层表面。
以图2A-图2L所示的方法形成的双面电容结构为例，本具体实施方式中的所述顶层支撑层即为所述第三支撑层205、所述中间支撑层即为所述第二支撑层203，所述双面电容结构还包括位于所述中间支撑层下方的底层支撑层(即所述第一支撑层201)。所述第一电极层24、所述电介质层和所述第二电极层30共同构成电容器。所述顶层支撑层中具有沿垂直于基底的方向贯穿所述顶层支撑层的电容开孔、所述中间支撑层中也具有沿垂直于所述基底的方向贯穿所述中间支撑层的电容开孔。
在平行于所述基底的平面上，所述中间支撑层的投影面积大于所述顶层支撑层的投影面积是指，所述中间支撑层至少在横向延伸长度上大于所述顶层支撑层。所述中间支撑层的投影完全覆盖所述顶层支撑层的投影。在所述电容器的边缘处会有所述支撑层(包括所述顶层支撑层和所述中间支撑层)侧壁包围整个所述电容器，所述电容器与所述顶层支撑层和所述中间支撑层相连，且垂直立于所述基底上，从而实现对所述电容器的稳定支撑。
可选的，所述中间支撑层与所述顶层支撑层中的所述电容开孔在所述基底上的投影重叠。
具体来说，所述中间支撑层中的电容开孔与所述顶层支撑层中的电容开孔对准，且所述中间支撑层中的电容开口的尺寸与所述顶层支撑层中的电容开孔的尺寸相等，以更好的支撑所述电容器。
可选的，所述双面电容结构还包括：
导电层31，覆盖于所属第二电极层30表面。
本具体实施方式提供的双面电容结构及其形成方法，先于电容孔的侧壁形成辅助层，后续在打开叠层结构顶部的支撑层之后，通过选择合适的刻蚀试剂同时去除所述辅助层和所述叠层结构中的所有牺牲层，从而无需对叠层结构中其他的支撑层再进行刻蚀，使得位于所述叠层结构中间的支撑层能够同时对一双面电容器的相对两侧进行支撑，一方面，能够提高双面电容结构的横向稳定性，从而改善DRAM的良率；另一方面，由于能够减少对叠层结构中支撑层的刻蚀步骤，从而有助于简化双面电容结构的形成工艺，缩短工艺制程时间。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (18)

  1. 一种双面电容结构的形成方法，包括如下步骤：
    提供基底，所述基底表面形成有电容触点；
    形成叠层结构于所述基底上，并覆盖所述电容触点；
    沿垂直于所述基底的方向形成电容孔贯穿所述叠层结构，并暴露所述电容触点，所述叠层结构包括交替叠置的牺牲层和支撑层；
    形成辅助层覆盖于所述电容孔侧壁；
    形成第一电极层覆盖所述辅助层表面和被暴露出的所述电容触点；
    去除所述叠层结构顶部的部分所述支撑层，以形成开口暴露所述牺牲层；
    沿所述开口同时去除所述牺牲层和所述辅助层，以形成空隙于所述支撑层和所述第一电极层之间；
    形成覆盖于所述第一电极层表面的电介质层、以及覆盖于所述电介质层表面的第二电极层，所述空隙内至少填充有所述电介质层。
  2. 根据权利要求1所述的双面电容结构的形成方法，其中，所述形成叠层结构于所述基底上的具体步骤包括：
    在所述基底上由下至上依次沉积第一支撑层、第一牺牲层、第二支撑层、第二牺牲层和第三支撑层，形成所述叠层结构，所述叠层结构覆盖所述电容触点。
  3. 根据权利要求1所述的双面电容结构的形成方法，其中，所述去除所述叠层结构顶部的部分所述支撑层之前，还包括如下步骤：
    形成填充层于所述第一电极层表面，并填充所述电容孔。
  4. 根据权利要求3所述的双面电容结构的形成方法，其中，所述填充层的材料为碳或者含碳有机物材料。
  5. 根据权利要求2所述的双面电容结构的形成方法，其中，所述形成开口暴露所述牺牲层的具体步骤包括：
    刻蚀所述第三支撑层，形成至少一个开口暴露所述第二牺牲层，每个所述开口与至少一个所述电容孔部分交叠。
  6. 根据权利要求2所述的双面电容结构的形成方法，其中，所述沿所述开口 同时去除所述牺牲层和所述辅助层的具体步骤包括：
    采用湿法刻蚀工艺沿所述开口同时去除所述第二牺牲层、所述第一牺牲层和所述辅助层，形成所述空隙于所述第一电极层和残留的所述叠层结构之间。
  7. 根据权利要求6所述的双面电容结构的形成方法，其中，所述形成覆盖于所述第一电极层表面的电介质层、以及覆盖于所述电介质层表面的第二电极层的具体步骤包括：
    于所述空隙中形成覆盖所述第一电极层表面的第一子电介质层；
    去除所述填充层；
    至少于所述电容孔内形成覆盖于所述第一电极层表面的第二子电介质层；
    形成覆盖于所述第一子电介质层表面和所述第二子电介质层表面的第二电极层。
  8. 根据权利要求7所述的双面电容结构的形成方法，其中，所述第二子电介质层还形成于所述空隙中，并覆盖所述第一子电介质层表面，所述第二电极层覆盖所述第二子电介质层表面。
  9. 根据权利要求1所述的双面电容结构的形成方法，其中，所述辅助层为单层结构；或者，
    所述辅助层为沿所述电容孔的径向方向叠置的多层结构。
  10. 根据权利要求1所述的双面电容结构的形成方法，其中，所述辅助层与所述牺牲层的材料相同。
  11. 根据权利要求10所述的双面电容结构的形成方法，其中，所述辅助层与所述牺牲层的材料均为二氧化硅。
  12. 一种双面电容结构，包括：
    基底，所述基底表面具有电容触点；
    顶层支撑层和中间支撑层，均具有若干电容开孔，且在平行于所述基底的平面上，所述中间支撑层的投影面积大于所述顶层支撑层的投影面积；
    第一电极层，呈顶部开口的空心柱状垂直于所述基底表面且通过所述电容开孔贯穿所述顶层支撑层和所述中间支撑层，所述第一电极层的底部与所 述电容触点连接；
    电介质层，覆盖于所述第一电极层、所述顶层支撑层和所述中间支撑层表面；
    第二电极层，覆盖于所述电介质层表面。
  13. 根据权利要求12所述的双面电容结构，其中，
    所述中间支撑层与所述顶层支撑层中的所述电容开孔在所述基底上的投影重叠。
  14. 根据权利要求12所述的双面电容结构，其中，所述电介质层包括：
    第一子电介质层，覆盖于所述第一电极层的外表面；
    第二子电介质层，至少覆盖于所述第一电极层的内表面。
  15. 根据权利要求14所述的双面电容结构，其中，所述第二子电介质层还覆盖于所述第一子电介质层表面，所述第二电极层覆盖于所述第二子电介质层表面。
  16. 根据权利要求15所述的双面电容结构，其中，所述第一子电介质层的材料和所述第二子电介质层的材料相同。
  17. 据权利要求15所述的双面电容结构，其中，所述第一子电介质层的厚度和所述第二子电介质层的厚度相同。
  18. 根据权利要求12所述的双面电容结构，还包括：
    导电层，覆盖于所属第二电极层表面。
PCT/CN2021/097161 2020-06-04 2021-05-31 双面电容结构及其形成方法 WO2021244466A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/503,607 US11894419B2 (en) 2020-06-04 2021-10-18 Double-sided capacitor and fabrication method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010498454.1 2020-06-04
CN202010498454.1A CN113764580B (zh) 2020-06-04 2020-06-04 双面电容结构及其形成方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/503,607 Continuation US11894419B2 (en) 2020-06-04 2021-10-18 Double-sided capacitor and fabrication method thereof

Publications (1)

Publication Number Publication Date
WO2021244466A1 true WO2021244466A1 (zh) 2021-12-09

Family

ID=78783460

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/097161 WO2021244466A1 (zh) 2020-06-04 2021-05-31 双面电容结构及其形成方法

Country Status (3)

Country Link
US (1) US11894419B2 (zh)
CN (1) CN113764580B (zh)
WO (1) WO2021244466A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050106806A1 (en) * 2003-11-13 2005-05-19 Fred Fishburn Methods of forming a double-sided capacitor or a contact using a sacrificial structure
CN107093604A (zh) * 2017-04-27 2017-08-25 睿力集成电路有限公司 动态随机存取存储器及其制造方法
CN108447864A (zh) * 2018-03-14 2018-08-24 睿力集成电路有限公司 半导体存储器件结构及其制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6737696B1 (en) * 1998-06-03 2004-05-18 Micron Technology, Inc. DRAM capacitor formulation using a double-sided electrode
US6838339B2 (en) 2003-06-05 2005-01-04 Infineon Technologies Ag Area-efficient stack capacitor
JP4524687B2 (ja) * 2007-01-15 2010-08-18 エルピーダメモリ株式会社 半導体装置
KR101262225B1 (ko) * 2007-10-23 2013-05-15 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR101728320B1 (ko) * 2011-06-30 2017-04-20 삼성전자 주식회사 반도체 소자의 제조 방법
KR101934093B1 (ko) * 2012-08-29 2019-01-02 삼성전자주식회사 반도체 장치 및 그 제조 방법
US10276651B2 (en) * 2017-09-01 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Low warpage high density trench capacitor
CN207165563U (zh) * 2017-09-14 2018-03-30 睿力集成电路有限公司 电容器阵列结构
US10312241B1 (en) * 2018-04-27 2019-06-04 Micron Technology, Inc. Integrated memory and integrated assemblies
CN110504284A (zh) * 2018-05-17 2019-11-26 长鑫存储技术有限公司 柱状电容器阵列结构及制备方法
WO2020029119A1 (zh) * 2018-08-08 2020-02-13 深圳市为通博科技有限责任公司 双面电容器及其制作方法
TWI671885B (zh) * 2018-08-16 2019-09-11 華邦電子股份有限公司 記憶體裝置及其製造方法
US11171146B2 (en) * 2019-12-12 2021-11-09 Micron Technology, Inc. Memory devices and methods of forming memory devices
CN113903709A (zh) 2020-06-22 2022-01-07 长鑫存储技术有限公司 存储器的形成方法及存储器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050106806A1 (en) * 2003-11-13 2005-05-19 Fred Fishburn Methods of forming a double-sided capacitor or a contact using a sacrificial structure
CN107093604A (zh) * 2017-04-27 2017-08-25 睿力集成电路有限公司 动态随机存取存储器及其制造方法
CN108447864A (zh) * 2018-03-14 2018-08-24 睿力集成电路有限公司 半导体存储器件结构及其制作方法

Also Published As

Publication number Publication date
US11894419B2 (en) 2024-02-06
US20220037460A1 (en) 2022-02-03
CN113764580B (zh) 2023-09-12
CN113764580A (zh) 2021-12-07

Similar Documents

Publication Publication Date Title
WO2021169787A1 (zh) 双面电容结构及其形成方法
CN108447864B (zh) 半导体存储器件结构及其制作方法
CN108550569B (zh) 半导体集成电路的电容装置及其制作方法
WO2021109504A1 (zh) 半导体存储器及其形成方法
WO2021179926A1 (zh) 电容阵列结构及其形成方法
JP2689031B2 (ja) 半導体記憶装置およびその製造方法
WO2021185040A1 (zh) 半导体结构的形成方法及半导体结构
TW202245069A (zh) 半導體裝置
CN112397509A (zh) 电容阵列结构及其形成方法、半导体存储器
WO2021175154A1 (zh) 电容器及其形成方法、dram存储器及其形成方法
US5457063A (en) Method for fabricating a capacitor for a dynamic random access memory cell
WO2021185108A1 (zh) 双面电容结构及其形成方法
JP2917912B2 (ja) 半導体記憶装置およびその製造方法
WO2022183642A1 (zh) 半导体结构及其形成方法
WO2021244466A1 (zh) 双面电容结构及其形成方法
WO2021204047A1 (zh) 半导体存储器件及其制备方法
WO2021169797A1 (zh) 半导体结构制备方法和半导体结构
US7781297B2 (en) Semiconductor device and method of fabricating the same
US20220285481A1 (en) Semiconductor structure and forming method thereof
WO2023029392A1 (zh) 半导体结构及其形成方法
US20230345712A1 (en) Semiconductor structure and method for forming semiconductor structure
EP4277448A1 (en) Memory and method for forming same
CN117529103B (zh) 半导体结构及其形成方法
WO2023178738A1 (zh) 存储器及其形成方法
US20220208764A1 (en) Memory and fabrication method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21818836

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21818836

Country of ref document: EP

Kind code of ref document: A1