WO2021185108A1 - 双面电容结构及其形成方法 - Google Patents

双面电容结构及其形成方法 Download PDF

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Publication number
WO2021185108A1
WO2021185108A1 PCT/CN2021/079544 CN2021079544W WO2021185108A1 WO 2021185108 A1 WO2021185108 A1 WO 2021185108A1 CN 2021079544 W CN2021079544 W CN 2021079544W WO 2021185108 A1 WO2021185108 A1 WO 2021185108A1
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Prior art keywords
layer
capacitor
auxiliary
electrode layer
substrate
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PCT/CN2021/079544
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English (en)
French (fr)
Inventor
胡文佳
吴晗
陆勇
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长鑫存储技术有限公司
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Priority to US17/310,899 priority Critical patent/US11916102B2/en
Publication of WO2021185108A1 publication Critical patent/WO2021185108A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/13—Energy storage using capacitors

Definitions

  • This application relates to the field of semiconductor manufacturing technology, and in particular to a double-sided capacitor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each memory cell usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the opening and closing of the transistor, so that the storage can be read through the bit line Data information in the capacitor, or write data information into the capacitor.
  • the height of the bottom electrode can be increased or the thickness of the bottom electrode can be reduced.
  • increasing the height of the bottom electrode or reducing the thickness of the bottom electrode will result in a relatively high length and a thinner thickness of the bottom electrode, which will affect the performance reliability of the capacitor array area. For example, it may cause the lower electrode to collapse or overturn, causing the adjacent lower electrode to short-circuit.
  • a method that can be adopted is to increase the stability of the lower electrode by adding a lateral continuous support layer of the electrode.
  • the single-layer lateral support layer has its height limit, so that the capacitance value of the capacitor is limited by the electrode height, and the risk of electrode overturning and collapse of the sheet still exists.
  • This application provides a double-sided capacitor structure and a method for forming the same, which are used to solve the problem of poor lateral stability in the capacitor array region, so as to improve the performance stability of the semiconductor device.
  • the present application provides a method for forming a double-sided capacitor structure, which includes the following steps:
  • a substrate includes a substrate, a plurality of capacitor contacts located in the substrate, a laminated structure located on the surface of the substrate, and a substrate penetrating the laminated structure and exposing the capacitor contacts
  • the laminated structure includes a sacrificial layer and a supporting layer alternately stacked in a direction perpendicular to the substrate;
  • auxiliary layer A part of the auxiliary layer, several layers of the support layer and the sacrificial layer are removed, the first electrode layer is exposed, and the remaining auxiliary layer is divided into multiple sub-auxiliary layers, each of which is at least connected to The two capacitor holes overlap;
  • a second dielectric layer covering the surface of the first electrode layer and the surface of the sub auxiliary layer and a third electrode layer covering the surface of the second dielectric layer are formed to form a double-sided capacitor structure.
  • the first electrode layer, the first dielectric layer, and the second electrode layer are sequentially stacked on the top surface of the laminated structure; the specific steps of forming the first conductive filling layer include:
  • the specific steps of forming an auxiliary layer that closes the capacitor hole include:
  • An auxiliary layer is formed to cover the second electrode layer on the top surface of the laminated structure and close the capacitor hole.
  • the laminated structure includes a first supporting layer, a first sacrificial layer, a second supporting layer, a second sacrificial layer, and a third supporting layer that are sequentially stacked in a direction perpendicular to the substrate; and a portion is removed.
  • the specific steps of the auxiliary layer, several layers of the supporting layer and the sacrificial layer include:
  • the auxiliary layer, the third supporting layer, the second sacrificial layer, the second supporting layer, and the first sacrificial layer are etched sequentially along the etching window, so that the remaining auxiliary layer is It is divided into a plurality of sub-auxiliary layers, and each of the sub-auxiliary layers overlaps the two capacitor holes.
  • the material of the auxiliary layer is the same as the material of the support layer.
  • the method further includes the following steps:
  • a second conductive material is deposited on the surface of the third electrode layer to form a second conductive filling layer.
  • the present application also provides a double-sided capacitor structure, including:
  • a substrate the substrate includes a substrate, a plurality of capacitor contacts located in the substrate, a laminated structure on the surface of the substrate, and a plurality of capacitor contacts penetrating through the laminated structure and exposing the capacitor contacts.
  • Capacitance holes, the laminated structure at least includes a plurality of supporting layers stacked in a direction perpendicular to the substrate;
  • the first electrode layer covers the inner wall of the capacitor hole
  • a first dielectric layer covering the sidewall surface and the bottom wall surface of the first electrode layer facing the capacitor hole;
  • a second electrode layer covering the sidewall surface and the bottom wall surface of the first dielectric layer facing the capacitor hole;
  • the first conductive filling layer is filled in the area surrounded by the second electrode layer;
  • a second dielectric layer covering the sidewall surface and top surface of the first electrode layer away from the capacitor hole, and the surface of the sub auxiliary layer;
  • the third electrode layer covers the surface of the second dielectric layer.
  • the laminated structure includes a first supporting layer, a second supporting layer, and a third supporting layer that are sequentially stacked in a direction perpendicular to the substrate;
  • Each section of the auxiliary sub-layer covers the surface of the two capacitor holes that overlap it and the surface of the third support layer between the two adjacent capacitor holes that overlap it.
  • the third supporting layer has a first opening corresponding to a gap area between two adjacent segments of the sub-auxiliary layer, and the width of the first opening is greater than the width of the gap area;
  • the second supporting layer has a second opening corresponding to the gap area between two adjacent segments of the sub-auxiliary layer.
  • the thickness of the sub-auxiliary layer is greater than that of the third supporting layer.
  • the material of the sub-auxiliary layer is the same as the material of the support layer.
  • it also includes:
  • the second conductive filling layer covers the surface of the third electrode layer.
  • the double-sided capacitor structure and its forming method provided by the present application on the one hand, fill the first conductive filling layer in the area surrounded by the second electrode layer in the capacitor hole, and perform the first electrode layer and the second electrode layer.
  • fill the first conductive filling layer in the area surrounded by the second electrode layer in the capacitor hole and perform the first electrode layer and the second electrode layer.
  • the stability of the top of the first electrode layer and the second electrode layer thereby further avoiding the risk of electrode collapse and overturning, improves the overall stability of the double-sided capacitor structure, and at the same time helps to increase the double-sided capacitor structure The capacitance value.
  • Fig. 1 is a flowchart of a method for forming a double-sided capacitor structure in a specific embodiment of the present application
  • Figures 2A-2M are schematic cross-sectional views of main processes in the process of forming a double-sided capacitor structure in a specific embodiment of the present application.
  • FIG. 1 is a flowchart of a method for forming a double-sided capacitor structure in a specific embodiment of the application. Schematic diagram of the main process cross-section in the process of the surface capacitor structure.
  • the double-sided capacitor structure described in this specific embodiment can be, but is not limited to, applied to a DRAM memory.
  • the method for forming a double-sided capacitor structure provided in this embodiment includes the following steps:
  • Step S11 providing a base, the base including a substrate, a plurality of capacitor contacts 20 located in the substrate, a stacked structure 21 located on the surface of the substrate, and the stacked structure 21 penetrated and exposed
  • the laminated structure 21 includes a sacrificial layer and a supporting layer alternately stacked in a direction perpendicular to the substrate, as shown in FIG. 2A.
  • the substrate has a plurality of active regions arranged in an array, and the capacitor contacts 20 are located in the active region.
  • the material of the capacitor contact 20 can be, but is not limited to, tungsten.
  • a plurality of the sacrificial layers and the supporting layers are alternately stacked in a direction perpendicular to the substrate, and the number of layers of the sacrificial layers and the supporting layers alternately stacked can be selected by those skilled in the art according to actual needs.
  • the number of layers of the supporting layer in the stack structure is at least two, and the number of layers of the sacrificial layer is at least one layer, so as to enhance the lateral stability of the capacitor array area.
  • the material of the sacrificial layer may be, but not limited to, an oxide material, such as silicon dioxide; the material of the support layer may be, but not limited to, a nitride material, such as silicon nitride.
  • Step S12 sequentially forming a first electrode layer 23, a first dielectric layer 24, and a second electrode layer 25 stacked along the radial direction of the capacitor hole 22 on the inner wall of the capacitor hole 22.
  • the capacitor hole 22 after the capacitor hole 22 is formed, materials such as titanium nitride are deposited on the inner wall surface of the capacitor hole 22 and the top surface of the laminated structure 21 (that is, the laminated structure is away from the substrate).
  • the first electrode layer 23 is formed, as shown in FIG. 2A; then, a dielectric layer material with a high dielectric constant is deposited on the surface of the first electrode layer 23 to form the first dielectric layer 24;
  • a material such as titanium nitride is deposited on the surface of the first dielectric layer 24 to form the second electrode layer 25, as shown in FIG. 2B.
  • Step S13 filling the capacitor hole 22 with a first conductive material to form a first conductive filling layer 26, as shown in FIG. 2D.
  • the first electrode layer 23, the first dielectric layer 24, and the second electrode layer 25 are also sequentially stacked on the top surface of the laminated structure 21; forming the first conductive filling layer 26
  • the specific steps include:
  • the first conductive material covering the surface of the second electrode layer 25 on the top surface of the laminated structure 21 is removed.
  • a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process may be used to deposit the first conductive material in the capacitor hole 22 to form the capacitor hole 22 (that is, the second electrode).
  • the layer 25 surrounds the capacitor hole 22) and covers the second electrode layer 25 on the surface of the laminated structure 21, as shown in FIG. 2C.
  • the first conductive material may be a metal material or a polysilicon material, which can be selected by those skilled in the art according to actual needs. After that, the first conductive material covering the top surface of the laminated structure 21 is removed, and only the first conductive material in the capacitor hole 22 remains, as shown in FIG. 2D.
  • Step S14 forming an auxiliary layer 27 that closes the capacitor hole 22, as shown in FIG. 2E.
  • the specific steps of forming the auxiliary layer 27 that closes the capacitor hole 22 include:
  • An auxiliary layer 27 that covers the second electrode layer 25 on the top surface of the laminated structure 21 and closes the capacitor hole 22 is formed.
  • the first conductive filling layer 26 makes the top surface of the first electrode layer 23, the top surface of the first dielectric layer 24, the top surface of the second electrode layer 25, and the first conductive filling layer 26 The top surface of is flush with the top surface of the laminated structure 21, as shown in FIG. 2D.
  • an insulating material is deposited on the top surface of the first electrode layer 23, the top surface of the first dielectric layer 24, and the top surface of the second electrode layer 25 by using a chemical vapor deposition, physical vapor deposition or atomic layer deposition process.
  • the top surface of the first conductive filling layer 26 and the top surface of the laminated structure 21 are as shown in FIG. 2E.
  • the material of the auxiliary layer 27 is the same as the material of the support layer.
  • the auxiliary layer 27 can be set by those skilled in the art according to actual needs.
  • the auxiliary layer 27 is greater than the thickness of any of the supporting layers in the laminated structure 21; or, the thickness of the auxiliary layer 27 is greater than the supporting layer located on the top of the laminated structure 21 (that is, the uppermost layer of the laminated structure 21). The thickness of the support layer).
  • Step S15 removing part of the auxiliary layer 27, several layers of the supporting layer and the sacrificial layer, exposing the first electrode layer 23, and the remaining auxiliary layer 27 is divided into a plurality of sub-auxiliary layers 271, each The sub auxiliary layer 271 overlaps at least two of the capacitor holes 22, as shown in FIG. 2J.
  • the laminated structure 21 includes a first supporting layer 211, a first sacrificial layer 212, a second supporting layer 213, a second sacrificial layer 214, and a third supporting layer 211, which are sequentially stacked in a direction perpendicular to the substrate.
  • Supporting layer 215; The specific steps of removing part of the auxiliary layer 27, several layers of the supporting layer and the sacrificial layer include:
  • the auxiliary layer 27, the third supporting layer 215, the second sacrificial layer 214, the second supporting layer 213, and the first sacrificial layer 212 are sequentially etched along the etching window 281, so that the remaining
  • the auxiliary layer 27 is divided into a plurality of sub auxiliary layers 271, and each sub auxiliary layer 271 overlaps the two capacitor holes 22.
  • the auxiliary layer 27 and the third supporting layer 215 are made of the same material (for example, both are silicon nitride) as an example.
  • the photoresist layer 28 covering the auxiliary layer 27 is formed.
  • the photoresist layer 28 has an etching window 281 exposing the auxiliary layer 27.
  • the position of the etching window 281 is two adjacent to each other.
  • the gaps between the capacitor holes 22 correspond, as shown in FIG. 2F.
  • the second sacrificial layer 214 as an etch stop layer, a part of the third support layer 215 of the auxiliary layer 27 is etched away to obtain a structure as shown in FIG. 2G.
  • the continuous auxiliary layer 27 is divided into a plurality of mutually independent sub-auxiliary layers 271.
  • Two adjacent sub-auxiliary layers 271 are separated from each other by a gap region 272, and each segment
  • the sub auxiliary layer 271 continuously covers two adjacent capacitor holes.
  • the top surface of layer 214 is flush.
  • those skilled in the art can also adjust the position of the etching window 281 so that the first electrode layer 23, the first dielectric layer 24, and the second electrode layer 25 are not etched. eclipse.
  • the photoresist layer 28 is removed, and the second sacrificial layer 214 is removed by using an acid solution such as hydrofluoric acid to expose the second support layer 213, as shown in FIG. 2H.
  • an acidic solution such as hydrofluoric acid is used to remove the first sacrificial layer 212, exposing the surface of the first support layer 211 and the first electrode layer 23 away from the capacitor hole 22, as shown in FIG. 2J.
  • the capacitor hole 22 has been filled with the first conductive filling layer 26, the first electrode layer 23, the first dielectric layer 24, and the The stability of the second electrode layer 25 prevents the first electrode layer 23, the first dielectric layer 24, and the second electrode layer 25 from collapsing or overturning; on the other hand, the first electrode layer
  • the top surfaces of the layer 23, the first dielectric layer 24, and the second electrode layer 25 are also covered with the sub-auxiliary layer 271, which strengthens the first electrode layer 23, the first dielectric layer 24, and the The stability of the top of the second electrode layer 25 is described, thereby further avoiding the occurrence of electrode collapse or overturning.
  • Step S16 forming a second dielectric layer 29 covering the surface of the first electrode layer 23 and the surface of the sub auxiliary layer 271, and a third electrode layer 30 covering the surface of the second dielectric layer 29 to form a double-sided capacitor structure.
  • a dielectric material with a high dielectric constant is deposited on the exposed surface of the first support layer 211, the surface of the first electrode layer 23 away from the capacitor hole 22, and the top of the first electrode layer 23.
  • the surface, the surface of the first dielectric layer 24, the surface of the second electrode layer 25, and the surface of the sub auxiliary layer 271 form the second dielectric layer 29, as shown in FIG. 2K.
  • a conductive material such as titanium nitride is deposited on the surface of the second dielectric layer 29 to form the third electrode layer 30, as shown in FIG. 2L.
  • the material of the second dielectric layer 29 may be the same as or different from the material of the first dielectric layer 24, and those skilled in the art can choose according to actual needs.
  • the method further includes the following steps:
  • a second conductive material is deposited on the surface of the third electrode layer 30 to form a second conductive filling layer 31, as shown in FIG. 2M.
  • a second conductive material is deposited on the surface of the third electrode layer 30, and the formed second conductive filling layer 31 is completely filled to remove the third support layer 215, the second sacrificial layer 214, and the The second supporting layer 213, the first sacrificial layer 212, and some of the gaps formed after the auxiliary layer 27 further enhance the stability of the double-sided capacitor structure.
  • the material of the second conductive filling layer 31 may be the same as the material of the first conductive filling layer 26, for example, both are polysilicon materials.
  • this specific embodiment also provides a double-sided capacitor structure.
  • the double-sided capacitor structure provided in this embodiment can be formed by the method shown in FIGS. 1 and 2A-2M.
  • FIG. 2M For a schematic diagram of the double-sided capacitor structure provided in this embodiment, refer to FIG. 2M.
  • the double-sided capacitor structure provided in this embodiment includes:
  • a base the base includes a substrate, a plurality of capacitor contacts 20 located in the substrate, a stacked structure 21 located on the surface of the substrate, and a stacked structure 21 that penetrates the stacked structure 21 and exposes the capacitor contacts 20, a plurality of capacitor holes 22, the laminated structure 21 at least includes a plurality of supporting layers stacked in a direction perpendicular to the substrate;
  • the first electrode layer 23 covers the inner wall of the capacitor hole 22;
  • the first dielectric layer 24 covers the sidewall surface and the bottom wall surface of the first electrode layer 23 facing the capacitor hole 22;
  • the second electrode layer 25 covers the sidewall surface and the bottom wall surface of the first dielectric layer 24 facing the capacitor hole 22;
  • the first conductive filling layer 26 is filled in the area surrounded by the second electrode layer 25;
  • the second dielectric layer 29 covers the sidewall surface and the top surface of the first electrode layer 23 away from the capacitor hole 22 and the surface of the sub auxiliary layer 271;
  • the third electrode layer 30 covers the surface of the second dielectric layer 29.
  • each segment of the auxiliary sub-layer 271 continuously covers two adjacent capacitor holes 22.
  • the first electrode layer 23 located in the same capacitor hole 22 has a height difference on both sides of the capacitor hole 22 in the radial direction, and the first electrode layer 23 is directly connected to the sub auxiliary layer 271.
  • the height of one side of the contact is greater than the height of the other side, that is, the top surface of the first electrode layer 23 that is in direct contact with the sub-auxiliary layer 271 is located above the top surface of the other side.
  • those skilled in the art can also adjust the manufacturing process so that the first electrode layer 23 located in the same capacitor hole 22 has the same height on both sides of the capacitor hole 22 in the radial direction. .
  • the stacked structure 21 includes a first supporting layer 211, a second supporting layer 213, and a third supporting layer 215 that are sequentially stacked in a direction perpendicular to the substrate;
  • Each section of the auxiliary sub-layer 271 covers the surface of the two capacitor holes 22 that overlap it and the surface of the third support layer 215 between the two adjacent capacitor holes 22 that overlap it.
  • the third support layer 215 has a first opening 2151 corresponding to the gap area 272 between the two adjacent sub-auxiliary layers 271, and the width of the first opening 2151 is larger than the gap area 272 width;
  • the second supporting layer 213 has a second opening corresponding to the gap area 272 between the two adjacent sub-auxiliary layers 271.
  • the width of the first opening 2151 is greater than the width of the gap region 272, that is, the third supporting layer 215 does not separate from the gap between the two adjacent sub-auxiliary layers 271.
  • the area 272 extends; in this specific embodiment, the width of the second opening in the second supporting layer 213 is the same as the first opening 2151, that is, the second supporting layer 213 does not extend horizontally.
  • the direction protrudes from the sub auxiliary layer 271.
  • the thickness of the sub auxiliary layer 271 is greater than that of the third support layer 215.
  • those skilled in the art can also set the thickness of the sub-assisted layer 271 to be equal to the thickness of the third support layer 215 according to actual needs.
  • the material of the sub auxiliary layer 271 is the same as the material of the support layer.
  • they are all nitride materials (such as silicon nitride) to simplify the manufacturing process.
  • the double-sided capacitor structure further includes:
  • the second conductive filling layer 31 covers the surface of the third electrode layer 30.
  • the second conductive filling layer 31 fills the gap region 272, the first opening, and the second opening.
  • the material of the second conductive filling layer 31 may be the same as the material of the first conductive filling layer 26, for example, both are polysilicon materials.
  • the double-sided capacitor structure and the method for forming the same provided in this embodiment, on the one hand, by filling the first conductive filling layer in the area surrounded by the second electrode layer in the capacitor hole, the first electrode layer and the second electrode The layer is supported, reducing or even avoiding the risk of electrode collapse and overturning; on the other hand, by forming multiple sub-assisted layers that close the capacitor holes, and each segment of the sub-assisted layer overlaps at least two capacitor holes to enhance This improves the stability of the top of the first electrode layer and the second electrode layer, thereby further avoiding the risk of electrode collapse and overturning, improving the overall stability of the double-sided capacitor structure, and also helping to increase the double-sided The capacitance value of the capacitor structure.

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Abstract

本申请涉及一种双面电容结构及其形成方法。所述双面电容结构的形成方法包括如下步骤：提供一基底，所述基底包括衬底、位于所述衬底内的多个电容触点、位于所述衬底表面的叠层结构、以及贯穿所述叠层结构并暴露所述电容触点的多个电容孔，所述叠层结构包括交替堆叠的牺牲层和支撑层；依次形成第一电极层、第一电介质层和第二电极层于所述电容孔的内壁；形成第一导电填充层于所述电容孔内；形成封闭所述电容孔的辅助层；去除部分所述辅助层、若干层所述支撑层和所述牺牲层，暴露所述第一电极层；形成第二电介质层和第三电极层。本申请减少甚至是避免了电极坍塌和倾覆的风险，同时还有助于增大双面电容结构的电容值。

Description

双面电容结构及其形成方法
相关申请引用说明
本申请要求于2020年3月20日递交的中国专利申请号202010199381.6、申请名为“双面电容结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种双面电容结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体结构，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启与关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
随着半导体器件尺寸的微缩，其在衬底上的横向面积减小。为了提高或者维持电容器具有足够高的电容值，可以通过增加下电极(bottom electrode)的高度或者是减小下电极的厚度。但是，增加下电极的高度或者是减小下电极的厚度会导致下电极的长径比较高，厚度较薄，从而对电容阵列区域的性能可靠性造成影响。比如，会引起下电极的坍塌或者倾覆，导致相邻的下电极短路。
为了解决这一问题，可以采用的做法是通过添加电极的横向连续支撑层，以增加下电极的稳定性。但是，单层的横向支撑层有其高度极限，从而使得电容器的电容值受到电极高度的限制，电极倾覆和成片坍塌的风险依然存在。
因此，如何解决电容阵列区域横向不稳定的问题，减小下电极坍塌或者倾覆的风险，提高半导体器件的性能稳定性，是目前亟待解决的技术问题。
发明内容
本申请提供了一种双面电容结构及其形成方法，用于解决电容阵列区域横向稳定性较差的问题，以提高半导体器件的性能稳定性。
为了解决上述问题，本申请提供了一种双面电容结构的形成方法，包括如 下步骤：
提供一基底，所述基底包括衬底、位于所述衬底内的多个电容触点、位于所述衬底表面的叠层结构、以及贯穿所述叠层结构并暴露所述电容触点的多个电容孔，所述叠层结构包括沿垂直于所述衬底的方向交替堆叠的牺牲层和支撑层；
依次形成沿所述电容孔的径向方向叠置的第一电极层、第一电介质层和第二电极层于所述电容孔的内壁；
填充第一导电材料于所述电容孔内，形成第一导电填充层；
形成封闭所述电容孔的辅助层；
去除部分所述辅助层、若干层所述支撑层和所述牺牲层，暴露所述第一电极层，残留的所述辅助层被分隔为多段子辅助层，每段所述子辅助层至少与两个所述电容孔交叠；
形成覆盖所述第一电极层表面和所述子辅助层表面的第二电介质层、以及覆盖于所述第二电介质层表面的第三电极层，形成双面电容结构。
可选的，所述第一电极层、所述第一电介质层和所述第二电极层还依次叠置于所述叠层结构的顶面；形成第一导电填充层的具体步骤包括：
沉积第一导电材料于所述电容孔内及位于所述叠层结构顶面的所述第二电极层表面；
去除覆盖于所述叠层结构顶面的所述第二电极层表面的所述第一导电材料。
可选的，形成封闭所述电容孔的辅助层的具体步骤包括：
去除覆盖于所述叠层结构顶面的所述第一电极层、所述第一电介质层和所述第二电极层；
形成覆盖所述叠层结构顶面的所述第二电极层并封闭所述电容孔的辅助层。
可选的，所述叠层结构包括沿垂直于所述衬底的方向依次叠置的第一支撑层、第一牺牲层、第二支撑层、第二牺牲层和第三支撑层；去除部分所述辅助层、若干层所述支撑层和所述牺牲层的具体步骤包括：
形成覆盖所述辅助层的光阻层，所述光阻层中具有暴露所述辅助层的刻蚀 窗口；
沿所述刻蚀窗口依次刻蚀所述辅助层、所述第三支撑层、所述第二牺牲层、所述第二支撑层和所述第一牺牲层，使得残留的所述辅助层被分隔为多段子辅助层，每段所述子辅助层与两个所述电容孔交叠。
可选的，所述辅助层的材料与所述支撑层的材料相同。
可选的，形成双面电容结构之后，还包括如下步骤：
沉积第二导电材料于所述第三电极层表面，形成第二导电填充层。
为了解决上述问题，本申请还提供了一种双面电容结构，包括：
基底，所述基底包括衬底、位于所述衬底内的多个电容触点、位于所述衬底表面的叠层结构、以及贯穿所述叠层结构并暴露所述电容触点的多个电容孔，所述叠层结构至少包括沿垂直于所述衬底的方向堆叠的若干支撑层；
第一电极层，覆盖于所述电容孔内壁；
第一电介质层，覆盖于所述第一电极层朝向所述电容孔的侧壁表面和底壁表面；
第二电极层，覆盖于所述第一电介质层朝向所述电容孔的侧壁表面和底壁表面；
第一导电填充层，填充于所述第二电极层围绕而成的区域内；
多段相互隔离的子辅助层，所述子辅助层覆盖于所述叠层结构的顶面，且每段所述子辅助层至少与两个所述电容孔交叠；
第二电介质层，覆盖于所述第一电极层背离所述电容孔的侧壁表面和顶面、以及所述子辅助层表面；
第三电极层，覆盖于所述第二电介质层表面。
可选的，所述叠层结构包括沿垂直于所述衬底的方向依次叠置的第一支撑层、第二支撑层和第三支撑层；
每段所述子辅助层覆盖于与其交叠的两个所述电容孔表面、以及覆盖于与其交叠的相邻两个电容孔之间的所述第三支撑层表面。
可选的，所述第三支撑层中具有与相邻两段所述子辅助层之间的间隙区域对应的第一开口，所述第一开口的宽度大于所述间隙区域的宽度；
所述第二支撑层中具有与相邻两段所述子辅助层之间的间隙区域对应的 第二开口。
可选的，所述子辅助层的厚度大于所述第三支撑层。
可选的，所述子辅助层的材料与所述支撑层的材料相同。
可选的，还包括：
第二导电填充层，覆盖于所述第三电极层表面。
本申请提供的双面电容结构及其形成方法，一方面，通过在电容孔内的第二电极层围绕而成的区域内填充第一导电填充层，对第一电极层和第二电极层进行了支撑，减少甚至是避免了电极坍塌和倾覆的风险；另一方面，通过形成封闭电容孔的多段子辅助层，且每段所述子辅助层与至少两个电容孔交叠，增强了所述第一电极层和所述第二电极层顶部的稳定性，从而进一步避免了电极坍塌和倾覆的风险，提高了双面电容结构整体的稳定性，同时还有助于增大双面电容结构的电容值。
附图说明
附图1是本申请具体实施方式中双面电容结构的形成方法流程图；
附图2A-2M是本申请具体实施方式在形成双面电容结构的过程中主要的工艺截面示意图。
具体实施方式
下面结合附图对本申请提供的双面电容结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种双面电容结构的形成方法，附图1是本申请具体实施方式中双面电容结构的形成方法流程图，附图2A-2M是本申请具体实施方式在形成双面电容结构的过程中主要的工艺截面示意图。本具体实施方式中所述的双面电容结构可以是但不限于应用于DRAM存储器中。如图1、图2A-图2M所示，本具体实施方式提供的双面电容结构的形成方法，包括如下步骤：
步骤S11，提供一基底，所述基底包括衬底、位于所述衬底内的多个电容触点20、位于所述衬底表面的叠层结构21、以及贯穿所述叠层结构21并暴露所述电容触点20的多个电容孔22，所述叠层结构21包括沿垂直于所述衬底的方向交替堆叠的牺牲层和支撑层，如图2A所示。
具体来说，所述衬底内部具有呈阵列排布的多个有源区，所述电容触点20位于所述有源区内。所述电容触点20的材料可以是但不限于钨。多个所述牺牲层和所述支撑层沿垂直于所述衬底的方向交替堆叠，所述牺牲层和所述支撑层交替堆叠的层数，本领域技术人员可以根据实际需要进行选择。在本具体实施方式中，所述堆叠结构中所述支撑层的层数至少为2层，所述牺牲层的层数至少为1层，以便于增强电容阵列区域的横向稳定性。所述牺牲层的材料可以是但不限于氧化物材料，例如二氧化硅；所述支撑层的材料可以是但不限于氮化物材料，例如氮化硅。
步骤S12，依次形成沿所述电容孔22的径向方向叠置的第一电极层23、第一电介质层24和第二电极层25于所述电容孔22的内壁。
具体来说，在形成所述电容孔22之后，沉积氮化钛等材料于所述电容孔22的内壁表面和所述叠层结构21的顶面(即所述叠层结构背离所述衬底的表面)，形成所述第一电极层23，如图2A所示；然后，沉积具有高介电常数的电介质层材料于所述第一电极层23表面，形成所述第一电介质层24；接着，沉积氮化钛等材料于所述第一电介质层24表面，形成所述第二电极层25，如图2B所示。
步骤S13，填充第一导电材料于所述电容孔22内，形成第一导电填充层26，如图2D所示。
可选的，所述第一电极层23、所述第一电介质层24和所述第二电极层25还依次叠置于所述叠层结构21的顶面；形成第一导电填充层26的具体步骤包括：
沉积第一导电材料于所述电容孔22内及位于所述叠层结构21顶面的所述第二电极层表面；
去除覆盖于所述叠层结构21顶面的所述第二电极层25表面的所述第一导电材料。
具体来说，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沉积所述第一导电材料于所述电容孔22内，形成填充满所述电容孔22(即所述第二电极层25在所述电容孔22内围绕而成的区域)并覆盖于所述叠层结构21表面的所述第二电极层25之上，如图2C所示。所述第一导电材料 可以是金属材料，也可以是多晶硅材料，本领域技术人员可以根据实际需要进行选择。之后，去除覆盖于所述叠层结构21顶面的所述第一导电材料，仅残留位于所述电容孔22内的所述第一导电材料，如图2D所示。
步骤S14，形成封闭所述电容孔22的辅助层27，如图2E所示。
可选的，形成封闭所述电容孔22的辅助层27的具体步骤包括：
去除覆盖于所述叠层结构21顶面的所述第一电极层23、所述第一电介质层24和所述第二电极层25；
形成覆盖所述叠层结构21顶面的所述第二电极层25并封闭所述电容孔22的辅助层27。
具体来说，去除覆盖于所述叠层结构21顶面的所述第一电极层23、所述第一电介质层24、所述第二电极层25、以及所述电容孔22内的部分所述第一导电填充层26，使得所述第一电极层23的顶面、所述第一电介质层24的顶面、所述第二电极层25的顶面、所述第一导电填充层26的顶面均与所述叠层结构21的顶面平齐，如图2D所示。之后，采用化学气相沉积、物理气相沉积或者原子层沉积工艺沉积绝缘材料于所述第一电极层23的顶面、所述第一电介质层24的顶面、所述第二电极层25的顶面、所述第一导电填充层26的顶面和所述叠层结构21的顶面，如图2E所示。
为了简化后续刻蚀工艺，可选的，所述辅助层27的材料与所述支撑层的材料相同。
所述辅助层27的具体厚度，本领域技术人员可以根据实际需要进行设置。在本具体实施方式中，为了进一步增强对所述第一电极层23、所述第一电介质层24和所述第二电极层25顶部的横向支撑作用，可选的，所述辅助层27的厚度大于所述叠层结构21中任一所述支撑层的厚度；或者，所述辅助层27的厚度大于位于所述叠层结构21的顶部的支撑层(即所述叠层结构21最上层的支撑层)的厚度。
步骤S15，去除部分所述辅助层27、若干层所述支撑层和所述牺牲层，暴露所述第一电极层23，残留的所述辅助层27被分隔为多段子辅助层271，每段所述子辅助层271至少与两个所述电容孔22交叠，如图2J所示。
可选的，所述叠层结构21包括沿垂直于所述衬底的方向依次叠置的第一 支撑层211、第一牺牲层212、第二支撑层213、第二牺牲层214和第三支撑层215；去除部分所述辅助层27、若干层所述支撑层和所述牺牲层的具体步骤包括：
形成覆盖所述辅助层27的光阻层28，所述光阻层28中具有暴露所述辅助层27的刻蚀窗口281；
沿所述刻蚀窗口281依次刻蚀所述辅助层27、所述第三支撑层215、所述第二牺牲层214、所述第二支撑层213和所述第一牺牲层212，使得残留的所述辅助层27被分隔为多段子辅助层271，每段所述子辅助层271与两个所述电容孔22交叠。
以下以所述辅助层27与所述第三支撑层215的材料相同(例如均为氮化硅)为例进行说明。首先，形成覆盖所述辅助层27的所述光阻层28，所述光阻层28中具有暴露所述辅助层27的刻蚀窗口281，所述刻蚀窗口281的位置与相邻两个所述电容孔22之间的间隙对应，如图2F所示。之后，以所述第二牺牲层214为刻蚀截止层，刻蚀掉部分的所述辅助层27的所述第三支撑层215，得到如图2G所示的结构。通过本步骤的刻蚀，连续的所述辅助层27被分割为多段相互独立的所述子辅助层271，相邻两个所述子辅助层271之间通过间隙区域272相互隔开，每段所述子辅助层271连续覆盖两个相邻的所述电容孔。在本步骤的刻蚀过程中，还有可能刻蚀掉位于所述电容孔22一侧的部分所述第一电极层23、所述第一电介质层24和所述第二电极层25，暴露出部分的所述第一导电填充层26，使得刻蚀后残留的所述第一电极层23、所述第一电介质层24和所述第二电极层25的顶面与所述第二牺牲层214的顶面平齐。本领域技术人员在实际操作过程中，也可以通过调整所述刻蚀窗口281的位置，使得所述第一电极层23、所述第一电介质层24和所述第二电极层25不被刻蚀。接着，去除所述光阻层28，并采用氢氟酸等酸性溶液去除所述第二牺牲层214，暴露所述第二支撑层213，如图2H所示。然后，继续沿所述间隙区域272刻蚀掉部分的所述第二支撑层213，暴露所述第一牺牲层212，如图2I所示。紧接着，采用氢氟酸等酸性溶液去除所述第一牺牲层212，暴露所述第一支撑层211和所述第一电极层23背离所述电容孔22的表面，如图2J所示。
在本步骤的刻蚀过程中，一方面，由于所述电容孔22内已填充满所述第 一导电填充层26，增强了所述第一电极层23、所述第一电介质层24和所述第二电极层25的稳定性，避免了所述第一电极层23、所述第一电介质层24和所述第二电极层25出现坍塌或者倾覆；另一方面，在所述第一电极层23、所述第一电介质层24和所述第二电极层25的顶面还覆盖有所述子辅助层271，增强了所述第一电极层23、所述第一电介质层24和所述第二电极层25的顶部的稳定性，从而进一步避免了电极坍塌或者倾覆的出现。
步骤S16，形成覆盖所述第一电极层23表面和所述子辅助层271表面的第二电介质层29、以及覆盖于所述第二电介质层29表面的第三电极层30，形成双面电容结构。
具体来说，沉积具有高介电常数的电介质材料于暴露的所述第一支撑层211表面、所述第一电极层23背离所述电容孔22的表面、所述第一电极层23的顶面、所述第一电介质层24的表面、所述第二电极层25的表面和所述子辅助层271的表面，形成所述第二电介质层29，如图2K所示。之后，沉积氮化钛等导电材料于所述第二电介质层29表面，形成所述第三电极层30，如图2L所示。其中，所述第二电介质层29的材料可以与所述第一电介质层24的材料相同，也可以不同，本领域技术人员可以根据实际需要进行选择。
可选的，形成双面电容结构之后，还包括如下步骤：
沉积第二导电材料于所述第三电极层30表面，形成第二导电填充层31，如图2M所示。
具体来说，沉积第二导电材料于所述第三电极层30的表面，形成的所述第二导电填充层31填充满去除所述第三支撑层215、所述第二牺牲层214、所述第二支撑层213、所述第一牺牲层212、以及部分所述辅助层27之后形成的空隙，从而进一步增强所述双面电容结构的稳定性。所述第二导电填充层31的材料可以与所述第一导电填充层26的材料相同，例如均为多晶硅材料。
不仅如此，本具体实施方式还提供了一种双面电容结构。本具体实施方式提供的双面电容结构可以采用如图1、图2A-图2M所示的方法形成。本具体实施方式提供的双面电容结构的示意图可参见图2M。如图2A-图2M所示，本具体实施方式提供的双面电容结构，包括：
基底，所述基底包括衬底、位于所述衬底内的多个电容触点20、位于所述 衬底表面的叠层结构21、以及贯穿所述叠层结构21并暴露所述电容触点20的多个电容孔22，所述叠层结构21至少包括沿垂直于所述衬底的方向堆叠的若干支撑层；
第一电极层23，覆盖于所述电容孔22内壁；
第一电介质层24，覆盖于所述第一电极层23朝向所述电容孔22的侧壁表面和底壁表面；
第二电极层25，覆盖于所述第一电介质层24朝向所述电容孔22的侧壁表面和底壁表面；
第一导电填充层26，填充于所述第二电极层25围绕而成的区域内；
多段相互隔离的子辅助层271，所述子辅助层271覆盖于所述叠层结构21的顶面，且每段所述子辅助层271至少与两个所述电容孔22交叠；
第二电介质层29，覆盖于所述第一电极层23背离所述电容孔22的侧壁表面和顶面、以及所述子辅助层271表面；
第三电极层30，覆盖于所述第二电介质层29表面。
在本具体实施方式中，每段所述子辅助层271连续覆盖两个相邻的所述电容孔22。位于同一个所述电容孔22内的所述第一电极层23沿所述电容孔22径向方向的两侧存在一高度差，所述第一电极层23中与所述子辅助层271直接接触的一侧的高度大于另一侧的高度，即所述第一电极层23中与所述子辅助层271直接接触的一侧的顶面位于另一侧的顶面之上。在其他具体实施方式中，本领域技术人员也可以通过调整制程工艺，使得位于同一个所述电容孔22内的所述第一电极层23沿所述电容孔22径向方向的两侧高度相同。
可选的，所述叠层结构21包括沿垂直于所述衬底的方向依次叠置的第一支撑层211、第二支撑层213和第三支撑层215；
每段所述子辅助层271覆盖于与其交叠的两个所述电容孔22表面、以及覆盖于与其交叠的相邻两个电容孔22之间的所述第三支撑层215表面。
可选的，所述第三支撑层215中具有与相邻两段所述子辅助层271之间的间隙区域272对应的第一开口2151，所述第一开口2151的宽度大于所述间隙区域272的宽度；
所述第二支撑层213中具有与相邻两段所述子辅助层271之间的间隙区域 272对应的第二开口。
具体来说，参见图2J，所述第一开口2151的宽度大于所述间隙区域272的宽度，即所述第三支撑层215不会自相邻两段所述子辅助层271之间的间隙区域272伸出；在本具体实施方式中，位于所述第二支撑层213中的所述第二开口的宽度与所述第一开口2151相同，即所述第二支撑层213不会沿水平方向突出于所述子辅助层271。通过限定所述间隙区域272与所述第一开口2151、所述第二开口之间的宽度关系，一方面，有助于在制程工艺中充分去除所述第二牺牲层214和所述第一牺牲层212；另一方面，还有助于进一步增大所述第三电极层30的高度，从而进一步增加所述电容器的电容值。
为了进一步增强各电极层顶部的稳定性，可选的，所述子辅助层271的厚度大于所述第三支撑层215。
在其他具体实施方式中，本领域技术人员还可以根据实际需要将所述子辅助层271的厚度设置的与所述第三支撑层215的厚度相等。
可选的，所述子辅助层271的材料与所述支撑层的材料相同。例如，均为氮化物材料(例如氮化硅)，以简化制程工艺。
可选的，所述双面电容结构还包括：
第二导电填充层31，覆盖于所述第三电极层30表面。
所述第二导电填充层31填充满所述间隙区域272、所述第一开口和所述第二开口。所述第二导电填充层31的材料可以与所述第一导电填充层26的材料相同，例如均为多晶硅材料。
本具体实施方式提供的双面电容结构及其形成方法，一方面，通过在电容孔内的第二电极层围绕而成的区域内填充第一导电填充层，对第一电极层和第二电极层进行了支撑，减少甚至是避免了电极坍塌和倾覆的风险；另一方面，通过形成封闭电容孔的多段子辅助层，且每段所述子辅助层与至少两个电容孔交叠，增强了所述第一电极层和所述第二电极层顶部的稳定性，从而进一步避免了电极坍塌和倾覆的风险，提高了双面电容结构整体的稳定性，同时还有助于增大双面电容结构的电容值。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通 技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (12)

  1. 一种双面电容结构的形成方法，包括如下步骤：
    提供一基底，所述基底包括衬底、位于所述衬底内的多个电容触点、位于所述衬底表面的叠层结构、以及贯穿所述叠层结构并暴露所述电容触点的多个电容孔，所述叠层结构包括沿垂直于所述衬底的方向交替堆叠的牺牲层和支撑层；
    依次形成沿所述电容孔的径向方向叠置的第一电极层、第一电介质层和第二电极层于所述电容孔的内壁；
    填充第一导电材料于所述电容孔内，形成第一导电填充层；
    形成封闭所述电容孔的辅助层；
    去除部分所述辅助层、若干层所述支撑层和所述牺牲层，暴露所述第一电极层，残留的所述辅助层被分隔为多段子辅助层，每段所述子辅助层至少与两个所述电容孔交叠；
    形成覆盖所述第一电极层表面和所述子辅助层表面的第二电介质层、以及覆盖于所述第二电介质层表面的第三电极层，形成双面电容结构。
  2. 如权利要求1所述方法，其中，所述第一电极层、所述第一电介质层和所述第二电极层还依次叠置于所述叠层结构的顶面；形成第一导电填充层的具体步骤包括：
    沉积第一导电材料于所述电容孔内及位于所述叠层结构顶面的所述第二电极层表面；
    去除覆盖于所述叠层结构顶面的所述第二电极层表面的所述第一导电材料。
  3. 如权利要求2所述方法，其中，形成封闭所述电容孔的辅助层的具体步骤包括：
    去除覆盖于所述叠层结构顶面的所述第一电极层、所述第一电介质层和所述第二电极层；
    形成覆盖所述叠层结构顶面的所述第二电极层并封闭所述电容孔的辅助层。
  4. 如权利要求1所述方法，其中，所述叠层结构包括沿垂直于所述衬底的方向依次叠置的第一支撑层、第一牺牲层、第二支撑层、第二牺牲层和第三支撑层；去除部分所述辅助层、若干层所述支撑层和所述牺牲层的具体步骤包括：
    形成覆盖所述辅助层的光阻层，所述光阻层中具有暴露所述辅助层的刻蚀窗口；
    沿所述刻蚀窗口依次刻蚀所述辅助层、所述第三支撑层、所述第二牺牲层、所述第二支撑层和所述第一牺牲层，使得残留的所述辅助层被分隔为多段子辅助层，每段所述子辅助层与两个所述电容孔交叠。
  5. 如权利要求1所述方法，其中，所述辅助层的材料与所述支撑层的材料相同。
  6. 如权利要求1所述方法，其中，形成双面电容结构之后，还包括如下步骤：
    沉积第二导电材料于所述第三电极层表面，形成第二导电填充层。
  7. 一种双面电容结构，包括：
    基底，所述基底包括衬底、位于所述衬底内的多个电容触点、位于所述衬底表面的叠层结构、以及贯穿所述叠层结构并暴露所述电容触点的多个电容孔，所述叠层结构至少包括沿垂直于所述衬底的方向堆叠的若干支撑层；
    第一电极层，覆盖于所述电容孔内壁；
    第一电介质层，覆盖于所述第一电极层朝向所述电容孔的侧壁表面和底壁表面；
    第二电极层，覆盖于所述第一电介质层朝向所述电容孔的侧壁表面和底壁表面；
    第一导电填充层，填充于所述第二电极层围绕而成的区域内；
    多段相互隔离的子辅助层，所述子辅助层覆盖于所述叠层结构的顶面，且每段所述子辅助层至少与两个所述电容孔交叠；
    第二电介质层，覆盖于所述第一电极层背离所述电容孔的侧壁表面和顶面、以及所述子辅助层表面；
    第三电极层，覆盖于所述第二电介质层表面。
  8. 如权利要求7所述结构，其中，所述叠层结构包括沿垂直于所述衬底的方向依次叠置的第一支撑层、第二支撑层和第三支撑层；
    每段所述子辅助层覆盖于与其交叠的两个所述电容孔表面、以及覆盖于与其交叠的相邻两个电容孔之间的所述第三支撑层表面。
  9. 如权利要求8所述结构，其中，所述第三支撑层中具有与相邻两段所述子辅助层之间的间隙区域对应的第一开口，所述第一开口的宽度大于所述间隙区域的宽度；
    所述第二支撑层中具有与相邻两段所述子辅助层之间的间隙区域对应的第二开口。
  10. 如权利要求8所述结构，其中，所述子辅助层的厚度大于所述第三支撑层。
  11. 如权利要求7所述结构，其中，所述子辅助层的材料与所述支撑层的材料相同。
  12. 如权利要求7所述结构，还包括：
    第二导电填充层，覆盖于所述第三电极层表面。
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Publication number Priority date Publication date Assignee Title
CN113540348B (zh) * 2020-04-14 2024-02-06 中国科学院微电子研究所 电容器、半导体器件、电子设备及其制造方法
US11942277B2 (en) * 2021-04-13 2024-03-26 Nanya Technology Corporation Method of manufacturing semiconductor structure and semiconductor structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127269A (ja) * 1999-10-25 2001-05-11 Nec Corp 半導体装置及びその製造方法
CN107393909A (zh) * 2017-07-25 2017-11-24 睿力集成电路有限公司 双面电容器及其制造方法
CN208336219U (zh) * 2018-06-27 2019-01-04 长鑫存储技术有限公司 双面电容器结构

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6737696B1 (en) * 1998-06-03 2004-05-18 Micron Technology, Inc. DRAM capacitor formulation using a double-sided electrode
KR101901787B1 (ko) * 2012-03-23 2018-09-28 삼성전자주식회사 반도체 기억 소자 및 반도체 기억 소자의 형성 방법
EP3297024A1 (en) * 2016-09-20 2018-03-21 Ipdia 3d-capacitor structure
KR102617422B1 (ko) * 2016-12-19 2023-12-21 삼성전자주식회사 반도체 장치
US10276651B2 (en) * 2017-09-01 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Low warpage high density trench capacitor
CN108447864B (zh) * 2018-03-14 2023-09-29 长鑫存储技术有限公司 半导体存储器件结构及其制作方法
US10312241B1 (en) * 2018-04-27 2019-06-04 Micron Technology, Inc. Integrated memory and integrated assemblies
CN110504283A (zh) * 2018-05-17 2019-11-26 长鑫存储技术有限公司 柱状电容器阵列结构及制备方法
CN208521929U (zh) * 2018-06-07 2019-02-19 长鑫存储技术有限公司 半导体集成电路的电容装置
CN208589442U (zh) * 2018-07-19 2019-03-08 长鑫存储技术有限公司 电容阵列结构
WO2020029119A1 (zh) * 2018-08-08 2020-02-13 深圳市为通博科技有限责任公司 双面电容器及其制作方法
TWI671885B (zh) * 2018-08-16 2019-09-11 華邦電子股份有限公司 記憶體裝置及其製造方法
US10916638B2 (en) * 2018-09-18 2021-02-09 International Business Machines Corporation Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance
US11171146B2 (en) * 2019-12-12 2021-11-09 Micron Technology, Inc. Memory devices and methods of forming memory devices
US11640971B2 (en) * 2020-12-18 2023-05-02 Taiwan Semiconductor Manufacturing Company Limited Deep trench capacitor including self-aligned plate contact via structures and methods of forming the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127269A (ja) * 1999-10-25 2001-05-11 Nec Corp 半導体装置及びその製造方法
CN107393909A (zh) * 2017-07-25 2017-11-24 睿力集成电路有限公司 双面电容器及其制造方法
CN208336219U (zh) * 2018-06-27 2019-01-04 长鑫存储技术有限公司 双面电容器结构

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