WO2021204047A1 - 半导体存储器件及其制备方法 - Google Patents

半导体存储器件及其制备方法 Download PDF

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Publication number
WO2021204047A1
WO2021204047A1 PCT/CN2021/084439 CN2021084439W WO2021204047A1 WO 2021204047 A1 WO2021204047 A1 WO 2021204047A1 CN 2021084439 W CN2021084439 W CN 2021084439W WO 2021204047 A1 WO2021204047 A1 WO 2021204047A1
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Prior art keywords
layer
electrode layer
upper electrode
dielectric layer
capacitor
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PCT/CN2021/084439
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English (en)
French (fr)
Inventor
权俊模
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长鑫存储技术有限公司
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Priority to US17/386,443 priority Critical patent/US20210358917A1/en
Publication of WO2021204047A1 publication Critical patent/WO2021204047A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • This application relates to the technical field of semiconductor device manufacturing, in particular to a semiconductor storage device and a manufacturing method thereof.
  • a semiconductor memory device and a manufacturing method thereof are provided.
  • a method for manufacturing a semiconductor memory device includes the following steps: providing a substrate; forming a stacked structure on the substrate, the stacked structure including forming a bottom dielectric layer, a sacrificial layer, and a top layer sequentially stacked from bottom to top A dielectric layer; forming a plurality of spaced capacitor holes in the stacked structure, the capacitor holes penetrating the stacked structure and exposing the substrate; forming a bottom electrode layer in the capacitor holes, the The lower electrode layer fills the capacitor hole; the top dielectric layer is removed to expose the upper part of the sacrificial layer and the lower electrode layer; on the exposed surface of the sacrificial layer and the lower electrode layer A first capacitor dielectric layer is formed on the upper surface; a first upper electrode layer is formed on the surface of the first capacitor dielectric layer; a plurality of openings are formed in the first upper electrode layer and the first capacitor dielectric layer, the The opening exposes the sacrificial layer; the sacrificial layer is removed based on the opening;
  • the top dielectric layer as the support layer is removed after the lower electrode layer is formed and before the sacrificial layer is removed, and the first capacitor dielectric layer and the first upper electrode layer are formed at the position where the top dielectric layer is removed.
  • a capacitor dielectric layer and the first upper electrode layer can not only serve as a supporting layer, but also can form a capacitor with the lower electrode layer, thereby increasing the capacitance of the columnar capacitor.
  • the opening overlaps a plurality of the capacitor holes at the same time.
  • the substrate includes a base and a cover medium layer on the surface of the base, the laminated structure is located on the surface of the cover medium layer; a plurality of storage nodes are formed in the cover medium layer Contact; the capacitor hole exposes the storage node contact.
  • the second capacitor dielectric layer further extends through the opening to cover the upper surface of the first upper electrode layer; the second upper electrode layer fills the adjacent lower electrode layer And extend through the opening to cover the second capacitor dielectric layer on the upper surface of the first upper electrode layer.
  • the step of forming an electrode lead-out structure is further included, and the electrode lead-out structure penetrates the second capacitor dielectric layer and the second capacitor dielectric layer on the upper surface of the first upper electrode layer.
  • the second upper electrode layer is located on the first upper electrode layer and extends into the first upper electrode layer.
  • An interconnection conductive layer is formed on the surface of the first upper electrode layer and the surface of the second upper electrode layer, and the interconnection conductive layer electrically connects the first upper electrode layer and the second upper electrode layer .
  • a step of forming an electrode extraction structure is further included, and the electrode extraction structure is electrically connected to the interconnection conductive layer.
  • forming a first upper electrode layer on the surface of the first capacitive dielectric layer includes the following steps: forming a first conductive layer on the surface of the first capacitive dielectric layer; The surface of the layer forms a second conductive layer.
  • a semiconductor storage device including: a substrate; and a plurality of capacitors, the capacitors including a lower electrode layer, a first capacitive dielectric layer, a second capacitive dielectric layer, a first upper electrode layer, and a second upper electrode layer;
  • the lower electrode layer has a columnar structure, and the second capacitor dielectric layer at least covers the surface of the lower part of the lower electrode layer, and is located at least between the second upper electrode layer and the lower electrode layer and the Between the second upper electrode layer and the substrate; the first capacitive dielectric layer is located at least part of the upper surface of the second upper electrode layer and the upper part of the lower electrode layer, the first upper electrode layer is located The upper surface of the first capacitor dielectric layer.
  • the first capacitive dielectric layer and the first upper electrode layer can both function as supporting layers. , It can also form a capacitor with the bottom electrode layer, thereby increasing the capacitance of the columnar capacitor.
  • the substrate includes: a base; and a cover dielectric layer located on the surface of the base; a plurality of storage node contacts are formed in the cover dielectric layer; the bottom electrode layer is connected to each of the storage node contacts in a one-to-one correspondence .
  • the semiconductor memory device further includes a plurality of openings, and the openings overlap a plurality of the lower electrode layers at the same time; the second capacitive dielectric layer also extends to Covering the upper surface of the first upper electrode layer; the second upper electrode layer fills the gap between the adjacent lower electrode layers, and extends through the opening to cover the first upper electrode layer The second capacitive dielectric layer on the surface.
  • the semiconductor storage device further includes an electrode lead-out structure that penetrates the second capacitor dielectric layer on the upper surface of the first upper electrode layer and the first upper electrode The second upper electrode layer on the layer and extends into the first upper electrode layer.
  • the semiconductor memory device further includes: a plurality of openings, the openings penetrate the first upper electrode layer and the first capacitive dielectric layer, and simultaneously intersect with the plurality of lower electrode layers.
  • the second capacitor dielectric layer is also located on the sidewall of the opening; the second upper electrode layer fills the gap between the adjacent lower electrode layers and extends into the opening; and A conductive layer is connected, and the interconnection conductive layer covers the first upper electrode layer and the exposed second upper electrode layer, and electrically connects the first upper electrode layer and the second upper electrode layer.
  • the semiconductor storage device further includes an electrode lead-out structure, and the electrode lead-out structure is electrically connected to the interconnection conductive layer.
  • the first upper electrode layer includes: a first conductive layer located on the surface of the first capacitive dielectric layer; and a second conductive layer located on the surface of the first conductive layer.
  • FIG. 1 is a flowchart of a manufacturing method of a semiconductor storage device in an embodiment
  • FIG. 2 is a schematic diagram of a cross-sectional structure of the structure obtained in step S11 in the method of manufacturing a semiconductor memory device in an embodiment
  • FIG. 3 is a schematic diagram of a cross-sectional structure of the structure obtained in step S12 in the method of manufacturing a semiconductor memory device in an embodiment
  • step S13 is a schematic cross-sectional structure diagram of the structure obtained in step S13 in the method of manufacturing a semiconductor memory device in an embodiment
  • FIG. 5 is a schematic diagram of a cross-sectional structure of the structure obtained in step S14 in the method of manufacturing a semiconductor memory device in an embodiment
  • FIG. 6 is a schematic cross-sectional structure diagram of the structure obtained in step S16 in the method of manufacturing a semiconductor memory device in an embodiment
  • FIG. 7 to 8 are schematic cross-sectional structural diagrams of the structure obtained in step S17 in the method of manufacturing a semiconductor memory device in an embodiment
  • FIG. 9 is a schematic top view of the structure obtained in step S18 in the method of manufacturing a semiconductor memory device in an embodiment
  • FIG. 10 is a schematic cross-sectional structure view along the AA direction in FIG. 9;
  • FIG. 11 is a schematic diagram of a cross-sectional structure of the structure obtained in step S19 in the method of manufacturing a semiconductor memory device in an embodiment
  • step S20 is a schematic diagram of a cross-sectional structure of the structure obtained in step S20 in the method of manufacturing a semiconductor memory device in an embodiment
  • FIG. 13 is a schematic cross-sectional structure diagram of the structure obtained in step S21 in the method of manufacturing a semiconductor memory device in an embodiment
  • FIG. 14 is a schematic cross-sectional structure diagram of a structure obtained after forming an electrode lead-out structure in an embodiment of a method for manufacturing a semiconductor memory device in an embodiment
  • FIG. 15 is a schematic cross-sectional structure diagram of the structure obtained after removing the second capacitor dielectric layer on the upper surface of the second conductive layer and the second upper electrode layer on the second conductive layer in the method for manufacturing a semiconductor memory device in an embodiment
  • 16 is a schematic cross-sectional structure diagram of a structure obtained after forming an interconnection conductive layer in a method for manufacturing a semiconductor memory device in an embodiment
  • FIG. 17 is a schematic cross-sectional structure diagram of a structure obtained after forming an electrode lead-out structure in another embodiment of the method of manufacturing a semiconductor memory device in one embodiment.
  • a method for manufacturing a semiconductor storage device includes the following steps:
  • S12 forming a laminated structure on the substrate, the laminated structure including a bottom dielectric layer, a sacrificial layer, and a top dielectric layer that are sequentially stacked from bottom to top;
  • the substrate 10 provided in step S11 may include a substrate 101 and a covering medium layer 102 on the surface of the base 101; a plurality of storage nodes located in the storage structure are formed in the covering medium layer 102.
  • Contact 103 the storage structure further includes a transistor word line (Word Line) and a bit line (Bit Line), and the storage node contact 103 is connected to the source of the transistor in the storage structure.
  • step S12 a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process may be used to sequentially form the bottom dielectric layer 111, the sacrificial layer 112, and the top dielectric layer in the stacked structure 11 ⁇ 113.
  • the removal rate of the sacrificial layer 112 is much greater than the removal rate of the bottom dielectric layer 111 and the removal rate of the top dielectric layer 113; specifically, the bottom dielectric layer 111 may include But not limited to the silicon nitride layer, the sacrificial layer 112 may include but is not limited to a silicon oxide layer, and the top dielectric layer 113 may include but is not limited to a silicon nitride layer.
  • a photolithography process may be used to form a capacitor hole 12 in the laminated structure 11, and the capacitor hole 12 penetrates the laminated structure 11 in the thickness direction.
  • the capacitor holes 12 may be arranged in an array, for example, a hexagonal array and so on.
  • the capacitor hole 12 exposes the storage node contact 103.
  • step S14 may include the following steps:
  • a lower electrode material layer (not shown) in the capacitor hole 12 and the surface of the top dielectric layer 113; specifically, it can be formed by but not limited to a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process
  • the bottom electrode material layer; the bottom electrode material layer can be a single metal layer, for example, the bottom electrode material layer can include but is not limited to a titanium nitride layer; in other examples, the bottom electrode material layer can also be a multilayer conductive layer, such as ,
  • the lower electrode material layer may include a titanium nitride layer and a polysilicon layer or a silicon germanium layer on the surface of the titanium nitride layer;
  • the upper surface of the lower electrode layer 13 may be flush with the upper surface of the top dielectric layer 113 (as shown in FIG. 5), or may be slightly higher or slightly lower than the upper surface of the top dielectric layer 113.
  • bottom electrode layer 13 fills up the capacitor hole 12 in step S14 can be used for the bottom electrode layer 13 to fill the capacitor hole 12 seamlessly, or it can be filled in due to the small size of the capacitor hole 12
  • the lower electrode layer 13 in the capacitor hole 12 has a cavity or the like.
  • an etching process may be used, but not limited to, an etching process to remove the top dielectric layer 113. After the top dielectric layer 113 is removed, the upper portion of the lower electrode layer 13 and the upper surface of the sacrificial layer 112 are exposed.
  • step S16 as shown in FIG. 6; specifically, a physical vapor deposition process, a chemical vapor deposition process, or an atomic deposition process may be used to form the first capacitive dielectric layer 14; the first capacitive dielectric layer 14 may include but It is not limited to one or a combination of zirconium oxide, aluminum oxide, silicon oxide layer, silicon nitride layer, silicon oxynitride layer, etc., but can also be other high-K dielectrics, which is not limited.
  • step S17 may include the following steps:
  • S171 Form a first conductive layer 151 on the surface of the first capacitor dielectric layer 14, as shown in FIG. 7; specifically, the first conductive layer 151 may be formed by using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.
  • the first conductive layer 151 may include, but is not limited to, a titanium nitride layer; and
  • S172 forming a second conductive layer 152 on the surface of the first conductive layer 151, as shown in FIG. 8; specifically, the second conductive layer 152 may be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process;
  • the second conductive layer 152 may include, but is not limited to, a silicon germanium (SiGe) layer.
  • the first conductive layer 151 and the second conductive layer 152 together constitute the first upper electrode layer 15.
  • only one conductive layer can be used as the first upper electrode layer 15, and it can be set as required.
  • the top dielectric layer 113 as the support layer is removed after the bottom electrode layer 13 is formed and before the sacrificial layer 112 is removed, and the first capacitor dielectric layer 14 and the first upper dielectric layer 14 are formed at the position where the top dielectric layer 113 is removed.
  • the electrode layer 15, the first capacitor dielectric layer 14 and the first upper electrode layer 15 formed can not only serve as a supporting layer, but also form a capacitor with the lower electrode layer 13, thereby increasing the capacitance of the columnar capacitor.
  • a photolithography process may be used to form the opening 17; the opening 17 may penetrate the second conductive layer 152, the first conductive layer 151, and the first capacitor dielectric layer. 14 until the sacrificial layer 112 is exposed.
  • the opening 17 may overlap multiple capacitor holes 12 at the same time.
  • one opening 17 overlaps three capacitor holes 12 at the same time as an example; of course, in other examples, one opening 17 overlaps at the same time.
  • the number of capacitor holes 12 can be set according to actual needs, and there is no limitation here.
  • the cross-sectional shape of the opening 17 may be rectangular, circular, elliptical, triangular, or the like.
  • the diameter of the opening 17 may be larger than the distance between adjacent lower electrode layers 13, that is, after the opening 17 is formed, part of the upper portion of the lower electrode layer 13 will be removed, as shown in FIG. 10.
  • the position and shape of the opening 17 can be set as required, or it does not overlap with the capacitor hole 12, as long as the opening that can expose the sacrificial layer can be used in this application.
  • a wet removal solution may be used, but not limited to, to remove the sacrificial layer 112 based on the opening 17.
  • a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process may be used to form the second capacitor dielectric layer 18; the second capacitor dielectric layer 18 covers the lower electrode layer 13 All surfaces exposed.
  • the second capacitor dielectric layer 18 may include, but is not limited to, one or a combination of zirconia, aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, etc., and may also be other high-K dielectrics, which are not limited. .
  • the second capacitor dielectric layer 18 covers all the exposed surfaces of the lower electrode layer 13 and the surface of the exposed bottom dielectric layer 111, and is also located on the sidewalls of the opening 17 and the upper surface of the second conductive layer 152. , As shown in Figure 12.
  • a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process may be used to form the second upper electrode layer 19 on the surface of the second capacitor dielectric layer 18.
  • the second upper electrode layer 19 fills the gap between the adjacent lower electrode layers 13 and extends through the opening 17 to cover the second capacitive dielectric layer 18 on the upper surface of the second conductive layer 152, as shown in FIG. It should be noted that “the second upper electrode layer 19 fills the gap between the adjacent lower electrode layers 13” may mean that the second upper electrode layer 19 seamlessly fills the gap between the adjacent lower electrode layers 13 The gap may also be due to voids in the second upper electrode layer 19 filled in the gap between the adjacent lower electrode layers 13.
  • the step of forming an electrode lead-out structure 20 is further included, as shown in FIG. 14; the electrode lead-out structure 20 penetrates the second capacitor dielectric layer 18 and The second upper electrode layer 19 is located on the second conductive layer 152 and extends into the second conductive layer 152.
  • the electrode lead-out structure 20 is also used to electrically lead out the electrode layer.
  • the electrode lead-out structure 20 may include, but is not limited to, lead-out structures such as titanium nitride and tungsten.
  • interconnection conductive layer 21 on the surface of the second conductive layer 152 and the surface of the second upper electrode layer 17, as shown in FIG. 16; the interconnection conductive layer 21 connects the first upper electrode layer 15 and the second upper electrode layer
  • the electrode layer 19 is electrically connected.
  • a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process may be used to form the interconnection conductive layer 21; the interconnection conductive layer 21 may include, but is not limited to, a silicon germanium layer.
  • the step of forming an electrode lead-out structure 20 is further included.
  • the electrical lead-out structure 20 may be located on the upper surface of the interconnection conductive layer 21, and the electrode lead-out structure 20 penetrates the interconnection.
  • the conductive layer 21 extends into the second conductive layer 152.
  • the electrode lead-out structure 20 may include, but is not limited to, a titanium nitride lead-out structure.
  • the present invention also provides a semiconductor storage device.
  • the semiconductor storage device includes a substrate 10; and a plurality of capacitors.
  • the capacitors include lower electrodes.
  • the lower electrode layer 13 has a columnar structure, and the second capacitor dielectric layer 18 covers at least the lower electrode
  • the surface of the lower part of the layer 13 is located at least between the second upper electrode layer 19 and the lower electrode layer 13 and between the second upper electrode layer 19 and the substrate 10;
  • the first capacitive dielectric layer 14 is located at least part of the second upper electrode
  • the upper surface of the layer 19 and the upper portion of the lower electrode layer 13, and the first upper electrode layer 15 is located on the upper surface of the first capacitor dielectric layer 14.
  • the first capacitive dielectric layer 14 and the first upper electrode layer 15 may be It functions as a supporting layer and can form a capacitor with the bottom electrode layer 13, thereby increasing the capacitance of the columnar capacitor.
  • the substrate 10 may include a base 101 and a cover dielectric layer 102 on the surface of the base 101; a plurality of storage node contacts 103 located in a memory array structure are formed in the cover dielectric layer 102.
  • the memory array structure further includes a transistor word line (Word Line) and a bit line (Bit Line), and the storage node contact 103 is connected to the source of the transistor in the memory array structure.
  • the lower electrode layer 13 may include, but is not limited to, a titanium nitride layer.
  • the upper surface of the lower electrode layer 13 may be flush with the upper surface of the top dielectric layer 113, or may be slightly higher or lower than the upper surface of the top dielectric layer 113.
  • the first capacitive dielectric layer 14 and the second capacitive dielectric layer 18 may include, but are not limited to, one or a combination of zirconium oxide, aluminum oxide, silicon oxide layer, silicon nitride layer, or silicon oxynitride layer. For other high-K media, this is not limited.
  • the first upper electrode layer 15 includes: a first conductive layer 151, which is located on the surface of the first capacitive dielectric layer 14; and a second conductive layer 152, which is located on the first conductive layer.
  • the first conductive layer 151 may include, but is not limited to, a titanium nitride layer; the second conductive layer 152 may include, but is not limited to, a silicon germanium layer.
  • the semiconductor memory device further includes a plurality of openings 171, and the openings 171 overlap the plurality of lower electrode layers 13 at the same time; the second capacitive dielectric layer 18 also passes through the openings 171 Extends to cover the upper surface of the second conductive layer 152; the second upper electrode layer 19 fills the gap between the adjacent lower electrode layers 13, and extends through the opening 171 to cover the second capacitor on the upper surface of the second conductive layer 152 Medium layer 18.
  • the opening 171 can overlap a plurality of capacitor holes 12 at the same time.
  • one opening 171 overlaps with three capacitor holes 12 at the same time as an example; of course, in other examples, one opening 171 At the same time, the number of overlapping capacitor holes 12 can be set according to actual needs, and there is no limitation here.
  • the cross-sectional shape of the opening 171 may be rectangular, circular, elliptical, triangular, or the like.
  • the diameter of the opening portion 171 may be greater than the distance between adjacent lower electrode layers 13, that is, after the opening portion 171 is formed, part of the upper portion of the lower electrode layer 13 may be removed.
  • the position and shape of the opening 171 can be set as required, and any opening that can expose the sacrificial layer can be used in this application.
  • the semiconductor memory device further includes an electrode lead-out structure 20, which penetrates through the second capacitive dielectric layer 18 located on the upper surface of the second conductive layer 152 and the second upper electrode layer 19 located on the second conductive layer 152 , And extend into the second conductive layer 152.
  • the electrode lead-out structure 20 may include, but is not limited to, a titanium nitride lead-out structure.
  • the semiconductor memory device further includes: a plurality of openings 171, the openings 171 penetrate the first conductive layer 151, the second conductive layer 152, and the first capacitive dielectric layer 14. , And overlap with a plurality of lower electrode layers 13 at the same time; the second capacitor dielectric layer 18 is also located on the sidewall of the opening 171; the second upper electrode layer 19 fills the gap between the adjacent lower electrode layers 13 and extends to And the interconnection conductive layer 21, which covers the second conductive layer 152 and the exposed second upper electrode layer 19.
  • the interconnection conductive layer 21 may include, but is not limited to, a silicon germanium layer.
  • the semiconductor storage device further includes an electrode lead-out structure 20, and the electrode lead-out structure 20 penetrates the interconnection conductive layer 21 and extends into the second conductive layer 152.
  • the electrode lead-out structure 20 may include, but is not limited to, lead-out structures such as titanium nitride and tungsten.

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Abstract

一种半导体存储器件的制备方法包括：提供衬底；于衬底上形成叠层结构；于叠层结构内形成多个间隔排布电容孔；于电容孔内形成下电极层；去除顶层介质层；于暴露出的牺牲层的表面及下电极层的上部表面形成第一电容介质层；于第一电容介质层的表面形成第一上电极层；于第一上电极层及第一电容介质层内形成多个开口；基于开口去除牺牲层；至少于下电极层的表面及暴露出的底层介质层的表面形成第二电容介质层；于第二电容介质层的表面形成第二上电极层。

Description

半导体存储器件及其制备方法
相关申请的交叉引用
本申请要求于2020年4月8日提交中国专利局、申请号为2020102674521、发明名称为“半导体存储器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件制造技术领域，特别是涉及一种半导体存储器件及其制备方法。
背景技术
随着半导体工艺的发展，半导体工艺节点越来越小，DRAM(Dynamic Random Access Memory，动态随机存取存储器)中的图形结构(譬如，电容器结构)正加速微型化。随着电容孔的尺寸越来越小，现有工艺很难在电容孔内制备包括下电极层、电容介质层及上电极层的电容器结构。在此基础上，柱状电容器将被用于替代现有DRAM中的电容器结构。然而，柱状电容器存在电容容量较小的问题。
发明内容
根据各个实施例，提供一种半导体存储器件及其制备方法。
一种半导体存储器件的制备方法，包括如下步骤：提供衬底；于所述衬底上形成叠层结构，所述叠层结构包括由下至上依次叠置的形成底层介质层、牺牲层及顶层介质层；于所述叠层结构内形成多个间隔排布电容孔，所述电容孔贯穿所述叠层结构且暴露出所述衬底；于所述电容孔内形成下电极层，所述下电极层填满所述电容孔；去除所述顶层介质层，以暴露出所述牺牲层及所述下电极层的上部；于暴露出的所述牺牲层的表面及所述下电极层的上部表面形成第一电容介质层；于所述第一电容介质层的表面形成第一上电极层；于所述第一上电极层及所述第一电容介质层内形成多个开 口，所述开口暴露出所述牺牲层；基于所述开口去除所述牺牲层；至少于所述下电极层的表面及暴露出的所述底层介质层的表面形成第二电容介质层；及于所述第二电容介质层的表面形成第二上电极层。
上述实施例中，通过在形成下电极层后且去除牺牲层之前去除作为支撑层的顶层介质层，并在去除顶层介质层的位置形成第一电容介质层及第一上电极层，形成的第一电容介质层及第一上电极层既可以起到支撑层的作用，又可以与下电极层形成电容，从而可以增大柱状电容的电容容量。
在其中一个实施例中，所述开口同时与多个所述电容孔交叠。
在其中一个实施例中，所述衬底包括基底及位于所述基底表面的覆盖介质层，所述叠层结构位于所述覆盖介质层的表面；所述覆盖介质层内形成有多个存储节点接触；所述电容孔暴露出所述存储节点接触。
在其中一个实施例中，所述第二电容介质层还经由所述开口延伸至覆盖所述第一上电极层的上表面；所述第二上电极层填满相邻所述下电极层之间的间隙，并经由所述开口延伸覆盖位于所述第一上电极层上表面的所述第二电容介质层。
在其中一个实施例中，形成所述第二上电极层之后还包括形成电极引出结构的步骤，所述电极引出结构贯穿位于所述第一上电极层上表面的所述第二电容介质层及位于所述第一上电极层上的所述第二上电极层，并延伸至所述第一上电极层内。
在其中一个实施例中，形成所述第二上电极层之后还包括如下步骤：
去除所述第一上电极层上表面的所述第二电容介质层及位于所述第一上电极层上的所述第二上电极层，以裸露出所述第一上电极层；及
于所述第一上电极层的表面及所述第二上电极层的表面形成互连导电层，所述互连导电层将所述第一上电极层与所述第二上电极层电连接。
在其中一个实施例中，形成所述互连导电层之后还包括形成电极引出结构的步骤，所述电极引出结构与所述互连导电层电连接。
在其中一个实施例中，于所述第一电容介质层的表面形成第一上电极层包括如下步骤：于所述第一电容介质层的表面形成第一导电层；及于所述第一导电层的表面形成第二导电层。
还提供一种半导体存储器件，包括：衬底；及多个电容器，所述电容器包括下电极层、第一电容介质层、第二电容介质层、第一上电极层及第二上电极层；所述下电极层为柱状结构，所述第二电容介质层至少包覆所述下电极层中下部的表面，且至少位于所述第二上电极层与所述下电极层之间及所述第二上电极层与所述衬底之间；所述第一电容介质层位于至少部分所述第二上电极层的上表面及所述下电极层的上部，所述第一上电极层位于所述第一电容介质层的上表面。
上述实施例中，通过在下电极层的上部及第二上电极层上设置第一电容介质层及第一上电极层，第一电容介质层及第一上电极层既可以起到支撑层的作用，又可以与下电极层形成电容，从而可以增大柱状电容的电容容量。
在其中一个实施例中。所述衬底包括：基底；及覆盖介质层，位于所述基底的表面；所述覆盖介质层内形成有多个存储节点接触；所述下电极层与各所述存储节点接触一一对应连接。
在其中一个实施例中，所述半导体存储器件还包括多个开口部，所述开口部同时与多个所述下电极层交叠；所述第二电容介质层还经由所述开口部延伸至覆盖所述第一上电极层的上表面；所述第二上电极层填满相邻所述下电极层之间的间隙，并经由所述开口部延伸覆盖位于所述第一上电极层上表面的所述第二电容介质层。
在其中一个实施例中，所述半导体存储器件还包括电极引出结构，所述电极引出结构贯穿位于所述第一上电极层上表面的所述第二电容介质层及位于所述第一上电极层上的所述第二上电极层，并延伸至所述第一上电极层内。
在其中一个实施例中，所述半导体存储器件还包括：多个开口部，所述开口部贯穿所述第一上电极层及第一电容介质层，且同时与多个所述下电极层交叠；所述第二 电容介质层还位于所述开口部的侧壁；所述第二上电极层填满相邻所述下电极层之间的间隙，并延伸至所述开口部内；及互连导电层，所述互连导电层覆盖所述第一上电极层及裸露的所述第二上电极层，并将所述第一上电极层与所述第二上电极层电连接。
在其中一个实施例中，所述半导体存储器件还包括电极引出结构，所述电极引出结构与所述互连导电层电连接。
在其中一个实施例中，所述第一上电极层包括：第一导电层，位于所述第一电容介质层的表面；及第二导电层，位于所述第一导电层的表面。
附图说明
图1为一个实施例中半导体存储器件的制备方法的流程图；
图2为一个实施例中半导体存储器件的制备方法中步骤S11所得结构的截面结构示意图；
图3为一个实施例中半导体存储器件的制备方法中步骤S12所得结构的截面结构示意图；
图4为一个实施例中半导体存储器件的制备方法中步骤S13所得结构的截面结构示意图；
图5为一个实施例中半导体存储器件的制备方法中步骤S14所得结构的截面结构示意图；
图6为一个实施例中半导体存储器件的制备方法中步骤S16所得结构的截面结构示意图；
图7至图8为一个实施例中半导体存储器件的制备方法中步骤S17所得结构的截面结构示意图；
图9为一个实施例中半导体存储器件的制备方法中步骤S18所得结构的俯视结构示意图；
图10为沿图9中AA方向的截面结构示意图；
图11为一个实施例中半导体存储器件的制备方法中步骤S19所得结构的截面结构示意图；
图12为一个实施例中半导体存储器件的制备方法中步骤S20所得结构的截面结构示意图；
图13为一个实施例中半导体存储器件的制备方法中步骤S21所得结构的截面结构示意图；
图14为一个实施例中半导体存储器件的制备方法的一个实施例中形成电极引出结构后所得结构的截面结构示意图；
图15为一个实施例中半导体存储器件的制备方法中去除第二导电层上表面的第二电容介质层及位于第二导电层上的第二上电极层后所得结构的截面结构示意图；
图16为一个实施例中半导体存储器件的制备方法中形成互连导电层后所得结构的截面结构示意图；
图17为一个实施例中半导体存储器件的制备方法的另一个实施例中形成电极引出结构后所得结构的截面结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
需要说明的是，当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件并与之结合为一体，或者可能同时存在居中元件。本文所使用的术语“安装”、“一端”、“另一端”以及类似的表述只是为了说明的目的。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描 述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在一个实施例中，如图1所示，一种半导体存储器件的制备方法，包括以下步骤：
S11：提供衬底；
S12：于所述衬底上形成叠层结构，所述叠层结构包括由下至上依次叠置的形成底层介质层、牺牲层及顶层介质层；
S13：于所述叠层结构内形成多个间隔排布电容孔，所述电容孔贯穿所述叠层结构且暴露出所述衬底；
S14：于所述电容孔内形成下电极层，所述下电极层填满所述电容孔；
S15：去除所述顶层介质层，以暴露出所述牺牲层及所述下电极层的上部；
S16：于暴露出的所述牺牲层的表面及所述下电极层的上部表面形成第一电容介质层；
S17：于所述第一电容介质层的表面形成第一上电极层；
S18：于所述第一上电极层及所述第一电容介质层内形成多个开口，所述开口暴露出所述牺牲层；
S19：基于所述开口去除所述牺牲层；
S20：至少于所述下电极层的表面及暴露出的所述底层介质层的表面形成第二电容介质层；及
S21：于所述第二电容介质层的表面形成第二上电极层。
在一个示例中，如图2所示，步骤S11中提供的衬底10可以包括基底101及位于基底101表面的覆盖介质层102；覆盖介质层102内形成有多个位于存储结构中的存储节点接触103。具体的，所述存储结构中还包括有晶体管字符线(Word Line)及位线(Bit Line)，存储节点接触103连接存储结构中的晶体管的源极。
在一个示例中，如图3所示，步骤S12中，可以采用物理气相沉积工艺、化学气 相沉积工艺或原子层沉积工艺依次形成叠层结构11中的底层介质层111、牺牲层112及顶层介质层113。
在一个示例中，至少在某一相同刻蚀条件下，牺牲层112的去除速率要远远大于底层介质层111的去除速率及顶层介质层113的去除速率；具体的，底层介质层111可以包括但不仅限于氮化硅层，牺牲层112可以包括但不仅限于氧化硅层，顶层介质层113可以包括但不仅限于氮化硅层。
在一个示例中，如图4所示，步骤S13中，可以采用光刻刻蚀工艺于叠层结构11中形成电容孔12，电容孔12沿厚度方向贯穿叠层结构11。电容孔12可以呈阵列排布，譬如，六方阵列等等。电容孔12暴露出存储节点接触103。
在一个示例中，步骤S14可以包括如下步骤：
S141：于电容孔12内及所述顶层介质层113的表面形成下电极材料层(未示出)；具体的，可以采用但不仅限于物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成下电极材料层；下电极材料层可以为单层金属层，譬如，下电极材料层可以包括但不仅限于氮化钛层；在其他示例中，下电极材料层也可以为多层导电层，譬如，下电极材料层可以包括氮化钛层及位于氮化钛层表面的多晶硅层或锗硅层；
S142：去除位于顶层介质层113表面的下电极材料层，保留于电容孔12内的下电极材料层即为下电极层；具体的，可以采用回刻工艺或化学机械研磨(CMP)工艺去除位于顶层介质层113表面的下电极材料层。
在一个示例中，下电极层13的上表面可以与顶层介质层113的上表面相平齐(如图5所示)，也可以略高于或略低于顶层介质层113的上表面。
需要说明的是，步骤S14中所述的“下电极层13填满电容孔12”可以为下电极层13无缝隙填满电容孔12，也可以为由于电容孔12尺寸较小导致的填充于电容孔12内的下电极层13内具有空洞等。
在一个示例中，步骤S15中，可以采用但不仅限于刻蚀工艺去除顶层介质层113。 去除顶层介质层113之后，下电极层13的上部及牺牲层112的上表面被暴露出来。
在一个示例中，步骤S16中，如图6所示；具体的，可以采用物理气相沉积工艺、化学气相沉积工艺或原子沉积工艺形成第一电容介质层14；第一电容介质层14可以包括但不仅限于氧化锆、氧化铝、氧化硅层、氮化硅层或氮氧化硅层等的一种或组合，也可以是其他高K介质，对此不做限定。
在一个示例中，步骤S17中可以包括如下步骤：
S171：于第一电容介质层14的表面形成第一导电层151，如图7所示；具体的，可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成第一导电层151，第一导电层151可以包括但不仅限于氮化钛层；及
S172：于第一导电层151的表面形成第二导电层152，如图8所示；具体的，可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成第二导电层152；第二导电层152可以包括但不仅限于锗硅(SiGe)层。第一导电层151与第二导电层152共同构成第一上电极层15。当然，本领域内技术人员应当理解，也可以只用一层导电层来作为第一上电极层15，可以根据需要自行设置。
在上述实施例中，通过在形成下电极层13后且去除牺牲层112之前去除作为支撑层的顶层介质层113，并在去除顶层介质层113的位置形成第一电容介质层14及第一上电极层15，形成的第一电容介质层14及第一上电极层15既可以起到支撑层的作用，又可以与下电极层13形成电容，从而可以增大柱状电容的电容容量。
在一个示例中，如图9及图10所示，步骤S18中，可以采用光刻刻蚀工艺形成开口17；开口17可以贯穿第二导电层152、第一导电层151、第一电容介质层14直至暴露出牺牲层112。
在一个示例中，开口17可以同时与多个电容孔12交叠，图9中以一个开口17同时与三个电容孔12交叠作为示例；当然，在其他示例中，一个开口17同时交叠的电容孔12的数量可以根据实际需要进行设定，此处不做限制。
具体的，开口17的横截面形状可以为矩形、圆形、椭圆形或三角形等等。
在一个示例中，开口17的直径可以大于相邻下电极层13之间的间距，即在形成开口17之后，部分下电极层13的上部会被去除部分，如图10所示。当然，在其他示例中，开口17的位置及形状可以根据需要进行设置，也可以不与电容孔12交叠，只要能够暴露出牺牲层的开口均可以用在本申请中。
在一个示例中，如图11所示，步骤S19中，可以采用但不仅限于湿法去除溶液基于开口17去除牺牲层112。
在一个示例中，如图12所示，步骤S20中，可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成第二电容介质层18；第二电容介质层18包覆下电极层13裸露的所有表面。第二电容介质层18可以包括但不仅限于氧化锆、氧化铝、氧化硅层、氮化硅层或氮氧化硅层等的一种或组合，也可以是其他高K介质，对此不做限定。
在一个示例中，第二电容介质层18除了包覆下电极层13裸露的所有表面及位于裸露的底层介质层111表面之外，还位于开口17的侧壁及第二导电层152的上表面，如图12所示。
在一个可选的示例中，步骤S21中，可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺于第二电容介质层18的表面形成第二上电极层19。第二上电极层19填满相邻下电极层13之间的间隙，并经由开口17延伸覆盖位于第二导电层152上表面的第二电容介质层18，如图13所示。需要说明的是，此处所述的“第二上电极层19填满相邻下电极层13之间的间隙”可以为第二上电极层19无缝隙填满相邻下电极层13之间的间隙，也可以为由于填充于相邻下电极层13之间的间隙的第二上电极层19内具有空洞等。
在一个示例中，形成第二上电极层19之后还包括形成电极引出结构20的步骤，如图14所示；电极引出结构20贯穿位于第二导电层152上表面的第二电容介质层18 及位于第二导电层152上的第二上电极层19，并延伸至第二导电层152内。电极引出结构20除了将第一上电极层15与第二上电极层19电连接外，还用于实现将电极层电学引出。电极引出结构20可以包括但不仅限于氮化钛、钨等引出结构。
在又一个示例中，如图15及图16所示，形成第二上电极层19之后还包括如下步骤：
S22：去除第二导电层152上表面的第二电容介质层18及位于第二导电层152上的第二上电极层19，以裸露出第二导电层152，如图15所示；具体的，可以采用刻蚀工艺或化学机械研磨工艺去除第二导电层152上表面的第二电容介质层18及位于第二导电层152上的第二上电极层19；及
S23：于第二导电层152的表面及第二上电极层17的表面形成互连导电层21，如图16所示；互连导电层21将第一上电极层15与所述第二上电极层19电连接。具体的，可以采用但不仅限于物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成互连导电层21；互连导电层21可以包括但不仅限于锗硅层。
在一个示例中，如图17所示，形成互连导电层21之后还包括形成电极引出结构20的步骤，电引出结构20可以位于互连导电层21的上表面，电极引出结构20贯穿互连导电层21，并延伸至第二导电层152内。电极引出结构20可以包括但不仅限于氮化钛引出结构。
在又一个实施例中，请结合图2至图12继续参阅图13至图14，本发明还提供一种半导体存储器件，半导体存储器件包括：衬底10；及多个电容器，电容器包括下电极层13、第一电容介质层14、第二电容介质层18、第一上电极层15及第二上电极层19；下电极层13为柱状结构，第二电容介质层18至少包覆下电极层13中下部的表面，且至少位于第二上电极层19与下电极层13之间及第二上电极层19与衬底10之间；第一电容介质层14位于至少部分第二上电极层19的上表面及下电极层13的上部，第一上电极层15位于第一电容介质层14的上表面。
上述实施例中，通过在下电极层13的上部及第二上电极层19上设置第一电容介质层14及第一上电极层15，第一电容介质层14及第一上电极层15既可以起到支撑层的作用，又可以与下电极层13形成电容，从而可以增大柱状电容的电容容量。
在一个示例中，衬底10可以包括基底101及位于基底101表面的覆盖介质层102；覆盖介质层102内形成有多个位于内存数组结构中的存储节点接触103。具体的，所述内存数组结构中还包括有晶体管字符线(Word Line)及位线(Bit Line)，存储节点接触103连接内存数组结构中的晶体管的源极。
在一个示例中，下电极层13可以包括但不仅限于氮化钛层。
在一个示例中，下电极层13的上表面可以与顶层介质层113的上表面相平齐，也可以略高于或略低于顶层介质层113的上表面。
具体的，第一电容介质层14和第二电容介质层18可以包括但不仅限于氧化锆、氧化铝、氧化硅层、氮化硅层或氮氧化硅层等的一种或组合，也可以是其他高K介质，对此不做限定。
在一个示例中，第一上电极层15包括：第一导电层151，第一导电层151位于第一电容介质层14的表面；及第二导电层152，第二导电层152位于第一导电层151的表面。第一导电层151可以包括但不仅限于氮化钛层；第二导电层152可以包括但不仅限于锗硅层。
在一个示例中，如图13及图14所示，半导体存储器件还包括多个开口部171，开口部171同时与多个下电极层13交叠；第二电容介质层18还经由开口部171延伸至覆盖第二导电层152的上表面；第二上电极层19填满相邻下电极层13之间的间隙，并经由开口部171延伸覆盖位于第二导电层152上表面的第二电容介质层18。
在一个示例中，开口部171可以同时与多个电容孔12交叠，图9中以一个开口部171同时与三个电容孔12交叠作为示例；当然，在其他示例中，一个开口部171同时交叠的电容孔12的数量可以根据实际需要进行设定，此处不做限制。
具体的，开口部171的横截面形状可以为矩形、圆形、椭圆形或三角形等等。
在一个示例中，开口部171的直径可以大于相邻下电极层13之间的间距，即在形成开口部171之后，部分下电极层13的上部会被去除部分。当然，在其他示例中，开口部171的位置及形状可以根据需要进行设置，只要能够暴露出牺牲层的开口均可以用在本申请中。
在一个示例中，半导体存储器件还包括电极引出结构20，电极引出结构20贯穿位于第二导电层152上表面的第二电容介质层18及位于第二导电层152上的第二上电极层19，并延伸至第二导电层152内。电极引出结构20可以包括但不仅限于氮化钛引出结构。
在另一个实施例中，如图16及图17所示，半导体存储器件还包括：多个开口部171，开口部171贯穿第一导电层151、第二导电层152及第一电容介质层14，且同时与多个下电极层13交叠；第二电容介质层18还位于开口部171的侧壁；第二上电极层19填满相邻下电极层13之间的间隙，并延伸至开口部171内；及互连导电层21，互连导电层21覆盖第二导电层152及裸露的第二上电极层19。互连导电层21可以包括但不仅限于锗硅层。
在一个示例中，如图17所示，半导体存储器件还包括电极引出结构20，电极引出结构20贯穿互连导电层21，并延伸至第二导电层152内。电极引出结构20可以包括但不仅限于氮化钛、钨等引出结构。
上所述实施例的各技术特征可以进行任意的组合，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体存储器件的制备方法，包括：
    提供衬底；
    于所述衬底上形成叠层结构，所述叠层结构包括由下至上依次叠置的形成底层介质层、牺牲层及顶层介质层；
    于所述叠层结构内形成多个间隔排布电容孔，所述电容孔贯穿所述叠层结构且暴露出所述衬底；
    于所述电容孔内形成下电极层，所述下电极层填满所述电容孔；
    去除所述顶层介质层，以暴露出所述牺牲层及所述下电极层的上部；
    于暴露出的所述牺牲层的表面及所述下电极层的上部表面形成第一电容介质层；
    于所述第一电容介质层的表面形成第一上电极层；
    于所述第一上电极层及所述第一电容介质层内形成多个开口，所述开口暴露出所述牺牲层；
    基于所述开口去除所述牺牲层；
    至少于所述下电极层的表面及暴露出的所述底层介质层的表面形成第二电容介质层；及
    于所述第二电容介质层的表面形成第二上电极层。
  2. 根据权利要求1所述的方法，其特征在于，所述开口同时与多个所述电容孔交叠。
  3. 根据权利要求1所述的方法，其特征在于，所述衬底包括基底及位于所述基底表面的覆盖介质层，所述叠层结构位于所述覆盖介质层的表面；所述覆盖介质层内形成有多个存储节点接触；所述电容孔暴露出所述存储节点接触。
  4. 根据权利要求1所述的方法，其特征在于，所述第二电容介质层还经由所述开口延伸至覆盖所述第一上电极层的上表面；所述第二上电极层填满相邻所述下电极层之间的间隙，并经由所述开口延伸覆盖位于所述第一上电极层上表面的所述第二电容介质 层。
  5. 根据权利要求4所述的方法，其特征在于，在形成所述第二上电极层之后，所述方法还包括形成电极引出结构，所述电极引出结构贯穿位于所述第一上电极层上表面的所述第二电容介质层及位于所述第一上电极层上的所述第二上电极层，并延伸至所述第一上电极层内。
  6. 根据权利要求4所述的方法，其特征在于，在形成所述第二上电极层之后，所述方法还包括：
    去除所述第一上电极层上表面的所述第二电容介质层及位于所述第一上电极层上的所述第二上电极层，以裸露出所述第一上电极层；及
    于所述第一上电极层的表面及所述第二上电极层的表面形成互连导电层，所述互连导电层将所述第一上电极层与所述第二上电极层电连接。
  7. 根据权利要求6所述的方法，其特征在于，在形成所述互连导电层之后，所述方法还包括形成电极引出结构，所述电极引出结构与所述互连导电层电连接。
  8. 根据权利要求1所述的方法，其特征在于，于所述第一电容介质层的表面形成第一上电极层包括：
    于所述第一电容介质层的表面形成第一导电层；及
    于所述第一导电层的表面形成第二导电层。
  9. 一种半导体存储器件，包括：
    衬底；及
    多个电容器，所述电容器包括下电极层、第一电容介质层、第二电容介质层、第一上电极层及第二上电极层；所述下电极层为柱状结构，所述第二电容介质层至少包覆所述下电极层中下部的表面，且至少位于所述第二上电极层与所述下电极层之间及所述第二上电极层与所述衬底之间；所述第一电容介质层位于至少部分所述第二上电极层的上表面及所述下电极层的上部，所述第一上电极层位于所述第一电容介质层的 上表面。
  10. 根据权利要求9所述的半导体存储器件，其特征在于，所述衬底包括：
    基底；及
    覆盖介质层，位于所述基底的表面；所述覆盖介质层内形成有多个存储节点接触；所述下电极层与各所述存储节点接触一一对应连接。
  11. 根据权利要求9所述的半导体存储器件，其特征在于，所述半导体存储器件还包括多个开口部，所述开口部同时与多个所述下电极层交叠；所述第二电容介质层还经由所述开口部延伸至覆盖所述第一上电极层的上表面；所述第二上电极层填满相邻所述下电极层之间的间隙，并经由所述开口部延伸覆盖位于所述第一上电极层上表面的所述第二电容介质层。
  12. 根据权利要求11所述的半导体存储器件，其特征在于，所述半导体存储器件还包括电极引出结构，所述电极引出结构贯穿位于所述第一上电极层上表面的所述第二电容介质层及位于所述第一上电极层上的所述第二上电极层，并延伸至所述第一上电极层内。
  13. 根据权利要求9所述的半导体存储器件，其特征在于，所述半导体存储器件还包括：
    多个开口部，所述开口部贯穿所述第一上电极层及所述第一电容介质层，且同时与多个所述下电极层交叠；所述第二电容介质层还位于所述开口部的侧壁；所述第二上电极层填满相邻所述下电极层之间的间隙，并延伸至所述开口部内；及
    互连导电层，所述互连导电层覆盖所述第一上电极层及裸露的所述第二上电极层，并将所述第一上电极层与所述第二上电极层电连接。
  14. 根据权利要求13所述的半导体存储器件，其特征在于，所述半导体存储器件还包括电极引出结构，所述电极引出结构与所述互连导电层电连接。
  15. 根据权利要求9所述的半导体存储器件，其特征在于，所述第一上电极层包括：
    第一导电层，位于所述第一电容介质层的表面；及
    第二导电层，位于所述第一导电层的表面。
PCT/CN2021/084439 2020-04-08 2021-03-31 半导体存储器件及其制备方法 WO2021204047A1 (zh)

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