WO2022247013A1 - 存储器的制作方法及存储器 - Google Patents

存储器的制作方法及存储器 Download PDF

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Publication number
WO2022247013A1
WO2022247013A1 PCT/CN2021/111438 CN2021111438W WO2022247013A1 WO 2022247013 A1 WO2022247013 A1 WO 2022247013A1 CN 2021111438 W CN2021111438 W CN 2021111438W WO 2022247013 A1 WO2022247013 A1 WO 2022247013A1
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WIPO (PCT)
Prior art keywords
layer
hole
sacrificial
capacitor
supporting
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PCT/CN2021/111438
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English (en)
French (fr)
Inventor
宛强
夏军
占康澍
刘涛
徐朋辉
李森
Original Assignee
长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/516,807 priority Critical patent/US20220384445A1/en
Publication of WO2022247013A1 publication Critical patent/WO2022247013A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • the present application relates to the technical field of storage devices, in particular to a manufacturing method of a memory and the memory.
  • Dynamic random access memory (Dynamic random access memory, referred to as Dram) is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage devices or devices. DRAM typically includes capacitors that store data by storing electrical charge.
  • a stacked structure when fabricating a memory, a stacked structure is usually first formed on a substrate, and the stacked structure includes a support layer and a sacrificial layer located between adjacent support layers; then, capacitor holes are formed in the stacked structure, and the The hole wall and the hole bottom of the capacitor hole form the first plate; then remove part of the support layer on the top layer to form a capacitor opening hole, and the capacitor opening hole exposes the sacrificial layer; then remove the sacrificial layer so that the sacrificial layer removed in the capacitor hole The dielectric layer and the second plate are formed on the position.
  • each sacrificial layer is located between two adjacent supporting layers.
  • multiple support layers need to be removed.
  • the support layer usually requires a long time of pickling to reduce defects.
  • the support layer is easy to damage the first plate during pickling, which reduces the yield rate of the memory.
  • An embodiment of the present application provides a method for fabricating a memory, which includes: forming a stacked structure on a substrate, the stacked structure including alternately arranged sacrificial layers and support layers; wherein, the number of layers of the sacrificial layer is greater than 1,
  • the top layer of the stacked structure is the support layer, and the support layer located between the two sacrificial layers is provided with a middle hole, and the middle hole is filled with a sacrificial material; part of the stacked structure is removed , forming a capacitor hole through the stacked structure; forming a first plate at the hole wall and bottom of the capacitor hole; removing the support layer located on the top layer of the stacked structure opposite to the middle hole area, forming a capacitance opening hole, and the capacitance opening hole exposes the sacrificial layer; through the capacitance opening hole, all the sacrificial layer and all the sacrificial material in the middle hole are removed to expose the first An outer peripheral surface of a pole
  • a stacked structure is first formed on the substrate, and the stacked structure includes alternately arranged sacrificial layers and support layers; wherein, the number of layers of the sacrificial layer is greater than 1, and the top layer of the stacked structure is A supporting layer, and the supporting layer between the two sacrificial layers is provided with an intermediate hole, and the intermediate hole is filled with a sacrificial material; part of the stacked structure is removed to form a capacitance hole that runs through the stacked structure; and then the hole wall of the capacitance hole and the The first plate is formed at the bottom of the hole; the area opposite to the middle hole in the support layer located on the top layer of the stack structure is removed to form a capacitor opening hole, and the capacitor opening hole exposes the sacrificial layer; through the capacitor opening hole, all sacrificial layers and all intermediate holes are removed.
  • the sacrificial layer and sacrificial material can be removed by one etching, without opening the support layer layer by layer, which reduces the number of etching times and etching time for the support layer after the formation of the first plate, thereby reducing the possibility of damage to the first plate , improve the yield rate of the memory.
  • the embodiment of the present application also provides a memory.
  • the memory is manufactured by the method for manufacturing the memory as described above.
  • the manufactured memory has the advantages of less damage to the first plate and a higher yield rate of the memory. For specific effects, refer to the above described in the text and will not be repeated here.
  • Fig. 1 is a structural schematic diagram after removing part of the third support layer in the related art
  • FIG. 2 is a schematic diagram of the structure after removing the second sacrificial layer in the related art
  • Fig. 3 is a structural schematic diagram after removing part of the second supporting layer in the related art
  • FIG. 4 is a schematic structural diagram after removing the first sacrificial layer in the related art
  • FIG. 5 is a flowchart of a method for manufacturing a memory in an embodiment of the present application.
  • FIG. 6 is a schematic structural view after forming a stacked structure in an embodiment of the present application.
  • FIG. 7 is a schematic structural view after forming a second photoresist layer in the embodiment of the present application.
  • Figure 8 is a top view of Figure 7;
  • FIG. 9 is a schematic structural diagram after forming a capacitance hole in an embodiment of the present application.
  • Figure 10 is a top view of Figure 9;
  • FIG. 11 is a schematic structural view of the first pole plate formed in the embodiment of the present application.
  • FIG. 12 is a schematic structural view after forming a third photoresist layer in the embodiment of the present application.
  • FIG. 13 is a schematic structural view of forming capacitor opening holes in the embodiment of the present application.
  • FIG. 14 is a schematic diagram of the structure after removing the sacrificial layer in the embodiment of the present application.
  • Fig. 15 is a flow chart of forming a laminated structure in the embodiment of the present application.
  • FIG. 16 is a schematic structural view after forming the first photoresist layer in the embodiment of the present application.
  • Figure 17 is a top view of Figure 16;
  • Fig. 18 is a schematic structural view of the formation of the middle hole in the embodiment of the present application.
  • FIG. 19 is a schematic structural view of the deposited sacrificial material in the embodiment of the present application.
  • FIG. 20 is a schematic diagram of the structure after removing the sacrificial material on the second supporting layer in the embodiment of the present application.
  • a capacitor opening hole 290 is formed in the third support layer 250 on the top layer of the structure 200; as shown in FIG. As shown in FIG. 3 , the second supporting layer 230 exposed in the capacitor opening hole 290 is removed; and as shown in FIG. 4 , the entire layer of the first sacrificial layer 220 is removed by using the capacitor opening hole 290 .
  • the third support layer 250 , the second sacrificial layer 240 , the second support layer 230 , and the first sacrificial layer are alternately removed, and the etching process needs to be switched constantly.
  • the removal of the third supporting layer 250 and the second supporting layer 230 usually requires a long time of pickling, especially when the second supporting layer 230 is pickled, it is easy to damage the first electrode plate 300 .
  • an embodiment of the present application provides a method for fabricating a memory.
  • An intermediate hole is provided in the support layer between two adjacent sacrificial layers.
  • the intermediate hole penetrates the support layer and is filled with a sacrificial material.
  • the contact, sacrificial layer and sacrificial material can be removed by one etching, without opening the support layer layer by layer, which reduces the number of etching times and etching time for the support layer after the formation of the first plate, thus reducing the risk of damage to the first plate Possibility, improve the yield rate of memory.
  • Fig. 5 is the flow chart of the manufacturing method of the memory in the embodiment of the present application, and this manufacturing method comprises the following steps:
  • Step S100 forming a stacked structure on the substrate, the stacked structure includes alternately arranged sacrificial layers and supporting layers; wherein, the number of layers of the sacrificial layer is greater than 1, and the top layer of the stacked structure is a supporting layer, and is located between the two sacrificial layers
  • the supporting layer in between is provided with a middle hole, and the middle hole is filled with a sacrificial material.
  • the substrate 100 serves as a supporting member of the memory for supporting other components disposed thereon.
  • the substrate 100 also includes a capacitive contact (not shown in the figure), and the subsequently formed capacitor is electrically connected to the capacitive contact, and the capacitor and the peripheral circuit are connected through the capacitive contact, so that the voltage signal of the peripheral circuit can be transmitted to the capacitor, thereby controlling the charging and discharging of the capacitor .
  • a stacked structure 200 is formed on the substrate 100 , and the stacked structure 200 is used to support a capacitor.
  • the laminated structure 200 includes a sacrificial layer and a supporting layer. After forming the first pole plate of the capacitor, the sacrificial layer and the sacrificial material are removed to expose the outer peripheral surface of the first pole plate; the supporting layer remains to support the first pole plate and prevent the second pole plate from One plate collapses or the adjacent first plate 300 touches.
  • the sacrificial layer and the supporting layer are arranged alternately, the number of layers of the sacrificial layer is at least two, and the top layer of the laminated structure 200 is a supporting layer, wherein, the top layer of the laminated structure 200 means that the laminated structure 200 is away from the base
  • the outer layer of 100 as shown in FIG. 6 , the top layer of the laminated structure 200 refers to the uppermost layer of the laminated structure 200 , and correspondingly, the layer of the laminated structure 200 in contact with the substrate 100 is the bottom layer of the laminated structure 200 .
  • the number of supporting layers is at least two, and providing multiple supporting layers can increase the stability of the device.
  • the material of the sacrificial layer can be silicon oxide (such as silicon dioxide), and the material of the supporting layer can be silicon nitride.
  • the sacrificial layer and the supporting layer can be formed through a deposition process.
  • a deposition process may be a chemical vapor deposition (Chemical Vapor Deposition, CVD for short) process, a physical vapor deposition (Physical Vapor Deposition, PVD for short) process or an atomic layer deposition (Atomic Layer Deposition, ALD for short) process, etc.
  • the bottom layer of the stacked structure 200 can also be a supporting layer, that is, the layer in the stacked structure 200 that is in contact with the substrate 100 is also a supporting layer.
  • the outermost layers on the upper and lower sides of the laminated structure 200 are support layers, that is to say, the number of layers of the support layer is greater than the number of layers of the sacrificial layer, and each sacrificial layer is arranged on two adjacent sides. Between the supporting layers, the supporting layer can serve as an etching barrier layer to protect the substrate 100 .
  • the laminated structure 200 includes two layers of sacrificial layers and three layers of supporting layers, and the supporting layer, the sacrificial layer, the supporting layer, the sacrificial layer, and the supporting layer are stacked in sequence.
  • the laminated structure 200 includes three layers of sacrificial layers and four layers of support layers, and the support layer, the sacrifice layer, the support layer, the sacrifice layer, the support layer, the sacrifice layer, and the support layer are stacked in sequence.
  • the number of layers of the sacrificial layer is greater than 1, and the support layer between the two sacrificial layers is provided with a middle hole, the middle hole runs through the support layer, and the middle hole is filled with a sacrificial material 270, that is, the sacrificial material 270 and the corresponding Two adjacent sacrificial layers are in contact, and the middle hole can serve as a communication channel between the two adjacent sacrificial layers.
  • the support layer inside the laminated structure 200 is provided with an intermediate hole.
  • the two support layers inside the laminated structure 200 are provided with intermediate holes, and the projections of the intermediate holes provided in different support layers on the substrate can be coincident.
  • the middle hole is filled with the sacrificial material 270 , and the etching rate selectivity ratio between the sacrificial material 270 and the sacrificial layer is 1.
  • the material of the sacrificial material 270 and the sacrificial layer is the same, that is, the sacrificial material 270 is silicon oxide.
  • the laminated structure 200 includes two sacrificial layers and three supporting layers.
  • the two sacrificial layers are respectively defined as the first sacrificial layer 220 and the second sacrificial layer 240
  • the three supporting layers are respectively defined as the first supporting layer 210 , the second supporting layer 230 and the third supporting layer 250 .
  • the first supporting layer 210, the first sacrificial layer 220, the second supporting layer 230, the second sacrificial layer 240 and the third supporting layer 250 are stacked, and the first supporting layer 210 is arranged on the base 100, and the second supporting layer 230 is arranged There is a central hole 260 .
  • Step S200 removing part of the stacked structure to form capacitor holes penetrating through the stacked structure.
  • the capacitor hole 280 is a through hole, which penetrates the stacked structure 200 , and the capacitor hole 280 exposes the substrate 100 .
  • the capacitor hole 280 may be staggered from the middle hole 260 , that is, the sacrificial material 270 in the middle hole 260 is not removed during the process of forming the capacitor hole 280 .
  • Capacitor hole 280 may also partially overlap with middle hole 260 of each layer, part of the hole wall of capacitor hole 280 is located in sacrificial material 270 in the middle hole, that is, part of sacrificial material 270 in middle hole is removed during the process of forming capacitor hole 280 , the sacrificial material 270 is also exposed in the capacitor hole 280 .
  • FIG. 10 there are multiple intermediate holes 260 located in the same support layer, and three capacitor holes 280 are distributed in the circumferential direction of each intermediate hole, and the three capacitor holes 280 are not connected to each other.
  • the capacitor holes 280 The pore walls extend into the sacrificial material.
  • the centers of the three capacitance holes 280 form a virtual triangle
  • the center of the middle hole 260 coincides with the center of the virtual triangle
  • the middle hole 260 and the partial area of each capacitance hole 280 coincide.
  • the outer contour of the remaining sacrificial material 270 is shown by the dotted line in FIG. 10 , and the remaining sacrificial material 270 forms three concave regions in the circumferential direction.
  • removing part of the stacked structure 200 and forming the capacitance hole 280 penetrating through the stacked structure 200 may include:
  • a second mask layer 400 is formed on the stacked structure 200 .
  • the second mask layer 400 may be a spin-on hardmask (Spin on Hardmask, SOH for short) layer. As shown in FIG. 7 , the second mask layer 400 covers the top surface of the laminated structure 200 .
  • a second photoresist layer 500 is formed on the second mask layer 400, the second photoresist layer 500 having a second pattern.
  • the second photoresist layer 500 is coated on the second mask layer 400, and a second pattern is formed through processes such as exposure and development.
  • the second pattern includes a plurality of second openings 510 arranged at intervals and a second shielding area isolating each second opening 510 .
  • the second opening 510 exposes the second mask layer 400 , and in the top view shown in FIG. 8 , the second mask layer 400 is exposed in the circle shown by the solid line.
  • the orthographic projection of the second opening 510 on the substrate 100 partially coincides with the orthographic projection of the sacrificial material 270 on the substrate 100 , and the sacrificial material 270 located in one middle hole 260 corresponds to three second openings 510 .
  • the second mask layer 400 is etched using the second photoresist layer 500 as a mask to form a second etching hole penetrating through the second mask layer 400 .
  • the second mask layer 400 covered by the second photoresist layer 500 remains, the second mask layer 400 not covered by the second photoresist layer 500 is removed, and the second pattern of the second photoresist layer 500 is transferred to The second mask layer 400 , a second etching hole is formed in the second mask layer 400 , and the stacked structure 200 is exposed in the second etching hole.
  • the stacked structure 200 is etched along the second etching hole to form the capacitor hole 280 in the stacked structure 200 .
  • the capacitor hole 280 penetrates the stacked structure 200 to expose a capacitor contact (not shown) in the substrate 100 .
  • the second mask layer 400 will also be etched away at the same time.
  • the second mask layer 400 is also completely removed, and the stacked structure 200 is exposed.
  • the second photoresist layer 500 when the second mask layer 400 is etched, the second photoresist layer 500 will also be etched away simultaneously. In some embodiments, after forming the second etching hole, the second photoresist layer 500 is also completely removed, and the second mask layer 400 is exposed. In other embodiments, after the second etching hole is formed, the second photoresist layer 500 remains, and the remaining second photoresist layer 500 can be removed by ashing or other processes, so that the second mask layer 400 exposed.
  • Step S300 forming a first plate on the hole wall and the bottom of the capacitor hole.
  • the material of the first pole plate 300 may include conductive materials such as titanium nitride, the side of the first pole plate 300 is in contact with the laminated structure 200, and the bottom of the first pole plate 300 is in contact with the capacitance in the substrate 100 ( (not shown in the figure) are in contact with each other to realize the electrical connection between the first plate 300 and the capacitor contact.
  • the first plate 300 can be formed through the following process:
  • a conductive layer is deposited on the wall and bottom of the capacitor hole 280 and the stacked structure 200 .
  • the conductive layer located in the capacitor hole 280 forms a filling hole 310 so that a double-sided capacitor can be formed later to increase the capacity of the capacitor.
  • etching removes the conductive layer on the laminated structure 200 , retains the conductive layer in the capacitor hole 280 , and the retained conductive layer forms the first plate 300 .
  • etching for example, dry etching
  • Step S400 removing a part of the supporting layer located on the top layer of the laminated structure opposite to the middle hole to form a capacitor opening hole, which exposes the sacrificial layer.
  • a capacitive open hole 290 is formed through the support layer 250 to expose the sacrificial layer 240 .
  • the capacitor opening hole 290 is opposite to the middle hole 260 .
  • the width of the capacitor opening hole 290 is the same as that of the remaining sacrificial material 270 .
  • the capacitor opening hole 290 exposes part of the outer peripheral surface of the first plate 300 .
  • the outer peripheral surface refers to the surface of the first electrode plate 300 in contact with the supporting layer, the sacrificial layer and the sacrificial material.
  • the laminated structure 200 includes a first support layer 210 , a first sacrificial layer 220 , a second support layer 230 , a second sacrificial layer 240 and a third support layer 250 arranged in a stack, and the first support layer 210 is disposed on the substrate 100, the second support layer 230 is provided with a middle hole 260, and the area opposite to the middle hole 260 in the support layer on the top layer of the laminated structure 200 is removed to form a capacitor open hole 290, which exposes the sacrificial hole 290.
  • Layers include:
  • a third mask layer 600 is formed on the stacked structure 200 .
  • the third mask layer 600 includes a second amorphous carbon (ACL) layer 610 and a second silicon oxynitride layer 620 , and the second amorphous carbon layer 610 is formed on the stacked structure 200 Specifically, the second amorphous carbon layer 610 is formed on the third supporting layer 250 , and the second silicon oxynitride layer 620 is formed on the second amorphous carbon layer 610 .
  • ACL amorphous carbon
  • the second amorphous carbon layer 610 is formed by a deposition process.
  • the deposition rate is controlled to seal the second amorphous carbon layer 610 . That is, a larger deposition rate is adopted, so that the second amorphous carbon layer 610 is formed on the stacked structure 200 and not formed in the filled hole 310 .
  • a third photoresist layer 700 is formed on the third mask layer 600 , and the third photoresist layer 700 has a third pattern.
  • the third photoresist layer 700 covers the top surface of the third mask layer 600 , and the third pattern includes a plurality of third openings (not shown in the figure) arranged at intervals and a third shielding area isolating each third opening.
  • the orthographic projection of the third opening on the substrate 100 at least covers the orthographic projection of the middle hole 260 on the substrate 100 .
  • the third mask layer 600 is etched using the third photoresist layer 700 as a mask to form a third etching hole penetrating through the third mask layer 600 630.
  • the third mask layer 600 covered by the third photoresist layer 700 remains, the third mask layer 600 not covered by the third photoresist layer 700 is removed, and a third etching hole 630 is formed in the third mask layer 600, The top surfaces of the laminated structure 200 and the first electrode plate 300 are exposed in the third etching hole 630 .
  • the stacked structure 200 is etched along the third etching hole 630 to remove the third supporting layer exposed in the third etching hole 630 250.
  • Capacitor opening holes 290 are formed in the third supporting layer 250 on the top layer of the laminated structure 200 , and the second sacrificial layer 240 is exposed in the capacitor opening holes 290 .
  • the third mask layer 600 will also be etched away at the same time. As shown in FIG. 13 , after the capacitor opening hole 290 is formed, the third mask layer 600 is also removed, and the remaining third supporting layer 250 and the first electrode plate 300 are exposed.
  • the third photoresist layer 700 will also be etched away at the same time. After the third etching hole 630 is formed, if the third photoresist layer 700 remains, the remaining third photoresist layer 700 may be removed by ashing or other processes to expose the third mask layer 600 .
  • Step S500 opening the holes through capacitors, removing all the sacrificial layers and all the sacrificial materials in the middle holes, so as to expose the outer peripheral surface of the first pole plate.
  • the etching gas or etching solution is introduced through the opening hole 290 of the capacitor to remove all the sacrificial layer and all the sacrificial material 270, and the outer peripheral surface of the first electrode plate 300 is exposed. As shown in FIG. 14 , the etching gas or etching solution is introduced through the opening hole 290 of the capacitor to remove all the sacrificial layer and all the sacrificial material 270, and the outer peripheral surface of the first electrode plate 300 is exposed. As shown in FIG.
  • the sacrificial layer in contact with the first pole plate 300 is removed, and the capacitance opening hole 290 extends to the first support layer 210, that is, the sacrificial layer between adjacent first pole plates 300 is removed, and the sacrificial The outer peripheral surface of the first pole plate 300 in layer contact is exposed, so as to form a dielectric layer on the inner peripheral surface and the outer peripheral surface of the first pole plate 300, thereby forming a double-sided capacitor, wherein the inner peripheral surface refers to the first pole The surface of the plate 300 facing away from the support layer, the sacrificial layer and the sacrificial material.
  • the sacrificial layer and the sacrificial material 270 are removed by one etching, without opening the supporting layer layer by layer, which reduces the number of times of etching the supporting layer, thereby reducing the etching support.
  • the possibility of layer damage to the first electrode plate 300 improves the yield rate of the memory.
  • there is no need to alternately etch the sacrificial layer and the support layer and it is also avoided that the etching process is different due to the different materials of the support layer and the sacrificial layer, reducing the time for changing the etching process, thereby reducing the etching time of the stacked structure 200.
  • the eclipse time is improved to improve the production efficiency of the memory.
  • the memory manufacturing method of the embodiment of the present application also includes include:
  • a dielectric layer is formed on the exposed surface of the first electrode plate 300 .
  • the first pole plate 300 is cylindrical, the first pole plate 300 forms a filling hole 310, a dielectric layer (not shown) covers the wall and bottom of the filling hole 310, and the top surface of the first pole plate 300, and the outer peripheral surface of the first pole plate 300 .
  • the material of the dielectric layer may be a dielectric material with a high dielectric constant, for example, one or more of zirconium oxide, hafnium oxide, antimony oxide, ruthenium oxide, and aluminum oxide.
  • a second pole plate (not shown) is formed on the dielectric layer, and the first pole plate 300, the dielectric layer and the second pole plate form a capacitor. Part of the second pole plate is located in the filling hole 310 of the first pole plate 300, and part of the second pole plate is located in the space after the sacrificial layer and sacrificial material 270 are removed.
  • the first pole plate 300, the dielectric layer and the second pole plate form a double The capacitor on the surface to increase the storage capacity of the capacitor.
  • the stacked structure 200 is first formed on the substrate 100, and the stacked structure 200 includes alternately arranged sacrificial layers and supporting layers; wherein, the number of layers of the sacrificial layer is greater than 1 , the top layer of the stacked structure 200 is a support layer, and the support layer between the two sacrificial layers is provided with a middle hole 260, and the middle hole 260 is filled with a sacrificial material 270; part of the stacked structure 200 is removed to form a through stacked structure
  • the capacitor hole 280 of 200 form the first plate 300 at the hole wall and the bottom of the hole of the capacitor hole 280 again; remove the area opposite to the middle hole 260 in the support layer positioned at the top layer of the laminated structure 200, form the capacitor opening hole 290, and the capacitor Opening the hole 290 to expose the sacrificial layer; opening the hole 290 through capacitance, removing all the sacrificial layer and
  • the sacrificial layer and the sacrificial material 270 can be removed by one etching, without opening the support layer layer by layer, which reduces the number of etching times and etching time for the support layer after the first pole plate 300 is formed, thereby reducing the damage of the first pole plate 300 The possibility of improving the yield rate of the memory.
  • FIG. 15 is a flow chart of forming a laminated structure in an embodiment of the present application.
  • the laminated structure 200 includes a stacked first support layer 210 , a first sacrificial layer 220 , The second supporting layer 230, the second sacrificial layer 240 and the third supporting layer 250, and the first supporting layer 210 is arranged on the base 100, and the second supporting layer 230 is provided with an intermediate hole 260, correspondingly, a stack is formed on the base 100
  • Layer structure 200 includes:
  • Step S110 sequentially depositing a first support layer, a first sacrificial layer and a second support layer on the substrate, and the second support layer is formed with a middle hole.
  • a first mask layer 800 is formed by depositing on the second supporting layer 230 .
  • the first mask layer 800 covers the second supporting layer 230.
  • a first silicon oxynitride layer 820 is formed on the first amorphous carbon layer 810 .
  • a first photoresist layer 900 is deposited on the first mask layer 800, and the first photoresist layer 900 has a first pattern. 16 and 17, the first photoresist layer 900 covers the upper surface of the first mask layer 800, and the first pattern includes a plurality of first openings 910 arranged at intervals and a first shielding layer isolating each first opening 910 .
  • the first mask layer 800 is exposed in the first opening 910 surrounded by a circle as shown in FIG. The center of the virtual triangle.
  • the first mask layer 800 is etched to form a first etching hole penetrating through the first mask layer 800 .
  • the first mask layer 800 covered by the first photoresist layer 900 remains, the first mask layer 800 not covered by the first photoresist layer 900 is removed, and a first etching hole is formed in the first mask layer 800, the second The second supporting layer 230 is exposed in the etching hole.
  • the second supporting layer 230 is etched along the first etching hole to form the middle hole 260 .
  • the first mask layer 800 will also be etched away at the same time. As shown in FIG. 18 , after the middle hole 260 is formed, the first mask layer 800 is also completely removed, and the second supporting layer 230 is exposed.
  • the first photoresist layer 900 will also be etched away at the same time. After forming the first etching hole, if the first photoresist layer 900 remains, the remaining first photoresist layer 900 is removed by ashing or other processes to expose the first mask layer 800 .
  • Step S120 deposit a sacrificial material in the middle hole and on the second support layer, the sacrificial material fills the middle hole and covers the second support layer.
  • the sacrificial material 270 may be a spin-on dielectric (SOD).
  • SOD spin-on dielectric
  • an insulating medium such as silicon oxide is spin-coated in the middle hole 260 and on the second supporting layer 230 .
  • the sacrificial material 270 is in contact with the first sacrificial layer 220 .
  • Step S130 removing the sacrificial material on the second support layer to expose the second support layer.
  • the sacrificial material 270 in the middle hole 260 remains, and the remaining sacrificial material 270 is removed.
  • dry etching removes the sacrificial material 270 on the second supporting layer 230, and the remaining sacrificial material 270 is flush with the second supporting layer 230, and the surface formed by the sacrificial material 270 and the second supporting layer 230 is relatively flat , so as to form other film layers on the second support layer 230 .
  • the sacrificial material 270 located on the second supporting layer 230 may also be removed by chemical mechanical polishing (CMP) and other processes.
  • CMP chemical mechanical polishing
  • Step S140 sequentially depositing a second sacrificial layer and a third supporting layer on the second supporting layer and the remaining sacrificial material.
  • the third supporting layer 250 covers the second sacrificial layer 240 to form the laminated structure 200 .
  • the embodiment of the present application also provides a memory.
  • the memory is manufactured by the above-mentioned manufacturing method of the memory.
  • the manufactured memory has the advantages of less damage to the first plate and a high yield rate of the memory. For specific effects, refer to the above. I won't repeat them here.

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Abstract

本申请提供一种存储器的制作方法及存储器，涉及存储设备技术领域，用于解决第一极板易损伤、存储器的良品率低的技术问题。该制作方法包括：在基底上形成叠层结构，叠层结构包括交替设置的牺牲层和支撑层，叠层结构顶层为支撑层，且位于两个牺牲层之间的支撑层设有中间孔，中间孔内填充有牺牲材料；形成贯穿叠层结构的电容孔；在电容孔的孔壁和孔底形成第一极板；去除叠层结构顶层的支撑层中与中间孔相对的区域，形成暴露牺牲层的电容打开孔；通过电容打开孔，去除所有牺牲层和所有牺牲材料。牺牲层和牺牲材料可以通过一次刻蚀去除，无需逐层打开支撑层，减少形成第一极板后对支撑层的刻蚀，降低第一极板损伤的可能性，提高存储器的良品率。

Description

存储器的制作方法及存储器
本申请要求于2021年05月26日提交中国专利局、申请号为202110579258.1、申请名称为“存储器的制作方法及存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储设备技术领域，尤其涉及一种存储器的制作方法及存储器。
背景技术
动态随机存储器(Dynamic random access memory，简称Dram)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。动态随机存储器通常包括电容器，电容器通过存储电荷的方式保存数据。
相关技术中，制作存储器时，通常先在基底上形成叠层结构，叠层结构包括支撑层以及位于相邻的支撑层之间的牺牲层；然后，在叠层结构内形成电容孔，并在电容孔的孔壁和孔底形成第一极板；再去除顶层的部分支撑层，形成电容打开孔，电容打开孔暴露牺牲层；之后去除牺牲层，以便于在电容孔内及去除的牺牲层的位置上形成介质层和第二极板。
当叠层结构包括多层牺牲层时，每个牺牲层均位于相邻的两层支撑层之间。去除牺牲层的过程中需去除多层支撑层，支撑层通常需要较长时间的酸洗来减少缺陷，支撑层酸洗时易损伤到第一极板，降低存储器的良品率。
发明内容
本申请实施例提供一种存储器的制作方法，其包括：在基底上形成叠层结构，所述叠层结构包括交替设置的牺牲层和支撑层；其中，所述牺牲层的层数大于1，所述叠层结构的顶层为所述支撑层，且位于两个所述牺 牲层之间的所述支撑层设有中间孔，所述中间孔内填充有牺牲材料；去除部分所述叠层结构，形成贯穿所述叠层结构的电容孔；在所述电容孔的孔壁和孔底形成第一极板；去除位于所述叠层结构的顶层的所述支撑层中与所述中间孔相对的区域，形成电容打开孔，所述电容打开孔暴露所述牺牲层；通过所述电容打开孔，去除所有所述牺牲层和所有所述中间孔内的所述牺牲材料，以暴露所述第一极板的外周面。
本申请实施例提供的存储器的制作方法至少具有如下优点：
本申请实施例提供的存储器的制作方法中，先在基底上形成叠层结构，叠层结构包括交替设置的牺牲层和支撑层；其中，牺牲层的层数大于1，叠层结构的顶层为支撑层，且位于两个牺牲层之间的支撑层设有中间孔，中间孔内填充有牺牲材料；去除部分叠层结构，形成贯穿叠层结构的电容孔；再在电容孔的孔壁和孔底形成第一极板；去除位于叠层结构的顶层的支撑层中与中间孔相对的区域，形成电容打开孔，电容打开孔暴露牺牲层；通过电容打开孔，去除所有牺牲层和所有中间孔内的牺牲材料，以暴露第一极板的外周面。牺牲层和牺牲材料可以通过一次刻蚀去除，无需逐层打开支撑层，减少了形成第一极板后对支撑层的刻蚀次数和刻蚀时间，从而降低了第一极板损伤的可能性，提高存储器的良品率。
本申请实施例还提供一种存储器，存储器通过如上所述的存储器的制作方法制得，制得的存储器具有第一极板的损伤较少，存储器的良品率较高的优点，具体效果参照上文所述，在此不再赘述。
附图说明
图1为相关技术中的去除部分第三支撑层后的结构示意图；
图2为相关技术中的去除第二牺牲层后的结构示意图；
图3为相关技术中的去除部分第二支撑层后的结构示意图；
图4为相关技术中的去除第一牺牲层后的结构示意图；
图5为本申请实施例中的存储器的制作方法的流程图；
图6为本申请实施例中的形成叠层结构后的结构示意图；
图7为本申请实施例中的形成第二光刻胶层后的结构示意图；
图8为图7的俯视图；
图9为本申请实施例中的形成电容孔后的结构示意图；
图10为图9的俯视图；
图11为本申请实施例中的形成第一极板后的结构示意图；
图12为本申请实施例中的形成第三光刻胶层后的结构示意图；
图13为本申请实施例中的形成电容打开孔后的结构示意图；
图14为本申请实施例中的去除牺牲层后的结构示意图；
图15为本申请实施例中的形成叠层结构的流程图；
图16为本申请实施例中的形成第一光刻胶层后的结构示意图；
图17为图16的俯视图；
图18为本申请实施例中的形成中间孔后的结构示意图；
图19为本申请实施例中的沉积牺牲材料后的结构示意图；
图20为本申请实施例中的去除第二支撑层上的牺牲材料后的结构示意图。
具体实施方式
参照图1至图4，相关技术中，形成第一极板300后，去除叠层结构200中的第一牺牲层220和第二牺牲层240时，如图1所示，通常先在叠层结构200顶层的第三支撑层250中形成电容打开孔290；再如图2所示，利用电容打开孔290去除整层第二牺牲层240后，电容打开孔290暴露第二支撑层230；之后如图3所示，去除暴露在电容打开孔290内的第二支撑层230；再如图4所示，利用电容打开孔290去除整层第一牺牲层220。然而，上述过程中，第三支撑层250、第二牺牲层240、第二支撑层230、第一牺牲层交替去除，刻蚀工艺需不断切换。此外，去除第三支撑层250和第二支撑层230时通常需要较长时间的酸洗，尤其是第二支撑层230酸洗时易损伤第一极板300。
鉴于此，本申请实施例提供一种存储器的制作方法，在相邻两层牺牲层之间的支撑层内设置中间孔，中间孔贯穿支撑层并填充有牺牲材料，即牺牲材料与牺牲层相接触，牺牲层和牺牲材料可以通过一次刻蚀去除，无需逐层打开支撑层，减少了形成第一极板后对支撑层的刻蚀次数和刻蚀时间，从而降低了第一极板损伤的可能性，提高存储器的良品率。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下 面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
参照图5，图5为本申请实施例中的存储器的制作方法的流程图，该制作方法包括以下步骤：
步骤S100、在基底上形成叠层结构，叠层结构包括交替设置的牺牲层和支撑层；其中，牺牲层的层数大于1，叠层结构的顶层为支撑层，且位于两个牺牲层之间的支撑层设有中间孔，中间孔内填充有牺牲材料。
参照图6，基底100作为存储器的支撑部件，用于支撑设置在其上的其他部件。基底100中还包括电容接触(图中未标示)，后续形成的电容器与电容接触电连接，通过电容接触连通电容器和外围电路，使外围电路的电压信号能传输到电容器，从而控制电容器的充放电。
如图6所示，基底100上形成有叠层结构200，叠层结构200用于支撑电容器。叠层结构200包括牺牲层和支撑层，形成电容器的第一极板后，牺牲层和牺牲材料去除，以暴露第一极板的外周面；支撑层保留，以支撑第一极板，防止第一极板坍塌或者相邻的第一极板300相接触。
继续参照图6，牺牲层和支撑层交替设置，牺牲层的层数至少为两层，且叠层结构200的顶层为支撑层，其中，叠层结构200的顶层是指叠层结构200远离基底100的外层，如图6所示，叠层结构200的顶层是指叠层结构200的最上层，相应的，叠层结构200中与基底100接触的一层为叠层结构200的底层。如此设置，支撑层的层数至少也为两层，设置多层支撑层可以增加器件的稳定性。牺牲层的材质可以为氧化硅(例如二氧化硅)，支撑层的材质可以为氮化硅。
牺牲层和支撑层可以通过沉积工艺形成，示例性的，沉积一层牺牲层后，再在该牺牲层上沉积一层支撑层，直至牺牲层和支撑层的层数达到预设值。沉积工艺可以为化学气相沉积(Chemical Vapor Deposition，简称CVD)工艺、物理气相沉积(Physical Vapor Deposition，简称PVD)工艺或者原子层沉积(Atomic Layer Deposition，简称ALD)工艺等。
为了防止基底100在刻蚀叠层结构200时损伤，叠层结构200的底层 也可以为支撑层，即叠层结构200中与基底100接触的一层也为支撑层。如图6所示，叠层结构200上下两侧的最外一层均为支撑层，也就是说，支撑层的层数大于牺牲层的层数，每个牺牲层均设置在相邻的两个支撑层之间，支撑层可以作为刻蚀阻挡层，对基底100进行保护。
示例性的，如图6所示，叠层结构200包括两层牺牲层和三层支撑层，支撑层、牺牲层、支撑层、牺牲层、支撑层依次堆叠设置。或者，叠层结构200包括三层牺牲层和四层支撑层，支撑层、牺牲层、支撑层、牺牲层、支撑层、牺牲层、支撑层依次堆叠设置。
继续参照图6，牺牲层的层数大于1，位于两个牺牲层之间的支撑层设有中间孔，中间孔贯穿支撑层，且中间孔内填充有牺牲材料270，即牺牲材料270与相邻的两个牺牲层相接触，中间孔可以作为相邻两个牺牲层之间的连通通道。当牺牲层为两层时，位于叠层结构200内部的一层支撑层设有中间孔。当牺牲层为三层时，位于叠层结构200内部的两层支撑层设有中间孔，设置在不同支撑层中的中间孔在基底上的投影可以相重合。
牺牲材料270填充满中间孔，牺牲材料270与牺牲层的刻蚀速率选择比为1，例如，牺牲材料270与牺牲层的材质相同，即牺牲材料270为氧化硅。如此设置，全部的牺牲层与全部的牺牲材料270可以在一次刻蚀时去除，减少牺牲层的刻蚀次数，提高牺牲层的刻蚀效率。
在一种可能的示例中，如图6所示，叠层结构200包括两层牺牲层和三层支撑层。为了方便描述，将两层牺牲层分别定义为第一牺牲层220和第二牺牲层240，将三层支撑层分别定义为第一支撑层210、第二支撑层230和第三支撑层250。第一支撑层210、第一牺牲层220、第二支撑层230、第二牺牲层240和第三支撑层250堆叠设置，且第一支撑层210设在基底100上，第二支撑层230设有中间孔260。
步骤S200、去除部分叠层结构，形成贯穿叠层结构的电容孔。
参照图7至图10，电容孔280为直通孔，其贯穿叠层结构200，电容孔280内暴露基底100。电容孔280可以与中间孔260错开，即形成电容孔280的过程中未去除中间孔260内的牺牲材料270。电容孔280也可以与每一层的中间孔260部分重合，电容孔280的部分孔壁位于中间孔内的牺牲材料270中，即形成电容孔280的过程中去除中间孔内的部分牺牲材料270，电容孔280内也暴露出牺牲材料270。
示例性的，参照图10，位于同一支撑层中的中间孔260的数量为多个，每个中间孔的周向分布有三个电容孔280，且三个电容孔280互不连通，电容孔280的孔壁延伸至牺牲材料中。
如图10所示的点划线框内，三个电容孔280的中心形成虚拟三角形，中间孔260的中心与虚拟三角形的中心相重合，且中间孔260与每个电容孔280的部分区域相重合。形成电容孔280后，剩余的牺牲材料270的外轮廓如图10中虚线所示，剩余的牺牲材料270周向形成三个凹陷区。
在一些可能的示例中，去除部分叠层结构200，形成贯穿叠层结构200的电容孔280可以包括：
参照图7，在叠层结构200上形成第二掩膜层400。第二掩膜层400可以为旋涂硬掩模(Spin on Hardmask，简称SOH)层，如图7所示，第二掩膜层400覆盖叠层结构200的顶面。
参照图7和图8，形成第二掩膜层400之后，在第二掩膜层400上形成第二光刻胶层500，第二光刻胶层500具有第二图案。第二光刻胶层500涂覆在第二掩膜层400上，通过曝光、显影等工艺形成第二图案。第二图案包括多个间隔设置的第二开口510和隔离各第二开口510的第二遮挡区。第二开口510暴露出第二掩膜层400，如图8所示的俯视图中，实线所示的圆形中暴露第二掩膜层400。第二开口510在基底100上的正投影与牺牲材料270在基底100上的正投影部分重合，且位于一个中间孔260内的牺牲材料270对应三个第二开口510。
形成第二光刻胶层500之后，以第二光刻胶层500为掩膜，刻蚀第二掩膜层400，形成贯穿第二掩膜层400的第二刻蚀孔。被第二光刻胶层500覆盖的第二掩膜层400保留，未被第二光刻胶层500覆盖的第二掩膜层400去除，第二光刻胶层500的第二图案传递到第二掩膜层400，第二掩膜层400中形成第二刻蚀孔，第二刻蚀孔内暴露叠层结构200。
参照图9和图10，形成贯穿第二掩膜层400的第二刻蚀孔之后，沿第二刻蚀孔刻蚀叠层结构200，以在叠层结构200中形成电容孔280。电容孔280贯穿叠层结构200，以暴露基底100内的电容接触(图中未标示)。在刻蚀电容孔280的过程中，第二掩膜层400也会同时被刻蚀去除。如图9和图10所示，形成电容孔280后，第二掩膜层400也被完全去除，叠层结构200暴露出来。
需要说明的是，在刻蚀第二掩膜层400的同时，第二光刻胶层500也会被同时刻蚀去除。在一些实施例中，形成第二刻蚀孔后，第二光刻胶层500也被完全去除，第二掩膜层400暴露出来。在另一些实施例中，形成第二刻蚀孔后，第二光刻胶层500有剩余，剩余的第二光刻胶层500可以通过灰化等工艺去除，以将第二掩膜层400暴露出来。
步骤S300、在电容孔的孔壁和孔底形成第一极板。
参照图11，第一极板300的材质可以包括氮化钛等导电材料，第一极板300的侧部与叠层结构200接触，第一极板300的底部与基底100中的电容接触(图中未标示)相接触，以实现第一极板300与电容接触之间的电连接。
示例性的，第一极板300可以通过以下过程形成：
首先，在电容孔280的孔壁和孔底，以及叠层结构200上沉积导电层。位于电容孔280内的导电层围合成填充孔310，以使后续可以形成双面电容，提高电容器的容量。
其次，刻蚀(例如干法刻蚀)去除位于叠层结构200上的导电层，保留位于电容孔280内的导电层，保留的导电层形成第一极板300。如图11所示，位于叠层结构200顶面上的导电层被去除，叠层结构200的顶面暴露出来。
步骤S400、去除位于叠层结构的顶层的部分支撑层中与中间孔相对的区域，形成电容打开孔，电容打开孔暴露牺牲层。
参考图13，去除叠层结构200顶层的部分支撑层250，形成贯穿该支撑层250的电容打开孔290，以暴露牺牲层240。电容打开孔290与中间孔260相对，示例性的，电容打开孔290的宽度与剩余的牺牲材料270的宽度相同，电容打开孔290暴露出第一极板300的部分外周面。其中，外周面是指第一极板300与支撑层、牺牲层及牺牲材料相接触的表面。
在一些可能的示例中，叠层结构200包括堆叠设置的第一支撑层210、第一牺牲层220、第二支撑层230、第二牺牲层240和第三支撑层250，且第一支撑层210设在基底100上，第二支撑层230设有中间孔260，去除位于叠层结构200的顶层的支撑层中与中间孔260相对的区域，形成电容打开孔290，电容打开孔290暴露牺牲层包括：
参照图12，在叠层结构200上形成第三掩膜层600。示例性的，如图 12所示，第三掩膜层600包括第二非晶碳(ACL)层610和第二氮氧化硅层620，第二非晶碳层610形成在叠层结构200上，具体的，第二非晶碳层610形成在第三支撑层250上，第二氮氧化硅层620形成在第二非晶碳层610上。
第二非晶碳层610通过沉积工艺形成，沉积第二非晶碳层610时，通过控制沉积速率，以使第二非晶碳层610封口。即采用较大的沉积速率，使得第二非晶碳层610形成在叠层结构200上，不形成在填充孔310内。
继续参照图12，形成第三掩膜层600之后，在第三掩膜层600上形成第三光刻胶层700，第三光刻胶层700具有第三图案。第三光刻胶层700覆盖第三掩膜层600的顶面，第三图案包括多个间隔设置的第三开口(图中未标示)和隔离各第三开口的第三遮挡区。第三开口在基底100上的正投影至少覆盖中间孔260在基底100上的正投影。
继续参照图12，形成第三光刻胶层700之后，以第三光刻胶层700为掩膜，刻蚀第三掩膜层600，形成贯穿第三掩膜层600的第三刻蚀孔630。第三光刻胶层700覆盖的第三掩膜层600保留，第三光刻胶层700未覆盖的第三掩膜层600去除，第三掩膜层600中形成第三刻蚀孔630，第三刻蚀孔630内暴露叠层结构200和第一极板300的顶面。
参照图13，形成贯穿第三掩膜层600的第三刻蚀孔630之后，沿第三刻蚀孔630刻蚀叠层结构200，去除暴露在第三刻蚀孔630内的第三支撑层250。位于叠层结构200顶层的第三支撑层250中形成电容打开孔290，电容打开孔290内暴露第二牺牲层240。在刻蚀第三支撑层250的过程中，第三掩膜层600也会同时被刻蚀去除。如图13所示，形成电容打开孔290后，第三掩膜层600也去除，剩余的第三支撑层250和第一极板300暴露出来。
可以理解的是，在刻蚀第三掩膜层600的过程中，第三光刻胶层700也会同时被刻蚀去除。形成第三刻蚀孔630后，如果第三光刻胶层700仍有剩余，剩余的第三光刻胶层700可以通过灰化等工艺去除，以暴露第三掩膜层600。
步骤S500、通过电容打开孔，去除所有牺牲层和所有中间孔内的牺牲材料，以暴露第一极板的外周面。
参照图14，通过电容打开孔290通入刻蚀气体或者刻蚀液，去除全部 的牺牲层和全部的牺牲材料270，第一极板300的外周面暴露。如图14所示，与第一极板300接触的牺牲层被去除，电容打开孔290延伸至第一支撑层210，即相邻的第一极板300之间的牺牲层被去除，与牺牲层接触的第一极板300的外周面暴露出来，以便于在第一极板300的内周面及外周面上形成介质层，从而形成双面电容，其中，内周面是指第一极板300背离支撑层、牺牲层及牺牲材料的表面。
本申请实施例中，形成第一极板300后，通过一次刻蚀去除全部的牺牲层和牺牲材料270，无需逐层打开支撑层，减少了支撑层的刻蚀次数，从而减少了刻蚀支撑层损伤第一极板300的可能性，提高了存储器的良品率。此外，无需交替刻蚀牺牲层和支撑层，也避免了因支撑层和牺牲层的材料的不同而导致刻蚀工艺不同，减少了变更刻蚀工艺的时间，进而减少了叠层结构200的刻蚀时间，提高存储器的制作效率。
需要说明的是，通过电容打开孔290，去除所有牺牲层和所有中间孔260内的牺牲材料270，以暴露第一极板300的外周面的步骤之后，本申请实施例的存储器的制作方法还包括：
继续参照图14，在第一极板300暴露的表面上形成介质层。示例性的，第一极板300呈筒状，第一极板300形成填充孔310，介质层(未示出)覆盖填充孔310的孔壁和孔底、第一极板300的顶面，以及第一极板300的外周面。介质层的材质可以为具有高介电常数的介电材料，例如，氧化锆、氧化铪、氧化锑、氧化钌、氧化铝中的一种或者多种。
形成介质层后，在介质层上形成第二极板(未示出)，第一极板300、介质层和第二极板构成电容器。部分第二极板位于第一极板300的填充孔310内，部分第二极板位于牺牲层和牺牲材料270去除后的空间内，第一极板300、介质层和第二极板形成双面的电容器，以提高电容器的存储量。
综上所述，本申请实施例的存储器的制作方法中，先在基底100上形成叠层结构200，叠层结构200包括交替设置的牺牲层和支撑层；其中，牺牲层的层数大于1，叠层结构200的顶层为支撑层，且位于两个牺牲层之间的支撑层设有中间孔260，中间孔260内填充有牺牲材料270；去除部分叠层结构200，形成贯穿叠层结构200的电容孔280；再在电容孔280的孔壁和孔底形成第一极板300；去除位于叠层结构200顶层的支撑层中与中间孔260相对的区域，形成电容打开孔290，电容打开孔290暴露牺 牲层；通过电容打开孔290，去除所有牺牲层和所有中间孔260内的牺牲材料270，以暴露第一极板300的外周面。牺牲层和牺牲材料270可以通过一次刻蚀去除，无需逐层打开支撑层，减少了形成第一极板300后对支撑层的刻蚀次数和刻蚀时间，从而减少了第一极板300损伤的可能性，提高存储器的良品率。
需要说明的是，参照图15至图20，图15为本申请实施例中的形成叠层结构的流程图，该叠层结构200包括堆叠设置的第一支撑层210、第一牺牲层220、第二支撑层230、第二牺牲层240和第三支撑层250，且第一支撑层210设在基底100上，第二支撑层230设有中间孔260，相应的，在基底100上形成叠层结构200包括：
步骤S110、在基底上依次沉积第一支撑层、第一牺牲层和第二支撑层，第二支撑层形成有中间孔。
示例性的，参照图16，首先，在第二支撑层230上沉积形成第一掩膜层800。第一掩膜层800覆盖第二支撑层230，如图16所示，第一掩膜层800包括第一非晶碳层810和第一氮氧化硅层820，第一非晶碳层810形成在第二支撑层230上，第一氮氧化硅层820形成在第一非晶碳层810上。
其次，在第一掩膜层800上沉积形成第一光刻胶层900，第一光刻胶层900具有第一图案。参照图16和图17，第一光刻胶层900覆盖第一掩膜层800的上表面，第一图案包括多个间隔设置的第一开口910和隔离各第一开口910的第一遮挡层。如图17中圆形围合的第一开口910内暴露第一掩膜层800，第一开口910在基底100上的正投影的中心位于三个电容接触(图中未标示)所围合的虚拟三角形的中心。
然后，以第一光刻胶层900为掩膜，刻蚀第一掩膜层800，形成贯穿第一掩膜层800的第一刻蚀孔。第一光刻胶层900覆盖的第一掩膜层800保留，第一光刻胶层900未覆盖的第一掩膜层800去除，第一掩膜层800中形成第一刻蚀孔，第一刻蚀孔内暴露第二支撑层230。
再次，沿第一刻蚀孔刻蚀第二支撑层230，以形成中间孔260。在刻蚀第二支撑层230的过程中，第一掩膜层800也会同时被刻蚀去除。如图18所示，形成中间孔260后，第一掩膜层800也被完全去除，第二支撑层230暴露出来。
需要说明的是，在刻蚀第一掩膜层800的过程中，第一光刻胶层900 也会同时被刻蚀去除。形成第一刻蚀孔后，如果第一光刻胶层900仍有剩余，剩余的第一光刻胶层900通过灰化等工艺去除，以暴露第一掩膜层800。
步骤S120、在中间孔内和第二支撑层上沉积牺牲材料，牺牲材料填充满中间孔且覆盖第二支撑层。
参照图19，牺牲材料270可以为旋涂绝缘介质(SOD)，示例性的，将氧化硅等绝缘介质旋涂在中间孔260内和第二支撑层230上。牺牲材料270与第一牺牲层220相接触。
步骤S130、去除位于第二支撑层上的牺牲材料，以暴露第二支撑层。
参照图20，保留中间孔260内的牺牲材料270，去除剩余的牺牲材料270。示例性的，干法刻蚀去除位于第二支撑层230上的牺牲材料270，剩余的牺牲材料270与第二支撑层230齐平，牺牲材料270和第二支撑层230所形成的表面较为平整，以便于在第二支撑层230上形成其他膜层。当然，也可以通过化学机械研磨(Chemical Mechanical Polishing，简称CMP)等工艺去除位于第二支撑层230上的牺牲材料270。
步骤S140、在第二支撑层和剩余的牺牲材料上依次沉积第二牺牲层和第三支撑层。
参照图6，先在第二支撑层230和剩余的牺牲材料270上沉积第二牺牲层240，第二牺牲层240覆盖第二支撑层230和牺牲材料270；再在第二牺牲层240上沉积第三支撑层250，第三支撑层250覆盖第二牺牲层240，以形成叠层结构200。
本申请实施例还提供一种存储器，存储器通过上述的存储器的制作方法制得，制得的存储器具有第一极板的损伤较少，存储器的良品率较高的优点，具体效果参照上文，在此不再赘述。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结 构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种存储器的制作方法，包括：
    在基底上形成叠层结构，所述叠层结构包括交替设置的牺牲层和支撑层；其中，所述牺牲层的层数大于1，所述叠层结构的顶层为所述支撑层，且位于两个所述牺牲层之间的所述支撑层设有中间孔，所述中间孔内填充有牺牲材料；
    去除部分所述叠层结构，形成贯穿所述叠层结构的电容孔；
    在所述电容孔的孔壁和孔底形成第一极板；
    去除位于所述叠层结构的顶层的所述支撑层中与所述中间孔相对的区域，形成电容打开孔，所述电容打开孔暴露所述牺牲层；
    通过所述电容打开孔，去除所有所述牺牲层和所有所述中间孔内的所述牺牲材料，以暴露所述第一极板的外周面。
  2. 根据权利要求1所述的存储器的制作方法，其中，所述电容孔的部分孔壁位于所述中间孔内的所述牺牲材料中。
  3. 根据权利要求2所述的存储器的制作方法，其中，位于同一所述支撑层中的所述中间孔的数量为多个，每个所述中间孔内的周向分布有三个所述电容孔，且三个所述电容孔互不连通。
  4. 根据权利要求1所述的存储器的制作方法，其中，所述支撑层的材质为氮化硅，所述牺牲层的材质为氧化硅，所述牺牲材料为氧化硅。
  5. 根据权利要求1所述的存储器的制作方法，其中，所述叠层结构包括堆叠设置的第一支撑层、第一牺牲层、第二支撑层、第二牺牲层和第三支撑层，所述第一支撑层设在所述基底上，所述第二支撑层设有所述中间孔。
  6. 根据权利要求5所述的存储器的制作方法，其中，在基底上形成叠层结构，所述叠层结构包括交替设置的牺牲层和支撑层的步骤包括：
    在所述基底上依次沉积所述第一支撑层、所述第一牺牲层和所述第二支撑层，所述第二支撑层形成有所述中间孔；
    在所述中间孔内和所述第二支撑层上沉积牺牲材料，所述牺牲材料填充满所述中间孔且覆盖所述第二支撑层；
    去除位于所述第二支撑层上的所述牺牲材料，以暴露所述第二支撑层；
    在所述第二支撑层和剩余的所述牺牲材料上依次沉积所述第二牺牲层和所述第三支撑层。
  7. 根据权利要求6所述的存储器的制作方法，其中，在所述基底上依次沉积所述第一支撑层、所述第一牺牲层和所述第二支撑层，所述第二支撑层形成有所述中间孔的步骤包括：
    在所述第二支撑层上形成第一掩膜层；
    在所述第一掩膜层上形成第一光刻胶层，所述第一光刻胶层具有第一图案；
    以所述第一光刻胶层为掩膜，刻蚀所述第一掩膜层，形成贯穿所述第一掩膜层的第一刻蚀孔；
    沿所述第一刻蚀孔刻蚀所述第二支撑层，以形成所述中间孔。
  8. 根据权利要求7所述的存储器的制作方法，其中，所述第一掩膜层包括形成在所述第二支撑层上的第一非晶碳层，以及形成在所述第一非晶碳层上的第一氮氧化硅层。
  9. 根据权利要求6所述的存储器的制作方法，其中，去除位于所述第二支撑层上的所述牺牲材料，以暴露所述第二支撑层的步骤包括：
    干法刻蚀去除位于所述第二支撑层上的所述牺牲材料，剩余的所述牺牲材料与所述第二支撑层齐平。
  10. 根据权利要求5所述的存储器的制作方法，其中，去除部分所述叠层结构，形成贯穿所述叠层结构的电容孔的步骤包括：
    在所述叠层结构上形成第二掩膜层；
    在所述第二掩膜层上形成第二光刻胶层，所述第二光刻胶层具有第二图案；
    以所述第二光刻胶层为掩膜，刻蚀所述第二掩膜层，形成贯穿所述第二掩膜层的第二刻蚀孔；
    沿所述第二刻蚀孔刻蚀所述叠层结构，以在所述叠层结构中形成所述电容孔。
  11. 根据权利要求5所述的存储器的制作方法，其中，在所述电容孔的孔壁和孔底形成第一极板的步骤包括：
    在所述电容孔的孔壁和孔底，以及所述第三支撑层上沉积导电层；
    刻蚀去除位于所述第三支撑层上的所述导电层，保留位于所述电容孔 内的所述导电层，保留的所述导电层形成所述第一极板。
  12. 根据权利要求5所述的存储器的制作方法，其中，去除位于所述叠层结构的顶层的所述支撑层中与所述中间孔相对的区域，形成电容打开孔，所述电容打开孔暴露所述牺牲层的步骤包括：
    在所述叠层结构上形成第三掩膜层；
    在所述第三掩膜层上形成第三光刻胶层，所述第三光刻胶层具有第三图案；
    以所述第三光刻胶层为掩膜，刻蚀所述第三掩膜层，形成贯穿所述第三掩膜层的第三刻蚀孔；
    沿所述第三刻蚀孔刻蚀所述叠层结构，去除暴露在所述第三刻蚀孔内的所述第三支撑层。
  13. 根据权利要求12所述的存储器的制作方法，其中，所述第三掩膜层包括形成在所述叠层结构上的第二非晶碳层，以及形成在所述第二非晶碳层上的第二氮氧化硅层。
  14. 根据权利要求1所述的存储器的制作方法，其中，通过所述电容打开孔，去除所有所述牺牲层和所有所述中间孔内的所述牺牲材料，以暴露所述第一极板的外周面的步骤之后，还包括：
    在所述第一极板暴露的表面上形成介质层；
    在所述介质层上形成第二极板，所述第一极板、所述介质层和所述第二极板构成电容器。
  15. 一种存储器，所述存储器通过如权利要求1所述的存储器的制作方法制得。
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