WO2023142521A1 - 具有垂直沟道晶体管的存储器及其制造方法 - Google Patents

具有垂直沟道晶体管的存储器及其制造方法 Download PDF

Info

Publication number
WO2023142521A1
WO2023142521A1 PCT/CN2022/124290 CN2022124290W WO2023142521A1 WO 2023142521 A1 WO2023142521 A1 WO 2023142521A1 CN 2022124290 W CN2022124290 W CN 2022124290W WO 2023142521 A1 WO2023142521 A1 WO 2023142521A1
Authority
WO
WIPO (PCT)
Prior art keywords
vertical channel
memory
semiconductor
channel transistor
bit lines
Prior art date
Application number
PCT/CN2022/124290
Other languages
English (en)
French (fr)
Inventor
金镇湖
Original Assignee
东芯半导体股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 东芯半导体股份有限公司 filed Critical 东芯半导体股份有限公司
Publication of WO2023142521A1 publication Critical patent/WO2023142521A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells

Definitions

  • the present invention relates to a semiconductor element and its manufacturing method, and in particular to a memory with a vertical channel transistor and its manufacturing method.
  • DRAM Dynamic Random Access Memory
  • Each memory cell is mainly composed of a transistor and a capacitor, and each memory cell is electrically connected to each other through a word line (WL, WL) and a bit line (Bit Line, BL).
  • a surround-type gate electrode is formed to surround a semiconductor pillar extending vertically on a semiconductor substrate, and source and drain regions are formed on the upper and lower portions of the semiconductor pillar above and below the gate electrode, respectively, so that the vertical form channels. Therefore, even if the transistor area is reduced, the channel length can be maintained.
  • bit lines are usually formed in the semiconductor substrate below the semiconductor pillars, and the body of the vertical channel transistors floats, which reduces device reliability.
  • the current memory cell structure has reached the limit of cell reliability, the process margin is insufficient, and the reliability of the device is reduced. And continuing to reduce the design rules requires huge costs.
  • the present invention is completed in order to solve the above problems, and its purpose is to provide a memory with a vertical channel transistor and a manufacturing method thereof that avoid floating of the main body of the vertical channel transistor, reduce the size of the device, and improve the reliability of the device.
  • the present invention provides a memory with a vertical channel transistor, which includes:
  • a plurality of semiconductor columns extending perpendicularly to the horizontal surface of the semiconductor substrate, arranged in an array in a first direction and in a second direction intersecting the first direction, each semiconductor column forming a vertical channel the active area of the transistor;
  • a plurality of word lines, the plurality of word lines extending along the second direction are arranged in parallel, above the plurality of bit lines, and surrounding the plurality of bit lines through an intermediate insulating layer.
  • the outer wall of a semiconductor pillar is formed.
  • each word line is formed symmetrically with respect to each semiconductor pillar in the first direction.
  • the intermediate insulating layer is an oxide film.
  • adjacent two of the plurality of bit lines are isolated from each other by trenches for device isolation.
  • adjacent two of the plurality of word lines are isolated from each other by an air gap.
  • a storage element is further included, and the storage element is electrically connected to the storage node buried in the storage node hole above the semiconductor pillar and the word line.
  • the storage element is a capacitor.
  • the cell configuration size of the semiconductor pillar on the semiconductor substrate is 4F 2 , where F is a feature size in the memory.
  • the present invention also provides a method for manufacturing a memory with a vertical channel transistor, which includes the following steps:
  • a plurality of word lines extending in the second direction and arranged in parallel are formed around the outer walls of the plurality of semiconductor pillars with an intermediate insulating layer interposed between the plurality of bit lines. process.
  • the step of forming the bit line includes: depositing a first oxide layer on the semiconductor substrate formed with the plurality of semiconductor pillars, and forming only the first nitride layer on the semiconductor substrate; depositing the second an oxide layer; etching the second oxide layer, the first nitride layer, and the first oxide layer to form bit line cuts and implant impurities; removing only outer walls surrounding lower portions of the plurality of semiconductor pillars the first nitride layer and the first oxide layer; deposit a conductive material and perform etching to form the bit line.
  • the process of forming the word line includes: sequentially depositing a second nitride layer and a third oxide layer on the intermediate insulating layer; etching the third oxide layer and the second nitride layer to Forming vertical channel transistor kerfs; removing only the second nitride layer surrounding outer walls of the plurality of semiconductor pillars; and depositing gate electrode material and etching to form the word lines.
  • the conductive material is TiN/W, TaN/W or WN/W.
  • the gate electrode material is high-K dielectric/TiN/W, high-K dielectric/TaN/W or high-K dielectric/WN/W.
  • the memory with a vertical channel transistor and its manufacturing method of the present invention by forming a plurality of bit lines around the outer wall of the lower part of the semiconductor pillar, a plurality of word lines are surrounded by interposing an intermediate insulating layer above the plurality of bit lines
  • the outer wall of the semiconductor column is formed so that the main body of the vertical trench transistor can directly contact the semiconductor substrate, thereby preventing the main body of the vertical trench transistor from floating, reducing the size of the device, and improving the reliability of the device.
  • the gate stack structure is only formed through deposition and etching processes, no photolithography process is required, and word lines are formed without photomasks, and the structure and process are relatively simple. , so that the memory can be extended below 10nm by using existing equipment and materials.
  • FIG. 1 is a perspective view schematically showing the structure of a vertical channel transistor in a memory according to an embodiment of the present invention.
  • FIG. 2A is a schematic cross-sectional structure diagram showing a memory with a vertical channel transistor according to an embodiment of the present invention.
  • 2B to 2D are plan views respectively showing the arrangement of bit lines, the arrangement of word lines and the arrangement of capacitors in a memory having vertical channel transistors according to an embodiment of the present invention.
  • FIG. 3A and FIG. 3B are schematic cross-sectional structures showing the formation of semiconductor pillars in the method of manufacturing a memory having a vertical channel transistor according to an embodiment of the present invention.
  • FIG. 4A to FIG. 4G are schematic cross-sectional structures showing the formation of bit lines in the manufacturing method of the memory having vertical channel transistors according to the embodiment of the present invention.
  • FIG. 5A and FIG. 5B are schematic cross-sectional structures showing the formation of an intermediate insulating layer in a method of manufacturing a memory having a vertical channel transistor according to an embodiment of the present invention.
  • FIG. 6A to FIG. 6E are schematic cross-sectional structures showing the formation of vertical channel transistors in the method of manufacturing a memory having vertical channel transistors according to an embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view showing an air gap formed in a method of manufacturing a memory having a vertical channel transistor according to an embodiment of the present invention.
  • FIGS. 8A to 8D are schematic cross-sectional structures showing the formation of storage nodes in the manufacturing method of the memory having vertical channel transistors according to the embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional view showing a capacitor formed in a method of manufacturing a memory having a vertical channel transistor according to an embodiment of the present invention.
  • spatially relative terms such as “under”, “under”, “under”, “above”, “upper”, etc., may be used herein to describe the relative relation of one element or feature as shown in the figures. A relationship between elements or properties. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features.
  • Embodiments of the invention are described herein with reference to cross-section and top view illustrations that are schematic illustrations of idealized embodiments of the invention. Thus, embodiments of the invention should not be constructed as to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing processes.
  • An etched region illustrated as a rectangle, for example, will, typically, have rounded or curved features. Accordingly, the areas illustrated in the figures are schematic in nature and are not intended to limit the scope of the invention.
  • a DRAM is used as a memory for description, but the present invention is not limited thereto, and other memories may be used.
  • FIG. 1 is a perspective view schematically showing the structure of a vertical channel transistor in a memory according to an embodiment of the present invention.
  • FIG. 2A is a schematic cross-sectional structure diagram showing a memory with a vertical channel transistor according to an embodiment of the present invention.
  • 2B to 2D are plan views respectively showing the arrangement of bit lines, the arrangement of word lines and the arrangement of capacitors in a memory having vertical channel transistors according to an embodiment of the present invention.
  • the memory 1 with vertical channel transistors includes a plurality of semiconductor pillars 10 , a plurality of bit lines 20 and a plurality of word lines 30 .
  • a plurality of semiconductor columns 10 extend vertically to the horizontal surface of the semiconductor substrate 11, and are arranged in an array in a first direction and a second direction intersecting the first direction, and each semiconductor column 10 constitutes an active region of a vertical channel transistor .
  • one of the cell transistors of the DRAM cell is electrically connected to the bit line 20 through the semiconductor pillar 10 .
  • Fig. 2A is a cross-sectional view along the line XX' in Fig. 2B.
  • the plurality of bit lines 20 are arranged in parallel extending in the Y direction as the first direction, and are formed around outer walls of lower portions of the plurality of semiconductor pillars 10 .
  • adjacent two of the plurality of bit lines 20 are isolated from each other by trenches 201 for device isolation.
  • a plurality of word lines 30 are arranged in parallel extending along the X direction as the second direction, and above the plurality of bit lines 20, there is an intermediate insulating layer 40 between the plurality of bit lines 20. And it is formed around the outer walls of the plurality of semiconductor pillars 10 . In addition, adjacent two of the plurality of word lines 30 are isolated from each other by air gaps 301 . In the DRAM cell disclosed according to the present invention, the word line 30 is formed without the aid of a photomask.
  • each word line 30 is formed symmetrically with respect to each semiconductor pillar in the Y direction.
  • the intermediate insulating layer 40 is, for example, an oxide film.
  • each cell transistor of the DRAM cell is electrically connected to the storage element 50 through a storage node formed to be buried in the storage node hole.
  • the memory element 50 is assumed to be a capacitor.
  • the required layout area is significantly reduced and a single cell of 4F 2 size as shown in FIG. 2D can be manufactured.
  • F is the feature size in memory.
  • the vertical channel transistor as the cell transistor shown in FIG. 1 can be obtained.
  • the main body of the vertical channel transistor can directly contact the semiconductor substrate, thereby avoiding the floating of the main body of the vertical channel transistor, reducing the size of the device, and improving the reliability of the device.
  • the present invention also provides a method for manufacturing the above-mentioned memory device with vertical channel transistors, which includes the following steps: forming a plurality of semiconductor pillars on the semiconductor substrate, and the plurality of semiconductor pillars are vertical to the horizontal surface of the semiconductor substrate.
  • Extending arranged in an array in the first direction and in the second direction crossing the first direction; forming a plurality of bit lines extending in the first direction and arranged in parallel around the outer wall of the lower part of the plurality of semiconductor pillars; and A step of forming a plurality of word lines extending in the second direction and arranged in parallel on the plurality of bit lines and surrounding the outer walls of the plurality of semiconductor pillars with an intermediate insulating layer interposed between the plurality of bit lines.
  • FIG. 3A and FIG. 3B are schematic cross-sectional structures showing the formation of semiconductor pillars in the method of manufacturing a memory having a vertical channel transistor according to an embodiment of the present invention.
  • a silicon pillar is used as a semiconductor pillar for description, but the present invention is not limited thereto.
  • a substrate insulating film 12 is deposited and formed on a semiconductor substrate 11 on which a substrate oxide film is formed.
  • the substrate insulating film 12 may be formed of silicon nitride (SiN) or the like.
  • the silicon pillar array In the formation of the silicon pillar array, as shown in FIG. 3B , separate pillars are formed in the semiconductor substrate 11 on which the substrate insulating film 12 is formed. At this time, a process of forming the separation column may be performed using a photomask, which is well known to those skilled in the art, and thus a detailed description thereof is omitted here. Subsequently, channel impurities are implanted into the pillar surfaces and the horizontal surface of the semiconductor substrate 11 to form transistor channels of the cell transistors.
  • FIG. 4A to FIG. 4G are schematic cross-sectional structures showing the formation of bit lines in the manufacturing method of the memory having vertical channel transistors according to the embodiment of the present invention.
  • a first oxide layer 110 and a first nitride layer 111 are sequentially deposited on the previous structure of FIG. 3B .
  • the first nitride layer 111 can use insulating materials such as SiN. Conventional etching techniques are used so that only the first nitride layer 111 remains on the semiconductor substrate 11 .
  • the second oxide layer 112 is deposited as an insulating layer, for example, a planarized oxide and insulating film can be used using conventional CMP technology.
  • bit line cutout CUT1 is formed in the structure of FIG. 4A described above.
  • a formation process of bit line cutouts may be performed using a photomask, which is well known to those skilled in the art, and thus a detailed description thereof is omitted here.
  • N+ impurities are implanted on the surface of the bit line cutout CUT1 , and the outer wall surrounding the lower part of the semiconductor pillar, that is, the first nitride layer and the first oxide layer at the vertical position are etched away.
  • a conductive material is deposited.
  • the deposited conductive material for example, TiN/W (titanium nitride/tungsten), TaN/W (tantalum nitride/tungsten), or WN/W (tungsten nitride/tungsten) can be used.
  • the deposited conductive material is etched by conventional etching techniques to form bit lines 20 . Such etching techniques are well known in the related art. Therefore, its detailed description is omitted here.
  • etching is performed in the above-mentioned FIG. 4E to form the trench 201 .
  • an etching technique may be used to perform the formation process of the trench 201 . This process is well known to those skilled in the art, so its detailed description is omitted here.
  • P-type ion impurities such as boron (B) ions and boron fluoride (BF 2 ) ions are implanted into the surface of the trench 201 .
  • the oxide attached to the silicon pillars is removed by an etching technique.
  • etching techniques are well known in the related art. A detailed description thereof is therefore omitted here.
  • FIG. 5A and FIG. 5B are schematic cross-sectional structures showing the formation of an intermediate insulating layer in a method of manufacturing a memory having a vertical channel transistor according to an embodiment of the present invention.
  • an intermediate oxide film is deposited as an intermediate insulating layer and a CMP planarization process is performed.
  • a certain amount of the intermediate oxide film is removed to obtain the intermediate insulating layer 40 .
  • the figure on the left is a cross-sectional view along the X direction
  • the figure on the right is a cross-sectional view along the Y direction, and the same applies to subsequent figures.
  • the process of FIG. 5B may be performed using an etching technique. This process is well known to those skilled in the art, so its detailed description is omitted here.
  • FIG. 6A to FIG. 6E are schematic cross-sectional structures showing the formation of vertical channel transistors in the method of manufacturing a memory having vertical channel transistors according to an embodiment of the present invention.
  • a second nitride layer 113 and a third oxide layer 114 are sequentially deposited on the structure of FIG. 5B , and a planarization process is performed.
  • the second nitride layer 113 is, for example, SiN, etc.
  • the third oxide layer 114 is, for example, SiO 2 or the like.
  • a vertical channel transistor cutout CUT2 is formed in the aforementioned FIG. 6A .
  • a process of forming the vertical channel transistor cutout CUT2 may be performed using a photomask. This process is well known to those skilled in the art, so its detailed description is omitted here. Subsequently, using an etching technique, the vertical channel transistor cutout CUT2 is etched. This process is also well known to those skilled in the art, so its detailed description is omitted here.
  • FIG. 6C In the process of forming the vertical channel transistor, as shown in FIG. 6C , only the outer walls surrounding the plurality of semiconductor pillars in FIG. 6B , that is, the second nitride layer 113 in the middle vertical position, are removed. At this time, the process of FIG. 6C can be performed using an etching technique, which is well known to those skilled in the art, and thus its detailed description is omitted here.
  • gate electrode material is deposited.
  • the gate electrode material is, for example, high-K dielectric/TiN/W, high-K dielectric/TaN/W, or high-K dielectric/WN/W (where K is a dielectric constant).
  • the deposited gate electrode material is etched by conventional etching techniques to form word lines 30 . Such etching techniques are well known in the related art. A detailed description thereof is therefore omitted here.
  • the word line 30 is formed without using a photomask.
  • the deposited gate electrode material is removed and becomes the gate electrode by conventional etching techniques.
  • Such an etching technique is well known in the related art, and thus a detailed description thereof is omitted here.
  • FIG. 7 is a schematic cross-sectional view showing an air gap formed in a method of manufacturing a memory having a vertical channel transistor according to an embodiment of the present invention.
  • a capping oxide is formed on the structure shown in FIG. 6E , thereby obtaining an air gap 101 .
  • FIGS. 8A to 8D are schematic cross-sectional structures showing the formation of storage nodes in the manufacturing method of the memory having vertical channel transistors according to the embodiment of the present invention.
  • FIG. 8A In the process of forming the storage node, as shown in FIG. 8A , CMP planarization is performed, and the top oxide layer of the silicon pillar is removed, exposing the storage node. Further, N+ impurities are implanted on the surface of the storage node to form a storage node junction. Subsequently, as shown in FIG. 8B , perform selective epitaxial growth (SEG: Selectivity Epi Growth), deposit cobalt silicide (Co-Silicidation: CoSix) layer or N+ polysilicon layer and perform CMP planarization to form storage nodes.
  • SEG Selectivity Epi Growth
  • Co-Silicidation CoSix
  • an interlayer dielectric (ILD) 115 is deposited and CMP planarization is performed.
  • FIG. 8D storage nodes are formed on the above-mentioned structure in FIG. 8C .
  • a process of forming a storage node may be performed using a photomask, which is well known to those skilled in the art, and thus a detailed description thereof is omitted here.
  • a barrier metal 116 such as TiN, WN, TaN, and W is deposited and CMP planarization is performed.
  • Fig. 9 is a schematic cross-sectional view showing a capacitor formed in a method of manufacturing a memory having a vertical channel transistor according to an embodiment of the present invention.
  • a capacitor 50 is formed on the structure formed in FIG. 8D described above.
  • a process of forming a capacitor may be performed using a photomask, which is well known to those skilled in the art, and thus a detailed description thereof is omitted here.
  • capacitor material may be deposited on the side surfaces of the capacitor.
  • the formation of the capacitor material may sequentially include: depositing a first electrode material on the side surface of the capacitor, the first electrode material includes a conductive material 501A and a dielectric material 501B, and then filling the second electrode material 502, the second The electrode material 502 is a conductive material.
  • the memory having the vertical channel transistor according to the embodiment of the present invention is finally formed.
  • the gate stack structure is formed only through deposition and etching processes, no photolithography process is required, and word lines are formed without a photomask, and the structure and process are relatively simple, thereby
  • the memory can be extended below 10nm by using existing equipment and materials.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

本发明提供具有垂直沟道晶体管的存储器及其制造方法。通过将多条位线围绕半导体柱的下部的外壁形成，将多条字线在多条位线的上方隔着中间绝缘层而围绕半导体柱的外壁形成，使得垂直沟槽晶体管的主体能够直接接触半导体衬底，从而避免垂直沟槽晶体管的主体浮动，且可以缩小器件尺寸，提高器件可靠性。此外，仅通过沉积和蚀刻工艺来形成栅堆叠结构，无需光刻工艺，不借助光掩模而形成字线，结构和工艺较为简单，从而沿用现有设备和材料即可将存储器扩展到10nm以下。

Description

具有垂直沟道晶体管的存储器及其制造方法 技术领域
本发明涉及一种半导体元件及其制造方法，且特别是涉及一种具有垂直沟道晶体管的存储器及其制造方法。
背景技术
近来，存储器的制作技术已成为半导体产业重要的技术之一。动态随机存取存储器(Dynamic Random Access Memory，DRAM)属于一种易失性存储器，其是由多个存储单元构成。每一个存储单元主要是由一个晶体管与一个电容器所构成，且每一个存储单元通过字线(Word Line，WL)与位线(Bit Line，BL)彼此电性连接。
随着半导体产生的不断发展，要求缩减元件尺寸，对40nm以下的存储器的需求已经逐渐增加。然而，使用具有8F 2或6F 2单元结构(其中‘F’表示存储器中的特征尺寸)的常规平面或凹陷栅极晶体管难以实现具有40nm或更小线宽的缩微化存储器件。为此，现有技术中已经提出了具有垂直沟道晶体管的存储器结构。
在垂直沟道晶体管中，形成包围型栅电极以包围在半导体衬底上垂直延伸的半导体柱，并且在栅电极上方和下方的半导体柱的上部和下部分别形成源极和漏极区，从而垂直形成沟道。因此，即使缩小晶体管面积，也可以保持沟道长度。
发明内容
发明所要解决的技术问题
然而，现有的具有垂直沟道晶体管的存储器结构中，通常在半导体柱下方的半导体衬底中形成掩埋式位线，存在垂直沟道晶体管的主体浮动，器件可靠性下降的问题。
此外，当前的存储器单元结构已达到了单元可靠性的极限，工艺余量不足，器件可靠性下降。而继续降低设计规则需要巨大的成本。
本发明是为了解决上述问题而完成的，其目的在于提供一种避免垂直沟槽晶体管的主体浮动，且可以缩小器件尺寸，提高器件可靠性的具有垂直沟道晶体管的存储器及其制造方法。
解决技术问题的技术方案
本发明提供一种具有垂直沟道晶体管的存储器，其包括：
多个半导体柱，该多个半导体柱垂直于半导体衬底的水平表面而延伸，在第一方向上及与所述第一方向交叉的第二方向上排列成阵列，各半导体柱构成垂直沟道晶体管的有源区；
多条位线，该多条位线沿所述第一方向延伸而平行设置，且围绕所述多个半导体柱的下部的外壁形成；及
多条字线，该多条字线沿所述第二方向延伸而平行设置，且在所述多条位线的上方，与所述多条位线之间隔着中间绝缘层而围绕所述多个半导体柱的外壁形成。
优选为，各字线在所述第一方向上相对于各半导体柱形成为对称。
优选为，所述中间绝缘层为氧化膜。
优选为，所述多条位线中的相邻两条之间通过用于器件隔离的沟槽而彼此隔离。
优选为，所述多条字线中的相邻两条之间通过空气间隙而彼此隔离。
优选为，还包括存储元件，所述存储元件在所述半导体柱和所述字线上方与掩埋在存储节点孔中的存储节点电连接。
优选为，所述存储元件为电容器。
优选为，所述半导体柱在所述半导体衬底上的单元配置尺寸为4F 2，其中F为所述存储器中的特征尺寸。
本发明还提供一种具有垂直沟道晶体管的存储器的制造方法，其包括如下工序：
在半导体衬底上形成多个半导体柱的工序，该多个半导体柱垂直于半导体衬底的水平表面而延伸，在第一方向上及与所述第一方向交叉的第二 方向上排列成阵列；
围绕所述多个半导体柱的下部的外壁形成沿所述第一方向延伸而平行设置的多条位线的工序；及
在所述多条位线的上方，与所述多条位线之间隔着中间绝缘层而围绕所述多个半导体柱的外壁形成沿所述第二方向延伸而平行设置的多条字线的工序。
优选为，形成所述位线的工序包括：在形成有所述多个半导体柱的半导体衬底上沉积第一氧化物层，并仅在半导体衬底上形成第一氮化物层；沉积第二氧化物层；蚀刻所述第二氧化物层、所述第一氮化物层和所述第一氧化物层以形成位线切口并注入杂质；仅去除围绕所述多个半导体柱的下部的外壁的所述第一氮化物层和所述第一氧化物层；沉积导电材料并进行蚀刻来形成所述位线。
优选为，形成所述字线的工序包括：在所述中间绝缘层上依次沉积第二氮化物层和第三氧化物层；蚀刻所述第三氧化物层和所述第二氮化物层以形成垂直沟道晶体管切口；仅去除围绕所述多个半导体柱的外壁的所述第二氮化物层；及沉积栅电极材料并进行蚀刻来形成所述字线。
优选为，所述导电材料为TiN/W、TaN/W或WN/W。
优选为，所述栅电极材料为高K介质/TiN/W、高K介质/TaN/W或高K介质/WN/W。
发明效果
根据本发明的具有垂直沟道晶体管的存储器及其制造方法，通过将多条位线围绕半导体柱的下部的外壁形成，将多条字线在多条位线的上方隔着中间绝缘层而围绕半导体柱的外壁形成，使得垂直沟槽晶体管的主体能够直接接触半导体衬底，从而避免垂直沟槽晶体管的主体浮动，且可以缩小器件尺寸，提高器件可靠性。
此外，根据本发明的具有垂直沟道晶体管的存储器及其制造方法，仅通过沉积和蚀刻工艺来形成栅堆叠结构，无需光刻工艺，不借助光掩模而形成字线，结构和工艺较为简单，从而沿用现有设备和材料即可将存储器扩展到10nm以下。
附图说明
图1是示意性表示本发明实施方式的存储器中的垂直沟道晶体管的结构的透视图。
图2A是表示本发明实施方式的具有垂直沟道晶体管的存储器的剖面结构示意图。
图2B至图2D是分别表示本发明实施方式的具有垂直沟道晶体管的存储器中的位线排列配置、字线排列配置和电容器排列配置的俯视图。
图3A和图3B是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方法中形成半导体柱时的剖面结构示意图。
图4A至图4G是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方法中形成位线时的剖面结构示意图。
图5A和图5B是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方法中形成中间绝缘层时的剖面结构示意图。
图6A至图6E是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方法中形成垂直沟道晶体管时的剖面结构示意图。
图7是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方法中形成空气间隙时的剖面结构示意图。
图8A至图8D是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方法中形成存储节点时的剖面结构示意图。
图9是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方法中形成电容器时的剖面结构示意图。
具体实施方式
在下面参照附图更全面地描述本发明，在其中示出本发明的实施例。然而，本发明可以以不同的方式实施，而不应限制于在此阐述的实施例。在附图中可以为了清楚起见放大层和区域的尺寸和相对尺寸。
为了描述的方便，可在此使用空间相对术语，例如“之下”、“下方”、“下”、“上方”、“上”等，来描述如图所示的一个元件或特性相对于另一元件或特性 的关系。应理解，空间相对术语旨在包括除了在图中所示的指向之外的使用或操作的器件不同指向。例如，如果将图中的器件翻转，描述为在其它元件或特性“之下”或“下”的元件将被定向为在其它元件或特性“之上”。
在此参照剖面图和俯视图说明描述本发明的实施例，该剖面图和俯视图的说明是本发明的理想化实施例的原理说明。因此，本发明的实施例不应构建为在此说明的区域的特定形状，而是包括由于例如制造工艺所导致的形状的偏差。例如示为长方形的蚀刻区域将典型地具有圆形或弯曲的特性。因此，在图中说明的区域本质上是原理性的，并且不旨在限制本发明的范围。
除非另外限定，在此使用的术语具有与本发明所属领域的普通技术人员所通常理解相同的含义。术语应理解为具有与相关技术的上下文中的含义一致的含义，并不应以理想化或过度形式化来理解，除非在此明显地这样限定。
以下，参照图1、图2A至图2D来说明本发明实施方式的具有垂直沟道晶体管的存储器的结构。在本实施方式中，以DRAM作为存储器来进行说明，但本发明并不限于此，也可以是其他存储器。
图1是示意性表示本发明实施方式的存储器中的垂直沟道晶体管的结构的透视图。图2A是表示本发明实施方式的具有垂直沟道晶体管的存储器的剖面结构示意图。图2B至图2D是分别表示本发明实施方式的具有垂直沟道晶体管的存储器中的位线排列配置、字线排列配置和电容器排列配置的俯视图。
如图2A至图2D所示，具有垂直沟道晶体管的存储器1包括多个半导体柱10、多条位线20及多条字线30。
多个半导体柱10垂直于半导体衬底11的水平表面而延伸，在第一方向上及与第一方向交叉的第二方向上排列成阵列，各半导体柱10构成垂直沟道晶体管的有源区。此时，DRAM单元的单元晶体管之一通过半导体柱10电连接到位线20。
本实施方式中，如图2B所示，设Y方向为第一方向，设X方向为第二方向，X方向与Y方向正交，但本发明并不限于此。
图2A是沿图2B中的X-X’线方向的剖视图。如图2A和图2B所示，多条位线20沿作为第一方向的Y方向延伸而平行设置，且围绕多个半导体柱10的下部的外壁形成。此外，多条位线20中的相邻两条之间通过用于器件隔离的沟槽201而彼此隔离。
此外，参照图2A和图2C，多条字线30沿作为第二方向的X方向延伸而平行设置，且在多条位线20的上方，与多条位线20之间隔着中间绝缘层40而围绕多个半导体柱10的外壁形成。此外，多条字线30中的相邻两条之间通过空气间隙301而彼此隔离。在根据本发明公开的DRAM单元中，字线30不借助光掩模而形成。
此外，如图2C所示，优选为各字线30在Y方向上相对于各半导体柱形成为对称。中间绝缘层40例如为氧化膜。
另外，如图2A和图2D所示，在半导体柱10和字线30的上方，DRAM单元的各个单元晶体管的另一个结通过形成为掩埋在存储节点孔中的存储节点电连接到存储元件50。在本实施方式中，设存储元件50为电容器。
根据本实施方式的存储器，所需的布局面积显著减小并且可以制造如图2D所示的4F 2尺寸的单个单元。其中，F为存储器中的特征尺寸。
此外，根据图2A至图2D所示的存储器的结构，可得到图1所示的作为单元晶体管的垂直沟道晶体管。该垂直沟道晶体管的主体能够直接接触半导体衬底，从而避免垂直沟槽晶体管的主体浮动，且可以缩小器件尺寸，提高器件可靠性。
此外，本发明还提供上述具有垂直沟道晶体管的存储器的制造方法，其包括如下工序：在半导体衬底上形成多个半导体柱的工序，该多个半导体柱垂直于半导体衬底的水平表面而延伸，在第一方向上及与第一方向交叉的第二方向上排列成阵列；围绕多个半导体柱的下部的外壁形成沿第一方向延伸而平行设置的多条位线的工序；及在多条位线的上方，与多条位线之间隔着中间绝缘层而围绕多个半导体柱的外壁形成沿第二方向延伸而平行设置的多条字线的工序。
接下来，参照图3至图9，具体说明上述制造方法。
<半导体柱的形成>
图3A和图3B是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方法中形成半导体柱时的剖面结构示意图。在本实施方式中，以硅柱作为半导体柱来进行说明，但本发明并不限于此。
如图3A所示，在其上形成有衬底氧化膜的半导体衬底11上沉积并形成衬底绝缘膜12。此时，衬底绝缘膜12可以由氮化硅(SiN)等形成。
在硅柱阵列的形成过程中，如图3B所示，在其上形成有衬底绝缘膜12的半导体衬底11中形成分离柱。此时，可以使用光掩模来执行形成分离柱的工艺，该工艺为本领域技术人员所熟知，因此其详细描述在此省略。随后，将沟道杂质注入到柱体表面和半导体衬底11的水平表面中以形成单元晶体管的晶体管沟道。
<位线的形成>
图4A至图4G是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方法中形成位线时的剖面结构示意图。
如图4A所示，在之前的图3B的结构上依次沉积第一氧化物层110和第一氮化物层111。该第一氮化物层111可使用SiN等绝缘材料。使用常规的蚀刻技术，使得仅在半导体衬底11上保留该第一氮化物层111。然后，沉积第二氧化物层112以作为绝缘层，例如可使用传统的CMP技术平坦化后的氧化物和绝缘膜等。
在位线的形成过程中，如图4B所示，在上述的图4A的结构中形成位线切口CUT1。此时，可以使用光掩模执行位线切口的形成工艺，该工艺为本领域技术人员所熟知，因此其详细描述在此省略。随后，如图4C所示，在位线切口CUT1表面注入N+杂质，并蚀刻掉围绕半导体柱的下部的外壁即垂直位置处的第一氮化物层和第一氧化物层。
接着，如图4D所示，沉积导电材料。作为沉积的导电材料，例如可利用TiN/W(氮化钛/钨)、TaN/W(氮化钽/钨)或WN/W(氮化钨/钨)等。然后，如图4E所示，通过常规的蚀刻技术对沉积的导电材料进行蚀刻以形成位线20。这种蚀刻技术在相关领域中是众所周知的。因此，其详细描述在此省略。
在形成位线与位线之间的隔离结构时，如图4F所示，在上述的图4E中 进行刻蚀以形成沟槽201。此时可以采用刻蚀技术来执行沟槽201的形成工艺。该工艺为本领域技术人员所熟知，因此其详细描述在此省略。
随后，如图4F所示，将硼(B)离子、氟化硼(BF2)离子等P型离子杂质注入到沟槽201的表面。
然后，如图4G所示，通过蚀刻技术去除附着在硅柱上的氧化物。这种蚀刻技术在相关领域中是众所周知的。因此其详细描述在此省略。
<中间绝缘层的形成>
图5A和图5B是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方法中形成中间绝缘层时的剖面结构示意图。
如图5A所示，沉积作为中间绝缘层的中间氧化膜并执行CMP平坦化工艺。此外，如图5B所示，去除一定量的中间氧化膜，得到中间绝缘层40。图5B中，左侧的图为沿X方向的剖视图，右侧的图为沿Y方向的剖视图，之后的图也是同样的情况。此时，可以使用蚀刻技术来执行图5B的工艺。该工艺为本领域技术人员所熟知，因此其详细描述在此省略。
<垂直沟道晶体管的形成>
图6A至图6E是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方法中形成垂直沟道晶体管时的剖面结构示意图。
在形成垂直沟道晶体管(VCT)的过程中，如图6A所示，在图5B的结构上依次沉积第二氮化物层113和第三氧化物层114，并执行平坦化工艺。第二氮化物层113例如SiN等，第三氧化物层114例如为SiO 2等。
进一步地，如图6B所示，在上述的图6A中形成了垂直沟道晶体管切口CUT2。此时，可以使用光掩模来执行形成垂直沟道晶体管切口CUT2的工艺。该工艺为本领域技术人员所熟知，因此其详细描述在此省略。随后，使用蚀刻技术，对垂直沟道晶体管切口CUT2进行蚀刻。该工艺也是本领域技术人员所熟知的，因此其详细描述在此省略。
在形成垂直沟道晶体管的过程中，如图6C所示，只去除了上述图6B中的围绕多个半导体柱的外壁即中间垂直位置的第二氮化物层113。此时，可以使用蚀刻技术进行图6C的工艺，该工艺为本领域技术人员所熟知，因此其详细描述在此省略。
接着，如图6D所示，沉积栅电极材料。该栅电极材料例如高K介质/TiN/W、高K介质/TaN/W或高K介质/WN/W等(其中，K为介电常数)。进一步地，在图6D中，通过常规的蚀刻技术对沉积的栅电极材料进行蚀刻以形成字线30。这种蚀刻技术在相关领域中是众所周知的。因此其详细描述在此省略。由此，字线30不借助光掩模而形成。
在栅电极的形成过程中，如图6E所示，沉积的栅电极材料被去除，并通过常规的蚀刻技术成为栅电极。这种蚀刻技术在相关领域中是众所周知的，因此其详细描述在此省略。
<空气间隙的形成>
图7是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方法中形成空气间隙时的剖面结构示意图。
如图7所示，在图6E所示的结构上形成遮盖氧化物，由此获得空气间隙101。
<存储节点的形成>
图8A至图8D是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方法中形成存储节点时的剖面结构示意图。
在形成存储节点的过程中，如图8A所示，执行CMP平坦化，硅柱的顶部氧化层被去除，暴露出存储节点。进一步地，在存储节点表面注入N+杂质，以形成存储节点结。随后，如图8B所示，进行选择性外延生长(SEG：Selectivity Epi Growth)，沉积硅化钴(Co-Silicidation：CoSix)层或N+多晶硅层并执行CMP平坦化，以形成存储节点。
在形成存储节点的过程中，如图8C所示，沉积层间电介质(ILD)115并执行CMP平坦化。
进一步地，如图8D所示，在上述图8C的结构上形成存储节点。此时，可以使用光掩模进行形成存储节点的工艺，该工艺为本领域技术人员所熟知，因此其详细描述在此省略。随后，如图8D所示，沉积诸如TiN、WN、TaN和W等阻挡层金属116并执行CMP平坦化。
<电容器的形成>
图9是表示本发明实施方式的具有垂直沟道晶体管的存储器的制造方 法中形成电容器时的剖面结构示意图。
如图9所示，在上述图8D所形成的结构上形成电容器50。此时，可以使用光掩模进行形成电容器的工艺，该工艺为本领域技术人员所熟知，因此其详细描述在此省略。
此外，电容器材料可以沉积在电容器的侧表面上。在这种情况下，电容器材料的形成可以依次包括：在电容器的侧表面沉积第一电极材料，该第一电极材料包括导电材料501A和介电材料501B，然后填充第二电极材料502，第二电极材料502为导电材料。
由此，最终形成本发明实施方式的具有垂直沟道晶体管的存储器。
根据本实施方式的具有垂直沟道晶体管的存储器的制造方法，仅通过沉积和蚀刻工艺来形成栅堆叠结构，无需光刻工艺，不借助光掩模而形成字线，结构和工艺较为简单，从而沿用现有设备和材料即可将存储器扩展到10nm以下。
本发明进行了详细的说明，但上述实施方式仅是所有实施方式中的示例，本发明并不局限于此。本发明可以在该发明的范围内对各实施方式进行自由组合，或对各实施方式的任意构成要素进行变形，或省略各实施方式的任意的构成要素。

Claims (13)

  1. 一种具有垂直沟道晶体管的存储器，其特征在于，包括：
    多个半导体柱，该多个半导体柱垂直于半导体衬底的水平表面而延伸，在第一方向上及与所述第一方向交叉的第二方向上排列成阵列，各半导体柱构成垂直沟道晶体管的有源区；
    多条位线，该多条位线沿所述第一方向延伸而平行设置，且围绕所述多个半导体柱的下部的外壁形成；及
    多条字线，该多条字线沿所述第二方向延伸而平行设置，且在所述多条位线的上方，与所述多条位线之间隔着中间绝缘层而围绕所述多个半导体柱的外壁形成。
  2. 如权利要求1所述的具有垂直沟道晶体管的存储器，其特征在于，
    各字线在所述第一方向上相对于各半导体柱形成为对称。
  3. 如权利要求1所述的具有垂直沟道晶体管的存储器，其特征在于，
    所述中间绝缘层为氧化膜。
  4. 如权利要求1所述的具有垂直沟道晶体管的存储器，其特征在于，
    所述多条位线中的相邻两条之间通过用于器件隔离的沟槽而彼此隔离。
  5. 如权利要求1所述的具有垂直沟道晶体管的存储器，其特征在于，
    所述多条字线中的相邻两条之间通过空气间隙而彼此隔离。
  6. 如权利要求1所述的具有垂直沟道晶体管的存储器，其特征在于，
    还包括存储元件，所述存储元件在所述半导体柱和所述字线上方与掩埋在存储节点孔中的存储节点电连接。
  7. 如权利要求6所述的具有垂直沟道晶体管的存储器，其特征在于，
    所述存储元件为电容器。
  8. 如权利要求1至7中任一项所述的具有垂直沟道晶体管的存储器，其特征在于，
    所述半导体柱在所述半导体衬底上的单元配置尺寸为4F 2，其中F为所述存储器中的特征尺寸。
  9. 一种具有垂直沟道晶体管的存储器的制造方法，其特征在于，包括如下工序：
    在半导体衬底上形成多个半导体柱的工序，该多个半导体柱垂直于半导体衬底的水平表面而延伸，在第一方向上及与所述第一方向交叉的第二方向上排列成阵列；
    围绕所述多个半导体柱的下部的外壁形成沿所述第一方向延伸而平行设置的多条位线的工序；及
    在所述多条位线的上方，与所述多条位线之间隔着中间绝缘层而围绕所述多个半导体柱的外壁形成沿所述第二方向延伸而平行设置的多条字线的工序。
  10. 如权利要求9所述的具有垂直沟道晶体管的存储器的制造方法，其特征在于，
    形成所述位线的工序包括：
    在形成有所述多个半导体柱的半导体衬底上沉积第一氧化物层，并仅在半导体衬底上形成第一氮化物层；
    沉积第二氧化物层；
    蚀刻所述第二氧化物层、所述第一氮化物层和所述第一氧化物层以形成位线切口并注入杂质；
    仅去除围绕所述多个半导体柱的下部的外壁的所述第一氮化物层和所述第一氧化物层；
    沉积导电材料并进行蚀刻来形成所述位线。
  11. 如权利要求9或10所述的具有垂直沟道晶体管的存储器的制造方法，其特征在于，
    形成所述字线的工序包括：
    在所述中间绝缘层上依次沉积第二氮化物层和第三氧化物层；
    蚀刻所述第三氧化物层和所述第二氮化物层以形成垂直沟道晶体管切口；
    仅去除围绕所述多个半导体柱的外壁的所述第二氮化物层；及
    沉积栅电极材料并进行蚀刻来形成所述字线。
  12. 如权利要求10所述的具有垂直沟道晶体管的存储器的制造方法，其特征在于，
    所述导电材料为TiN/W、TaN/W或WN/W。
  13. 如权利要求11所述的具有垂直沟道晶体管的存储器的制造方法，其特征在于，
    所述栅电极材料为高K介质/TiN/W、高K介质/TaN/W或高K介质/WN/W。
PCT/CN2022/124290 2022-01-30 2022-10-10 具有垂直沟道晶体管的存储器及其制造方法 WO2023142521A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210113278.4 2022-01-30
CN202210113278.4A CN114446965A (zh) 2022-01-30 2022-01-30 具有垂直沟道晶体管的存储器及其制造方法

Publications (1)

Publication Number Publication Date
WO2023142521A1 true WO2023142521A1 (zh) 2023-08-03

Family

ID=81371002

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/124290 WO2023142521A1 (zh) 2022-01-30 2022-10-10 具有垂直沟道晶体管的存储器及其制造方法

Country Status (2)

Country Link
CN (1) CN114446965A (zh)
WO (1) WO2023142521A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114446965A (zh) * 2022-01-30 2022-05-06 东芯半导体股份有限公司 具有垂直沟道晶体管的存储器及其制造方法
CN117765991A (zh) * 2022-09-26 2024-03-26 华为技术有限公司 一种环形反相器、锁存器、存储电路、存储器及电子设备
CN117832252A (zh) * 2022-09-27 2024-04-05 长鑫存储技术有限公司 半导体结构及其读写控制方法和制造方法
CN118742014A (zh) * 2023-03-28 2024-10-01 北京超弦存储器研究院 半导体器件及其制造方法、电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070087499A1 (en) * 2005-10-14 2007-04-19 Samsung Electronics Co., Ltd. Semiconductor memory device with vertical channel transistor and method of fabricating the same
US20120119286A1 (en) * 2010-11-11 2012-05-17 Samsung Electronics Co., Ltd. Semiconductor devices having vertical channel transistors and methods for fabricating the same
WO2013091374A1 (en) * 2011-12-23 2013-06-27 Tsinghua University Memory array structure and method for forming the same
US20140024214A1 (en) * 2012-07-17 2014-01-23 SK Hynix Inc. Method for fabricating semiconductor device
US20140369126A1 (en) * 2013-06-17 2014-12-18 Seoul National University R&Db Foundation Simplified nonvolatile memory cell string and nand flash memory array using the same
CN114446965A (zh) * 2022-01-30 2022-05-06 东芯半导体股份有限公司 具有垂直沟道晶体管的存储器及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070087499A1 (en) * 2005-10-14 2007-04-19 Samsung Electronics Co., Ltd. Semiconductor memory device with vertical channel transistor and method of fabricating the same
US20120119286A1 (en) * 2010-11-11 2012-05-17 Samsung Electronics Co., Ltd. Semiconductor devices having vertical channel transistors and methods for fabricating the same
WO2013091374A1 (en) * 2011-12-23 2013-06-27 Tsinghua University Memory array structure and method for forming the same
US20140024214A1 (en) * 2012-07-17 2014-01-23 SK Hynix Inc. Method for fabricating semiconductor device
US20140369126A1 (en) * 2013-06-17 2014-12-18 Seoul National University R&Db Foundation Simplified nonvolatile memory cell string and nand flash memory array using the same
CN114446965A (zh) * 2022-01-30 2022-05-06 东芯半导体股份有限公司 具有垂直沟道晶体管的存储器及其制造方法

Also Published As

Publication number Publication date
CN114446965A (zh) 2022-05-06

Similar Documents

Publication Publication Date Title
WO2023142521A1 (zh) 具有垂直沟道晶体管的存储器及其制造方法
US8058683B2 (en) Access device having vertical channel and related semiconductor device and a method of fabricating the access device
US7569878B2 (en) Fabricating a memory cell array
TWI413214B (zh) 埋入式位元線結構、具其之場效電晶體結構及其製法
US7449382B2 (en) Memory device and fabrication method thereof
US20070284623A1 (en) Semiconductor device having vertical channel transistor
US9196618B2 (en) Semiconductor device and method of manufacturing the same
US9209192B2 (en) Semiconductor device and method of fabricating the same
KR20030019639A (ko) 반도체 메모리 셀 배열 및 그 제조 방법
KR20070079060A (ko) 트랜지스터와 이의 제조방법 및 메모리 셀
US11502087B2 (en) Semiconductor structure and method for fabricating the same
KR20220122293A (ko) 반도체 장치 및 그 제조 방법
JP5430981B2 (ja) 半導体記憶装置及びその製造方法
US7312114B2 (en) Manufacturing method for a trench capacitor having an isolation collar electrically connected with a substrate on a single side via a buried contact for use in a semiconductor memory cell
US7939411B2 (en) Method for fabricating semiconductor device with vertical gate
US10242726B1 (en) Memory arrays, and methods of forming memory arrays
KR100985883B1 (ko) 4ｆ2 트랜지스터를 갖는 반도체 소자 및 그 제조방법
TWI833319B (zh) 半導體裝置
US7998816B2 (en) Method for fabricating semiconductor device having vertical gate
US9231066B2 (en) Semiconductor device having vertical channel
WO2023173504A1 (zh) 半导体结构及其制造方法、存储器及其制造方法
US6908811B2 (en) Ram
US6599797B1 (en) SOI DRAM without floating body effect
US20240130116A1 (en) Semiconductor device
US20240023325A1 (en) Semiconductor device

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE