WO2023206685A1 - 半导体结构及半导体结构的制作方法 - Google Patents

半导体结构及半导体结构的制作方法 Download PDF

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WO2023206685A1
WO2023206685A1 PCT/CN2022/095309 CN2022095309W WO2023206685A1 WO 2023206685 A1 WO2023206685 A1 WO 2023206685A1 CN 2022095309 W CN2022095309 W CN 2022095309W WO 2023206685 A1 WO2023206685 A1 WO 2023206685A1
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contact
contact structure
substrate
layer
semiconductor structure
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PCT/CN2022/095309
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English (en)
French (fr)
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刘翔
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长鑫存储技术有限公司
长鑫集电(北京)存储技术有限公司
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Publication of WO2023206685A1 publication Critical patent/WO2023206685A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to a semiconductor structure and a method of manufacturing the semiconductor structure.
  • the present disclosure provides a semiconductor structure and a manufacturing method of the semiconductor structure.
  • a first aspect of the present disclosure provides a semiconductor structure, the semiconductor structure comprising:
  • a substrate having a plurality of active regions spaced apart along a first direction
  • the contact structure includes a first contact structure and a second contact structure, one end of the first contact structure is disposed close to the substrate and is connected to the active area, and the second contact structure is connected to the The other end of the first contact structure is connected, wherein the projection of the second contact structure on the substrate is located within the projection of the first contact structure on the substrate.
  • the width of the second contact structure is 1-6 nm smaller than the width of the first contact structure.
  • the semiconductor structure further includes a plurality of word line structures spaced apart along the second direction, wherein the word line structures are disposed in the active region.
  • the semiconductor structure further includes a bit line structure connected to the active region through a bit line contact structure.
  • an isolation spacer is provided on both sides of the bit line structure.
  • the semiconductor structure further includes a connection pad disposed on the second contact structure, the connection pad including a tungsten layer.
  • a second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, including:
  • first contact hole on the first dielectric layer, the first contact hole extending into the substrate toward one end of the substrate and exposing at least part of the active area
  • first contact structure in the first contact hole, having a first preset height between a top surface of the first contact structure and a top surface of the substrate;
  • a second contact structure is formed within the second contact hole, wherein the first contact structure and the second contact structure form a contact structure.
  • the pore diameter of the second contact hole is 1-6 nm smaller than the pore diameter of the first contact hole.
  • the method of manufacturing the semiconductor structure before forming the first dielectric layer on the substrate, the method of manufacturing the semiconductor structure further includes:
  • first barrier layer on the sidewalls of the gate metal layer and the gate oxide layer, remove excess first barrier layer, and form a gate structure
  • a doping process is performed on the active regions on both sides of the gate structure to form source regions and drain regions on both sides of the gate structure.
  • the method of manufacturing the semiconductor structure before forming the first dielectric layer on the substrate, the method of manufacturing the semiconductor structure further includes:
  • a bit line structure is formed on the substrate.
  • forming a bit line structure on the substrate includes:
  • An isolation side wall is formed on the side wall of the first groove, and a second groove is formed between adjacent isolation side walls in the first groove;
  • the bit line structure is formed within the second groove.
  • forming a bit line structure in the second groove includes:
  • a transition layer, a conductive layer and an insulating layer that are stacked in sequence are formed in the second groove, wherein the transition layer is positioned close to the active area.
  • the method of manufacturing the semiconductor structure before forming a bit line structure in the second groove, the method of manufacturing the semiconductor structure further includes:
  • a bit line contact structure is formed in the second groove, and a top surface of the bit line contact structure is lower than a top surface of the second groove.
  • the method of manufacturing the semiconductor structure before forming a bit line contact structure in the second groove, the method of manufacturing the semiconductor structure further includes:
  • a word line structure is formed within the substrate.
  • forming a second contact hole on the first contact structure includes:
  • the initial dielectric layer located on the top surface of the first contact structure is removed to expose the top surface of the first contact structure.
  • the first contact structure and the adjacent isolation sidewall form the third Two contact holes, wherein the projection of the second contact hole on the substrate is located within the projection of the first contact structure on the substrate, and the aperture of the second contact hole is smaller than the first contact structure aperture.
  • the method of manufacturing the semiconductor structure further includes:
  • connection pad is formed on the second contact structure, wherein the connection pad includes a tungsten layer.
  • the cross-sectional area of the second contact structure is smaller than that of the second contact structure.
  • the cross-sectional area of a contact structure can effectively reduce the influence of parasitic capacitance, improve the overlap problem between the contact structure and the active area caused by adjusting the size of the contact structure, and the trade-off between the parasitic capacitance of the contact structure and the bit line, and thus Improving the performance and yield of semiconductor structures.
  • FIG. 1 is a schematic diagram of a semiconductor structure illustrating an exemplary embodiment.
  • FIG. 2 is a schematic diagram of a semiconductor structure according to an exemplary embodiment.
  • FIG. 3 is a flowchart of a method of fabricating a semiconductor structure according to an exemplary embodiment.
  • FIG. 4 is a schematic diagram of forming a first dielectric layer in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 5 is a schematic diagram of forming a first contact hole in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 6 is a schematic diagram of forming a first contact structure in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 7 is a schematic diagram of forming an initial dielectric layer in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 8 is a schematic diagram of forming a second dielectric layer and a second contact hole in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 9 is a schematic diagram of forming a second contact structure in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 10 is a schematic diagram of a semiconductor structure of a planar gate structure in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 11 is a schematic diagram of forming a contact structure and contact pads in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • Substrate 1. Substrate; 2. First active area;
  • bit line structure 60. Bit line structure; 70. Bit line contact structure;
  • First contact structure 220.
  • Second contact structure
  • Transition layer 610.
  • Transition layer 620.
  • Conductive layer 620.
  • Insulating layer 631. First insulating layer;
  • First isolation layer 820. Second isolation layer;
  • Gate metal layer 930. First barrier layer.
  • the characteristic size of semiconductor structures is also shrinking, and the process window corresponding to the production of semiconductor structures is also becoming smaller, which in turn makes the semiconductor structure smaller.
  • the spacing between adjacent conductive devices (such as bit lines) in the structure is also constantly shrinking, resulting in an increasing parasitic capacitance value between adjacent conductive devices.
  • the characteristic size of semiconductor structures continues to shrink, the process difficulty of subsequent semiconductor structures increases and the process complexity increases.
  • a plurality of spaced first active regions 2 are generally provided in a substrate 1 , that is, a plurality of transistor structures are formed.
  • the word line 3 in the substrate 1 is connected to the gate structures of a plurality of transistors in the first active area 2, the bit line 4 on the substrate 1 is connected to the sources or drains of the plurality of transistors, and the word line 3
  • the extension mode and the extension direction of the bit line 4 may be arranged perpendicular to each other, or may be arranged to intersect along a predetermined angle.
  • a capacitive contact structure 5 is provided between adjacent bit lines.
  • the capacitive contact structure 5 partially overlaps the first active area 2 and is connected to the capacitive contact structure 5 .
  • the capacitive contact structure 5 is a rectangular window formed by self-aligned double patterning (SADP).
  • the process window of the semiconductor structure shrinks, when using the SADP process, small process errors will cause large overlaps between the capacitive contact structure 5 and the first active region 2 in the semiconductor structure.
  • the error causes the overlap of the capacitor contact structure 5 and the first active area 2 to have the following problems.
  • the overlapping area becomes smaller, which will make the conductivity of the capacitor contact structure worse and affect the transistor's reading and writing speed of data in the capacitor; when overlapping The larger area can short circuit the capacitive contact structure with adjacent bit lines, thereby reducing the performance and yield of the semiconductor structure.
  • FIG. 2 shows a schematic diagram of a semiconductor structure provided according to an exemplary embodiment.
  • the semiconductor structure will be introduced below with reference to FIG. 2 .
  • the semiconductor structure is a storage transistor in the core area of a dynamic random access memory (DRAM) as an example for introduction below.
  • DRAM dynamic random access memory
  • this embodiment is not limited to this.
  • the semiconductor structure in this embodiment Other structures are also possible.
  • a semiconductor structure provided by an exemplary embodiment of the present disclosure includes a substrate 10 and a contact structure 20 .
  • the substrate 10 serves as a supporting component of the dynamic random access memory, and is used to support other components provided thereon.
  • the substrate 10 can be made of a semiconductor material, and the semiconductor material can be silicon, germanium, silicon germanium compounds, and silicon carbon. One or more compounds.
  • the substrate 10 is made of silicon material. The reason why this embodiment uses silicon material as the base 10 is to facilitate those skilled in the art to understand the subsequent formation method, and does not constitute a limitation. In the actual application process, the silicon material can be used as needed. Choose the appropriate substrate material.
  • first direction X is the X direction in Figure 1. It should be noted that the first direction X may be along the extending direction of the word line 3 in FIG. 1 .
  • an isolation structure 40 is provided between adjacent active areas 30 .
  • the isolation structure 40 can be made of insulating materials, such as silicon dioxide, silicon oxynitride, etc., and the multiple active regions 30 can be insulatingly separated by the isolation structure 40 .
  • the contact structure 20 includes a first contact structure 210 and a second contact structure 220 .
  • the bottom end of the first contact structure 210 faces the substrate 10 and is disposed close to the substrate 10 , and the bottom end of the first contact structure 210 is connected to one of the plurality of active regions 30 .
  • the material of the first contact structure 210 may include, but is not limited to, polysilicon, titanium nitride, or tungsten.
  • the bottom end of the second contact structure 220 is connected to the top end of the first contact structure 210 .
  • the material of the second contact structure 220 includes polysilicon, titanium nitride, tungsten, etc.
  • the materials of the second contact structure 220 and the first contact structure 210 may be the same or different. It should be noted that in this embodiment, the contact structure 20 may be a capacitive contact structure.
  • the projection of the second contact structure 220 on the substrate 10 is located within the projection of the first contact structure 210 on the substrate 10 . That is, taking a plane perpendicular to the top surface of the substrate 10 as a cross section, the cross-sectional area of the first contact structure 210 is larger than the cross-sectional area of the second contact structure 220 . Therefore, in this embodiment, the contact structure 20 is designed as a two-section structure arranged in the up and down direction, and the cross-sectional size of the first contact structure 210 connected to the active area 30 is increased, thereby facilitating the connection between the contact structure 20 and the active area 30 . The alignment between the active areas 30 reduces the overlap error between the contact structure 20 and the active area 30 .
  • the contact area between the contact structure 20 and the active area 30 is also increased, which can reduce the contact resistance between the contact structure 20 and the active area 30 and improve the conductive performance of the semiconductor structure.
  • the width of the second contact structure 220 is 1-6 nm smaller than the width of the first contact structure 210 .
  • the width of the second contact structure 220 can be understood as the size along the first direction, or if the shape of the second contact structure 220 is irregular, the width of the second contact structure 220 can be understood as the size of the second contact structure. The average value of the dimensions of multiple positions of 220 in the first direction.
  • the width of the first contact structure 210 and the width of the second contact structure 220 are understood to be the same, and will not be described again in this embodiment.
  • the diameter of the second contact structure 220 may be the same as the size of the contact structure in the existing process, but in this embodiment, the diameter of the first contact structure 210 is correspondingly increased, thereby facilitating contact.
  • the structure 20 and the active area 30 are aligned, and the overlay error between the contact structure 20 and the active area 30 is reduced.
  • the first contact structure 210 that increases the size range will not affect other structures in the semiconductor structure, such as bit line structures, isolation spacers, etc.
  • the widths of the first contact structure 210 and the second contact structure 220 are basically the same. At this time, it cannot solve the problem that the overlapping area is difficult to align. Accurate question.
  • the width of the isolation sidewalls 80 located on both sides of the first contact structure 210 will be reduced, thereby reducing the isolation effect of the isolation sidewalls 80 , furthermore, it is easy to cause the bit line structure 60 and the first contact structure 210 to be electrically connected, affecting the conductive performance of the semiconductor structure and reducing the yield of the semiconductor structure.
  • the active area 30 has a plurality of word line structures (not shown in the figure) spaced along the second direction Y. It should be noted that the second direction Y may be along the bit lines in FIG. 1 The direction in which line 4 extends.
  • the word line structure is disposed in the active area 30. It should be noted that the word line structure can define the gate structure in the semiconductor structure.
  • the semiconductor structure includes a bit line structure 60 .
  • a bit line contact structure 70 is provided at one end of the bit line structure 60 close to the active area 30.
  • the material of the bit line contact structure 70 may include but is not limited to Conductive materials such as polysilicon.
  • the bit line structure 60 is connected to the active area 30 through the bit line contact structure 70 .
  • the bit line structure 60 includes a transition layer 610, a conductive layer 620 and an insulating layer 630 that are sequentially stacked on the bit line contact structure 70.
  • the material of transition layer 610 may include, but is not limited to, titanium silicon nitride.
  • the material of conductive layer 620 may include, but is not limited to, tungsten.
  • the material of the insulating layer 630 may include, but is not limited to, silicon nitride, silicon dioxide, borophosphosilicate glass, and the like.
  • the width of the second contact structure 220 is 1-6 nm smaller than the width of the first contact structure 210 , the first contact structure 210 is disposed away from the bit line structure 60 . Therefore, in this embodiment, the distance between the first contact structure 210 and the bit line structure 60 formed in the substrate 10 is increased, thereby reducing the problem of aligning the bit lines due to the enlarged cross-sectional size of the first contact structure 210 Effect of parasitic capacitance of structure 60.
  • the cross-sectional size of the second contact structure 220 located in the upper section is smaller than the cross-sectional size of the first contact structure 210.
  • This design can reduce the size of the second contact structure 220 and the subsequent bit lines formed next to the second contact structure 220. Capacitance between structures.
  • the cross-sectional area of the second contact structure 220 is smaller than the cross-sectional area of the first contact structure 210,
  • an isolation spacer 80 is provided on both sides of each bit line structure 60 .
  • the isolation sidewall 80 includes a first isolation layer 810, a second isolation layer 820, and a third isolation layer 830 connected in sequence.
  • the first isolation layer 810 is in contact with the bit line structure 60 .
  • the materials of the first isolation layer 810, the second isolation layer 820 and the third isolation layer 830 may be the same or different.
  • the materials of the first isolation layer 810 , the second isolation layer 820 and the third isolation layer 830 may include isolation materials such as silicon dioxide, borophosphosilicate glass, etc., to protect the bit line structure 60 and the subsequently formed Contact structure 20 and other structures are isolated.
  • the first isolation layer 810 , the second isolation layer 820 and the third isolation layer 830 may include silicon nitride or silicon oxynitride to improve the isolation performance of the isolation sidewall 80 and facilitate subsequent structures. Selective etching is performed.
  • the first isolation layer 810 , the second isolation layer 820 and the third isolation layer 830 may include a low dielectric constant material or an air gap to reduce the contact structure 20 and the bit gap. Parasitic capacitance of line structure 60.
  • the isolation spacers 80 can effectively control the topography of the side walls on both sides of the bit line structure 60, thereby improving the performance and quality of the semiconductor structure. Rate.
  • the gate structure formed on the active region 30 is a buried gate structure, that is, a recessed channel transistor structure can be fabricated later.
  • the active region also includes a source-drain region and a contact structure. It can be disposed in one of the source and drain regions to be connected to the capacitor structure as a capacitor contact structure.
  • the gate structure formed on the active area can also be a planar gate structure. Subsequently, a planar transistor structure can be produced. The formed transistor can be located in the peripheral area of the DRAM chip.
  • the active area also includes a source and a drain.
  • the contact structure can be disposed on at least one of the source-drain region and the gate structure as an electrode lead-out structure to apply working voltage and draw out working current.
  • the contact structure adopts a two-stage structure.
  • the contact structure may include a first contact structure and a second contact structure, wherein the first contact structure has a larger cross-sectional size, which can reduce the contact resistance of the contact structure connected to the source and drain regions and increase the current of the semiconductor structure, and The cross-sectional size of the second contact structure is smaller, which can effectively reduce the parasitic capacitance between the gate structure and the source and drain regions, and reduce the delay effect of the transistor.
  • the semiconductor structure further includes a connection pad 130 disposed on the second contact structure 220 .
  • the material of the connection pad 130 may include tungsten.
  • the connection pads 130 are provided to facilitate the electrical connection between the contact structure 20 and a subsequently formed semiconductor structure, while ensuring the conductivity between the contact structure 20 and a subsequently formed semiconductor structure such as a capacitor structure.
  • a first metal layer 110 and a second metal layer 120 may also be provided between the connection pad 130 and the second contact structure 220 .
  • the first metal layer 110 and the second metal layer 120 may include cobalt silicide to increase conductivity between connection pad 130 and second contact structure 220 .
  • a sacrificial layer 140 may also be formed on the connection pad 130 . After subsequent semiconductor structures are formed, the sacrificial layer 140 can be removed.
  • an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
  • the manufacturing method of the semiconductor structure includes:
  • Step S100 Provide a substrate in which a plurality of active regions are formed at intervals along a first direction.
  • Step S200 Form a first dielectric layer on the substrate.
  • Step S300 Form a first contact hole on the first dielectric layer.
  • the first contact hole extends into the substrate toward one end of the substrate and exposes at least part of the active area.
  • Step S400 Form a first contact structure in the first contact hole, and the top surface of the first contact structure and the top surface of the substrate have a first preset height.
  • Step S500 Form a second contact hole on the first contact structure.
  • the diameter of the second contact hole is smaller than the diameter of the first contact hole.
  • Step S600 Form a second contact structure in the second contact hole, and the first contact structure and the second contact structure form a contact structure.
  • the contact structure is formed in two steps by dividing the first contact structure and the second contact structure, and in the direction perpendicular to the top surface of the substrate, the cross-sectional area of the second contact structure is smaller than the cross-sectional area of the first contact structure, whereby effectively reducing the influence of parasitic capacitance, improving the overlap problem between the contact structure and the active area caused by adjusting the size of the contact structure and the trade-off between the parasitic capacitance of the contact structure and the bit line structure, thereby improving the performance and good quality of the semiconductor structure. Rate.
  • this embodiment is a further explanation of step S100 above.
  • a substrate 10 is provided.
  • the substrate 10 serves as a support component of the dynamic random access memory and is used to support other components located on it.
  • the substrate 10 can be made of a semiconductor material, and the semiconductor material can be one of silicon, germanium, silicon germanium compounds, and silicon carbon compounds. kind or variety.
  • the substrate 10 is made of silicon material.
  • the use of silicon material as the base 10 in this embodiment is to facilitate those skilled in the art to understand the subsequent formation method, and does not constitute a limitation. In the actual application process, the choice can be made according to needs. Suitable substrate 10 material.
  • the substrate 10 has a plurality of active areas 30 spaced apart along the first direction X.
  • the active area 30 may be provided on the top surface of the substrate 10 or on the bottom surface of the substrate 10 .
  • the active area 30 may be formed by the following methods:
  • a photoresist layer (not shown in the figure) and a mask layer (not shown in the figure) are deposited on the top surface of the substrate 10 through an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process. (not shown), form a mask pattern on the photoresist layer by exposure or development etching, use the photoresist layer with the mask pattern as a mask, and remove part of the photoresist layer and part of the mask by etching film layer, thereby forming a plurality of isolation trenches (not shown in the figure) spaced apart along the first direction X on the substrate 10 . Then, the remaining photoresist layer and mask layer are removed by etching.
  • the isolation structure 40 is deposited in the isolation trench through an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process.
  • the portion of substrate 10 between adjacent isolation structures 40 forms active region 30 .
  • the isolation structure 40 can be made of insulating materials, such as silicon dioxide, silicon oxynitride, etc.
  • a word line structure may be formed in the substrate 10 first (not shown in the figure). (shown), etc., and then the bit line structure 60 is formed on the substrate 10.
  • bit line structure 60 can be formed using the following methods:
  • a second dielectric layer (not shown in the figure) is formed on the substrate 10 using an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process.
  • first grooves 170 spaced apart along the first direction During the formation of the first groove 170, an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, or other suitable processes may be used to form the first mask layer on the second dielectric layer (not shown in the figure). Shows). For example, a first photoresist layer with a predetermined thickness can be formed on the second dielectric layer through a coating process. After the first mask layer is formed, the mask layer is patterned, and exposure, development or etching are used to form a plurality of first openings arranged at intervals in the first mask layer. Each first opening is related to the subsequent openings to be formed.
  • the first grooves 170 correspond one to one.
  • first groove 170 can also extend to a predetermined depth in the substrate 10 and expose the active area 30 .
  • a deposition process is used to form isolation sidewalls 80 on the side walls of the first groove 170 .
  • the deposition process may include an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process.
  • the material of the isolation spacer 80 may include but is not limited to silicon oxide or silicon nitride. Moreover, the isolation side wall 80 may have a single-layer structure or a multi-layer structure. In some embodiments, when the isolation side wall 80 is a multi-layer structure, the following methods can be used to form it:
  • first isolation layer 810 the second isolation layer 820 and the third isolation layer 830 may be the same or different.
  • the materials of the first isolation layer 810 , the second isolation layer 820 and the third isolation layer 830 may include isolation materials such as silicon dioxide, borophosphosilicate glass, etc., to protect the bit line structure 60 and the subsequently formed Contact structure 20 and other structures are isolated.
  • the materials of the first isolation layer 810 , the second isolation layer 820 and the third isolation layer 830 may include silicon nitride or silicon oxynitride to improve the isolation performance of the isolation sidewall 80 and facilitate the Selective etching is performed in subsequent structures.
  • the first isolation layer 810 , the second isolation layer 820 and the third isolation layer 830 may include a low dielectric constant material or an air gap to reduce the parasitic capacitance of the contact structure 20 and the bit line structure 60 , wherein ,
  • Low dielectric constant materials usually refer to electrolytes whose dielectric constant is lower than the dielectric constant of silicon dioxide (3.9), such as organic polymers, amorphous chlorinated carbon, ultra-small foam plastics, silicon oxide and other materials .
  • a second groove 180 is formed between adjacent isolation side walls 80 in the first groove 170 .
  • bit line structure 60 is deposited in the second groove 180 .
  • the bit line structure 60 is formed in the second groove 180 .
  • an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process is used to form a transition layer 610, a conductive layer 620, and an insulating layer 630 that are sequentially stacked in the second groove 180.
  • the material of transition layer 610 may include, but is not limited to, silicon nitride.
  • the material of conductive layer 620 may include, but is not limited to, tungsten.
  • the material of the insulating layer 630 may include, but is not limited to, silicon nitride, silicon dioxide, borophosphosilicate glass, and the like. Wherein, the transition layer 610 is disposed close to the active area 30 .
  • a first insulating layer 631 can also be formed on the insulating layer 630 using a deposition process, wherein the top surface of the first insulating layer 631 is in contact with the isolation spacer 80
  • the top surface of the first insulating layer 631 may be the same as or different from the material of the insulating layer 630 .
  • bit line structure 60 is formed, the remaining second dielectric layer is removed to form a plurality of third grooves (not shown in the figure) spaced apart along the first direction X.
  • isolation spacers 80 are formed on both side walls of the first groove 170 .
  • the isolation sidewalls 80 can effectively control the topography of the sidewalls on both sides of the bitline structure 60 and prevent necking at the top of the bitline structure 60, thereby improving the performance and yield of the semiconductor structure.
  • Bit line contact structure 70 is formed within groove 180 .
  • the top surface of the bit line contact structure 70 is lower than the top surface of the second groove 180 .
  • the material of the bit line contact structure 70 may include, but is not limited to, conductive materials such as polysilicon to effectively ensure conductivity between the bit line structure 60 and the active region 30 .
  • the manufacturing method of the medium semiconductor structure also includes:
  • a photoresist layer and a mask layer are deposited on the substrate 10 using an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process, and a mask pattern is formed on the photoresist layer through exposure or development and etching. , using the photoresist layer with the mask pattern as a mask, etching and removing part of the photoresist layer and part of the mask layer, thereby forming a plurality of fourth grooves spaced apart along the second direction in the substrate 10 (Fig. not shown).
  • an initial gate oxide layer and an initial gate metal layer are deposited in the fourth groove through an atomic layer deposition process, a physical vapor deposition process, or a chemical vapor deposition process, and the initial gate oxide layer and the initial gate metal layer are etched back.
  • an initial gate insulating layer is deposited to fill the fourth groove to form a word line structure.
  • the material of the initial gate oxide layer may include but is not limited to silicon oxynitride, a stack of silicon oxide and silicon oxynitride, or a high-K dielectric material, where the high-K dielectric material refers to a relative dielectric constant greater than the relative dielectric constant of silicon oxide.
  • Constant materials high-K dielectric materials may include but are not limited to zirconium oxide, hafnium oxide, titanium zirconium oxide, ruthenium oxide or aluminum oxide, etc.
  • the material of the initial gate metal layer may include, but is not limited to, tungsten, titanium nitride, or a combination thereof, and the material of the initial gate insulating layer may include, but is not limited to, silicon nitride.
  • the active regions on both sides of the word line structure can be source-drain doped through an ion implantation process to form source-drain regions of the semiconductor structure. It should be noted that the number of implantations in the ion implantation process can be multiple times.
  • Preparation methods also include:
  • An atomic layer deposition process, a chemical vapor deposition process or a physical vapor process is used to form a sequentially stacked gate oxide layer 910 and a gate metal layer 920 on the active area 30 , and part of the gate oxide layer is removed through a preset mask window. 910 and gate metal layer 920 to form an initial gate structure.
  • the first barrier layer 930 is formed on the sidewalls and top surface of the initial gate structure using an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor process. The excess first barrier layer 930 is removed to form a gate structure.
  • an ion implantation process is used to ion-dope the active regions 30 on both sides of the gate structure to form a source region 31 and a drain region 32 on both sides of the gate structure.
  • the subsequently formed contact structure may be disposed on the source region 31 and the drain region 32 .
  • this embodiment is a further explanation of step S200 above.
  • the top surface of the substrate 10 is formed by an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process.
  • the first dielectric layer 160 is formed by deposition on the substrate.
  • the first dielectric layer 160 fills the third groove, extends outside the third groove, and covers the top surface of the bit line structure 60 .
  • the material of the first dielectric layer 160 may include, but is not limited to, silicon nitride, silicon dioxide, or silicon oxynitride.
  • the first dielectric layer 160 can form an isolation protection for the top of the bit line structure 60 to prevent other subsequent processes of the semiconductor structure from affecting the top surface of the bit line structure 60, thereby effectively ensuring the safety of the semiconductor structure. performance and yield.
  • this embodiment is a further explanation of step S300 above.
  • a third mask layer (not shown in the figure) is formed on the top surface of the substrate 10 using an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, or other suitable processes. (out), for example, a third photoresist layer with a predetermined thickness may be formed on the top surface of the substrate 10 through a coating process. After the third mask layer is formed, the third mask layer is patterned, and exposure, development, or etching are used to form a plurality of third openings arranged at intervals in the third mask layer, and each third opening is connected to the corresponding third opening. The areas between adjacent isolation side walls 80 correspond to each other.
  • first contact hole 230 extends into the substrate 10 toward one end of the substrate 10 and exposes at least part of the active area 30 .
  • this embodiment is a further explanation of step S400 above.
  • an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process is used to form the first contact structure 210 in the first contact hole 230 , wherein the top of the first contact structure 210 There is a first preset height between the surface and the top surface of the base.
  • the highest position of the first preset height of the first contact structure 210 may be flush with the top surface of the transition layer 610 in the bit line structure 60 , or flush with the top surface of the bit line contact structure 70 . together. This increases the distance between the first contact structure 210 and the adjacent bit line structure 60 and reduces the impact on the parasitic capacitance of the bit line structure.
  • this embodiment is a further explanation of step S500 above.
  • a second contact hole 240 is formed on the first contact structure 210 .
  • the diameter of the second contact hole 240 is smaller than the diameter of the first contact hole 230 .
  • the second contact hole 240 can be formed by the following method:
  • an atomic layer deposition process is used to form an initial dielectric layer 251 of a predetermined thickness on the top surface of the first contact structure 210 and the sidewalls of the adjacent isolation spacers 80 .
  • a second contact hole 240 is formed between the first contact structure 210 and the adjacent isolation sidewall 80 . There are a plurality of second contact holes 240 and they are spaced apart along the first direction X. The projection area of the second contact hole 240 on the substrate 10 is located within the projection area of the first contact structure 210 on the substrate 10 , and, in the extending direction along the first direction X, the aperture of the second contact hole 240 is smaller than the first The diameter of the contact hole 230.
  • this embodiment is a further explanation of step S600 above.
  • an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process is used to form a second contact structure 220 in the second contact hole 240 .
  • the top surface of the second contact structure 220 is lower than the isolation spacer 80 top surface.
  • the first contact structure 210 and the second contact structure 220 form the contact structure 20 .
  • along the extension direction of the first direction The diameter of the contact structure 210 , that is, the cross-sectional size of the second contact structure 220 located in the upper section is smaller than the cross-sectional size of the first contact structure 210 .
  • Such design can reduce the size of the second contact structure 220 and the size of the second contact structure 220 located next to the second contact structure 220 . Parasitic capacitance between bit line structures 60.
  • the influence of parasitic capacitance in the semiconductor structure can be effectively reduced, and the impact of the contact structure 20 and the active area 30 caused by adjusting the size of the contact structure 20 can be improved.
  • the trade-off between the overlap problem and the parasitic capacitance between the contact structure 20 and the bit line structure 60 thereby improves the performance and yield of the semiconductor structure.
  • the pore diameter of the second contact hole 240 is 1-6 nm smaller than the pore diameter of the first contact hole 230 .
  • the aperture of the second contact hole 240 may be the same as the size of the contact structure in the existing process. However, in this embodiment, the aperture of the first contact hole 230 is correspondingly increased, thereby forming a larger cross-sectional size.
  • the large first contact structure 210 facilitates the alignment between the contact structure 20 and the active area 30 and reduces the overlap error between the contact structure 20 and the active area 30 . At the same time, the first contact structure 210 that increases the size range will not affect other structures in the semiconductor structure, such as bit line structures, isolation spacers, etc.
  • an atomic layer deposition process, a physical vapor deposition process, or a chemical vapor deposition process is used to form a stacked first metal layer on the second contact structure 220 .
  • the first metal layer 110 and the second metal layer 120 may include cobalt silicide, and the material of the connection pad may include but is not limited to tungsten.
  • the first metal layer 110, the second metal layer 120 and the connection pads 130 are provided to facilitate the electrical connection between the contact structure 20 and the subsequently formed semiconductor structure, while ensuring that the contact structure 20 is connected to the subsequently formed semiconductor structure.
  • Conductivity between semiconductor structures such as capacitor structures.
  • the cross-sectional area of the second contact structure is less than The cross-sectional area of the first contact structure can effectively reduce the influence of parasitic capacitance, thereby improving the performance and yield of the semiconductor structure.

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Abstract

本公开公布了一种半导体结构及半导体结构的制作方法，涉及半导体技术领域。该半导体结构包括基底和接触结构，基底内设置有多个沿第一方向间隔设置的有源区；接触结构包括第一接触结构和第二接触结构，第一接触结构的一端靠近基底设置，并与有源区连接，第二接触结构与第一接触结构的另一端连接，其中，第二接触结构在基底上的投影位于第一接触结构在基底上的投影内。

Description

半导体结构及半导体结构的制作方法
本公开基于申请号为202210462567.5，申请日为2022年04月29日，申请名称为“半导体结构及半导体结构的制作方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及一种半导体结构及半导体结构的制作方法。
背景技术
随着芯片集成度越来越高，对半导体结构的集成度和功能的要求越来越高，使得半导体结构的特征尺寸不断缩小，对应制造半导体结构的制程工艺窗口也变小，进而使得半导体结构中相邻的导电器件(比如位线)的间距也不断缩小，导致相邻的导电器件之间的寄生电容值越来越大。另一方面，随着半导体结构的特征尺寸的不断缩小，增大了后续半导体结构的工艺难度，提高了工艺复杂度。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种半导体结构及半导体结构的制作方法。
本公开的第一方面提供了一种半导体结构，所述半导体结构包括：
基底，所述基底内设置有多个沿第一方向间隔设置的有源区；
接触结构，所述接触结构包括第一接触结构和第二接触结构，所述第一接触结构的一端靠近所述基底设置，并与所述有源区连接，所述第二接触结构与所述第一接触结构的另一端连接，其中，所述第二接触结构在所述基底上的投影位于所述第一接触结构在所述基底上的投影内。
根据本公开的一些实施例，在平行于所述基底的厚度方向的截面上，所述第二接触结构的宽度比所述第一接触结构的宽度小1-6nm。
根据本公开的一些实施例，所述半导体结构还包括多个沿第二方向间隔设置的字线结构，其中，所述字线结构设置在所述有源区内。
根据本公开的一些实施例，所述半导体结构还包括位线结构，所述位线结构通过位线接触结构与所述有源区连接。
根据本公开的一些实施例，所述位线结构的两侧均设有一个隔离侧墙。
根据本公开的一些实施例，所述半导体结构还包括设在所述第二接触结构上的连接垫，所述连接垫包括钨层。
本公开的第二方面提供了一种半导体结构的制作方法，包括：
提供基底，所述基底内形成有多个沿第一方向间隔设置的有源区；
在所述基底上形成第一介质层；
在所述第一介质层上形成第一接触孔，所述第一接触孔朝向所述基底的一端延伸至所述基底内，并至少暴露出部分所述有源区；
在所述第一接触孔内形成第一接触结构，所述第一接触结构的顶面与所述基底的顶面之间具有第一预设高度；
在所述第一接触结构上形成第二接触孔，所述第二接触孔的孔径小于所述第一接触孔的孔径；
在所述第二接触孔内形成第二接触结构，其中，所述第一接触结构和所述第二接触结构形成接触结构。
根据本公开的一些实施例，所述第二接触孔的孔径比第一接触孔的孔径小1-6nm。
根据本公开的一些实施例，在所述基底上形成第一介质层之前，所述半导体结构的制作方法还包括：
于所述有源区上形成依次层叠设置的栅极氧化层和栅极金属层；
于所述栅极金属层和所述栅极氧化层的侧壁上形成第一阻挡层，去除多余的第一阻挡层，形成栅极结构；
对所述栅极结构两侧的所述有源区进行掺杂工艺，以在所述栅极结构的两侧形成源极区和漏极区。
根据本公开的一些实施例，在所述基底上形成第一介质层之前，所述半导体结构的制作方法还包括：
在所述基底上形成位线结构。
根据本公开的一些实施例，在所述基底上形成位线结构，包括：
在所述基底上形成第二介质层；
在所述第二介质层上形成多个沿第一方向间隔设置的第一凹槽，所述第一凹槽的底端至少暴露出部分所述有源区；
在所述第一凹槽的侧壁上形成隔离侧墙，所述第一凹槽内相邻的所述隔离侧墙之间形成第二凹槽；
在所述第二凹槽内形成所述位线结构。
根据本公开的一些实施例，在所述第二凹槽内形成位线结构，包括：
在所述第二凹槽内形成依次层叠设置的过渡层、导电层和绝缘层，其中，所述过渡层靠近所述有源区设置。
根据本公开的一些实施例，在所述第二凹槽内形成位线结构之前，所述半导体结构的制作方法还包括：
在所述第二凹槽内形成位线接触结构，所述位线接触结构的顶面低于所述第二凹槽的顶面。
根据本公开的一些实施例，在所述第二凹槽内形成位线接触结构之前，所述半导体结构的制作方法还包括：
在所述基底内形成字线结构。
根据本公开的一些实施例，在所述第一接触结构上形成第二接触孔，包括：
在所述第一接触结构的顶面以及所述隔离侧墙的侧壁上形成预定厚度的初始介质层；
去除位于所述第一接触结构顶面上的所述初始介质层，暴露所述第一接触结构的顶面，所述第一接触结构和相邻的所述隔离侧墙之间形成所述第二接触孔，其中所述第二接触孔在所述基底上的投影位于所述第一接触结构在所述基底上的投影内，且所述第二接触孔的孔径小于所述第一接触结构的孔径。
根据本公开的一些实施例，所述半导体结构的制作方法还包括：
在所述第二接触结构上形成连接垫，其中，所述连接垫包括钨层。
本公开实施例所提供的半导体结构及半导体结构的制作方法中，通过将接触结构分成第一接触结构和第二接触结构，沿垂直于基底顶面的方向，第二接触结构的截面面积小于第一接触结构的截面面积，从而有效降低寄生电容的影响，改善因调 整接触结构的尺寸而导致的接触结构与有源区的重叠问题和接触结构与位线的寄生电容之间的权衡作用，进而提高半导体结构的性能和良率。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是一种示例性实施例示出的半导体结构的示意图。
图2是根据一示例性实施例示出的一种半导体结构的示意图。
图3是根据一示例性实施例示出的半导体结构的制作方法的流程图。
图4是根据一示例性实施例示出的半导体结构的制作方法中形成第一介质层的示意图。
图5是根据一示例性实施例示出的半导体结构的制作方法中形成第一接触孔的示意图。
图6是根据一示例性实施例示出的半导体结构的制作方法中形成第一接触结构的示意图。
图7是根据一示例性实施例示出的半导体结构的制作方法中形成初始介质层的示意图。
图8是根据一示例性实施例示出的半导体结构的制作方法中形成第二介质层和第二接触孔的示意图。
图9是根据一示例性实施例示出的半导体结构的制作方法中形成第二接触结构的示意图。
图10是根据一示例性实施例示出的半导体结构的制作方法中平面栅极结构的半导体结构的示意图。
图11是根据一示例性实施例示出的半导体结构的制作方法中形成接触结构和接触垫示意图。
附图标记：
1、衬底；2、第一有源区；
3、字线；4、位线；
5、电容接触结构；
10、基底；20、接触结构；
30、有源区；31、源极区；
32、漏极区；40、隔离结构；
60、位线结构；70、位线接触结构；
80、隔离侧墙；110、第一金属层；
120、第二金属层；130、连接垫；
140、牺牲层；160、第一介质层；
170、第一凹槽；180、第二凹槽；
210、第一接触结构；220、第二接触结构；
230、第一接触孔；240、第二接触孔；
250、第三介质层；251、初始介质层；
610、过渡层；620、导电层；
630、绝缘层；631、第一绝缘层；
810、第一隔离层；820、第二隔离层；
830、第三隔离层；910、栅极氧化层；
920、栅极金属层；930、第一阻挡层。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
随着芯片集成度越来越高，对半导体结构的集成度和功能的要求越来越高，使得半导体结构的特征尺寸也不断缩小，对应制作半导体结构的制程工艺窗口也变小，进而使得半导体结构中相邻的导电器件(比如位线)的间距也不断缩小，导致相邻的导电器件之间的寄生电容值越来越大。另一方面，随着半导体结构的特征尺寸的不断缩小，增大了后续半导体结构的工艺难度，提高了工艺复杂度。
如图1所示，在一些半导体结构中，一般在衬底1内设置有多个间隔的第一有源区2，即形成了多个晶体管结构。衬底1内的字线3连接处于第一有源区2内的多个晶体管的栅极结构，衬底1上的位线4与多个晶体管的源极或漏极连接，字线3的延伸方式与位线4的延伸方向可以相互垂直设置，或者沿预定角度相交设置。同时，在相邻的位线之间设置有电容接触结构5，电容接触结构5与第一有源区2部分重叠设置，电容接触结构5上连接有电容结构。其中，参照图1所示，电容接触结构5是通过自对准双重成像技术(Self-aligned Double Patterning，SADP)所形成的矩形窗口。
因此，随着半导体结构的制程工艺窗口的缩小，在使用SADP制程工艺时，微小的工艺误差就会导致半导体结构中的电容接触结构5与第一有源区2之间的重叠产生较大的误差，使得电容接触结构5与第一有源区2的重叠存在如下问题，比如重叠区域变小，会使电容接触结构的导电性变差，影响晶体管对电容中数据的读写速度；当重叠区域变大，会使得电容接触结构与相邻的位线短路，从而降低半导体结构的性能和良率。
为了解决上述技术问题之一，本公开示例性的实施例提供了一种半导体结构。如图2所示，图2示出了根据一示例性的实施例提供的半导体结构的示意图，下面结合图2对半导体结构进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)中核心区的存储晶体管为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图2所示，本公开一示例性的实施例提供的一种半导体结构包括基底10和接触结构20。
示例性地，基底10作为动态随机存储器的支撑部件，用于支撑设在其上的其他部件，其中，基底10可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。在本实施例中，基底10采用硅材料，而本实施例采用硅材料作为基底10是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底的材料。
参照图2所示，在基底10内设置有若干个有源区30。其中，若干个有源区30可以沿第一方向X间隔设置在基底10内。参考图1，以图中示出的方位为例，第一方向为图1中X方向。需要说明的是，第一方向X可以是沿图1中的字线3的延伸方向。
继续参照图2所示，相邻的有源区30之间设置有隔离结构40。其中，隔离结构40可采用绝缘材料，如二氧化硅、氮氧化硅等，通过隔离结构40可以绝缘性地分隔开多个有源区30。
在一些实施例中，如图2所示，接触结构20包括第一接触结构210和第二接触结构220。第一接触结构210的底端朝向基底10，并靠近基底10设置，且第一接触结构210的底端与多个有源区30中的其中之一连接。第一接触结构210的材料可以包括但不限于多晶硅、氮化钛或钨。
第二接触结构220的底端与第一接触结构210的顶端连接。第二接触结构220的材料包括多晶硅、氮化钛或钨等。其中，第二接触结构220与第一接触结构210的材料可以相同，也可以不相同。需要说明的是，在本实施例中，接触结构20可以是电容接触结构。
参照图2所示，在一些实施例中，第二接触结构220在基底10上的投影位于第一接触结构210在基底10上的投影内。即，以垂直于基底10顶面的平面为横截面，第一接触结构210的截面面积大于第二接触结构220的截面面积。因此，在本实施例中，将接触结构20设计为沿上下方向排布的两段结构，并且增加了与有源区30连接的第一接触结构210的截面尺寸，从而有利于接触结构20与有源区30之间的对准，降低接触结构20与有源区30两者之间的重叠误差。
同时，也增加了接触结构20与有源区30的接触面积，可以降低接触结构20与有源区30之间的接触电阻，提高半导体结构的导电性能。
在一些实施例中，在平行于基底10的厚度方向的截面上，即沿第一方向X的延伸方向，第二接触结构220的宽度比第一接触结构210的宽度小1-6nm。
需要说明的是，第二接触结构220的宽度可以理解为沿第一方向上的尺寸，或者，若是第二接触结构220的形状不规则，第二接触结构220的宽度可以理解为第二接触结构220的多个位置处在第一方向上的尺寸的平均值。此外，第一接触结构210的宽度与第二接触结构220的宽度的理解相同，本实施例在此不再多加赘述。
需要说明的是，第二接触结构220的直径可以与现有工艺中的接触结构的尺寸相同，而在本实施例中，相对应的增大了第一接触结构210的直径，从而有利于接触结构20与有源区30之间的对准，并降低接触结构20与有源区30两者之间的重叠误差。同时，增大了该尺寸范围的第一接触结构210并不会对半导体结构中的其他结构比如位线结构、隔离侧墙等造成影响。
其中，若第一接触结构210的宽度与第二接触结构220的宽度之差小于1nm，那么第一接触结构210和第二接触结构220的宽度基本一致，此时，并不能解决重叠区域难以对准的问题。若第一接触结构210的宽度与第二接触结构220的宽度之差大于6nm，会使得位于第一接触结构210两侧的隔离侧墙80的宽度降低，从而降低了隔离侧墙80的隔离效果，进而，易导致位线结构60与第一接触结构210发生电连接，影响半导体结构的导电性能，降低了半导体结构的良率。
在一些实施例中，有源区30上具有多个沿第二方向Y间隔设置的字线结构(图中未示出)，需要说明的是，第二方向Y可以是沿图1中的位线4的延伸方向。
字线结构设置在有源区30内，需要说明的是，字线结构可以定义半导体结构中的栅极结构。
继续参照图2所示，在一些实施例中，该半导体结构包括位线结构60。其中，为了 实现位线结构60与有源区30之间的电连接，位线结构60靠近有源区30的一端设置有位线接触结构70，位线接触结构70的材料可以包括但不限于多晶硅等导电材料。
其中，位线结构60通过位线接触结构70与有源区30连接。在本实施例中，位线结构60包括在位线接触结构70上依次层叠的过渡层610、导电层620和绝缘层630。过渡层610的材料可以包括但不限于氮化钛硅。导电层620的材料可以包括但不限于钨。绝缘层630的材料可以包括但不限于氮化硅、二氧化硅、硼磷硅玻璃等。
需要说明的是，由于第二接触结构220的宽度比第一接触结构210的宽度小1-6nm，其中，第一接触结构210远离位线结构60设置。因此，在本实施例中，增大了第一接触结构210与基底10中所形成的位线结构60的间距，由此，能够减小因第一接触结构210截面尺寸变大而对位线结构60的寄生电容的影响。
同时，位于上段的第二接触结构220的截面尺寸要小于第一接触结构210的截面尺寸，如此设计，可以降低第二接触结构220与后续在该第二接触结构220旁侧所形成的位线结构之间的电容。
本实施例中，通过将接触结构20分成第一接触结构210和第二接触结构220，沿垂直于基底顶面的方向，第二接触结构220的截面面积小于第一接触结构210的截面面积，从而有效降低寄生电容的影响，改善因调整接触结构的尺寸而导致的接触结构与有源区的重叠问题和接触结构与位线结构的寄生电容之间的权衡作用，进而提高半导体结构的性能和良率。
继续参照图2所示，在一些实施例中，在每个位线结构60的两侧均设有一个隔离侧墙80。在本实施例中，隔离侧墙80包括依次连接的第一隔离层810、第二隔离层820和第三隔离层830。其中，第一隔离层810与位线结构60相抵接。需要说明的是，第一隔离层810、第二隔离层820和第三隔离层830的材料可以相同，也可以不相同。在一个示例中，第一隔离层810、第二隔离层820和第三隔离层830的材料均可以包括二氧化硅、硼磷硅玻璃等隔离材料，以对位线结构60和后续所形成的接触结构20等结构进行隔离。在另一实施例中，第一隔离层810、第二隔离层820和第三隔离层830可以包括氮化硅或氮氧化硅，以提高隔离侧墙80的隔离性能，且有利于在后续结构中进行选择性刻蚀，在另一实施例中，第一隔离层810、第二隔离层820和第三隔离层830可以包括低介电常数材料或者空气间隙，以减小接触结构20与位线结构60的寄生电容。
在本实施例中，通过在每个位线结构60的两侧均设置隔离侧墙80，隔离侧墙80能够有效控制位线结构60两侧侧壁的形貌，从而提高半导体结构的性能和良率。
需要说明的是，上述实施例中，在有源区30上所形成的栅极结构为掩埋栅结构，即后续可以制作凹入式沟道晶体管结构，有源区还包括源漏区，接触结构可以设置在源漏区中的其中之一，作为电容接触结构与电容结构连接。
而在另一个示例中，在有源区上所形成的栅极结构还可以是平面栅结构，后续可以制作平面晶体管结构，形成的晶体管可以位于DRAM芯片的外围区，有源区还包括源漏区，接触结构可以设置在源漏区和栅极结构中的至少一个上，作为电极引出结构，施加工作电压、引出工作电流。
在该实施例中，接触结构采用两段式结构。该接触结构可以包括第一接触结构和第二接触结构，其中，第一接触结构的横截面尺寸较大，可以降低与源漏区连接的接触结构的接触电阻，增大半导体结构的电流，而第二接触结构的横截面尺寸较小，可以有效减少栅极结构和源漏区之间的寄生电容，降低晶体管的延时效应。
如图2所示，在一些实施例中，半导体结构还包括设在第二接触结构220上的连接垫130。其中，连接垫130的材料可以包括钨。在本实施例中，通过设置连接垫130，以便 于接触结构20与后续所形成的半导体结构进行电连接，同时保证接触结构20与后续所形成的半导体结构比如电容结构等之间的导电性。
其中，参照图2所示，在一个示例中，还可以在连接垫130和第二接触结构220之间设置第一金属层110和第二金属层120，第一金属层110、第二金属层120可以包括硅化钴，以增加连接垫130和第二接触结构220之间的导电性。
需要说明的是，在另一个示例中，为了便于后续形成其他的半导体结构比如电容结构等，还可以在连接垫130上形成牺牲层140。待后续半导体结构形成之后，可以去除牺牲层140。
如图3至图11所示，本公开一示例性的实施例提供了一种半导体结构的制作方法。参照图3所示，该半导体结构的制作方法包括：
步骤S100：提供基底，基底内形成有多个沿第一方向间隔设置的有源区。
步骤S200：在基底上形成第一介质层。
步骤S300：在第一介质层上形成第一接触孔，第一接触孔朝向基底的一端延伸至基底内，并至少暴露出部分有源区。
步骤S400：在第一接触孔内形成第一接触结构，第一接触结构的顶面与基底的顶面具有第一预设高度。
步骤S500：在第一接触结构上形成第二接触孔，第二接触孔的孔径小于第一接触孔的孔径。
步骤S600：在第二接触孔内形成第二接触结构，第一接触结构和第二接触结构形成接触结构。
本实施例中，通过将接触结构分成第一接触结构和第二接触结构两步形成，并且，沿垂直于基底顶面的方向，第二接触结构的截面面积小于第一接触结构的截面面积，从而有效降低寄生电容的影响，改善因调整接触结构的尺寸而导致的接触结构与有源区的重叠问题和接触结构与位线结构的寄生电容之间的权衡作用，进而提高半导体结构的性能和良率。
根据一个示例性实施例，本实施例是对上文中步骤S100的进一步说明。
如图3至图11所示，提供基底10。基底10作为动态随机存储器的支撑部件，用于支撑设在其上的其他部件，其中，基底10可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。在本实施例中基底10采用硅材料，而本实施例采用硅材料作为基底10是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底10的材料。
参照图4所示，基底10上具有多个沿第一方向X间隔设置的有源区30。有源区30可以设置在基底10的顶面上，或者设置在基底10的底面上。
其中，在一些实施例中，有源区30的形成可以采用以下方法：
参照图4所示，通过原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺在基底10的顶面上沉积层叠设置的光刻胶层(图中未示出)和掩膜层(图中未示出)，通过曝光或显影刻蚀的方式在光刻胶层上形成掩膜图案，以具有掩膜图案的光刻胶层为掩膜版，刻蚀去除部分光刻胶层和部分掩膜层，从而在基底10上形成多个沿第一方向X间隔设置的隔离沟槽(图中未示出)。而后，通过刻蚀去除剩余的光刻胶层和掩膜层。然后，通过原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺在隔离沟槽内沉积形成隔离结构40。相邻的隔离结构40之间的基底10部分形成有源区30。其中，隔离结构40可以采用绝缘材料，比如二氧化硅、氮氧化硅等。
需要说明的是，在一些实施例中，当有源区30为半导体结构中阵列区的有源区时， 待有源区30形成之后，可以先在基底10内形成字线结构(图中未示出)等，而后在基底10上形成位线结构60。
如图4所示，位线结构60的形成可以采用以下方法：
利用原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺在基底10上形成第二介质层(图中未示出)。
而后，通过刻蚀工艺在第二介质层上形成多个沿第一方向X间隔设置的第一凹槽170，第一凹槽170的底部至少暴露出部分有源区30。其中，在第一凹槽170的形成过程中，可以利用原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺或其他合适的工艺在第二介质层上形成第一掩膜层(图中未示出)。比如，可以通过涂覆的工艺在第二介质层上形成预定厚度的第一光刻胶层。待形成第一掩膜层之后，图形化掩膜层，采用曝光、显影或者刻蚀方式以在第一掩膜层内形成多个间隔设置的第一开口，每个第一开口与后续所要形成的第一凹槽170一一对应。而后，利用刻蚀液或者刻蚀气体，去除暴露在第一开口内的第二介质层，从而在第二介质层上形成多个间隔设置的第一凹槽170。需要说明的是，第一凹槽170的底部还可以延伸至基底10内预定深度，并暴露出有源区30。
待第一凹槽170形成之后，利用沉积工艺在第一凹槽170的侧壁上形成隔离侧墙80。其中，沉积工艺可以包括原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺。
其中，隔离侧墙80的材料可以包括但不限于氧化硅或氮化硅。并且，隔离侧墙80可以为单层结构，也可以为多层结构。在一些实施例中，当隔离侧墙80为多层结构时，可以采用以下方法形成：
待第一凹槽170形成之后，沿第一方向X，利用原子层沉积工艺在第一凹槽170的侧壁上依次形成层叠设置的第一隔离层810、第二隔离层820和第三隔离层830。此时，第一凹槽170内相邻的第三隔离层830之间形成第二凹槽180。需要说明的是，第一隔离层810、第二隔离层820和第三隔离层830的材料可以相同，也可以不相同。
在一个示例中，第一隔离层810、第二隔离层820和第三隔离层830的材料均可以包括二氧化硅、硼磷硅玻璃等隔离材料，以对位线结构60和后续所形成的接触结构20等结构进行隔离。
在另一实施例中，第一隔离层810、第二隔离层820和第三隔离层830的材料可以包括氮化硅或氮氧化硅，以提高隔离侧墙80的隔离性能，且有利于在后续结构中进行选择性刻蚀。
在又一个示例中，第一隔离层810、第二隔离层820和第三隔离层830可以包括低介电常数材料或者空气间隙，以减小接触结构20与位线结构60的寄生电容，其中，低介电常数材料通常指的是介电常数低于二氧化硅的介电常数(3.9)的电解质，例如为有机聚合物、无定型氯化碳、超小型泡沫塑料以及硅氧化物等材料。
第一凹槽170内相邻的隔离侧墙80之间形成第二凹槽180。
而后，在第二凹槽180内沉积形成位线结构60。
如图4所示，待隔离侧墙80形成之后，在第二凹槽180内形成位线结构60。沿第二方向Y，利用原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺在第二凹槽180形成依次层叠设置的过渡层610、导电层620和绝缘层630。过渡层610的材料可以包括但不限于氮化硅。导电层620的材料可以包括但不限于钨。绝缘层630的材料可以包括但不限于氮化硅、二氧化硅、硼磷硅玻璃等。其中，过渡层610靠近有源区30设置。
需要说明的是，在一些实施例中，待绝缘层630形成之后，还可以在绝缘层630上利用沉积工艺形成第一绝缘层631，其中，第一绝缘层631的顶面与隔离侧墙80的顶面平齐，其中，第一绝缘层631的材料可以与绝缘层630的材料相同或者不同。
需要说明的是，待位线结构60形成之后，去除剩余的第二介质层，以形成多个沿第一方向X间隔设置的第三凹槽(图中未示出)。
在本实施例中，在形成位线结构60之前，先在第一凹槽170的两侧侧壁上形成隔离侧墙80。隔离侧墙80能有效控制位线结构60两侧侧壁的形貌，防止位线结构60的顶端出现颈缩现象，从而提高半导体结构的性能和良率。
需要说明的是，如图4所示，在一些实施例中，在第二凹槽180内形成位线结构60之前，可以通过原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺在第二凹槽180内形成位线接触结构70。位线接触结构70的顶面低于第二凹槽180的顶面。在一个示例中，位线接触结构70的材料可以包括但不限于多晶硅等导电材料，以有效保证位线结构60与有源区30之间的导电性。
在一些实施例中，当有源区30为半导体结构的阵列区中的有源区30时，在提供基底10的步骤之后，在基底10上形成第一介质层160的步骤之前，本实施例中半导体结构的制作方法还包括：
利用原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺在基底10上沉积层叠设置的光刻胶层和掩膜层，通过曝光或显影刻蚀的方式在光刻胶层上形成掩膜图案，以具有掩膜图案的光刻胶层为掩模版，刻蚀去除部分光刻胶层和部分掩膜层，从而在基底10内形成多个沿第二方向间隔设置的第四凹槽(图中未示出)。然后，通过原子层沉积工艺、物理气相沉积工艺或者化学气相沉积工艺在第四凹槽内沉积形成初始栅极氧化层、初始栅极金属层，回刻初始栅极氧化层和初始栅极金属层并沉积初始栅极绝缘层，填充满第四凹槽，形成字线结构。初始栅极氧化层的材料可以包括但不限于氮氧化硅、氧化硅与氮氧化硅的叠层或高K介质材料，其中，高K介质材料指的是相对介电常数大于氧化硅相对介电常数的材料，高K介质材料可以包括但不限于氧化锆、氧化铪、氧化钛锆、氧化钌或氧化铝等。初始栅极金属层的材料可以包括但不限于钨、氮化钛或者二者的结合，初始栅极绝缘层的材料可以包括但不限于氮化硅等。
在一些实施例中，可以通过离子注入工艺对字线结构两侧的有源区进行源漏掺杂，形成半导体结构的源漏区。需要说明的是，离子注入工艺的注入次数可以为多次。
如图10所示，在一个示例中，当栅极结构为平面栅结构时，在提供基底10的步骤之后，在基底10上形成第一介质层160的步骤之前，本实施例中半导体结构的制作方法还包括：
利用原子层沉积工艺、化学气相沉积工艺或物理气相工艺在有源区30上形成依次层叠设置的栅极氧化层910和栅极金属层920，通过预设的掩膜窗口去除部分栅极氧化层910和栅极金属层920，形成初始栅极结构。
利用原子层沉积工艺、化学气相沉积工艺或物理气相工艺在初始栅极结构的侧壁和顶面上形成第一阻挡层930。去除多余的第一阻挡层930，形成栅极结构。
而后，利用离子注入工艺，对栅极结构两侧的有源区30进行离子掺杂，以在栅极结构的两侧形成源极区31和漏极区32。其中，后续所形成的接触结构可以设置在源极区31和漏极区32上。
根据一个示例性实施例，本实施例是对上文中步骤S200的进一步说明。
如图4所示，当有源区30为半导体结构中阵列区的有源区时，在一些实施例中，通过原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺在基底10的顶面上沉积形成第一介质层160。第一介质层160填充满第三凹槽，并延伸至第三凹槽外，并覆盖在位线结构60的顶面上。其中，第一介质层160的材料可以包括但不限于氮化硅、二氧化硅或氮氧化硅。
在本实施例中，第一介质层160可以对位线结构60的顶部形成隔离防护，防止后续的半导体结构的其他工艺制程中对位线结构60的顶面造成影响，从而有效保证半导体结构的性能和良率。
根据一个示例性实施例，本实施例是对上文中步骤S300的进一步说明。
参照图5所示，在一些实施例中，利用原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺或其他合适的工艺在基底10的顶面上形成第三掩膜层(图中未示出)，比如，可以通过涂覆的工艺在基底10的顶面上形成预定厚度的第三光刻胶层。待形成第三掩膜层之后，图形化第三掩膜层，采用曝光、显影或者刻蚀方式以在第三掩膜层内形成多个间隔设置的第三开口，每个第三开口与相邻的隔离侧墙80之间的区域相对应。而后，利用刻蚀液或者刻蚀气体，去除暴露在第三开口内的第一介质层160和部分基底10，从而在基底10上形成多个沿第一方向X间隔设置的第一接触孔230。其中，第一接触孔230朝向基底10的一端延伸至基底10内，并至少暴露出部分有源区30。
根据一个示例性实施例，本实施例是对上文中步骤S400的进一步说明。
如图6所示，在一些实施例中，利用原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺在第一接触孔230内形成第一接触结构210，其中，第一接触结构210的顶面与基底的顶面之间具有第一预设高度。
其中，在一个示例中，第一接触结构210的第一预设高度的最高位置处可以与位线结构60中的过渡层610的顶面平齐，或者与位线接触结构70的顶面平齐。由此来增加第一接触结构210和与其相邻的位线结构60之间的间距，降低对位线结构寄生电容的影响。
根据一个示例性实施例，本实施例是对上文中步骤S500的进一步说明。
如图7所示，在一些实施例中，在第一接触结构210上形成第二接触孔240。其中，第二接触孔240的孔径小于第一接触孔230的孔径。
需要说明的是，第二接触孔240的形成可以采用以下方法：
参照图7所示，利用原子层沉积工艺在第一接触结构210的顶面以及相邻的隔离侧墙80的侧壁上形成预定厚度的初始介质层251。
而后，可以通过刻蚀去除位于第一接触结构210顶面上的初始介质层251，暴露第一接触结构210的顶面，其中，被保留下来的初始介质层251形成第三介质层250。第一接触结构210和相邻的隔离侧墙80之间形成第二接触孔240。其中，第二接触孔240为多个且沿第一方向X间隔设置。第二接触孔240在基底10上的投影区域位于第一接触结构210在基底10上的投影区域内，并且，在沿第一方向X的延伸方向上，第二接触孔240的孔径小于第一接触孔230的孔径。
根据一个示例性实施例，本实施例是对上文中步骤S600的进一步说明。
如图9所示，利用原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺在第二接触孔240内形成第二接触结构220，第二接触结构220的顶面低于隔离侧墙80的顶面。第一接触结构210和第二接触结构220形成接触结构20。在本实施例中，沿第一方向X的延伸方向，由于第二接触孔240的孔径小于第一接触孔230的孔径，因此，本步骤中所形成的第二接触结构220的直径小于第一接触结构210的直径，即，位于上段的第二接触结构220的截面尺寸小于第一接触结构210的截面尺寸，如此设计，可以减低第二接触结构220和位于该第二接触结构220旁侧的位线结构60之间的寄生电容。
同时，通过上述第一接触结构210和第二接触结构220的结构设计，可以有效降低半导体结构中寄生电容的影响，并改善因调整接触结构20的尺寸而导致的接触结构20和有源区30之间的重叠问题与接触结构20和位线结构60之间的寄生电容的权衡作用，进而提高半导体结构的性能和良率。
如图4至图11所示，在一些实施例中，第二接触孔240的孔径比第一接触孔230的孔径小1-6nm。其中，第二接触孔240的孔径可以与现有工艺中的接触结构的尺寸相同，但在本实施例中，相对应的增大了第一接触孔230的孔径，进而可以形成横截面尺寸较大的第一接触结构210，从而有利于接触结构20与有源区30之间的对准，并降低接触结构20与有源区30两者之间的重叠误差。同时，增大了该尺寸范围的第一接触结构210并不会对半导体结构中的其他结构比如位线结构、隔离侧墙等造成影响。
如图11所示，在一些实施例中，待第二接触结构220形成之后，利用原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺在第二接触结构220上形成层叠设置的第一金属层110、第二金属层120和连接垫130。其中，第一金属层110、第二金属层120可以包括硅化钴，连接垫的材料可以包括但不限于钨。在本实施例中，通过设置第一金属层110、第二金属层120和连接垫130，以便于接触结构20与后续所形成的半导体结构进行电连接，同时保证接触结构20与后续所形成的半导体结构比如电容结构等之间的导电性。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的的半导体结构及半导体结构的制作方法中，通过将接触结构分成第一接触结构和第二接触结构，沿垂直于基底顶面的方向，第二接触结构的截面面积小于第一接触结构的截面面积，从而有效降低寄生电容的影响，进而提高半导体结构的性能和良率。

Claims (16)

  1. 一种半导体结构，所述半导体结构包括：
    基底，所述基底内设置有多个沿第一方向间隔设置的有源区；
    接触结构，所述接触结构包括第一接触结构和第二接触结构，所述第一接触结构的一端靠近所述基底设置，并与所述有源区连接，所述第二接触结构与所述第一接触结构的另一端连接，其中，所述第二接触结构在所述基底上的投影位于所述第一接触结构在所述基底上的投影内。
  2. 根据权利要求1所述的半导体结构，其中，在平行于所述基底的厚度方向的截面上，所述第二接触结构的宽度比所述第一接触结构的宽度小1-6nm。
  3. 根据权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括多个沿第二方向间隔设置的字线结构，其中，所述字线结构设置在所述有源区内。
  4. 根据权利要求3所述的半导体结构，其特征在于，所述半导体结构还包括位线结构，所述位线结构通过位线接触结构与所述有源区连接。
  5. 根据权利要求4所述的半导体结构，其中，所述位线结构的两侧均设有一个隔离侧墙。
  6. 根据权利要求4所述的半导体结构，其中，所述半导体结构还包括设在所述第二接触结构上的连接垫，所述连接垫包括钨层。
  7. 一种半导体结构的制作方法，包括：
    提供基底，所述基底内形成有多个沿第一方向间隔设置的有源区；
    在所述基底上形成第一介质层；
    在所述第一介质层上形成第一接触孔，所述第一接触孔朝向所述基底的一端延伸至所述基底内，并至少暴露出部分所述有源区；
    在所述第一接触孔内形成第一接触结构，所述第一接触结构的顶面与所述基底的顶面之间具有第一预设高度；
    在所述第一接触结构上形成第二接触孔，所述第二接触孔的孔径小于所述第一接触孔的孔径；
    在所述第二接触孔内形成第二接触结构，其中，所述第一接触结构和所述第二接触结构形成接触结构。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，所述第二接触孔的孔径比第一接触孔的孔径小1-6nm。
  9. 根据权利要求7所述的半导体结构的制作方法，其中，在所述基底上形成第一介质层之前，所述半导体结构的制作方法还包括：
    于所述有源区上形成依次层叠设置的栅极氧化层和栅极金属层；
    于所述栅极金属层和所述栅极氧化层的侧壁上形成第一阻挡层，去除多余的第一阻挡层，形成栅极结构；
    对所述栅极结构两侧的所述有源区进行掺杂工艺，以在所述栅极结构的两侧形成源极区和漏极区。
  10. 根据权利要求7所述的半导体结构的制作方法，其中，在所述基底上形成第一介质层之前，所述半导体结构的制作方法还包括：
    在所述基底上形成位线结构。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，在所述基底上形成位线 结构，包括：
    在所述基底上形成第二介质层；
    在所述第二介质层上形成多个沿第一方向间隔设置的第一凹槽，所述第一凹槽的底端至少暴露出部分所述有源区；
    在所述第一凹槽的侧壁上形成隔离侧墙，所述第一凹槽内相邻的所述隔离侧墙之间形成第二凹槽；
    在所述第二凹槽内形成所述位线结构。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，在所述第二凹槽内形成位线结构，包括：
    在所述第二凹槽内形成依次层叠设置的过渡层、导电层和绝缘层，其中，所述过渡层靠近所述有源区设置。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，在所述第二凹槽内形成位线结构之前，所述半导体结构的制作方法还包括：
    在所述第二凹槽内形成位线接触结构，所述位线接触结构的顶面低于所述第二凹槽的顶面。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，在所述第二凹槽内形成位线接触结构之前，所述半导体结构的制作方法还包括：
    在所述基底内形成字线结构。
  15. 根据权利要求11-14任一项所述的半导体结构的制作方法，其中，在所述第一接触结构上形成第二接触孔，包括：
    在所述第一接触结构的顶面以及所述隔离侧墙的侧壁上形成预定厚度的初始介质层；
    去除位于所述第一接触结构顶面上的所述初始介质层，暴露所述第一接触结构的顶面，所述第一接触结构和相邻的所述隔离侧墙之间形成所述第二接触孔，其中所述第二接触孔在所述基底上的投影位于所述第一接触结构在所述基底上的投影内，且所述第二接触孔的孔径小于所述第一接触结构的孔径。
  16. 根据权利要求15所述的半导体结构的制作方法，其中，所述半导体结构的制作方法还包括：
    在所述第二接触结构上形成连接垫，其中，所述连接垫包括钨层。
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