WO2023077666A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2023077666A1
WO2023077666A1 PCT/CN2022/070400 CN2022070400W WO2023077666A1 WO 2023077666 A1 WO2023077666 A1 WO 2023077666A1 CN 2022070400 W CN2022070400 W CN 2022070400W WO 2023077666 A1 WO2023077666 A1 WO 2023077666A1
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Prior art keywords
layer
trench
spin
sacrificial
semiconductor structure
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PCT/CN2022/070400
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English (en)
French (fr)
Inventor
于业笑
陈龙阳
刘忠明
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长鑫存储技术有限公司
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Priority to US18/161,124 priority Critical patent/US20230180465A1/en
Publication of WO2023077666A1 publication Critical patent/WO2023077666A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present application relates to the field of semiconductor technology, in particular to a semiconductor structure and a manufacturing method thereof.
  • DRAM Dynamic random access memory
  • DRAM includes a plurality of storage cells, each of which includes a transistor and a capacitor.
  • the capacitor stores data information, and the transistor controls reading and writing of the data information in the capacitor.
  • the gate of the transistor is electrically connected with the word line (Word Line, referred to as WL), and the opening and closing of the transistor is controlled by the voltage on the word line; one of the source and the drain of the transistor is connected with the bit line (Bit Line, referred to as WL).
  • BL bit line
  • the other of the source and the drain is electrically connected to the capacitor, and the data information is stored or output through the bit line.
  • bit lines usually a plurality of bit lines arranged at intervals and extending along the first direction are first formed on the substrate, and then a first supporting layer is formed between adjacent bit lines, and the bit lines and the first supporting layer are surrounded to form a filling hole.
  • a first supporting layer is formed between adjacent bit lines, and the bit lines and the first supporting layer are surrounded to form a filling hole.
  • embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which are used to reduce damage to the bit line and ensure the performance of the bit line.
  • the first aspect of the embodiments of the present application provides a method for fabricating a semiconductor structure, which includes: forming a spin-coated hard mask layer on a substrate, wherein a plurality of active regions arranged at intervals are arranged in the substrate, and the A plurality of bit lines arranged at intervals and extending along a first direction are provided on the substrate, each of the bit lines is electrically connected to at least one of the active regions, and the spin-coated hard mask layer is filled between the bit lines and cover the bit line; remove part of the spin-coated hard mask layer to form a plurality of first channels arranged at intervals and extending along the second direction; form a first sacrificial layer in the first channel, the The first sacrificial layer is filled in the first trench; the spin-coated hard mask layer between the first sacrificial layers is removed to form a second trench; a first support layer is formed in the second trench , the first supporting layer is filled in the second channel; the first sacrificial layer is removed,
  • the feature that the spin-on hard mask layer is difficult to etch is used to make the spin-on hard mask layer difficult to etch.
  • the mask layer and the bit line have a higher selectivity ratio, thereby reducing the loss of the part of the bit line away from the substrate during subsequent etching, and ensuring the performance of the bit line.
  • the second aspect of the embodiments of the present application provides a semiconductor structure, which is obtained by the above-mentioned semiconductor structure manufacturing method, and thus at least has the advantage of less bit line loss.
  • a semiconductor structure which is obtained by the above-mentioned semiconductor structure manufacturing method, and thus at least has the advantage of less bit line loss.
  • Fig. 1 is the flowchart of the manufacturing method of the semiconductor structure in the embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a substrate and a bit line in an embodiment of the present application
  • FIG. 3 is a perspective view after forming a photoresist layer in the embodiment of the present application.
  • Fig. 4 is a schematic cross-sectional view at A-A in Fig. 3;
  • Fig. 5 is a perspective view after forming a first sacrificial layer in the embodiment of the present application.
  • Fig. 6 is a schematic cross-sectional view at B-B in Fig. 5;
  • FIG. 7 is a perspective view after forming a second channel in the embodiment of the present application.
  • Fig. 8 is a perspective view after forming the first supporting layer in the embodiment of the present application.
  • FIG. 9 is a perspective view after removing the remaining spin-coated hard mask layer in the embodiment of the present application.
  • Fig. 10 is a schematic cross-sectional view at C-C in Fig. 9;
  • FIG. 11 is a schematic structural diagram of the contact hole extending to the active region in the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram after forming a first trench in an embodiment of the present application.
  • Fig. 13 is a schematic structural diagram after forming the first filling layer in the embodiment of the present application.
  • FIG. 14 is a schematic structural diagram after exposing the second sacrificial layer in the embodiment of the present application.
  • FIG. 15 is a schematic structural view after forming the first etching groove in the embodiment of the present application.
  • FIG. 16 is a schematic structural view of the first etching groove penetrating through the silicon-containing anti-reflective layer in the embodiment of the present application;
  • FIG. 17 is a schematic structural diagram after forming a first channel in an embodiment of the present application.
  • Fig. 18 is a schematic structural view of the first intermediate groove formed in the embodiment of the present application.
  • FIG. 19 is a schematic structural diagram after forming a third sacrificial layer in the embodiment of the present application.
  • FIG. 20 is a schematic structural diagram after removing part of the third sacrificial layer in the embodiment of the present application.
  • FIG. 21 is a schematic structural diagram after forming a first sacrificial layer in an embodiment of the present application.
  • FIG. 22 is a schematic diagram of the structure after removing the film layer above the spin-coated hard mask layer in the embodiment of the present application.
  • FIG. 23 is a schematic structural view after forming the first conductive layer in the embodiment of the present application.
  • FIG. 24 is a schematic structural view of the formation of conductive pillars in the embodiment of the present application.
  • FIG. 25 is a schematic diagram of the structure after forming the first protective layer in the embodiment of the present application.
  • an embodiment of the present application provides a fabrication method of a semiconductor structure, by forming a spin-on hard mask layer filled between bit lines and covering the bit lines, using a spin-on hard mask
  • the layer and the bit line have a high selectivity ratio, thereby reducing the loss of the bit line during subsequent etching and ensuring the performance of the bit line.
  • an embodiment of the present application provides a method for manufacturing a semiconductor structure, the method at least including the following steps:
  • Step S101 forming a spin-on hard mask layer on the substrate, wherein the substrate is provided with a plurality of active regions arranged at intervals, and the substrate is provided with a plurality of bit lines arranged at intervals and extending along the first direction, each bit line The wires are electrically connected to at least one active area, and a spin-on hard mask layer is filled between and covers the bit lines.
  • the filling patterns in the drawings in the embodiments of the present application are only used to distinguish different structures in the drawings, and are not used to represent the materials of the structures in the drawings.
  • the substrate 100 is used to support the film layers formed on the substrate 100 , such as the bit line 150 and the spin-on hard mask layer 200 .
  • each active region 111 can be defined by shallow trench isolation 112 (Shallow Trench Isolation, STI for short). Specifically, a portion of the substrate 100 is removed to a predetermined depth through an etching process to form a groove surrounding the plurality of active regions 111 , and an insulating material is deposited in the groove to isolate the active regions 111 .
  • the insulating material may be silicon oxide or silicon nitride.
  • the base 100 may include a substrate 110 , an insulating layer 120 and a barrier layer 130 which are sequentially stacked.
  • the substrate 110 may be a semiconductor substrate 110, such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a germanium-arsenic substrate, a silicon-on-insulator (Silicon On Insulator, SOI for short) substrate or a germanium-on-insulator (Germanium On Insulator, referred to as GOI) substrate, etc.
  • the substrate 110 may be doped or non-doped.
  • the substrate 110 may be an N-type substrate or a P-type substrate.
  • the active region 111 is formed in the substrate 110 and exposed on the upper surface of the substrate 110 .
  • a plurality of word lines 113 are also formed in the substrate 110 at intervals. As shown in FIG. 4 , a plurality of word lines 113 extend along the second direction, and each word line 113 is insulated from the active region 111 .
  • the word line 113 may be a buried word line (Buried Word Line, BWL for short), and the active region 111 is arranged obliquely relative to the extending direction of the word line 113, so as to increase the arrangement density of the active region 111.
  • an insulating layer 120 is formed on the substrate 110 to cover the active region 111 to isolate and protect the active region 111 .
  • the material of the insulating layer 120 can be the same as that of the insulating material in the shallow trench isolation 112 . After the insulating material is deposited to form the shallow trench isolation 112 , the insulating material is deposited to form the insulating layer 120 to simplify the manufacturing steps of the semiconductor structure.
  • a barrier layer 130 is formed on the insulating layer 120 , and the barrier layer 130 corresponds to the bit line 150 .
  • the barrier layer 130 can be made of silicon nitride or silicon oxynitride, which can be used as an etching stop layer later to reduce the etching of the insulating layer 120 .
  • a plurality of contact holes are formed in the barrier layer 130 and the insulating layer 120 , and each contact hole exposes the active region 111 . Exemplarily, two contact holes correspond to one active region 111 , and each of the two contact holes exposes one end of the active region 111 .
  • bit lines 150 are arranged at intervals on the substrate 100 , the bit lines 150 extend along a first direction, and each bit line 150 is electrically connected to at least one active region 111 .
  • a bit line plug (Bit Line Contact) 140 is disposed in the contact hole, and the bit line plug 140 is in contact with the active region 111 .
  • the bit line plug 140 can be a plurality of columnar structures filled in the contact hole, or, as shown in FIG. 2 , the bit line plug 140 can also be a comb-shaped structure, and each tooth is filled in the contact hole.
  • the barrier layer 130 is also etched, so that the barrier layer 130 corresponds to the bit line plug 140, that is, the bit line plug 140 located outside the contact hole disposed on the barrier layer 130 . It can be understood that the A-A section shown in FIG. 4 is a plane between adjacent bit lines, and the barrier layer 130 is not cut in this plane.
  • the bit line 150 includes a second conductive layer 151 and a second supporting layer 152 covering the second conductive layer 151 .
  • the second conductive layer 151 extends along the first direction and is in contact with the bit line plug 140 , and the bit line 150 is electrically connected to the active region 111 through the bit line plug 140 .
  • the second support layer 152 may also cover the substrate 100 between the second conductive layers 151 .
  • an oxide layer 153 next to the second conductive layer 151 is also provided in the second support layer 152.
  • an oxide layer 153 is respectively provided on both sides of the second conductive layer 151, and the The material layer 153 is not in contact with the second conductive layer 151.
  • the oxide layer 153 is not shown in FIG. 3 .
  • the material of the bit line plug 140 can be polysilicon (poly-silicon), and the second conductive layer 151 can be a metal layer or a metal stack.
  • the second conductive layer 151 includes a The titanium nitride layer in contact with the line plug 140 and the tungsten layer on the titanium nitride layer, the second supporting layer 152 may be a nitride layer, such as a silicon nitride layer.
  • nitride, oxide, and nitride (Nitride-oxide-Nitride, NON for short) in sequence.
  • a spin-on hardmask layer 200 (Spin on Hardmask, SOH for short) is filled between the bit lines 150 and covers the bit lines 150 .
  • the spin-on hard mask layer 200 can have a larger selectivity ratio to the second support layer 152 of the bit line 150, so that the etching loss of the second support layer 152 can be reduced during the subsequent etching of the spin-on hard mask layer 200. is smaller, thereby reducing the loss of the bit line 150 and ensuring the performance of the bit line 150 .
  • the selection ratio of the spin-on hard mask layer 200 to the second supporting layer 152 is greater than or equal to 5.
  • Step S102 removing part of the spin-coated hard mask layer to form a plurality of first trenches arranged at intervals and extending along the second direction.
  • Part of the spin-on hard mask layer 200 (refer to FIG. 4 ) is removed by dry etching or wet etching to form a plurality of first trenches arranged at intervals and extending along the second direction.
  • the second direction has an angle with the first direction, for example, the second direction is perpendicular to the first direction.
  • the spin-on hard mask layer 200 is divided into multiple pieces by the first trenches.
  • each first channel includes a second trench located above the bit line and extending along the second direction, and a filling hole located between adjacent bit lines and connected to the second trench. That is, in the process of forming the first trench, a second trench is formed in the spin-on hard mask layer 200 above the bit lines, a filling hole is formed in the spin-on hard mask layer 200 between the bit lines, and the second trench The groove communicates with the filling hole located below the second trench.
  • Step S103 forming a first sacrificial layer in the first trench, and filling the first trench with the first sacrificial layer.
  • a first sacrificial layer 220 is deposited in the first trench, and the first sacrificial layer fills the first trench.
  • the first sacrificial layer 220 is formed by chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD), physical vapor deposition (Physical Vapor Deposition, referred to as PVD) or atomic layer deposition (Atomic Layer Deposition, referred to as ALD).
  • a sacrificial layer 220 can be made of oxide, such as silicon oxide, for subsequent removal.
  • Step S104 removing the spin-coated hard mask layer between the first sacrificial layer to form a second channel.
  • the spin-on hard mask layer 200 between the first sacrificial layers 220 is removed by etching. It can be understood that, the spin-on hard mask layer 200 is removed twice, the first trench is formed after removing part of the spin-on hard mask layer 200 for the first time, and the remaining spin-on hard mask layer 200 is removed for the second time.
  • a second trench 230 is formed. The shape of the second channel 230 is substantially the same as that of the first channel.
  • Step S105 forming a first support layer in the second trench, and filling the second trench with the first support layer.
  • a first support layer 240 is deposited in the second trench 230 , and the first support layer 240 fills the second trench 230 .
  • the material of the first supporting layer 240 can be the same as that of the second supporting layer 152 of the bit line 150 , both of which are insulating materials, such as silicon nitride.
  • Step S106 removing the first sacrificial layer, and extending the first channel between adjacent bit lines to the active area.
  • the first sacrificial layer 220 is removed by etching.
  • the first sacrificial layer 220 is removed by wet method using an acidic etchant.
  • the first sacrificial layer 220 has a larger The selection ratio of , so as to reduce the damage of the first support layer 240 .
  • the first channel 210 is exposed. As shown in FIG. 11 , the first channel 210 between adjacent bit lines 150 also extends to the active region 111 to expose the active region 111 within the first channel 210 .
  • the substrate 100 includes a substrate 110, an insulating layer 120 disposed on the substrate 110, and a barrier layer 130 disposed on the insulating layer in sequence, and multiple active regions are disposed in the substrate 110 111 , the insulating layer 120 covers the active region 111 .
  • removing the first sacrificial layer 220 and extending the first channel 210 between adjacent bit lines 150 to the active region 111 specifically includes:
  • the first sacrificial layer 220 is etched to expose the first channels 210, each of which includes a second trench 211 located above the bit line 150 and extending along the second direction, and The filling hole 212 is located between adjacent bit lines 150 and communicates with the second trench 211 .
  • the second support layer 152 extending along the second direction and the first support layer 240 extending along the first direction form the aforementioned filling hole 212 .
  • the insulating layer 120 is etched along the filling hole 212 of the first trench 210 , so that the filling hole 212 exposes the active region 111 .
  • the filling hole 212 penetrates the insulating layer 120 and extends to the active region 111, so that the active region 111 is exposed in the filling hole 212, so that the active region 111 and the conductive column 250 formed in the filling hole 212 are convenient. electrical connection.
  • the filling hole 212 also penetrates the second support layer 152, that is, the filling hole 212 penetrates the second support layer 152 and the insulating layer 120, and extends to the active region 111 .
  • the spin-on hard mask layer 200 filled between the bit lines 150 and covering the bit lines 150, the spin-on hard mask layer 200 and the bit line 150 (Refer to FIG. 2 )
  • the higher selectivity ratio reduces the loss of the portion of the bit line 150 away from the substrate 100 during subsequent etching, ensuring the performance of the bit line 150 .
  • removing part of the spin-coated hard mask layer to form a plurality of first trenches arranged at intervals and extending along the second direction may include the following steps:
  • Step S1021 forming an intermediate layer and a silicon-containing anti-reflection layer stacked in sequence on the spin-on hard mask layer.
  • the silicon-containing anti-reflection layer has a plurality of first trenches arranged at intervals and extending along the second direction.
  • an intermediate layer 300 may be formed on the spin-on hard mask layer 200 and cover the spin-on hard mask layer 200 through a deposition process.
  • a silicon-containing anti-reflective layer 400 (SiARC) is formed on the intermediate layer 300 through a deposition process and covers the intermediate layer 300 .
  • the silicon-containing anti-reflection layer 400 can also be formed on the intermediate layer 300 by a spin-coating process.
  • the material of the middle layer 300 may be amorphous carbon (Amorphous Carbon Layer, ACL for short).
  • the silicon-containing anti-reflection layer 400 has high hardness, and is not easy to collapse and deform when etching the first groove 410 or other structures of the silicon-containing anti-reflection layer 400 , and the pattern precision formed after etching is also good.
  • a plurality of first grooves 410 are formed in the silicon-containing antireflection layer 400 , and the plurality of first grooves 410 are arranged at intervals and extend along the second direction.
  • the first trench 410 may or may not penetrate the silicon-containing anti-reflection layer 400 .
  • the groove bottom of the first groove 410 is located at the silicon-containing anti-reflection layer 400, that is, the first groove 410 is formed on the upper part of the silicon-containing anti-reflection layer 400 away from the substrate 100, and the first groove is subsequently used 410 forming a first etching groove in the lower part of the silicon-containing anti-reflection layer 400, the width of the first etching groove is smaller than the width of the first groove 410, and the density of the first etching groove is greater than the density of the first groove 410 In order to further reduce the feature size of the semiconductor structure and improve the integration degree of the semiconductor structure.
  • Step S1022 forming a second sacrificial layer on the sidewall of the first trench, and forming a third trench by the second sacrificial layer located in the first trench.
  • a second sacrificial layer 420 is deposited on the sidewalls and bottom of the first trench 410 and the silicon-containing antireflection layer 400 , and the second sacrificial layer 420 covers the silicon-containing antireflection layer 400 away from
  • the surface on one side of the substrate 100 that is, the second sacrificial layer 420 is a whole layer, so as to facilitate the formation of the second sacrificial layer 420 .
  • the material of the second sacrificial layer 420 may be silicon oxide.
  • Step S1023 forming a first filling layer in the third trench.
  • a first filling layer 430 is deposited in the third trench, and the material of the first filling layer 430 may be a spin-on hard mask.
  • the first filling layer 430 is deposited in the third trench and on the second sacrificial layer 420 .
  • the first filling layer 430 is filled in the third trench and covers the second sacrificial layer 420 .
  • part of the first filling layer 430 and part of the second sacrificial layer 420 are removed to expose the second sacrificial layer 420 on the sidewall of the first trench 410 .
  • the second sacrificial layer 420 and the first filling layer 430 located on the surface of the silicon-containing anti-reflection layer 400 facing away from the substrate 100 are removed to expose the surface of the silicon-containing anti-reflection layer 400 and the side walls of the first trench 410.
  • the second sacrificial layer 420 For example, part of the first filling layer 430 and part of the second sacrificial layer 420 are removed through an etching process or a planarization process.
  • Step S1024 removing the second sacrificial layer on the sidewall of the first trench to form a first etching groove.
  • the second sacrificial layer 420 is etched to form a first etching groove 440 . It can be understood that, during the process of etching the second sacrificial layer 420 , part of the silicon-containing anti-reflection layer 400 and the first filling layer 430 will also be etched away. The bottom of the first etching groove 440 exposes the silicon-containing anti-reflection layer 400 .
  • the selection ratios of the silicon-containing anti-reflection layer 400 and the first filling layer 430 are different. After the etching is completed, there is a certain height between the silicon-containing anti-reflection layer 400 and the first filling layer 430 Difference. Exemplarily, the etching rate of the silicon-containing anti-reflection layer 400 is slower than that of the first filling layer 430, and after the second sacrificial layer 420 is etched away, along the height direction, that is, along the direction perpendicular to the substrate 10 The silicon-containing anti-reflection layer 400 is etched to remove less height, and the first filling layer 430 is etched to remove more height. As shown in FIG. 15 , the surface of the remaining silicon-containing anti-reflection layer 400 facing away from the substrate 110 is higher than the surface of the remaining first filling layer 430 facing away from the substrate 110 .
  • Step S1025 Etching along the first etching groove to the spin-on hard mask layer to form a first channel.
  • the silicon-containing anti-reflection layer 400, the intermediate layer 300 and the spin-on hard mask layer 200 are etched along the first etching groove 440, and the first channel 210 is formed in the spin-on hard mask layer 200.
  • the silicon-containing anti-reflection layer 400 is used as a transition layer for etching patterns to reduce the size of the first etching groove 440, and no extreme ultraviolet (EUV) is used in this process.
  • EUV extreme ultraviolet
  • a stacked interlayer and a silicon-containing antireflection layer are formed on the spin-coated hard mask layer, and the silicon-containing antireflection layer has a plurality of intervals.
  • the step of arranging and extending the first groove along the second direction includes:
  • Step a forming a first mask layer, a second mask layer and a photoresist layer stacked in sequence on the silicon-containing anti-reflection layer.
  • a first mask layer 500 is deposited on the silicon-containing anti-reflection layer 400, the first mask layer 500 covers the silicon-containing anti-reflection layer 400, and a second mask is deposited on the first mask layer 500 layer 600, the second mask layer 600 covers the first mask layer 500, and spin coating (Spin on Coating), spray coating (Spray Coating) or rinse coating (Brush Coating) etc. on the first mask layer 500 to form photolithography Adhesive layer 700.
  • the first mask layer 500 includes a first base layer 510 disposed on the silicon-containing anti-reflection layer 400 , and a first anti-reflection layer disposed on the first base layer 510 Layer 520 ;
  • the second mask layer 600 includes a second base layer 610 disposed on the first anti-reflection layer 520 , and a second anti-reflection layer 620 disposed on the second base layer 610 .
  • the silicon-containing anti-reflection layer 400 , the first base layer 510 , the first anti-reflection layer 520 , the second base layer 610 , the second anti-reflection layer 620 and the photoresist layer 700 are sequentially stacked along the direction away from the substrate 100 .
  • the photoresist layer 700 is a patterned photoresist (Photo Resist, referred to as PR) layer, that is, the photoresist layer 700 has a preset pattern formed by processes such as exposure and development.
  • the photoresist layer 700 exposes a portion of the second anti-reflection layer 620 .
  • the second anti-reflection layer 620 can absorb light used for exposing the photoresist layer 700 , thereby reducing or preventing reflection of light on the second anti-reflection layer 620 , so as to improve the accuracy of the preset pattern of the photoresist layer 700 .
  • the material of the first base layer 510 is the same as that of the second base layer 610 , and the material of the first anti-reflection layer 520 and the second anti-reflection layer 620 is the same, so as to reduce the types of materials used in the manufacturing process of the semiconductor structure.
  • the material of the first base layer 510 and the second base layer 610 may be a spin-on hard mask composition, and the material of the first anti-reflection layer 520 and the second anti-reflection layer 620 may be silicon oxynitride.
  • Step b using the photoresist layer as a mask, etching the second mask layer, forming a plurality of first intermediate grooves arranged at intervals and extending along the second direction in the second mask layer.
  • the photoresist layer 700 is used as a mask to etch the second mask layer 600, the part not covered by the photoresist layer 700 in the second mask layer 600 is removed, and the second mask layer The portion of 600 covered by photoresist layer 700 remains.
  • a plurality of first intermediate grooves 630 arranged at intervals and extending along the second direction are formed in the second mask layer 600 , and the first intermediate grooves 630 penetrate through the second mask layer 600 to expose the first mask layer 500 . In this way, the predetermined pattern in the photoresist layer 700 is transferred to the second mask layer 600 , and the first intermediate groove 630 is formed in the second mask layer 600 .
  • Step c Depositing a third sacrificial layer on the sidewalls and bottom of the first middle groove, and on the second mask layer, the third sacrificial layer located in the first middle groove forms a second middle groove.
  • a third sacrificial layer 640 is deposited on the sidewall and bottom of the first intermediate groove 630, and the second mask layer 600, for example, the third sacrificial layer 640 is formed by an atomic layer deposition process, so as to A third sacrificial layer 640 with better quality is formed.
  • the material of the third sacrificial layer 640 may be silicon oxide.
  • Step d removing the third sacrificial layer located on the top of the second mask layer and the bottom of the second intermediate groove, and retaining the third sacrificial layer located on the sidewall of the first intermediate groove.
  • the third sacrificial layer 640 located on the top of the second mask layer 600 and the bottom of the second intermediate trench 650 is removed by an etching process, and the third sacrificial layer 640 located on the sidewall of the first intermediate trench 630 remains. After etching, the second mask layer 600 and the first mask layer 500 are exposed. That is, the third sacrificial layer 640 located on the sidewall of the first middle trench 630 is formed by deposition and etching back.
  • Step e using the remaining third sacrificial layer as a mask, etching the second mask layer, the first mask layer and the silicon-containing anti-reflection layer to form a first trench.
  • the second mask layer 600, the first mask layer 500 and the silicon-containing anti-reflection layer 400 located between the third sacrificial layer 640 are removed by etching, and the first silicon-containing anti-reflection layer 400 is formed in the silicon-containing anti-reflection layer 400. a groove 410 . After the first trench 410 is formed, other film layers on the silicon-containing anti-reflection layer 400 are removed to expose the silicon-containing anti-reflection layer 400 .
  • an intermediate layer and a silicon-containing anti-reflection layer are formed in a stacked manner, and the silicon-containing anti-reflection layer has a plurality of first trenches arranged at intervals and extending along the second direction. Formed in other ways, in some other possible examples, it includes the following steps:
  • Step a' forming a first mask layer, a second mask layer and a photoresist layer stacked in sequence on the silicon-containing anti-reflection layer.
  • Step b' using the photoresist layer as a mask, etching the second mask layer, forming a plurality of first intermediate grooves arranged at intervals and extending along the second direction in the second mask layer.
  • Step c' Depositing a third sacrificial layer on the side walls and bottom of the first middle groove, and on the second mask layer, the third sacrifice layer located in the first middle groove forms a second middle groove.
  • Step a', step b', and step c' in this example can respectively refer to step a, step b, and step c in the above example, and will not be repeated here.
  • Step d' forming a second filling layer on the second intermediate groove and the third sacrificial layer.
  • a second filling layer is formed through a deposition process, and the second filling layer fills up the second middle groove and covers the third sacrificial layer.
  • the material of the third filling layer may be a spin-on hard mask composition.
  • Step e' removing part of the second filling layer and part of the third sacrificial layer to expose the third sacrificial layer on the sidewall of the first intermediate layer.
  • part of the second filling layer and part of the third sacrificial layer on the surface of the second mask layer away from the substrate are removed to expose the surface and the sidewall of the first intermediate layer.
  • the third sacrificial layer is
  • Step f' etching the third sacrificial layer, the first mask layer and the silicon-containing anti-reflection layer to form a first trench.
  • the film layer above the silicon-containing anti-reflection layer is also removed at least in part. The remaining film layer can be removed separately through an etching process, and after the remaining film layer is removed, the silicon-containing anti-reflection layer is exposed.
  • an intermediate layer and a silicon-containing anti-reflection layer are formed in a stacked manner, and the silicon-containing anti-reflection layer has a plurality of different examples of first trenches arranged at intervals and extending along the second direction.
  • the patterns of the photoresist layer are different, so as to ensure that the positions of the first grooves finally formed are the same.
  • the first trench 410 is formed in the silicon-containing anti-reflection layer 400 through a self-aligned double patterning (SADP) process, and the characteristic size of the formed first trench 410 is decrease, increase density.
  • SADP self-aligned double patterning
  • the self-aligned double patterning process is performed again, so that the feature size of the first etching groove 440 is further reduced and the density is further increased. Therefore, the integration degree of the subsequently formed semiconductor structure is further improved.
  • a second sacrificial layer is deposited on the sidewall and bottom of the first trench, and on the silicon-containing anti-reflection layer, and correspondingly, on the third trench
  • the step of forming the first filling layer includes:
  • a first filling layer 430 is deposited in the third trench and on the second sacrificial layer 420 . As shown in FIG. 13 , the first filling layer 430 fills the third trench and covers the second sacrificial layer 420 , that is, the surface of the first filling layer 430 facing away from the substrate 100 is higher than the surface of the second sacrificial layer 420 facing away from the substrate 100 .
  • part of the first filling layer 430 and part of the second sacrificial layer 420 are removed to expose the second sacrificial layer 420 on the sidewall of the first trench 410 .
  • part of the first filling layer 430 and part of the second sacrificial layer 420 are removed through planarization, and the silicon-containing anti-reflection layer 400 and the second sacrificial layer 420 are exposed.
  • the step of forming the first sacrificial layer in the first trench includes: depositing the first sacrificial layer 220 in the first etching groove and in the first trench 210 .
  • the first sacrificial layer 220 is filled in the first trench 210 and the first etch groove, and may also cover the intermediate layer 300 or the silicon-containing anti-reflection layer 400 . It can be understood that, during the process of etching the spin-coated hard mask layer 200 to form the first channel 210, part of the silicon-containing anti-reflection layer 400 will also be etched away.
  • the first sacrificial layer 220 covers the silicon-containing anti-reflection layer 400; when the silicon-containing anti-reflection layer 400 is completely removed, the middle layer 300 is exposed, and the first sacrificial layer 220 covers the middle Layer 300.
  • the method further includes: removing the intermediate layer, the first sacrificial layer and the silicon-containing anti-reflection layer located above the spin-on hard mask layer, to expose the spin-on hardmask layer.
  • the intermediate layer, the first sacrificial layer and the silicon-containing anti-reflection layer located above the spin-on hard mask layer to expose the spin-on hardmask layer.
  • other film layers above the spin-on hard mask layer 200 are removed through a planarization process to expose the spin-on hard mask layer 200 , which facilitates subsequent removal of the spin-on hard mask layer 200 .
  • the first sacrificial layer is removed to expose the first channel, and after the step of extending the filling hole of the first channel to the active region, it further includes: forming a conductive pillar in the filling hole, the conductive pillar The active area is electrically connected.
  • the conductive pillar 250 is in contact with the active region 111 to realize the electrical connection between the conductive pillar 250 and the active region 111 .
  • a conductive post 250 is disposed in each filling hole 212 , and the conductive posts 250 are not connected to each other.
  • An active area 111 and a word line 113 are disposed in the substrate 110 , and the word line 113 is insulated from the active area 111 and staggered from the conductive pillar 250 .
  • the word line 113 passes through the middle region of the active region 111 , and the conductive pillar 250 is electrically connected to the end region of the active region 111 .
  • forming a conductive pillar 250 in the filling hole 212, and electrically connecting the conductive pillar 250 to the active region 111 may include:
  • a first conductive layer 251 is deposited in the first trench 210 and on the first supporting layer 240, the first conductive layer 251 is filled in the first trench 210 and covers the first supporting layer 240, the first conductive layer 251 is connected with the active Region 111 is electrically connected. As shown in FIG. 11 and FIG. 23 , the first conductive layer 251 is filled in the first trench 210 and covers the first supporting layer 240 .
  • the material of the first conductive layer 251 may be polysilicon.
  • the first conductive layer 251 is etched to retain a part of the first conductive layer 251 located in the filling hole 212 , and the remaining first conductive layer 251 forms a plurality of conductive columns 250 .
  • the first conductive layer 251 on the bit line and the first conductive layer 251 on the filled hole 212 are removed, and the first conductive layer 251 on the bottom of the filled hole 212 remains.
  • the remaining first conductive layer 251 is separated into multiple conductive layers by the first supporting layer 240 and the bit line, and the conductive columns 250 are arranged at intervals and are not connected to each other.
  • at least the first conductive layer 251 on the second support layer 152 of the bit line is removed, so as to isolate the first conductive layer 251 into multiple conductive layers.
  • a protective layer 260 is deposited on the conductive pillar 250 , and the protective layer 260 covers the surface of the conductive pillar 250 away from the substrate 100 .
  • the protection layer 260 can be made of nitride, such as silicon nitride. The thickness of the protective layer 260 is relatively thin, for example, the protective layer 260 can reduce or prevent the conductive pillars 250 from being oxidized when exposed to the air.
  • the embodiment of the present application also provides a semiconductor structure, which is obtained by the above-mentioned manufacturing method of the semiconductor structure, and thus at least has the advantage of less loss of the bit line 150 , the specific effects refer to the above, and will not be repeated here.

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Abstract

本申请提供一种半导体结构及其制作方法，涉及半导体技术领域，用于解决位线损失较多的技术问题，该半导体结构的制作方法包括：在基底上形成旋涂硬掩模层，基底内设置有多个间隔的有源区，基底上设置有多条间隔且沿第一方向延伸的位线，每条位线至少电连接一个有源区，旋涂硬掩模层填充在位线之间并覆盖位线；去除部分旋涂硬掩模层，形成多条间隔设置的第一沟道；在第一沟道内形成第一牺牲层；去除第一牺牲层之间的旋涂硬掩模层，形成第二沟道；在第二沟道内形成第一支撑层；去除第一牺牲层，并将位于相邻位线之间的第一沟道延伸至有源区。利用旋涂硬掩模层减少后续刻蚀中位线的损失。

Description

半导体结构及其制作方法
本申请要求于2021年11月08日提交中国专利局、申请号为202111311525.3、申请名称为“半导体结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
随着半导体技术的发展，半导体结构的应用越来越广泛。动态随机存储器(Dynamic Random Access Memory，简称DRAM)逐渐成为电子设备中常用的半导体存储器件。动态随机存储器包括多个存储单元，每个存储单元包括晶体管和电容器。电容器存储数据信息，晶体管控制电容器中的数据信息的读写。其中，晶体管的栅极与字线(Word Line，简称WL)电连接，通过字线上的电压控制晶体管的开启和关闭；晶体管的源极和漏极中的一个与位线(Bit Line，简称BL)电连接，源极和漏极中的另一个与电容器电连接，通过位线对数据信息进行存储或者输出。
相关技术中，通常先在基底上形成沿多条间隔设置且沿第一方向延伸的位线，再在相邻的位线之间形成第一支撑层，位线与第一支撑层围合成填充孔。然而，形成填充孔过程中，位线的远离基底的部分损失较多，影响位线的性能。
发明内容
鉴于上述问题，本申请实施例提供一种半导体结构及其制作方法，用于减少位线的损伤，保证位线的性能。
本申请实施例的第一方面提供一种半导体结构的制作方法，其包括：在基底上形成旋涂硬掩模层，其中，所述基底内设置有多个间隔设置的有源区，所述基底上设置有多条间隔设置且沿第一方向延伸的位线，每条所述位线至少电连接一个所述有源区，所述旋涂硬掩模层填充在所述位线之间并覆盖所述位线；去除部分所述旋涂硬掩模层，形成多条间隔设置且沿第二方向延伸的第一沟道；在所述第一沟道内形成第一牺牲层，所述第一牺牲层填充于所述第一沟道内；去除所述第一牺牲层之间的所述旋涂硬掩模层，形成第二沟道；在所述第二沟道内形成第一支撑层，所述第一支撑层填充于所述 第二沟道内；去除所述第一牺牲层，并将位于相邻所述位线之间的所述第一沟道延伸至所述有源区。
本申请实施例提供的半导体结构的制作方法至少具有如下优点：
本申请实施例中的半导体结构的制作方法，通过形成填充在位线之间并覆盖位线的旋涂硬掩模层，利用旋涂硬掩模层较难刻蚀的特点，使得旋涂硬掩模层与位线具有较高的选择比，从而减少后续刻蚀时位线远离基底的部分的损失，保证位线的性能。
本申请实施例的第二方面提供一种半导体结构，其通过上述的半导体结构的制作方法获得，因而至少具有位线损失少的优点，具体效果参照上文所述，在此不再赘述。
附图说明
图1为本申请实施例中的半导体结构的制作方法的流程图；
图2为本申请实施例中的基底和位线的结构示意图；
图3为本申请实施例中的形成光刻胶层后的立体图；
图4为图3中A-A处的截面示意图；
图5为本申请实施例中的形成第一牺牲层后的立体图；
图6为图5中B-B处的截面示意图；
图7为本申请实施例中的形成第二沟道后的立体图；
图8为本申请实施例中的形成第一支撑层后的立体图；
图9为本申请实施例中的去除剩余的旋涂硬掩模层后的立体图；
图10为图9中C-C处的截面示意图；
图11为本申请实施例中的接触孔延伸至有源区后的结构示意图；
图12为本申请实施例中的形成第一沟槽后的结构示意图；
图13为本申请实施例中的形成第一填充层后的结构示意图；
图14为本申请实施例中的暴露第二牺牲层后的结构示意图；
图15为本申请实施例中的形成第一刻蚀槽后的结构示意图；
图16为本申请实施例中的第一刻蚀槽贯穿含硅抗反射层的结构示意图；
图17为本申请实施例中的形成第一沟道后的结构示意图；
图18为本申请实施例中的形成第一中间槽后的结构示意图；
图19为本申请实施例中的形成第三牺牲层后的结构示意图；
图20为本申请实施例中的去除部分第三牺牲层后的结构示意图；
图21为本申请实施例中的形成第一牺牲层后的结构示意图；
图22为本申请实施例中的去除旋涂硬掩模层上方的膜层后的结构示意图；
图23为本申请实施例中的形成第一导电层后的结构示意图；
图24为本申请实施例中的形成导电柱后的结构示意图；
图25为本申请实施例中的形成第一保护层后的结构示意图。
具体实施方式
为了减少半导体结构制作过程中的位线损失，本申请实施例提供一个半导体结构的制作方法，通过形成填充在位线之间并覆盖位线的旋涂硬掩模层，利用旋涂硬掩模层与位线具有较高的选择比，从而减少后续刻蚀时位线的损失，保证位线的性能。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
参考图1，本申请实施例提供一种半导体结构的制作方法，该制作方法至少包括以下步骤：
步骤S101：在基底上形成旋涂硬掩模层，其中，基底内设置有多个间隔设置的有源区，基底上设置有多条间隔设置且沿第一方向延伸的位线，每条位线至少电连接一个有源区，旋涂硬掩模层填充在位线之间并覆盖位线。
参考图2至图4，本申请实施例中的附图中的填充图案仅用于区分该附图中的不同的结构，不用于表示该附图中的各结构的材质。如图2至图4所示，基底100用于支撑形成在基底100上的膜层，例如位线150和旋涂硬掩模层200。
如图2至图4所示，基底100内设置有多个间隔设置的有源区111。各有源区111可以通过浅沟槽隔离112(Shallow Trench Isolation，简称STI)定义出来。具体的，通过刻蚀工艺去除部分基底100至预设深度，以形成环绕多个有源区111的凹槽，再在凹槽内沉积绝缘材料，从而将各有源区111之间隔离。绝缘材料可以为氧化硅或者氮化硅等。
示例性的，基底100可以包括依次层叠设置的衬底110、绝缘层120和阻挡层130。其中，衬底110可以为半导体衬底110，例如硅衬底、锗衬底、硅锗衬底、锗砷衬底、绝缘体上硅(Silicon On Insulator，简称SOI)衬底或者绝缘体上锗(Germanium On Insulator，简称GOI)衬底等。衬底110可以为掺杂或者非掺杂，示例性的，衬底110可以为N型衬底或者P型衬底。
上述有源区111形成在衬底110内，且暴露于衬底110的上表面。衬底110内还 形成有多条间隔设置的字线113。如图4所示，多个字线113沿第二方向延伸，各字线113与有源区111之间绝缘设置。其中，字线113可以为埋入式字线(Buried Word Line，简称BWL)，有源区111相对于字线113的延伸方向倾斜设置，以增加有源区111的排布密度。
继续参考图2和图3，绝缘层120形成在衬底110上，覆盖有源区111，以对有源区111进行隔离和保护。绝缘层120的材质可以与浅沟槽隔离112中的绝缘材料相同，在沉积绝缘材料形成浅沟槽隔离112后，继续沉积该绝缘材料形成绝缘层120，以简化半导体结构的制作步骤。
阻挡层130形成在绝缘层120上，阻挡层130与位线150相对应。阻挡层130的材质可以为氮化硅或者氮氧化硅，后续可用作刻蚀停止层，减少绝缘层120的刻蚀。阻挡层130和绝缘层120中形成有多个接触孔，各接触孔以暴露有源区111。示例性的，两个接触孔对应一个有源区111，这两个接触孔的每个接触孔暴露有源区111的一端。
继续参考图2和图3，基底100上设置有多条间隔设置的位线150，各位线150沿第一方向延伸的，每条位线150至少电连接一个有源区111。示例性的，接触孔内设置有位线插塞(Bit Line Contact)140，位线插塞140与有源区111相接触。位线插塞140可以为多个填充在接触孔内的柱状结构，或者，如图2所示，位线插塞140还可以为梳齿状结构，各齿填充在接触孔内。在位线插塞140和位线150的刻蚀形成过程中，也对阻挡层130进行刻蚀，使得阻挡层130与位线插塞140相对应，即位于接触孔外的位线插塞140设置在阻挡层130上。可以理解的是，图4所示的A-A截面为位于相邻位线之间的平面，该平面内没有截得阻挡层130。
继续参考图2和图3，在一些可能的示例中，位线150包括第二导电层151，以及覆盖第二导电层151的第二支撑层152。第二导电层151沿第一方向延伸且与位线插塞140相接触，通过位线插塞140实现位线150与有源区111的电连接。如图2和图3所示，第二支撑层152还可以覆盖第二导电层151之间的基底100。
如图2所示，第二支撑层152内还设置有位于第二导电层151旁侧的氧化物层153，例如，第二导电层151的两侧分别设置有一个氧化物层153，且氧化物层153与第二导电层151不接触。图3中未画出氧化物层153。
其中，如图2所示，位线插塞140的材质可以为多晶硅(poly-silicon)，第二导电层151可以为金属层，也可以为金属叠层，例如第二导电层151包括与位线插塞140相接触的氮化钛层，以及位于氮化钛层上的钨层，第二支撑层152可以为氮化物层，例如氮化硅层。沿远离第二导电层151的侧壁的方向，依次为氮化物、氧化物、氮化 物(Nitride-oxide-Nitride，简称NON)。
参考图3和图4，旋涂硬掩模层200(Spin on Hardmask，简称SOH)填充在位线150之间并覆盖位线150。旋涂硬掩模层200可以与位线150的第二支撑层152具有较大的选择比，以在后续刻蚀旋涂硬掩模层200的过程中，第二支撑层152的刻蚀损失较小，从而减少位线150的损失，保证位线150的性能。示例性的，旋涂硬掩模层200与第二支撑层152的选择比大于或者等于5。
步骤S102：去除部分旋涂硬掩模层，形成多条间隔设置且沿第二方向延伸的第一沟道。
干法刻蚀或者湿法刻蚀去除部分旋涂硬掩模层200(参考图4)，形成多条间隔设置且沿第二方向延伸的第一沟道。第二方向与第一方向具有角度，例如第二方向与第一方向垂直。形成第一沟道后，旋涂硬掩模层200被第一沟道分隔成多块。
可以理解的是，每条第一沟道包括位于位线上方且沿第二方向延伸的第二沟槽，以及位于相邻位线之间且与第二沟槽连通的填充孔。即形成第一沟道的过程中，位线上方的旋涂硬掩模层200中形成了第二沟槽，位线之间的旋涂硬掩模层200中形成了填充孔，第二沟槽与位于第二沟槽下方的填充孔相连通。
步骤S103：在第一沟道内形成第一牺牲层，第一牺牲层填充于第一沟道内。
参考图5和图6，在第一沟道内沉积第一牺牲层220，第一牺牲层填充满第一沟道。示例性的，通过化学气相沉积(Chemical Vapor Deposition，简称CVD)、物理气相沉积(Physical Vapor Deposition，简称PVD)或者原子层沉积(Atomic Layer Deposition，简称ALD)等工艺形成第一牺牲层220，第一牺牲层220的材质可以为氧化物，例如氧化硅，以便于后续去除。
步骤S104：去除第一牺牲层之间的旋涂硬掩模层，形成第二沟道。
参考图7，形成第一牺牲层220后，刻蚀去除第一牺牲层220之间的旋涂硬掩模层200。可以理解的是，旋涂硬掩模层200分两次去除，第一次去除部分旋涂硬掩模层200后形成第一沟道，第二次去除剩余的旋涂硬掩模层200后形成第二沟道230。第二沟道230的形状与第一沟道的形状大致相同。
步骤S105：在第二沟道内形成第一支撑层，第一支撑层填充于第二沟道内。
参考图7和图8，在第二沟道230内沉积第一支撑层240，第一支撑层240填充满第二沟道230。第一支撑层240的材质可以与位线150的第二支撑层152的材质相同，均为绝缘材料，例如氮化硅。
步骤S106：去除第一牺牲层，并将位于相邻位线之间的第一沟道延伸至有源区。
参考图8至图11，刻蚀去除第一牺牲层220，示例性的，利用酸性刻蚀剂湿法去 除第一牺牲层220，第一牺牲层220相较于第一支撑层240具有较大的选择比，以减少第一支撑层240的损伤。去除第一牺牲层220后，第一沟道210暴露。如图11所示，位于相邻位线150之间的第一沟道210还延伸至有源区111，以在第一沟道210内暴露有源区111。
在一种可能的实施例中，基底100包括依次衬底110、设置在衬底110上的绝缘层120，以及设置在绝缘层上的阻挡层130，衬底110内设置有多个有源区111，绝缘层120覆盖有源区111。相应的，去除第一牺牲层220，并将位于相邻位线150之间的第一沟道210延伸至有源区111具体包括：
参考图8至图10，刻蚀第一牺牲层220，以暴露第一沟道210，每条第一沟道210包括位于位线150上方且沿第二方向延伸的第二沟槽211，以及位于相邻位线150之间且与第二沟槽211连通的填充孔212。如图9和图10所示，沿第二方向延伸的第二支撑层152和沿第一方向延伸的第一支撑层240围合成上述填充孔212。
参考图11，再沿第一沟道210的填充孔212刻蚀绝缘层120，以使填充孔212暴露有源区111。如图11所示填充孔212贯穿绝缘层120，并延伸至有源区111，以使有源区111暴露在填充孔212内，便于有源区111与形成在填充孔212内的导电柱250电连接。需要说明的是，当第二支撑层152还覆盖基底100时，填充孔212还贯穿第二支撑层152，即填充孔212贯穿第二支撑层152和绝缘层120，并延伸至有源区111。
综上，本申请实施例中的半导体结构的制作方法，通过形成填充在位线150之间并覆盖位线150的旋涂硬掩模层200，利用旋涂硬掩模层200与位线150(参考图2)较高的选择比，从而减少后续刻蚀时位线150远离基底100的部分的损失，保证位线150的性能。
在一些可能的示例中，参考图12至图17，去除部分旋涂硬掩模层，形成多条间隔设置且沿第二方向延伸的第一沟道(步骤S102)可以包括以下步骤：
步骤S1021：在旋涂硬掩模层上形成依次层叠设置的中间层和含硅抗反射层，含硅抗反射层具有多个间隔设置且沿第二方向延伸的第一沟槽。
参考图12，中间层300可以通过沉积工艺形成在旋涂硬掩模层200上，并覆盖旋涂硬掩模层200。含硅抗反射层400(SiARC)通过沉积工艺形成在中间层300上，并覆盖中间层300。当然，含硅抗反射层400也可以通过旋涂工艺形成在中间层300上。其中，中间层300的材质可以为非晶碳(Amorphous Carbon Layer，简称ACL)。含硅抗反射层400的硬度较高，在刻蚀含硅抗反射层400的第一沟槽410或者其他结构时不易坍塌和变形，刻蚀后所形成的图案精度也较好。
如图12所示，第一沟槽410形成在含硅抗反射层400中且数量为多条，多条第一 沟槽410间隔设置并沿第二方向延伸。第一沟槽410可以贯穿含硅抗反射层400，也可以不贯穿含硅抗反射层400。如图12所示，第一沟槽410的槽底位于含硅抗反射层400，即第一沟槽410形成在含硅抗反射层400远离基底100的上部，并在后续利用第一沟槽410在含硅抗反射层400的下部中形成第一刻蚀槽，第一刻蚀槽的宽度小于第一沟槽410的宽度，且第一刻蚀槽的密度大于第一沟槽410的密度，以使半导体结构的特征尺寸进一步缩小，提高半导体结构的集成度。
步骤S1022：在第一沟槽的侧壁上形成第二牺牲层，位于第一沟槽内的第二牺牲层围合成第三沟槽。
具体的，参考图12和13，在第一沟槽410的侧壁和槽底，以及含硅抗反射层400上沉积第二牺牲层420，第二牺牲层420覆盖含硅抗反射层400背离基底100的一侧的表面，即第二牺牲层420为一个整层，以便于第二牺牲层420的形成。第二牺牲层420的材质可以为氧化硅。
步骤S1023：在第三沟槽内形成第一填充层。
继续参考图12和图13，在第三沟槽内沉积第一填充层430，第一填充层430的材质可以为旋涂硬掩模物。在一些可能的示例中，如图13所示，在第三沟槽内，以及第二牺牲层420上沉积第一填充层430。第一填充层430填充在第三沟槽内，且覆盖第二牺牲层420。
参考图14，再去除部分第一填充层430和部分第二牺牲层420，以暴露位于第一沟槽410的侧壁上的第二牺牲层420。具体的，去除位于含硅抗反射层400背离基底100的表面上的第二牺牲层420和第一填充层430，以暴露含硅抗反射层400的表面和位于第一沟槽410侧壁上的第二牺牲层420。例如，通过刻蚀工艺或者平坦化处理工艺去除部分第一填充层430和部分第二牺牲层420。
步骤S1024：去除位于第一沟槽的侧壁上的第二牺牲层，形成第一刻蚀槽。
参考图15，刻蚀第二牺牲层420，形成第一刻蚀槽440。可以理解的是，在刻蚀第二牺牲层420的过程中，也会刻蚀去除部分含硅抗反射层400和第一填充层430。第一刻蚀槽440的槽底暴露含硅抗反射层400。
需要说明的是，继续参照图15，含硅抗反射层400和第一填充层430的选择比不同，刻蚀结束后，含硅抗反射层400与第一填充层430之间具有一定的高度差。示例性的，含硅抗反射层400的刻蚀速率慢于第一填充层430的刻蚀速率，当第二牺牲层420刻蚀去除后，沿高度方向，即沿垂直于衬底10的方向，含硅抗反射层400刻蚀去除的高度较少，第一填充层430刻蚀去除的高度较多。如图15所示，剩余的含硅抗反射层400背离衬底110的表面，高于剩余的第一填充层430背离衬底110的表面。
步骤S1025：沿第一刻蚀槽刻蚀至旋涂硬掩模层，以形成第一沟道。
参考图16和图17，沿第一刻蚀槽440刻蚀含硅抗反射层400、中间层300和旋涂硬掩模层200，在旋涂硬掩模层200中形成第一沟道210。本申请实施例中，利用含硅抗反射层400作为刻蚀图形的转接层，以缩小第一刻蚀槽440的尺寸，且在此过程中没有使用极紫外线(Extreme Ultra Violet，简称EUV)光刻工艺，减少了生产成本。
在一些可能的实施例中，参考图3、图4、图18至图20在旋涂硬掩模层上形成层叠设置的中间层和含硅抗反射层，含硅抗反射层具有多个间隔设置且沿第二方向延伸的第一沟槽的步骤包括：
步骤a：在含硅抗反射层上形成依次层叠设置的第一掩膜层、第二掩膜层和光刻胶层。
参考图3和图4，在含硅抗反射层400上沉积第一掩膜层500，第一掩膜层500覆盖含硅抗反射层400，在第一掩膜层500上沉积第二掩膜层600，第二掩膜层600覆盖第一掩膜层500，并在第一掩膜层500上旋涂(Spin on Coating)、喷涂(Spray Coating)或者涮涂(Brush Coating)等形成光刻胶层700。
示例性的，如图3和图4所示，第一掩膜层500包括设置在含硅抗反射层400上的第一基础层510，以及设置在第一基础层510上的第一抗反射层520；第二掩膜层600包括设置在第一抗反射层520上的第二基础层610，以及设置在第二基础层610上的第二抗反射层620。即含硅抗反射层400、第一基础层510、第一抗反射层520、第二基础层610、第二抗反射层620和光刻胶层700沿远离基底100的方向依次层叠设置。
其中，继续参考图3和图4，光刻胶层700为图案化后的光刻胶(Photo Resist，简称PR)层，即光刻胶层700通过曝光、显影等工艺形成有预设图案。光刻胶层700暴露有部分第二抗反射层620。第二抗反射层620可以吸收用于光刻胶层700曝光时的光线，从而减少或者防止光线在第二抗反射层620发生反射，以提高光刻胶层700的预设图案的准确性。第一基础层510的材质与第二基础层610的材质相同，第一抗反射层520和第二抗反射层620的材质相同，以减少半导体结构的制作过程中所用到的材料的种类。示例性的，第一基础层510和第二基础层610的材质可以为旋涂硬掩模组合物，第一抗反射层520和第二抗反射层620的材质可以为氮氧化硅。
步骤b：以光刻胶层为掩膜，刻蚀第二掩膜层，第二掩膜层内形成多条间隔设置且沿第二方向延伸的第一中间槽。
参考图4和图18，以光刻胶层700为掩膜，刻蚀第二掩膜层600，第二掩膜层600中未被光刻胶层700覆盖的部分去除，第二掩膜层600中被光刻胶层700覆盖的部分 保留。第二掩膜层600中形成多条间隔设置且沿第二方向延伸的第一中间槽630，第一中间槽630贯穿第二掩膜层600，以暴露第一掩膜层500。如此设置，光刻胶层700中的预设图案转移到第二掩膜层600，第二掩膜层600中形成第一中间槽630。
步骤c：在第一中间槽的侧壁和槽底，以及第二掩膜层上沉积第三牺牲层，位于第一中间槽内的第三牺牲层围合成第二中间槽。
参考图18和图19，在第一中间槽630的侧壁和槽底，以及第二掩膜层600上沉积第三牺牲层640，例如，通过原子层沉积工艺形成第三牺牲层640，以形成质量较好的第三牺牲层640。第三牺牲层640的材质可以为氧化硅。
步骤d：去除位于第二掩膜层顶部以及第二中间槽底部的第三牺牲层，保留位于第一中间槽侧壁的第三牺牲层。
参考图20，通过刻蚀工艺去除位于第二掩膜层600顶部以及第二中间槽650底部的第三牺牲层640，保留位于第一中间槽630侧壁的第三牺牲层640。刻蚀后，第二掩膜层600和第一掩膜层500暴露。即通过沉积并回刻，形成位于第一中间槽630的侧壁的第三牺牲层640。
步骤e：以保留的第三牺牲层为掩膜，刻蚀第二掩膜层、第一掩膜层和含硅抗反射层，以形成第一沟槽。
参考图20和图12，刻蚀去除位于第三牺牲层640之间的第二掩膜层600、第一掩膜层500和含硅抗反射层400，在含硅抗反射层400内形成第一沟槽410。形成第一沟槽410后，去除含硅抗反射层400上的其他膜层，以暴露含硅抗反射层400。
需要说明的是，在旋涂硬掩模层上形成层叠设置的中间层和含硅抗反射层，含硅抗反射层具有多个间隔设置且沿第二方向延伸的第一沟槽还可以通过其他方式形成，在另一些可能的示例中，其包括以下步骤：
步骤a’：在含硅抗反射层上形成依次层叠设置的第一掩膜层、第二掩膜层和光刻胶层。
步骤b’：以光刻胶层为掩膜，刻蚀第二掩膜层，第二掩膜层内形成多条间隔设置且沿第二方向延伸的第一中间槽。
步骤c’：在第一中间槽的侧壁和槽底，以及第二掩膜层上沉积第三牺牲层，位于第一中间槽内的第三牺牲层围合成第二中间槽。
该示例中的步骤a’，步骤b’，步骤c’分别可以参照上文示例中的步骤a，步骤b，步骤c，在此不再赘述。
步骤d’：在第二中间槽和第三牺牲层上形成第二填充层。
通过沉积工艺形成第二填充层，第二填充层填充满第二中间槽且覆盖第三牺牲层。 第三填充层的材质可以为旋涂硬掩模组合物。
步骤e’：去除部分第二填充层和部分第三牺牲层，以暴露位于第一中间层的侧壁上的第三牺牲层。
示例性的，通过平坦化处理工艺，去除位于第二掩膜层背离基底的表面上的部分第二填充层和部分第三牺牲层，以暴露该表面以及位于第一中间层的侧壁上的第三牺牲层。
步骤f’：刻蚀第三牺牲层、第一掩膜层和含硅抗反射层，以形成第一沟槽。
刻蚀第三牺牲层，以及位于第三牺牲层下方的第一掩膜层和含硅抗反射层，含硅抗反射层内形成第一沟槽。在刻蚀过程中，含硅抗反射层上方的膜层也会被去除至少部分。剩余的膜层可以通过刻蚀工艺单独去除，去除剩余的膜层后，含硅抗反射层暴露。
需要说明的是，在旋涂硬掩模层上形成层叠设置的中间层和含硅抗反射层，含硅抗反射层具有多个间隔设置且沿第二方向延伸的第一沟槽的不同示例中，光刻胶层的图案不同，以保证最终形成的第一沟槽的位置相同。
本申请实施例中，通过自对准双重图形化(Self-Aligned Double Patterning，简称SADP)工艺在含硅抗反射层400内形成第一沟槽410，所形成的第一沟槽410的特征尺寸减少，密度增加。此外，后续在含硅抗反射层400中形成第一刻蚀槽440过程中，在再一次进行自对准双重图形化工艺，使得第一刻蚀槽440的特征尺寸进一步减少，密度进一步增加，从而进一步提高了后续形成的半导体结构的集成度。
在本申请一种可能的示例中，参考图12至图14，在第一沟槽的侧壁和槽底，以及含硅抗反射层上沉积第二牺牲层，相应的，在第三沟槽内形成第一填充层的步骤包括：
参考图13，在第三沟槽内，以及第二牺牲层420上沉积第一填充层430。如图13所示，第一填充层430填充在第三沟槽且覆盖第二牺牲层420，即第一填充层430背离基底100的表面高于第二牺牲层420背离基底100的表面。
参考图14，去除部分第一填充层430和部分第二牺牲层420，以暴露位于第一沟槽410的侧壁上的第二牺牲层420。如图14所示，通过平坦化处理去除部分第一填充层430和部分第二牺牲层420，含硅抗反射层400和第二牺牲层420暴露出来。
本申请实施例中，形成第一沟道后，在第一沟道内形成第一牺牲层的步骤包括：在第一刻蚀槽内和第一沟道210内沉积第一牺牲层220。参考图21，第一牺牲层220填充在第一沟道210和第一刻蚀槽内，且还可以覆盖在中间层300或者含硅抗反射层400。可以理解是，在刻蚀旋涂硬掩模层200形成第一沟道210的过程中，含硅抗反射 层400也会被刻蚀去除部分。当含硅抗反射层400未被完全去除时，第一牺牲层220覆盖含硅抗反射层400，当含硅抗反射层400被完全去除时，中间层300暴露，第一牺牲层220覆盖中间层300。
需要说明的是，在所述第一沟道内形成第一牺牲层的步骤之后，还包括：去除位于所述旋涂硬掩模层上方的中间层、第一牺牲层和含硅抗反射层，以暴露所述旋涂硬掩模层。参考图22，通过平坦化工艺去除位于旋涂硬掩模层200上方的其他膜层，以暴露旋涂硬掩模层200，便于后续去除旋涂硬掩模层200。
在本申请一些可能的示例中，去除第一牺牲层，暴露第一沟道，第一沟道的填充孔延伸至有源区的步骤之后，还包括：在填充孔内形成导电柱，导电柱电连接有源区。
参考图10、图23至图25，导电柱250与有源区111相接触而实现导电柱250与有源区111的电连接。每个填充孔212内设置有一个导电柱250，且各导电柱250之间互不连接。衬底110内设置有有源区111和字线113，字线113与有源区111绝缘设置，且与导电柱250错开。示例性的，字线113穿过有源区111的中间区域，导电柱250与有源区111的端部区域电连接。
具体的，参考图11、图23和图24，在填充孔212内形成导电柱250，导电柱250电连接有源区111可以包括：
在第一沟道210内和第一支撑层240上沉积第一导电层251，第一导电层251填充在第一沟道210内且覆盖第一支撑层240，第一导电层251与有源区111电连接。如图11和图23所示，第一导电层251填充在第一沟道210内，并覆盖第一支撑层240。第一导电层251的材质可以为多晶硅。
形成第一导电层251后，刻蚀第一导电层251，保留位于填充孔212内的部分第一导电层251，保留的第一导电层251形成多个导电柱250。如图11和图24所示，去除位于位线上部的第一导电层251，以及位于填充孔212上部的第一导电层251，保留位于填充孔212底部的第一导电层251。保留的第一导电层251被第一支撑层240和位线隔离成多个导电层，各导电柱250之间间隔设置且互不相连。具体的，如图24所示，至少去除位于位线的第二支撑层152之上的第一导电层251，以将第一导电层251隔离成多个导电层。
需要说明的是，在填充孔212内形成导电柱250，导电柱250电连接有源区111的步骤之后，还包括：在导电柱250上沉积保护层260，保护层260覆盖导电柱250。参考图25，在导电柱250上沉积保护层260，保护层260覆盖导电柱250远离基底100的表面。保护层260的材质可以为氮化物，例如氮化硅。保护层260的厚度较薄，例如，保护层260可以减少或者避免导电柱250暴露在空气中而被氧化。
本申请实施例还提供一种半导体结构，该半导体结构通过上述的半导体结构的制作方法获得，因而至少具有位线150损失少的优点，具体效果参照上文所述，在此不再赘述。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (16)

  1. 一种半导体结构的制作方法，包括：
    在基底上形成旋涂硬掩模层，其中，所述基底内设置有多个间隔设置的有源区，所述基底上设置有多条间隔设置且沿第一方向延伸的位线，每条所述位线至少电连接一个所述有源区，所述旋涂硬掩模层填充在所述位线之间并覆盖所述位线；
    去除部分所述旋涂硬掩模层，形成多条间隔设置且沿第二方向延伸的第一沟道；
    在所述第一沟道内形成第一牺牲层，所述第一牺牲层填充于所述第一沟道内；
    去除所述第一牺牲层之间的所述旋涂硬掩模层，形成第二沟道；
    在所述第二沟道内形成第一支撑层，所述第一支撑层填充于所述第二沟道内；
    去除所述第一牺牲层，并将位于相邻所述位线之间的所述第一沟道延伸至所述有源区。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，去除部分所述旋涂硬掩模层，形成多条间隔设置的第一沟道，所述第一沟道暴露所述基底的步骤包括：
    在所述旋涂硬掩模层上形成依次层叠设置的中间层和含硅抗反射层，所述含硅抗反射层具有多个间隔设置且沿第二方向延伸的第一沟槽；
    在所述第一沟槽的侧壁上形成第二牺牲层，位于所述第一沟槽内的所述第二牺牲层围合成第三沟槽；
    在所述第三沟槽内形成第一填充层；
    去除位于所述第一沟槽的侧壁上的所述第二牺牲层，形成第一刻蚀槽；
    沿所述第一刻蚀槽刻蚀至所述旋涂硬掩模层，以形成所述第一沟道。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，所述第一沟槽的槽底位于所述含硅抗反射层。
  4. 根据权利要求2所述的半导体结构的制作方法，其中，在所述旋涂硬掩模层上形成层叠设置的中间层和含硅抗反射层，所述含硅抗反射层具有多个间隔设置且沿第二方向延伸的第一沟槽的步骤包括：
    在所述含硅抗反射层上形成依次层叠设置的第一掩膜层、第二掩膜层和光刻胶层；
    以所述光刻胶层为掩膜，刻蚀所述第二掩膜层，所述第二掩膜层内形成多条间隔设置且沿第二方向延伸的第一中间槽；
    在所述第一中间槽的侧壁和槽底，以及所述第二掩膜层上沉积第三牺牲层，位于所述第一中间槽内的所述第三牺牲层围合成第二中间槽；
    去除位于所述第二掩膜层顶部以及所述第二中间槽底部的所述第三牺牲层，保留位于所述第一中间槽侧壁的所述第三牺牲层；
    以保留的所述第三牺牲层为掩膜，刻蚀所述第二掩膜层、所述第一掩膜层和所述含硅抗反射层，以形成所述第一沟槽。
  5. 根据权利要求4所述的半导体结构的制作方法，其中，所述第一掩膜层包括设置在所述含硅抗反射层上的第一基础层，以及设置在所述第一基础层上的第一抗反射层；
    所述第二掩膜层包括设置在所述第一抗反射层上的第二基础层，以及设置在所述第二基础层上的第二抗反射层；
    所述第一基础层的材质与所述第二基础层的材质相同，所述第一抗反射层和所述第二抗反射层的材质相同。
  6. 根据权利要求2所述的半导体结构的制作方法，其中，在所述第一沟槽的侧壁上形成第二牺牲层，位于所述第一沟槽内的所述第二牺牲层围合成第三沟槽的步骤包括：
    在所述第一沟槽的侧壁和槽底，以及所述含硅抗反射层上沉积第二牺牲层。
  7. 根据权利要求6所述的半导体结构的制作方法，其中，在所述第三沟槽内形成第一填充层的步骤包括：
    在所述第三沟槽内，以及所述第二牺牲层上沉积所述第一填充层；
    去除部分所述第一填充层和部分所述第二牺牲层，以暴露位于所述第一沟槽的侧壁上的所述第二牺牲层。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，在所述第一沟道内形成第一牺牲层的步骤包括：
    在所述第一刻蚀槽内和所述第一沟道内沉积所述第一牺牲层。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，在所述第一沟道内形成第一牺牲层的步骤之后，还包括：
    去除位于所述旋涂硬掩模层上方的所述中间层、所述第一牺牲层和所述含硅抗反射层，以暴露所述旋涂硬掩模层。
  10. 根据权利要求1所述的半导体结构的制作方法，其中，去除所述第一牺牲层，暴露所述第一沟道，所述第一沟道的所述填充孔延伸至所述有源区的步骤之后，还包括：
    在所述填充孔内形成导电柱，所述导电柱电连接所述有源区。
  11. 根据权利要求1所述的半导体结构的制作方法，其中，所述基底包括衬底、设置在所述衬底上的绝缘层，以及设置在所述绝缘层上的阻挡层，所述衬底内设置有所述有源区，所述绝缘层覆盖所述有源区；
    去除所述第一牺牲层，并将位于相邻所述位线之间的所述第一沟道延伸至所述有源区的步骤包括：
    刻蚀所述第一牺牲层，以暴露所述第一沟道，每条所述第一沟道包括位于所述位线上方且沿第二方向延伸的第二沟槽，以及位于相邻所述位线之间且与所述第二沟槽连通的填充孔；
    沿所述第一沟道的填充孔刻蚀所述绝缘层，以使所述填充孔暴露所述有源区。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，在所述填充孔内形成导电柱，所述导电柱电连接所述有源区的步骤包括：
    在所述第一沟道内和所述第一支撑层上沉积第一导电层，所述第一导电层填充在所述第一沟道内且覆盖所述第一支撑层，所述第一导电层与所述有源区电连接；
    刻蚀所述第一导电层，保留位于所述填充孔内的部分所述第一导电层，保留的所述第一导电层形成多个所述导电柱。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，所述衬底内还设置有多条间隔设置且沿第二方向延伸的字线，所述字线与所述有源区绝缘设置，且与所述导电柱错开。
  14. 根据权利要求1所述的半导体结构的制作方法，其中，在所述填充孔内形成导电柱，所述导电柱电连接所述有源区的步骤之后，还包括：
    在所述导电柱上沉积保护层，所述保护层覆盖所述导电柱。
  15. 根据权利要求1所述的半导体结构的制作方法，其中，所述位线包括第二导电层，以及覆盖所述第二导电层的第二支撑层，所述第二支撑层内还设置有位于所述第二导电层旁侧的氧化物层，所述第二支撑层与所述第一支撑层的材质相同；
    所述旋涂硬掩模层与所述第二支撑层的选择比大于或者等于5。
  16. 一种半导体结构，所述半导体结构通过权利要求1所述的半导体结构的制作方法获得。
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