WO2023173482A1 - 存储器、半导体结构及其制备方法 - Google Patents

存储器、半导体结构及其制备方法 Download PDF

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Publication number
WO2023173482A1
WO2023173482A1 PCT/CN2022/083716 CN2022083716W WO2023173482A1 WO 2023173482 A1 WO2023173482 A1 WO 2023173482A1 CN 2022083716 W CN2022083716 W CN 2022083716W WO 2023173482 A1 WO2023173482 A1 WO 2023173482A1
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Prior art keywords
layer
isolation layer
bit line
conductive contact
isolation
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PCT/CN2022/083716
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English (en)
French (fr)
Inventor
吴润平
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长鑫存储技术有限公司
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Priority to US17/806,158 priority Critical patent/US20230301056A1/en
Publication of WO2023173482A1 publication Critical patent/WO2023173482A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a memory, a semiconductor structure and a preparation method thereof.
  • DRAM Dynamic Random Access Memory
  • the existing dynamic random access memory includes an array area and a peripheral area.
  • the patterning process of the array area affected by the manufacturing process, structural abnormalities are likely to occur in the peripheral area, resulting in a reduction in device yield.
  • the purpose of this disclosure is to overcome the above-mentioned shortcomings of the prior art and provide a memory device, a semiconductor structure and a preparation method thereof, which can reduce the risk of damage to the peripheral area and improve product yield.
  • a method for preparing a semiconductor structure including:
  • a substrate includes an array area and a peripheral area distributed side by side, the array area is formed with an isolation layer, a conductive contact plug and a plurality of spaced-apart bit line structures, the bit line structure is along a direction perpendicular to the Extending in the direction of the substrate, the isolation layer covers the sidewalls of the bit line structure, and the conductive contact plug is formed in an area surrounded by the isolation layer between adjacent bit line structures; the peripheral area Stacked film layers are formed;
  • the mask layer is etched to expose the top of the isolation layer.
  • the mask layer includes one or more sub-film layers, and etching the mask layer to expose the top of the isolation layer includes:
  • the sub-film layer is etched multiple times until the top of the isolation layer is exposed.
  • the isolation layer includes a first isolation layer and a second isolation layer, the first isolation layer covers the sidewalls of the bit line structure, and the second isolation layer Covering the surface of the first isolation layer, the conductive contact plug is formed in an area surrounded by the second isolation layer between adjacent bit line structures;
  • the stacked film layer includes a plurality of drive circuits and An insulating layer that separates each of the driving circuits, and the mask layer covers the surface of the insulating layer and the driving circuit; etching the mask layer to expose the top of the isolation layer includes:
  • the mask layer located on the surface of the bit line structure, the first isolation layer, the second isolation layer and the conductive contact plug is removed.
  • the preparation method further includes:
  • a sealing layer is formed covering the opening of the void.
  • the mask layer includes a plurality of sub-film layers formed to cover the bit line structure, the isolation layer, the conductive contact plug and the stack.
  • the mask layer of the film layer includes:
  • a second sub-film layer with a second predetermined thickness is formed on the surface of the first sub-film layer.
  • the first preset thickness is 2nm ⁇ 4nm
  • the second preset thickness is 3nm ⁇ 6nm.
  • the first sub-film layer and the second sub-film layer are made of the same material.
  • one of the conductive contact plugs is distributed between every two adjacently distributed bit line structures, and each of the conductive contact plugs is distributed in an array.
  • removing the mask layer located on the surface of the bit line structure, the first isolation layer, the second isolation layer and the conductive contact plug includes: :
  • the mask layer is dry etched in the development area to remove the mask layer located in the array area.
  • removing the first isolation layer to form a gap between the bit line structure and the second isolation layer includes:
  • the first isolation layer is removed using a dry etching process.
  • the dry etching includes plasma etching.
  • the etching gas for dry etching is HF.
  • the mask layer is made of silicon nitride.
  • a semiconductor structure including:
  • a substrate the substrate includes an array area and a peripheral area distributed side by side, a plurality of spaced-apart bit line structures are formed on the array area, and a second isolation layer extending in the same direction as the sidewalls of the bit line structure and a gap between the second isolation layer and the sidewall of the bit line structure, a conductive contact plug is formed in the area surrounded by the second isolation layer between adjacent bit line structures;
  • a stacked film layer is formed on the peripheral area;
  • a sealing layer covering the opening of the void A sealing layer covering the opening of the void.
  • a memory including the semiconductor structure described in any one of the above.
  • the memory device, semiconductor structure and preparation method thereof of the present disclosure can, on the one hand, insulate and protect both sides of the bit line structure and the conductive contact plug through the isolation layer, thereby preventing short circuits between the bit line structure and the conductive contact plug, reducing the risk of The risk of short circuit of the device is reduced and the product yield is improved.
  • the surface of the stacked film layer in the peripheral area can be protected through the mask layer to avoid etching the array area.
  • the mask layer can still be used as a protective barrier to protect the surface of the stacked film layers in the peripheral area, which can Further improve product yield.
  • Figure 1 is a schematic diagram of an array area in the related art
  • Figure 2 is a morphology diagram of the array area in the related art
  • Figure 3 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present disclosure
  • Figure 4 is a schematic structural diagram of the array area of the substrate in an embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram of the peripheral area of the substrate in an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of the array area after completing step S120 in an embodiment of the present disclosure
  • Figure 7 is a flow chart of step S120 in an embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram of the array area after completing step S130 in an embodiment of the present disclosure.
  • Figure 9 is a flow chart of step S130 in an embodiment of the present disclosure.
  • Figure 10 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram of the array area after completing step S140 in an embodiment of the present disclosure.
  • Figure 12 is a flow chart of step S140 in an embodiment of the present disclosure.
  • Figure 13 is a schematic diagram of etching gas diffusion in an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of the array area after step S150 is completed in an embodiment of the present disclosure.
  • Isolation layer 11. First isolation layer; 12. Second isolation layer; 2. Bit line structure; 21. First conductive layer; 22. First conductive layer; 23. First conductive layer; 3. Covering layer ; 4. Conductive contact plug; 5. Mask layer; 6. Stacked film layer; 7. Void; 8. Sealing layer; 100. Word line structure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the semiconductor structure mainly includes a substrate and multiple bit line structures and circuit structures formed in the substrate.
  • the bit line structures are separated by insulating materials.
  • the insulating materials need to be patterned. treatment to reduce parasitic capacitance between bit line structures.
  • the substrate includes an array area and a peripheral area.
  • Each bit line structure is mainly distributed in the array area
  • the circuit structure is mainly distributed in the peripheral area.
  • the insulation between adjacent bit line structures in the array area can be The layers are etched to form gaps to reduce parasitic capacitance between bit line structures.
  • the structure of the peripheral area is easily damaged, and the product yield is low.
  • the present disclosure provides a method for manufacturing a semiconductor structure to solve the above technical problems.
  • the semiconductor structure can be a dynamic random access memory (dynamic random access memory, DRAM), a static random access memory (static random access memory, SRAM), etc.
  • Figure 3 shows a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to Figure 3, the preparation method may include step S110 to step S130, wherein:
  • Step S110 Provide a substrate.
  • the substrate includes an array area and a peripheral area distributed side by side.
  • the array area is formed with an isolation layer, a conductive contact plug, and a plurality of spaced-apart bit line structures.
  • the bit line structures are vertically distributed along the Extending in the direction of the substrate, the isolation layer covers the sidewalls of the bit line structure, and the conductive contact plug is formed in an area surrounded by the isolation layer between adjacent bit line structures;
  • the peripheral area is formed with stacked film layers;
  • Step S120 forming a mask layer covering the bit line structure, the isolation layer, the conductive contact plug and the stacked film layer;
  • Step S130 Etch the mask layer to expose the top of the isolation layer.
  • the preparation method of the semiconductor structure of the present disclosure can, on the one hand, insulate and protect both sides of the bit line structure and the conductive contact plugs through the isolation layer, thereby preventing short circuits between the bit line structures and the conductive contact plugs and reducing the risk of short circuits in the device. , to improve product yield; on the other hand, during the process of etching to expose the top of the isolation layer, the surface of the stacked film layer in the peripheral area can be protected through the mask layer to avoid damaging the peripheral area during the etching process of the array area. causing damage to the film layer on the surface of the peripheral area; in addition, during the subsequent patterning process of the isolation layer, the mask layer can still serve as a protective barrier to protect the surface of the stacked film layers in the peripheral area, further improving product yield .
  • a substrate is provided.
  • the substrate includes an array area and a peripheral area distributed side by side.
  • the array area is formed with an isolation layer, a conductive contact plug, and a plurality of spaced-apart bit line structures.
  • the bit line structure extends in a direction perpendicular to the substrate, the isolation layer covers the sidewalls of the bit line structure, and the conductive contact plug is formed between adjacent bit line structures.
  • the area surrounded by the isolation layer; the peripheral area is formed with stacked film layers.
  • the substrate can have a flat structure, and the substrate contains a word line structure (not shown in the figure).
  • a bit line structure formation area and a capacitor contact hole formation area can be predefined on the substrate, and the bit line structure formation area can be used to form The bit line structure and capacitor contact hole formation area can be used to form conductive contact plugs.
  • the substrate can be rectangular, circular, elliptical, polygonal or irregularly shaped, and its material can be silicon or other semiconductor materials. The shape and material of the substrate are not specifically limited here.
  • the substrate may include an array region and a peripheral region, and the array region may be used to form a capacitor array and a bit line structure.
  • the array area can be a circular area, a rectangular area or an irregular graphic area, and is not specifically limited here.
  • the peripheral area can be distributed adjacent to the array area.
  • the peripheral area can be an annular area and can surround the outer periphery of the array area.
  • it can be a rectangular annular area, which is not particularly limited here.
  • the peripheral area can be used to form a circuit structure, and the circuit structure can be connected with the memory array module in the array area, so as to control the charging and discharging of the memory array module through the circuit structure.
  • the substrate may include a sacrificial layer, which may have the same thickness as the desired bit line structure.
  • the sacrificial layer can be formed by atomic layer deposition, vacuum evaporation, magnetron sputtering, chemical vapor deposition or physical vapor deposition.
  • the sacrificial layer can also be formed by other processes.
  • the forming process of the sacrificial layer is not specifically limited here. .
  • the sacrificial layer can be patterned using a photolithography process according to the predefined bit line formation area and capacitor contact hole formation area to form multiple trenches and multiple through holes distributed side by side in the sacrificial layer. It should be noted that the trenches may be distributed at least in the array area.
  • the trench may pass through both ends in a direction parallel to the substrate, and may extend in a direction parallel to the substrate.
  • the through hole may be a circular hole, a rectangular hole or an irregularly shaped hole structure, and is not specifically limited here.
  • each trench can form a group with each column of through-holes, and multiple groups of trenches and through-holes distributed side by side can be formed, and the columns composed of trenches and through-holes alternate in two adjacent groups. Distribution, that is, each through hole is distributed on both sides of the trench, and can be arranged at intervals along the extension direction of the trench.
  • An isolation layer can be formed on the side wall of each trench.
  • the isolation layer can be a film or coating conformally attached to the side wall of the trench, and is not specifically limited here.
  • the isolation layer may be made of an insulating material to insulate and protect the structures in each trench to prevent short circuiting of the structures.
  • the isolation layer 1 may include a first isolation layer 11 and a second isolation layer 12, and the second isolation layer 12 may be formed on the sidewall of each trench,
  • the second isolation layer 12 may be a film or coating conformally attached to the side wall of the trench, and is not specifically limited here.
  • the second isolation layer 12 may be made of an insulating material to insulate and protect the structures in each trench and prevent the structures from being short-circuited.
  • the material of the second isolation layer 12 may be silicon nitride.
  • the second isolation layer 12 can be formed on the sidewall of the trench using processes such as chemical vapor deposition, physical vapor deposition, thermal evaporation or atomic layer deposition. Of course, the second isolation layer 12 can also be formed through other processes, which are not specifically limited here. .
  • the first isolation layer 11 can be formed on the surface of the second isolation layer 12 away from the trench sidewall.
  • the first isolation layer 11 can be a film or coating conformally attached to the surface of the second isolation layer 12 , and there is no special requirement here. limited.
  • the first isolation layer 11 can be made of an insulating material, and the structures in each trench can be double insulated and protected through the first isolation layer 11 and the second isolation layer 12 to further prevent short circuits of the structures.
  • the material of the first isolation layer 11 may be silicon oxide.
  • the first isolation layer 11 can be formed on the surface of the second isolation layer 12 by processes such as chemical vapor deposition, physical vapor deposition, thermal evaporation or atomic layer deposition. Of course, the first isolation layer 11 can also be formed by other processes, which are not mentioned here. Make special restrictions.
  • the bit line structure 2 can be formed in each trench respectively.
  • the bit line structure 2 can be made of a conductive material.
  • the bit line structure 2 can include a first conductive layer 21, a second conductive layer 22 and a third conductive layer that are stacked and distributed.
  • Layer 23, the first conductive layer 21, the second conductive layer 22 and the third conductive layer 23 may be distributed in a direction perpendicular to the substrate, wherein the second conductive layer 22 is located between the first conductive layer 21 and the third conductive layer 23.
  • the material of the first conductive layer 21 may be polysilicon; the material of the second conductive layer 22 may be titanium nitride; and the material of the third conductive layer 23 may be tungsten.
  • processes such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, thermal evaporation or atomic layer deposition can be used to sequentially form the first conductive layer 21 and the second conductive layer 22 in the trench. and the third conductive layer 23 , and further form the bit line structure 2 through the first conductive layer 21 , the second conductive layer 22 and the third conductive layer 23 .
  • the bit line structure 2 is located in the trench, the first isolation layer 11 covers the sidewalls of the bit line structure 2, and the second isolation layer 12 covers the surface of the first isolation layer 11.
  • the bit line structure 2 can be formed first in the trench, and then the first isolation layer 11 is formed on the sidewall of the bit line structure 2 , and then, the first isolation layer 11 is formed on the side wall of the bit line structure 2 .
  • the second isolation layer 12 is formed on the surface. During this process, the second isolation layer 12 can fill the gap between the first isolation layer 11 and the trench, and can also cover the top of the first isolation layer 11 .
  • a covering layer 3 is also provided between the isolation layer 1 and the bit line structure 2, and processes such as chemical vapor deposition, physical vapor deposition, thermal evaporation or atomic layer deposition can be used to coat each bit line.
  • a covering layer 3 is formed on the surface of the structure 2 .
  • the covering layer 3 can cover the sidewalls and top of each bit line structure 2 .
  • the first isolation layer 11 and the second isolation layer 12 are located on the sidewalls of the covering layer 3 .
  • the covering layer 3 can be made of an insulating material, and the two adjacent bit line structures 2 can be triple insulated and protected through the covering layer 3, the first isolation layer 11 and the second isolation layer 12 to prevent the bit line structure 2 from interacting with other surrounding structures.
  • the material of the covering layer 3 can be the same as the material of the second isolation layer 12.
  • the material can be silicon nitride. Of course, it can be other insulating materials, which are not listed here.
  • the distance between the top of the covering layer 3 and the bottom of the capacitor contact hole may be 650 Angstroms, wherein the distance between the top of the isolation layer 1 and the top of the covering layer 3 is 300 Angstroms, which is beneficial to subsequent formation of gaps.
  • the etching gas enters smoothly; the distance between the top of the isolation layer 1 and the bottom of the capacitor contact hole can be 350 Angstroms.
  • the structure at the bottom of the capacitor contact hole can be prevented from being etched away, thereby avoiding void failure.
  • conductive material can be deposited in each through hole located in the array area to form conductive contact plugs 4.
  • the conductive contact plugs 4 can be filled in two adjacent ones.
  • the conductive contact plug 4 can fill the area surrounded by the second isolation layer 12 between two adjacent bit line structures 2 in the area surrounded by the isolation layer 1 between the bit line structures 2 .
  • the conductive material may be polysilicon or tungsten.
  • the conductive contact plugs 4 can be formed in each through hole using processes such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, thermal evaporation or atomic layer deposition. Of course, other processes can also be used to form the conductive contact plugs 4 , will not be listed one by one here.
  • each conductive contact plug 4 can be distributed in an array at intervals, and one conductive contact plug 4 can be distributed between every two adjacent distributed bit line structures 2, and an insulating material is passed between two adjacent conductive contact plugs 4. Separate to avoid short circuit or coupling between two adjacent conductive contact plugs 4 .
  • the insulating material may be the material of the isolation layer 1 or the covering layer 3 , and is not particularly limited here.
  • the conductive contact plug 4 can be in a "Z" shape, and the top surface of the bottom of the "Z” shape can be lower than the top of the isolation layer 1 , thereby avoiding damage to the capacitive contact during the etching process to form the gap. Plug 4 around the oxide.
  • the distance between the top surface of the bottom of the "Z” and the top of the isolation layer 1 may be 130 angstroms.
  • the thickness of the bevel in the "Z" shape can be 11nm to 12nm.
  • the thickness can be 11nm, 11.2nm, 11.4nm, 11.6nm, 11.8nm or 12nm. Of course, it can also be other thicknesses, which are not mentioned here. List them one by one.
  • the sacrificial layer can be removed.
  • an acidic solution can be used for wet etching.
  • the preparation ratio of the acidic solution and deionized water can be set according to the specific material of the sacrificial layer.
  • the peripheral area can be provided with a stacked film layer 6.
  • the stacked film layer 6 can include a driving circuit and an insulating layer. There can be multiple driving circuits, and the driving circuits can be separated by the insulating layer to prevent each driver from driving. Coupling or short circuit occurs between circuits.
  • step S120 a mask layer covering the bit line structure, the isolation layer, the conductive contact plug and the stacked film layer is formed.
  • the mask layer 5 can be formed on the surface of the bit line structure 2, the isolation layer 1, the conductive contact plug 4 and the stacked film layer 6.
  • the mask layer 5 can be attached to the bit line structure 2, the isolation layer 1 and the conductive contact plug according to the shape. 4 and the surface of the stacked film layer 6, which may be a thin film formed on the surface of the bit line structure 2, isolation layer 1, conductive contact plug 4 and stacked film layer 6, or may be formed on the bit line structure 2, isolation layer 1 , the coating on the surface of the conductive contact plug 4 and the stacked film layer 6, the type of the mask layer 5 is not specifically limited here.
  • the mask layer 5 can cover the surfaces of the insulating layer and the driving circuit at the same time, so that they can be protected by the mask layer 5 during subsequent etching of the array area.
  • the insulation layer and drive circuit surface in the peripheral area can avoid damage to the insulation layer and drive circuit in the peripheral area, which can improve product yield.
  • the material of the mask layer 5 can be an insulating material, for example, the material can be silicon nitride, and a process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, vacuum evaporation or magnetron sputtering can be used.
  • the mask layer 5 is formed on the surface of the bit line structure 2, isolation layer 1, conductive contact plug 4 and stacked film layer 6. Of course, other processes can also be used to form a mask layer 5 on the bit line structure 2, isolation layer 1, conductive contact plug 4 and stacked film.
  • a mask layer 5 is formed on the surface of layer 6 , and the formation process of mask layer 5 is not particularly limited here.
  • the thickness of the mask layer 5 may be 2 nm to 10 nm.
  • it may be 2 nm, 4 nm, 6 nm, 8 nm or 10 nm.
  • it may also be other thicknesses as long as It is enough to ensure that the peripheral area is not damaged when patterning the array area, and I will not list them one by one here.
  • the mask layer 5 may be deposited through multiple deposition processes.
  • the mask layer 5 may include one or more sub-film layers; when it includes a sub-film layer, the sub-film layer may be deposited through multiple deposition processes, and the thickness of each deposition is relatively small. , thereby avoiding thicker deposition in some areas and thinner deposition in other areas, ensuring that the thickness of the mask layer 5 in each area is approximately equal.
  • the materials of each sub-film layer can be the same or different. The materials of each sub-film layer are not specifically limited here.
  • each sub-film layer the materials of each sub-film layer can be deposited each time.
  • One sub-film layer, the thickness of adjacent sub-film layers can be the same or different, and is not specifically limited here.
  • the structure of the array area after completing step S120 is as shown in FIG. 6 .
  • the mask layer 5 may include multiple sub-film layers.
  • the mask layer 5 may include a first sub-film layer and a second sub-film layer to form the covering bit line structure 2 , isolation layer 1, conductive contact plug 4 and mask layer 5 of stacked film layer 6, that is, step S120 may include step S1201 and step S1202, as shown in Figure 7, wherein:
  • Step S1201 Form a first sub-film layer with a first predetermined thickness on the surface of the structure composed of the bit line structure, the isolation layer, the conductive contact plug and the stacked film layer.
  • the first sub-film layer may be a thin film formed on the surface of the bit line structure 2, isolation layer 1, conductive contact plug 4 and stacked film layer 6, or may be formed on the bit line structure 2, isolation layer 1, conductive contact plug 4 and
  • the coating on the surface of the stacked film layer 6 is not specifically limited to the specific form of the first sub-film layer.
  • the material of the first sub-film layer may be an insulating material, for example, it may be silicon nitride.
  • a process such as physical vapor deposition, chemical vapor deposition or atomic layer deposition may be used to form a first sub-film layer with a first predetermined thickness on the surfaces of the bit line structure 2, the isolation layer 1, the conductive contact plug 4 and the stacked film layer 6.
  • other processes may also be used to form the first sub-film layer, and the formation process of the first sub-film layer is not specifically limited here.
  • the first preset thickness can be 2nm ⁇ 4nm.
  • it can be 2nm, 2.5nm, 3nm, 3.5nm or 4nm.
  • it can also be other thicknesses, which are not listed here. enumerate.
  • Step S1202 Form a second sub-film layer with a second preset thickness on the surface of the first sub-film layer.
  • the second sub-film layer may be formed on a side of the first sub-film layer facing away from the substrate.
  • the second sub-film layer may be a thin film formed on the surface of the first sub-film layer, or may be a coating formed on the surface of the first sub-film layer.
  • the specific form of the second sub-film layer is not particularly limited here.
  • the material of the second sub-film layer may be an insulating material, which may be the same as the material of the first sub-film layer.
  • the materials of the first sub-film layer and the second sub-film layer may both be silicon nitride.
  • a process such as physical vapor deposition, chemical vapor deposition or atomic layer deposition can be used to form a second sub-film layer with a second preset thickness on the surface of the first sub-film layer. Of course, other processes can also be used to form the second sub-film layer.
  • the formation process of the second sub-film layer is not particularly limited here.
  • the second preset thickness may be 3 nm to 6 nm.
  • it may be 3 nm, 4 nm, 5 nm or 6 nm.
  • it may also be other thicknesses, which are not listed here.
  • step S130 the mask layer is etched to expose the top of the isolation layer.
  • An etching process can be used to remove the mask layer 5 located on the top of the isolation layer 1 to expose the top of the isolation layer 1 .
  • the mask layer 5 located in other areas within the array area can be removed together with the same etching process, avoiding the need for additional etching processes to remove the mask layer 5 located in other areas within the array area, thus simplifying the process. ,reduce manufacturing cost. That is, the mask layer 5 located on the surface of the bit line structure 2, the first isolation layer 11, the second isolation layer 12 and the conductive contact plug 4 can be removed at the same time, leaving only the insulating layer located in the peripheral area and the mask layer on the surface of the driving circuit. 5.
  • a dry etching process can be used to remove the mask layer 5 on the surface of the bit line structure 2, the first isolation layer 11, the second isolation layer 12 and the conductive contact plug 4, leaving only the insulation layer and driver in the peripheral area.
  • Mask layer 5 on the circuit surface can be used to remove the mask layer 5 on the surface of the bit line structure 2, the first isolation layer 11, the second isolation layer 12 and the conductive contact plug 4, leaving only the insulation layer and driver in the peripheral area.
  • the sub-film layer when the mask layer 5 includes a sub-film layer, the sub-film layer can be etched multiple times, and in each etching process, the bit line structure can be etched simultaneously. 2.
  • the mask layer 5 on a certain part is etched first, in the next etching process, the area outside the area can be etched instead of etching the area to avoid damage to the structure in the area. , which helps to improve the product yield; of course, when the mask layer 5 includes a sub-film layer, the sub-film layer can also be etched once, as long as the structure in each area in the array area is not damaged. There is no special limit on the number of etching times.
  • each sub-layer when the mask layer 5 includes multiple sub-layers, each sub-layer can be etched in layers, and in each etching process, the bit lines can be etched simultaneously.
  • Structure 2 the first isolation layer 11, the second isolation layer 12 and the mask layer 5 on the surface of the conductive contact plug 4 until the top of the isolation layer 1 is exposed, that is, the mask layer 5 can be etched multiple times, each time
  • the etching process can etch a sub-film layer. In this way, the thickness of each etching is small, which can ensure that the mask layer 5 on the surface of the area corresponding to each part of the structure in the array area can be etched exactly without damaging the array.
  • any part of the structure in the area if the mask layer 5 on a certain part is etched first, in the next etching process, the area outside this area can be etched, and the area will no longer be etched. Etching to avoid damage to the structure in this area helps to improve product yield; of course, when the mask layer 5 includes multiple sub-layers, the multiple sub-layers can also be etched at once, as long as they are not It is enough to damage the structures in each area of the array area, and there is no special limit on the number of etching times.
  • the structure of the array area after completing step S130 is as shown in FIG. 8 .
  • step S130 may include steps S1301- Step S1303, as shown in Figure 9, where:
  • Step S1301 Form a photoresist layer on the surface of the mask layer.
  • a photoresist layer can be formed on the surface of the mask layer 5 facing away from the substrate by spin coating or other methods.
  • the material of the photoresist layer can be a positive photoresist or a negative photoresist, and is not specifically limited here.
  • Step S1302 Expose and develop the photoresist layer to form a developed area, and the developed area exposes the mask layer located in the array area.
  • the photoresist layer can be exposed using a mask.
  • the pattern of the mask can match the desired pattern of the photoresist layer.
  • the mask pattern can match the shape of the array area and its size can match the size of the array area. Dimensions are the same.
  • the exposed photoresist layer can be developed to form a developed area, and the developed area can expose the mask layer 5 .
  • Step S1303 dry etching the mask layer in the development area to remove the mask layer located in the array area.
  • the mask layer 5 can be etched in the development area by dry etching to form an opening, which can expose the conductive contact plug 4, the top of the isolation layer 1 and the capping layer 3 on top of the bit line structure 2 in the array area, thereby retaining Mask layer 5 located on the surface of the peripheral area.
  • etching gas can be used to perform plasma etching on the mask layer 5, thereby removing the mask on the surface of the conductive contact plug 4, the top of the isolation layer 1, and the surface of the covering layer 3 located on the top of the bit line structure 2 in the array area.
  • Layer 5 the mask material layer can be selectively etched with an etching gas.
  • the etching gas can be HF.
  • the etching gas can diffuse in the device space and then enter laterally to Etch away the mask.
  • the method for preparing a semiconductor structure of the present disclosure may further include step S140 and step S150, as shown in Figure 10, wherein:
  • Step S140 Remove the first isolation layer to form a gap between the bit line structure and the second isolation layer.
  • a dry etching process can be used to remove the first isolation layer 11, thereby forming a gap 7 between the bit line structure 2 and the second isolation layer 12.
  • the parasitic capacitance between the bit line structures 2 can be reduced through the provision of the gap 7.
  • the structural surface of the peripheral area is covered by the mask layer 5, even if the film layer on the surface of the peripheral area is consumed during this process, it is also the material of the mask layer 5 that is consumed and will not cause any damage to the mask layer 5. Damage is caused to the insulation layer in the peripheral area and the surface of the drive circuit.
  • the structure of the array area after completing step S140 is as shown in Figure 11.
  • the height of the gap 7 can be greater than 100 angstroms.
  • it can be 100 angstroms, 120 angstroms, 140 angstroms, 160 angstroms, 180 angstroms or 200 angstroms.
  • it can also be other heights, where No more listing them one by one.
  • step S140 may include step S1401 and step S1402 , as shown in FIG. As shown in 12, where:
  • Step S1401 Use a dry etching process to remove the second isolation layer located on top of the first isolation layer to expose the top of the first isolation layer.
  • a plasma etching process can be used to remove the second isolation layer 12 located on top of the first isolation layer 11 to expose the top of the first isolation layer 11 .
  • the second isolation layer 12 located on the top of the first isolation layer 11 can be exposed by etching gas.
  • the second isolation layer 12 is selectively etched.
  • the etching gas may be HF.
  • Step S1402 use a dry etching process to remove the first isolation layer.
  • the first isolation layer 11 can be removed using a plasma etching process, thereby forming a gap 7 between the bit line structure 2 and the second isolation layer 12 .
  • the parasitic capacitance between the bit line structures 2 can be reduced through the provision of the gap 7 .
  • the first isolation layer 11 can be selectively etched using an etching gas.
  • the etching gas can be HF. As shown in FIG.
  • the etching gas can diffuse in the gap between the word line structure 100 , the bit line structure 2 and the capacitor contact plug 4 along the direction indicated by the arrow in FIG. 13 , and then diffuse to the bit line structure 2
  • the first isolation layer 11 is located on the side wall, so that the first isolation layer 11 is removed.
  • Step S150 Form a sealing layer covering the opening of the gap.
  • the gap 7 can be sealed to enhance the structural support strength.
  • a process such as physical vapor deposition, chemical vapor deposition or atomic layer deposition can be used to form the sealing layer 8 at the opening of the gap 7 .
  • the material of the sealing layer 8 may be an insulating material, for example, the material thereof may be silicon nitride.
  • the sealing layer 8 can be formed simultaneously on the surface of the structure composed of the bit line structure 2 , the second isolation layer 12 and the conductive contact plug 4 .
  • the thickness of the sealing layer 8 can be set according to product requirements and is not particularly limited here. For example, the thickness can be 100 angstroms.
  • the structure of the array area after completing step S150 is as shown in Figure 14.
  • the embodiment of the present disclosure also provides a semiconductor structure.
  • Figure 13 shows a schematic diagram of the semiconductor structure of the embodiment of the present disclosure.
  • the semiconductor structure may include a substrate, a mask layer 5 and a sealing layer 8, wherein :
  • the substrate includes an array area and a peripheral area distributed side by side.
  • a plurality of spaced bit line structures 2 are formed on the array area, a second isolation layer 12 extending in the same direction as the sidewalls of the bit line structure 2 and a second isolation layer 12 located on the second isolation layer.
  • the gap 7 between 12 and the sidewall of the bit line structure 2, and the area surrounded by the second isolation layer 12 between adjacent bit line structures 2 are formed with conductive contact plugs 4; a stacked film layer 6 is formed on the peripheral area;
  • the mask layer 5 covers the surface of the stacked film layer 6;
  • the sealing layer 8 covers the opening of the void 7 .
  • Embodiments of the present disclosure also provide a memory, which may include the semiconductor structure in any of the above embodiments.
  • a memory which may include the semiconductor structure in any of the above embodiments.
  • the specific details, formation processes and beneficial effects have been detailed in the corresponding preparation method of the semiconductor structure and the semiconductor structure. Description will not be repeated here.
  • the memory can be dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (static random access memory, SRAM), etc.
  • DRAM Dynamic Random Access Memory
  • SRAM static random access memory
  • other storage devices may also be used, which are not listed here.

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Abstract

一种存储器、半导体结构及其制备方法，涉及半导体技术领域。该制备方法包括：提供衬底，衬底包括并排分布的阵列区和外围区，阵列区形成有隔离层、导电接触塞及多个间隔分布的位线结构，位线结构沿垂直于衬底的方向延伸，隔离层覆盖位线结构的侧壁，导电接触塞形成于相邻位线结构之间的隔离层围成的区域；外围区形成有堆叠膜层（S110）；形成覆盖位线结构、隔离层、导电接触塞及堆叠膜层的掩膜层（S120）；蚀刻掩膜层，以露出隔离层的顶部（S130）。该制备方法可降低外围区损伤风险，提高产品良率。

Description

存储器、半导体结构及其制备方法
交叉引用
本公开要求于2022年3月15日提交的申请号为202210255938.2，名称均为“存储器、半导体结构及其制备方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种存储器、半导体结构及其制备方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)因具有体积小、集成化程度高及传输速度快等优点，被广泛应用于手机、平板电脑等移动设备中。
现有动态随机存储器包括阵列区和外围区，然而，在对阵列区进行图形化工艺的过程中，受制备工艺影响，易使外围区出现结构异常，致使器件良率降低。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种存储器件、半导体结构及其制备方法，可降低外围区损伤风险，提高产品良率。
根据本公开的一个方面，提高一种半导体结构的制备方法，包括：
提供衬底，所述衬底包括并排分布的阵列区和外围区，所述阵列区形成有隔离层、导电接触塞及多个间隔分布的位线结构，所述位线结构沿垂直于所述衬底的方向延伸，所述隔离层覆盖所述位线结构的侧壁，所述导电接触塞形成于相邻所述位线结构之间的所述隔离层围成的区域； 所述外围区形成有堆叠膜层；
形成覆盖所述位线结构、所述隔离层、所述导电接触塞及所述堆叠膜层的掩膜层；
蚀刻所述掩膜层，以露出所述隔离层的顶部。
在本公开的一种示例性实施例中，所述掩膜层包括一层或多层子膜层，所述蚀刻所述掩膜层，以露出所述隔离层的顶部，包括：
对所述子膜层进行多次蚀刻，直至露出所述隔离层的顶部。
在本公开的一种示例性实施例中，所述隔离层包括第一隔离层和第二隔离层，所述第一隔离层覆盖于所述位线结构的侧壁，所述第二隔离层覆盖于所述第一隔离层的表面，所述导电接触塞形成于相邻所述位线结构之间的所述第二隔离层围成的区域；所述堆叠膜层包括多个驱动电路和分隔各所述驱动电路的绝缘层，所述掩膜层覆盖所述绝缘层及所述驱动电路的表面；所述蚀刻所述掩膜层，以露出所述隔离层的顶部，包括：
去除位于所述位线结构、所述第一隔离层、所述第二隔离层及所述导电接触塞表面的所述掩膜层。
在本公开的一种示例性实施例中，所述制备方法还包括：
去除所述第一隔离层，以在所述位线结构和所述第二隔离层之间形成空隙；
形成覆盖所述空隙的开口的封闭层。
在本公开的一种示例性实施例中，所述掩膜层包括多层所述子膜层，所述形成覆盖所述位线结构、所述隔离层、所述导电接触塞及所述堆叠膜层的掩膜层，包括：
在所述位线结构、所述隔离层、所述导电接触塞及所述堆叠膜层共同构成的结构的表面形成第一预设厚度的第一子膜层；
在所述第一子膜层的表面形成第二预设厚度的第二子膜层。
在本公开的一种示例性实施例中，所述第一预设厚度为2nm～4nm，所述第二预设厚度为3nm～6nm。
在本公开的一种示例性实施例中，所述第一子膜层和所述第二子膜层的材料相同。
在本公开的一种示例性实施例中，每两个相邻分布的所述位线结构之间分布一个所述导电接触塞，各所述导电接触塞呈阵列分布。
在本公开的一种示例性实施例中，所述去除位于所述位线结构、所述第一隔离层、所述第二隔离层及所述导电接触塞表面的所述掩膜层，包括：
在所述掩膜层的表面形成光阻层；
对所述光阻层进行曝光并显影，以形成显影区，所述显影区露出位于所述阵列区的所述掩膜层；
在所述显影区对所述掩膜层进行干法蚀刻，以去除位于所述阵列区的所述掩膜层。
在本公开的一种示例性实施例中，所述去除所述第一隔离层，以在所述位线结构和所述第二隔离层之间形成空隙，包括：
采用干法蚀刻工艺去除位于所述第一隔离层顶部的所述第二隔离层，以露出所述第一隔离层的顶部；
采用干法蚀刻工艺去除所述第一隔离层。
在本公开的一种示例性实施例中，所述干法蚀刻包括等离子体蚀刻。
在本公开的一种示例性实施例中，所述干法蚀刻的蚀刻气体为HF。
在本公开的一种示例性实施例中，所述掩膜层的材料为氮化硅。
根据本公开的一个方面，提供一种半导体结构，包括：
衬底，所述衬底包括并排分布的阵列区和外围区，所述阵列区上形成有多个间隔分布的位线结构、与所述位线结构的侧壁同向延伸的第二隔离层及位于所述第二隔离层和所述位线结构的侧壁之间的空隙，相邻所述位线结构之间的所述第二隔离层围成的区域形成有导电接触塞；所述外围区上形成有堆叠膜层；
掩膜层，覆盖于所述堆叠膜层的表面；
封闭层，覆盖所述空隙的开口。
根据本公开的一个方面，提供一种存储器，包括上述任意一项所述的半导体结构。
本公开的存储器件、半导体结构及其制备方法，一方面，可通过隔离层对位线结构及导电接触塞的两侧进行绝缘保护，进而防止位线结构 与导电接触塞之间发生短路，降低器件的短路风险，提高产品良率；另一方面，在蚀刻露出隔离层的顶部的过程中，可通过掩膜层对外围区的堆叠膜层的表面进行保护，避免在对阵列区进行蚀刻的过程中对外围区表面的膜层造成损伤；此外，在对隔离层进行后续图案化处理的过程中，掩膜层仍然可作为保护屏障，对外围区内的堆叠膜层的表面进行保护，可进一步提高产品良率。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中阵列区的示意图；
图2为相关技术中阵列区的形貌图；
图3为本公开一实施方式中半导体结构的制备方法的流程图；
图4为本公开实施方式中衬底的阵列区的结构示意图；
图5为本公开实施方式中衬底的外围区的结构示意图；
图6为本公开实施方式中完成步骤S120后阵列区的结构示意图；
图7为本公开实施方式中步骤S120的流程图；
图8为本公开实施方式中完成步骤S130后阵列区的结构示意图；
图9为本公开实施方式中步骤S130的流程图；
图10为本公开一实施方式中半导体结构的制备方法的流程图；
图11为本公开实施方式中完成步骤S140后阵列区的结构示意图；
图12为本公开实施方式中步骤S140的流程图；
图13为本公开实施方式中蚀刻气体扩散示意图；
图14为本公开实施方式中完成步骤S150后阵列区的结构示意图。
附图标记说明：
1、隔离层；11、第一隔离层；12、第二隔离层；2、位线结构；21、第一导电层；22、第一导电层；23、第一导电层；3、覆盖层；4、导电接触塞；5、掩膜层；6、堆叠膜层；7、空隙；8、封闭层；100、字线结构。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
如图1所示，半导体结构主要包括衬底和形成于衬底内的多个位线结构及电路结构，各位线结构之间通过绝缘材料隔开，在制造过程中，需要对绝缘材料进行图案化处理以减小位线结构之间的寄生电容。具体而言，衬底包括阵列区和外围区，各位线结构主要分布于阵列区，电路结构主要分布于外围区，在产品制造过程中，可对阵列区中相邻位线结构之间的绝缘层进行蚀刻形成空隙，以便减小各位线结构之间的寄生电 容。然而，在此过程中，受工艺限制，易损伤外围区的结构，产品良率较低，例如，如图1及图2所示，在蚀刻阵列区的过程中易损伤外围区中A区域的绝缘层，进而在A区域出现孔洞，使得后续沉积绝缘层比较困难，且在对阵列区进行蚀刻以形成空隙的过程中，蚀刻气体易穿过孔洞，进而与外围区内部电路接触，容易对外围区的内部电路造成蚀刻损伤，降低产品良率。
基于此，本公开提供了一种半导体结构的制备方法以解决上述技术问题。该半导体结构可为动态随机存取存储器(dynamic random access memory，DRAM)、静态随机存取存储器(static random access memory，SRAM)等。图3示出了本公开实施方式的半导体结构的制备方法的流程图，参见图3所示，该制备方法可包括步骤S110-步骤S130，其中：
步骤S110，提供衬底，所述衬底包括并排分布的阵列区和外围区，所述阵列区形成有隔离层、导电接触塞及多个间隔分布的位线结构，所述位线结构沿垂直于所述衬底的方向延伸，所述隔离层覆盖所述位线结构的侧壁，所述导电接触塞形成于相邻所述位线结构之间的所述隔离层围成的区域；所述外围区形成有堆叠膜层；
步骤S120，形成覆盖所述位线结构、所述隔离层、所述导电接触塞及所述堆叠膜层的掩膜层；
步骤S130，蚀刻所述掩膜层，以露出所述隔离层的顶部。
本公开的半导体结构的制备方法，一方面，可通过隔离层对位线结构及导电接触塞的两侧进行绝缘保护，进而防止位线结构与导电接触塞之间发生短路，降低器件的短路风险，提高产品良率；另一方面，在蚀刻露出隔离层的顶部的过程中，可通过掩膜层对外围区的堆叠膜层的表面进行保护，避免在对阵列区进行蚀刻的过程中对外围区表面的膜层造成损伤；此外，在对隔离层进行后续图案化处理的过程中，掩膜层仍然可作为保护屏障，对外围区内的堆叠膜层的表面进行保护，进一步提高产品良率。
下面对本公开实施方式半导体结构的制备方法的各步骤进行详细说明：
如图3所示，在步骤S110中，提供衬底，所述衬底包括并排分布的 阵列区和外围区，所述阵列区形成有隔离层、导电接触塞及多个间隔分布的位线结构，所述位线结构沿垂直于所述衬底的方向延伸，所述隔离层覆盖所述位线结构的侧壁，所述导电接触塞形成于相邻所述位线结构之间的所述隔离层围成的区域；所述外围区形成有堆叠膜层。
衬底可呈平板结构，衬底内含有字线结构(图中未示出)，可在衬底上预先定义出位线结构形成区域和电容接触孔形成区域，位线结构形成区域可用于形成位线结构，电容接触孔形成区域可用于形成导电接触塞。衬底可为矩形、圆形、椭圆形、多边形或不规则图形，其材料可以是硅或其他半导体材料，在此不对衬底的形状及材料做特殊限定。
衬底可包括阵列区和外围区，该阵列区可用于形成电容阵列和位线结构。阵列区可为圆形区域、矩形区域或不规则图形区域，在此不做特殊限定。外围区可与阵列区邻接分布。举例而言，外围区可为环形区域，并可环绕于阵列区的外周，例如，其可为矩形环区域，在此不做特殊限定。外围区可用于形成电路结构，该电路结构可与阵列区中的存储阵列模块连接，以便通过电路结构控制存储阵列模块充放电。
衬底可包括牺牲层，牺牲层的厚度可与所需的位线结构的厚度相同。可通过原子层沉积、真空蒸镀、磁控溅射、化学气相沉积或物理气相沉积等方式形成牺牲层，当然，还可通过其他工艺形成牺牲层，在此不对牺牲层的成型工艺做特殊限定。
可根据预先定义好的位线形成区域和电容接触孔形成区域采用光刻工艺对牺牲层进行图案化处理，以在牺牲层中形成并排分布的多个沟槽及多个通孔。需要说明的是，沟槽可至少分布于阵列区。
在平行于衬底的方向上沟槽可两端贯通，并可沿平行于衬底的方向延伸。通孔可为圆形孔、矩形孔或不规则形状的孔状结构，在此不做特殊限定。
通孔可为多个，多个通孔可排成一列，并可沿沟槽的延伸方向间隔设置。在一实施方式中，每条沟槽可与每列通孔构成一组，可形成多组并排分布的沟槽和通孔，且在相邻两组中沟槽与通孔所构成的列交替分布，即：各通孔分布于沟槽两侧，并可延沟槽的延伸方向间隔设置。
可在各沟槽的侧壁形成隔离层，隔离层可以是随形贴附于沟槽侧壁 的薄膜或涂层，在此不做特殊限定。隔离层可由绝缘材料构成，以便对各沟槽中的结构进行绝缘保护，防止结构短路。
在本公开的一种示例性实施方式中，如图4所示，隔离层1可包括第一隔离层11和第二隔离层12，可在各沟槽的侧壁形成第二隔离层12，第二隔离层12可以是随形贴附于沟槽侧壁的薄膜或涂层，在此不做特殊限定。
第二隔离层12可由绝缘材料构成，以便对各沟槽中的结构进行绝缘保护，防止结构短路。例如，第二隔离层12的材料可为氮化硅。可采用化学气相沉积、物理气相沉积、热蒸发或原子层沉积等工艺在沟槽侧壁形成第二隔离层12，当然，也可通过其他工艺形成第二隔离层12，在此不做特殊限定。
可在第二隔离层12背离沟槽侧壁的表面形成第一隔离层11，第一隔离层11可以是随形贴附于第二隔离层12表面的薄膜或涂层，在此不做特殊限定。第一隔离层11可由绝缘材料构成，进而可通过第一隔离层11和第二隔离层12对各沟槽中的结构进行双重绝缘保护，进一步防止结构短路。举例而言，第一隔离层11的材料可为氧化硅。可采用化学气相沉积、物理气相沉积、热蒸发或原子层沉积等工艺在第二隔离层12的表面形成第一隔离层11，当然，也可通过其他工艺形成第一隔离层11，在此不做特殊限定。
可在各沟槽内分别形成位线结构2，位线结构2可由导电材料构成，举例而言，位线结构2可包括堆叠分布的第一导电层21、第二导电层22及第三导电层23，第一导电层21、第二导电层22及第三导电层23可沿垂直于衬底的方向分布，其中，第二导电层22位于第一导电层21和第三导电层23之间，第一导电层21的材料可为多晶硅；第二导电层22的材料可为氮化钛；第三导电层23的材料可为钨。
在一实施方式中，可采用真空蒸镀、磁控溅射、化学气相沉积、物理气相沉积、热蒸发或原子层沉积等工艺在沟槽内依次形成第一导电层21、第二导电层22和第三导电层23，进而通过第一导电层21、第二导电层22和第三导电层23共同构成位线结构2。需要说明的是，位线结构2位于沟槽内，第一隔离层11覆盖于位线结构2的侧壁，第二隔离层 12覆盖于第一隔离层11的表面。
在本公开的另一种示例性实施方式中，可先在沟槽内形成位线结构2，再在位线结构2的侧壁形成第一隔离层11，随后，在第一隔离层11的表面形成第二隔离层12，在此过程中，第二隔离层12可填满第一隔离层11与沟槽之间的间隙，并可同时覆盖第一隔离层11的顶部。
在本公开的一种示例性实施方式中，隔离层1与位线结构2之间还设有覆盖层3，可采用化学气相沉积、物理气相沉积、热蒸发或原子层沉积等工艺在各位线结构2的表面形成覆盖层3，举例而言，覆盖层3可覆盖各位线结构2的侧壁及顶部，第一隔离层11和第二隔离层12位于覆盖层3的侧壁。覆盖层3可由绝缘材料构成，进而可通过覆盖层3、第一隔离层11及第二隔离层12对相邻两个位线结构2进行三重绝缘保护，防止位线结构2与周围其他结构之间发生短路，降低器件的短路风险。覆盖层3的材料可与第二隔离层12的材料相同，举例而言，其材料可为氮化硅，当然，可以是其他绝缘材料，在此不再一一列举。
在一实施方式中，覆盖层3的顶部与电容接触孔的底部的之间的距离可为650埃，其中，隔离层1顶部与覆盖层3顶部的距离为300埃，进而有利于后续形成空隙的过程中蚀刻气体顺利进入；隔离层1的顶部与电容接触孔底部的距离可为350埃，在后续蚀刻过程中，可避免电容接触孔底部的结构被蚀刻掉，进而避免空隙失效。
在本公开的一种示例性实施方式中，可在位于阵列区的各通孔中沉积导电材料，进而形成导电接触塞4，如图4所示，导电接触塞4可填充于相邻两个位线结构2之间的隔离层1围成的区域，举例而言，导电接触塞4可填充于相邻两个位线结构2之间的第二隔离层12围成的区域。举例而言，导电材料可为多晶硅或钨。可采用真空蒸镀、磁控溅射、化学气相沉积、物理气相沉积、热蒸发或原子层沉积等工艺在各通孔内形成导电接触塞4，当然，也可采用其他工艺形成导电接触塞4，在此不再一一列举。
需要说明的是，各导电接触塞4可呈阵列间隔分布，每两个相邻分布的位线结构2之间可分布一个导电接触塞4，相邻两个导电接触塞4之间通过绝缘材料隔开，进而避免相邻两个导电接触塞4之间发生短路 或耦合。该绝缘材料可以是隔离层1的材料，也可以是覆盖层3的材料，在此不做特特殊限定。
在一实施方式中，导电接触塞4可呈“Z”字型，其“Z”字的底部的顶表面可低于隔离层1的顶部，进而避免在蚀刻形成空隙的过程中，损伤电容接触塞4周围的氧化物。举例而言，“Z”字的底部的顶表面与隔离层1的顶部的间距可为130埃。“Z”字型中斜面的厚度可为11nm～12nm，举例而言，其厚度可为11nm、11.2nm、11.4nm、11.6nm、11.8nm或12nm，当然，也可以是其他厚度，在此不再一一列举。
在形成导电接触塞4后可去除牺牲层，举例而言，可采用酸性溶液进行湿法蚀刻，在使用时，可根据牺牲层的具体材料设定酸性溶液与去离子水的配制比例，在此不对蚀刻溶液的配比及浓度做特殊限定。
如图5所示，外围区可设有堆叠膜层6，堆叠膜层6可包括驱动电路和绝缘层，驱动电路可为多个，可通过绝缘层将各驱动电路分隔开，以免各驱动电路之间发生耦合或短路。
如图3所示，在步骤S120中，形成覆盖所述位线结构、所述隔离层、所述导电接触塞及所述堆叠膜层的掩膜层。
可在位线结构2、隔离层1、导电接触塞4及堆叠膜层6的表面形成掩膜层5，掩膜层5可随型贴附于位线结构2、隔离层1、导电接触塞4及堆叠膜层6的表面，其可以是形成于位线结构2、隔离层1、导电接触塞4及堆叠膜层6的表面的薄膜，也可以是形成于位线结构2、隔离层1、导电接触塞4及堆叠膜层6的表面的涂层，在此不对掩膜层5的类型做特殊限定。
需要说明的是，当堆叠膜层6包括绝缘层及驱动电路时，掩膜层5可同时覆盖绝缘层及驱动电路的表面，以便在对阵列区进行后续蚀刻的过程中通过掩膜层5保护外围区内的绝缘层及驱动电路表面，避免外围区内的绝缘层及驱动电路损伤，可提高产品良率。
举例而言，掩膜层5的材料可为绝缘材料，例如，其材料可为氮化硅，可采用物理气相沉积、化学气相沉积、原子层沉积、真空蒸镀或磁控溅射等工艺在位线结构2、隔离层1、导电接触塞4及堆叠膜层6的表面形成掩膜层5，当然，还可通过其他工艺在位线结构2、隔离层1、导 电接触塞4及堆叠膜层6的表面形成掩膜层5，在此不对掩膜层5的形成工艺做特殊限定。
在本公开的一种示例性实施方式中，掩膜层5的厚度可为2nm～10nm，举例而言，其可为2nm、4nm、6nm、8nm或10nm，当然，也可以是其他厚度，只要能保证在对阵列区做图案化处理时，外围区不被损伤即可，在此不再一一列举。
在本公开的一种示例性实施方式中，为了保证各个区域中的掩膜层5的厚度均相等，可通过多次沉积工艺沉积形成掩膜层5。举例而言，掩膜层5可包括一层或多层子膜层；当其包括一层子膜层时，可通过多次沉积工艺沉积形成该子膜层，每次沉积的厚度相对较小，进而避免在一部分区域沉积的较厚，另一部分区域沉积的较薄，保证各个区域中的掩膜层5的厚度大致相等。当其包括多层子膜层时，各子膜层的材料可以相同，也可以不同，在此不对各子膜层的材料做特殊限定，在沉积各子膜层的过程中，每次可沉积一层子膜层，相邻子膜层的厚度可以相同，也可以不同，在此不做特殊限定。在本公开实施方式中，完成步骤S120后阵列区的结构如图6所示。
在本公开的一种示例性实施方式中，掩膜层5可包括多层子膜层，例如，掩膜层5可包括第一子膜层和第二子膜层，形成覆盖位线结构2、隔离层1、导电接触塞4及堆叠膜层6的掩膜层5，即步骤S120可包括步骤S1201及步骤S1202，如图7所示，其中：
步骤S1201，在所述位线结构、所述隔离层、所述导电接触塞及所述堆叠膜层共同构成的结构的表面形成第一预设厚度的第一子膜层。
第一子膜层可以是形成于位线结构2、隔离层1、导电接触塞4及堆叠膜层6表面的薄膜，也可以是形成于位线结构2、隔离层1、导电接触塞4及堆叠膜层6表面的涂层，在此不对第一子膜层的具体形式做特殊限定。
第一子膜层的材料可为绝缘材料，例如，其可为氮化硅。可采用物理气相沉积、化学气相沉积或原子层沉积等工艺在位线结构2、隔离层1、导电接触塞4及堆叠膜层6的表面形成第一预设厚度的第一子膜层，当然，也可采用其他工艺形成第一子膜层，在此不对第一子膜层的形成工 艺做特殊限定。
在一实施方式中，第一预设厚度可为2nm～4nm，举例而言，其可为2nm、2.5nm、3nm、3.5nm或4nm，当然，也可以是其他厚度，在此不再一一列举。
步骤S1202，在所述第一子膜层的表面形成第二预设厚度的第二子膜层。
第二子膜层可形成于第一子膜层背离衬底的一侧。第二子膜层可以是形成于第一子膜层表面的薄膜，也可以是形成于第一子膜层表面的涂层，在此不对第二子膜层的具体形式做特殊限定。
第二子膜层的材料可为绝缘材料，其与第一子膜层的材料可以相同，举例而言，第一子膜层和第二子膜层的材料可均为氮化硅。可采用物理气相沉积、化学气相沉积或原子层沉积等工艺在第一子膜层的表面形成第二预设厚度的第二子膜层，当然，也可采用其他工艺形成第二子膜层，在此不对第二子膜层的形成工艺做特殊限定。
在一实施方式中，第二预设厚度可为3nm～6nm，举例而言，其可为3nm、4nm、5nm或6nm，当然，也可以是其他厚度，在此不再一一列举。
如图3所示，在步骤S130中，蚀刻所述掩膜层，以露出所述隔离层的顶部。
可采用蚀刻工艺去除位于隔离层1顶部的掩膜层5，以将隔离层1的顶部暴露出来。在此过程中，可通过同一次蚀刻工艺一并去除位于阵列区内的其他区域中的掩膜层5，避免额外设置蚀刻工艺去除阵列区内的其他区域中的掩膜层5，可简化工艺，降低生产成本。即：可同时去除位于位线结构2、第一隔离层11、第二隔离层12及导电接触塞4表面的掩膜层5，只保留位于外围区的绝缘层及驱动电路表面的掩膜层5。
举例而言，可采用干法蚀刻工艺去除位于位线结构2、第一隔离层11、第二隔离层12及导电接触塞4表面的掩膜层5，只保留位于外围区的绝缘层及驱动电路表面的掩膜层5。
在本公开的一种示例性实施方式中，当掩膜层5包括一层子膜层时，可对子膜层进行多次蚀刻，在每一次蚀刻的过程中均可同时蚀刻位于位线结构2、第一隔离层11、第二隔离层12及导电接触塞4表面的掩膜层 5，直至其露出隔离层1的顶部，即，每一次蚀刻工艺均可蚀刻一定厚度子膜层，如此，每一次蚀刻的厚度较小，可保证阵列区中每一部分结构对应的区域的表面的掩膜层5都可被恰好蚀刻完，而不会损伤阵列区中任何一部分结构，在此过程中，若有某一部分上的掩膜层5被最先蚀刻完，在下一次蚀刻工艺时，可针对该区域以外的区域进行蚀刻，而不再对该区域进行蚀刻，以避免该区域内的结构被损伤，有助于提高产品良率；当然，当掩膜层5包括一层子膜层时，也可对该子膜层进行一次蚀刻，只要不损伤阵列区中各区域内的结构即可，在此不对蚀刻次数做特殊限定。
在本公开的一种示例性实施方式中，当掩膜层5包括多层子膜层时，可对各子膜层进行分层蚀刻，在每一次蚀刻的过程中均可同时蚀刻位于位线结构2、第一隔离层11、第二隔离层12及导电接触塞4表面的掩膜层5，直至其露出隔离层1的顶部，即，可对掩膜层5进行多次蚀刻，每一次蚀刻工艺可蚀刻一层子膜层，如此，每一次蚀刻的厚度较小，可保证阵列区中每一部分结构对应的区域的表面的掩膜层5都可被恰好蚀刻完，而不会损伤阵列区中任何一部分结构，在此过程中，若有某一部分上的掩膜层5被最先蚀刻完，在下一次蚀刻工艺时，可针对该区域以外的区域进行蚀刻，而不再对该区域进行蚀刻，以避免该区域内的结构被损伤，有助于提高产品良率；当然，当掩膜层5包括多层子膜层时，也可对多层子膜层进行一次性蚀刻，只要不损伤阵列区中各区域内的结构即可，在此不对蚀刻次数做特殊限定。在本公开实施方式中，完成步骤S130后阵列区的结构如图8所示。
在本公开的一种示例性实施方式中，去除位于位线结构2、第一隔离层11、第二隔离层12及导电接触塞4表面的掩膜层5，即步骤S130可包括步骤S1301-步骤S1303，如图9所示，其中：
步骤S1301，在所述掩膜层的表面形成光阻层。
可通过旋涂或其它方式在掩膜层5背离衬底的表面形成光阻层，光阻层的材料可以是正性光刻胶或负性光刻胶，在此不做特殊限定。
步骤S1302，对所述光阻层进行曝光并显影，以形成显影区，所述显影区露出位于所述阵列区的所述掩膜层。
可采用掩膜版对光阻层进行曝光，该掩膜版的图案可与光阻层所需的图案匹配，例如，掩膜图案可与阵列区的形状相匹配，其尺寸可与阵列区的尺寸相同。可对曝光后的光阻层进行显影，从而形成显影区，该显影区可露出掩膜层5。
步骤S1303，在所述显影区对所述掩膜层进行干法蚀刻，以去除位于所述阵列区的所述掩膜层。
可通过干法蚀刻在显影区对掩膜层5进行蚀刻，以形成开口，开口可露出导电接触塞4、隔离层1的顶部以及位于阵列区的位线结构2顶部的覆盖层3，进而保留位于外围区表面的掩膜层5。
举例而言，可采用蚀刻气体对掩膜层5进行等离子体蚀刻，进而去除位于导电接触塞4表面、隔离层1的顶部以及位于阵列区的位线结构2顶部的覆盖层3表面的掩膜层5。在一实施方式中，可通过蚀刻气体对掩膜材料层进行选择性蚀刻，举例而言，蚀刻气体可为HF，在等离子体蚀刻过程中蚀刻气体可在设备空间内扩散，进而横向进入，以将掩膜蚀刻掉。
在本公开的一种示例性实施方式中，本公开的半导体结构的制备方法还可包括步骤S140及步骤S150，如图10所示，其中：
步骤S140，去除所述第一隔离层，以在所述位线结构和所述第二隔离层之间形成空隙。
可采用干法蚀刻工艺去除第一隔离层11，进而在位线结构2和第二隔离层12之间形成空隙7，可通过空隙7的设置减小各位线结构2之间的寄生电容。在此过程中，由于外围区的结构表面被掩膜层5覆盖，在此过程中，即便会对外围区表面的膜层有所消耗，其消耗的也是掩膜层5的材料，不会对外围区的绝缘层及驱动电路的表面造成损伤。在本公开实施方式中，完成步骤S140后阵列区的结构如图11所示。
在一实施方式中，空隙7的高度可大于100埃，举例而言，其可为100埃、120埃、140埃、160埃、180埃或200埃，当然，也可以是其他高度，在此不再一一列举。
在一实施方式中，去除所述第一隔离层11，以在所述位线结构2和所述第二隔离层12之间形成空隙7，即步骤S140可包括步骤S1401及 步骤S1402，如图12所示，其中：
步骤S1401，采用干法蚀刻工艺去除位于所述第一隔离层顶部的所述第二隔离层，以露出所述第一隔离层的顶部。
可采用等离子体蚀刻工艺去除位于第一隔离层11顶部的第二隔离层12，以将第一隔离层11的顶部露出，举例而言，可通过蚀刻气体对位于第一隔离层11顶部的第二隔离层12进行选择性蚀刻，举例而言，蚀刻气体可为HF。在此过程中，由于外围区的结构表面被掩膜层5覆盖，即便会对外围区表面的膜层有所消耗，其消耗的也是掩膜层5的材料，不会对外围区的绝缘层及驱动电路的表面造成损伤。
步骤S1402，采用干法蚀刻工艺去除所述第一隔离层。
可采用等离子体蚀刻工艺去除第一隔离层11，进而在位线结构2和第二隔离层12之间形成空隙7，可通过空隙7的设置减小各位线结构2之间的寄生电容。在此过程中，由于外围区的结构表面被掩膜层5覆盖，在此过程中，即便会对外围区表面的膜层有所消耗，其消耗的也是掩膜层5的材料，不会对外围区的绝缘层及驱动电路的表面造成损伤。举例而言，可通过蚀刻气体对位于第一隔离层11进行选择性蚀刻，举例而言，蚀刻气体可为HF。如图13所示，在蚀刻过程中蚀刻气体可沿图13中箭头所示方向在字线结构100、位线结构2及电容接触塞4之间的间隙处扩散，进而扩散至位线结构2侧壁上的第一隔离层11所在位置，从而将第一隔离层11去除。
步骤S150，形成覆盖所述空隙的开口的封闭层。
在去除第一隔离层11后，可对空隙7进行封口处理，以增强结构支撑强度。例如，可采用物理气相沉积、化学气相沉积或原子层沉积等工艺在空隙7的开口处形成封闭层8。封闭层8的材料可为绝缘材料，例如，其材料可为氮化硅。
需要说明的是，为了工艺方便，可在位线结构2、第二隔离层12及导电接触塞4共同构成的结构的表面同时形成封闭层8。封闭层8的厚度可根据产品需要设定，在此不做特殊限定，例如，其厚度可为100埃。在本公开实施方式中，完成步骤S150后阵列区的结构如图14所示。
需要说明的是，尽管在附图中以特定顺序描述了本公开中半导体结 构的制备方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开实施例还提供一种半导体结构，图13示出了本公开实施方式的半导体结构的示意图，参见图13所示，该半导体结构可包括衬底、掩膜层5及封闭层8，其中：
衬底包括并排分布的阵列区和外围区，阵列区上形成有多个间隔分布的位线结构2、与位线结构2的侧壁同向延伸的第二隔离层12及位于第二隔离层12和位线结构2的侧壁之间的空隙7，相邻位线结构2之间的第二隔离层12围成的区域形成有导电接触塞4；外围区上形成有堆叠膜层6；
掩膜层5覆盖于堆叠膜层6的表面；
封闭层8覆盖空隙7的开口。
上述半导体结构中各部分的具体细节、制备工艺以及有益效果已经在对应的半导体结构的制备方法中进行了详细描述，因此，此处不再赘述。
本公开实施例还提供一种存储器，该存储器可包括由上述任一实施方式中的半导体结构，其具体细节、形成工艺以及有益效果已经在对应的半导体结构的制备方法及半导体结构中进行了详细说明，此处不再赘述。
举例而言，该存储器可以是动态随机存取存储器(Dynamic Random Access Memory，DRAM)、静态随机存取存储器(static random access memory，SRAM)等。当然，还可以是其它存储装置，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权 利要求指出。

Claims (15)

  1. 一种半导体结构的制备方法，包括：
    提供衬底，所述衬底包括并排分布的阵列区和外围区，所述阵列区形成有隔离层、导电接触塞及多个间隔分布的位线结构，所述位线结构沿垂直于所述衬底的方向延伸，所述隔离层覆盖所述位线结构的侧壁，所述导电接触塞形成于相邻所述位线结构之间的所述隔离层围成的区域；所述外围区形成有堆叠膜层；
    形成覆盖所述位线结构、所述隔离层、所述导电接触塞及所述堆叠膜层的掩膜层；
    蚀刻所述掩膜层，以露出所述隔离层的顶部。
  2. 根据权利要求1所述的制备方法，其中，所述掩膜层包括一层或多层子膜层，所述蚀刻所述掩膜层，以露出所述隔离层的顶部，包括：
    对所述子膜层进行多次蚀刻，直至露出所述隔离层的顶部。
  3. 根据权利要求1所述的制备方法，其中，所述隔离层包括第一隔离层和第二隔离层，所述第一隔离层覆盖于所述位线结构的侧壁，所述第二隔离层覆盖于所述第一隔离层的表面，所述导电接触塞形成于相邻所述位线结构之间的所述第二隔离层围成的区域；所述堆叠膜层包括多个驱动电路和分隔各所述驱动电路的绝缘层，所述掩膜层覆盖所述绝缘层及所述驱动电路的表面；所述蚀刻所述掩膜层，以露出所述隔离层的顶部，包括：
    去除位于所述位线结构、所述第一隔离层、所述第二隔离层及所述导电接触塞表面的所述掩膜层。
  4. 根据权利要求3所述的制备方法，其中，所述制备方法还包括：
    去除所述第一隔离层，以在所述位线结构和所述第二隔离层之间形成空隙；
    形成覆盖所述空隙的开口的封闭层。
  5. 根据权利要求2所述的制备方法，其中，所述掩膜层包括多层所述子膜层，所述形成覆盖所述位线结构、所述隔离层、所述导电接触塞及所述堆叠膜层的掩膜层，包括：
    在所述位线结构、所述隔离层、所述导电接触塞及所述堆叠膜层共 同构成的结构的表面形成第一预设厚度的第一子膜层；
    在所述第一子膜层的表面形成第二预设厚度的第二子膜层。
  6. 根据权利要求5所述的制备方法，其中，所述第一预设厚度为2nm～4nm，所述第二预设厚度为3nm～6nm。
  7. 根据权利要求5所述的制备方法，其中，所述第一子膜层和所述第二子膜层的材料相同。
  8. 根据权利要求1所述的制备方法，其中，每两个相邻分布的所述位线结构之间分布一个所述导电接触塞，各所述导电接触塞呈阵列分布。
  9. 根据权利要求3所述的制备方法，其中，所述去除位于所述位线结构、所述第一隔离层、所述第二隔离层及所述导电接触塞表面的所述掩膜层，包括：
    在所述掩膜层的表面形成光阻层；
    对所述光阻层进行曝光并显影，以形成显影区，所述显影区露出位于所述阵列区的所述掩膜层；
    在所述显影区对所述掩膜层进行干法蚀刻，以去除位于所述阵列区的所述掩膜层。
  10. 根据权利要求4所述的制备方法，其中，所述去除所述第一隔离层，以在所述位线结构和所述第二隔离层之间形成空隙，包括：
    采用干法蚀刻工艺去除位于所述第一隔离层顶部的所述第二隔离层，以露出所述第一隔离层的顶部；
    采用干法蚀刻工艺去除所述第一隔离层。
  11. 根据权利要求9或10所述的制备方法，其中，所述干法蚀刻包括等离子体蚀刻。
  12. 根据权利要求9或10所述的制备方法，其中，所述干法蚀刻的蚀刻气体为HF。
  13. 根据权利要求1-10任一项所述的制备方法，其中，所述掩膜层的材料为氮化硅。
  14. 一种半导体结构，包括：
    衬底，所述衬底包括并排分布的阵列区和外围区，所述阵列区上形成有多个间隔分布的位线结构、与所述位线结构的侧壁同向延伸的第二 隔离层及位于所述第二隔离层和所述位线结构的侧壁之间的空隙，相邻所述位线结构之间的所述第二隔离层围成的区域形成有导电接触塞；所述外围区上形成有堆叠膜层；
    掩膜层，覆盖于所述堆叠膜层的表面；
    封闭层，覆盖所述空隙的开口。
  15. 一种存储器，包括权利要求14所述的半导体结构。
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CN114121778A (zh) * 2020-08-26 2022-03-01 长鑫存储技术有限公司 存储器及其制造方法

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