WO2024040697A1 - 半导体结构及其形成方法、存储器 - Google Patents

半导体结构及其形成方法、存储器 Download PDF

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Publication number
WO2024040697A1
WO2024040697A1 PCT/CN2022/124071 CN2022124071W WO2024040697A1 WO 2024040697 A1 WO2024040697 A1 WO 2024040697A1 CN 2022124071 W CN2022124071 W CN 2022124071W WO 2024040697 A1 WO2024040697 A1 WO 2024040697A1
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Prior art keywords
layer
trench
word line
insulating
substrate
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PCT/CN2022/124071
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English (en)
French (fr)
Inventor
韩清华
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP22924575.8A priority Critical patent/EP4350736A1/en
Priority to US18/366,819 priority patent/US20240074164A1/en
Publication of WO2024040697A1 publication Critical patent/WO2024040697A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor technology, and specifically, to a semiconductor structure, a method of forming the same, and a memory.
  • DRAM Dynamic Random Access Memory
  • the present disclosure provides a semiconductor structure, a method of forming the same, and a memory, which can reduce parasitic capacitance, reduce power consumption, and improve product stability.
  • a method for forming a semiconductor structure including:
  • the substrate includes a substrate and an insulating dielectric layer, the substrate includes a plurality of first trenches spaced apart along a first direction, and the insulating dielectric layer fills each of the first trenches;
  • An air gap is formed between two adjacent word line structures
  • the air gap is sealed.
  • the forming method further includes:
  • An insulation layer is formed between adjacent word line structures, and the air gap is located in the insulation layer.
  • forming the insulating layer includes:
  • first insulating layer within the second trench having the first insulating material layer, the top of the first insulating layer being lower than the top of the first insulating material layer;
  • the surface of the second insulating material layer is planarized so that the top of the second insulating material layer is flush with the surface of the substrate, and the remaining second insulating material layer is flush with the first surface.
  • the insulating material layers together constitute the second insulating layer;
  • a predetermined thickness of the protective layer is removed to form a word line filling trench, and the word line filling trench does not expose the bottom of the second trench.
  • forming the word line structure includes:
  • word line filling trench with the inter-gate dielectric layer with a first conductive material filling the word line filling trench with the inter-gate dielectric layer with a first conductive material to form a word line structure.
  • forming the air gap includes:
  • the first insulating layer is removed to form the air gap.
  • sealing the air gap includes:
  • a sealing layer is formed on the surface of the passivation layer having the air gap, and the sealing layer at least covers the opening of the air gap.
  • the forming method further includes:
  • bit line structure is formed at the bottom of the second trench, the bit line structure traverses a plurality of the second trenches, and the bit line structure and the word line structure Insulation settings.
  • bit line structure includes:
  • a second conductive material is filled in the third trench to form the bit line structure.
  • the protective layer is located between the bit line structure and the word line structure, and the bit line structure and the word line structure are insulated by the protective layer.
  • a semiconductor structure including:
  • a substrate the substrate includes a substrate and an insulating dielectric layer, the substrate includes a plurality of first trenches spaced apart along a first direction and a plurality of second trenches spaced apart along a second direction, the insulating medium Each first trench is filled with a layer, the second trench penetrates each first trench and the insulating dielectric layer inside, and the second direction intersects with the first direction;
  • a plurality of word line structures are respectively formed in each of the second trenches, and an air gap is formed between two adjacent word line structures;
  • the sealing layer covers at least the opening of the air gap.
  • the semiconductor structure further includes:
  • An insulating layer is formed between adjacent word line structures, and the air gap is located in the insulating layer.
  • the insulating layer includes:
  • Passivation layer filling the second trench with the protective layer, and in a direction perpendicular to the substrate, a word line filling trench is formed on one end of the passivation layer away from the protective layer , the air gap is located in the passivation layer between adjacent word line filling trenches, and the air gap and the word line filling trench are insulated by the passivation layer.
  • the word line structure includes:
  • An inter-gate dielectric layer is formed at the bottom of the word line filling trench and the sidewall of the word line filling trench away from the insulating layer;
  • a first conductive layer fills the word line filling trench with the inter-gate dielectric layer.
  • the semiconductor structure further includes:
  • a bit line structure is formed at the bottom of the second trench, the bit line structure traverses a plurality of the second trenches, and the bit line structure is insulated from the word line structure.
  • the protective layer is located between the bit line structure and the word line structure, and the bit line structure and the word line structure are insulated by the protective layer.
  • a memory including the semiconductor structure described in any one of the above.
  • the semiconductor structure and its formation method and memory of the present disclosure help to save structural space and improve device integration by forming a second trench in the substrate and burying the word line structure in the second trench.
  • an air gap can be formed between two adjacent word line structures. Since the dielectric constant of the air gap is small, the parasitic capacitance between the word line structures can be effectively reduced and the power consumption of the device can be reduced; again On the other hand, by sealing the air gap, the air gap can be sealed between adjacent word line structures, which can prevent the final formed semiconductor structure from breaking at the opening of the air gap and improve product yield.
  • FIG. 1 is a flow chart of a method of forming a semiconductor structure in an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of a substrate in an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of the substrate in an embodiment of the present disclosure cut along a second direction;
  • FIG. 4 is a schematic diagram of the word line structure in an embodiment of the present disclosure, cut along a second direction;
  • Figure 5 is a schematic diagram of the protective layer in an embodiment of the present disclosure.
  • Figure 6 is a schematic diagram of the first insulating material layer in an embodiment of the present disclosure.
  • Figure 7 is a schematic diagram of the first insulating layer in an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of the second insulating layer in an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram cut along the second direction after step S460 is completed in the embodiment of the present disclosure.
  • Figure 10 is a schematic diagram cut along the dotted line in Figure 9 after step S460 is completed in an embodiment of the present disclosure
  • Figure 11 is a schematic diagram cut along the second direction after step S470 is completed in the embodiment of the present disclosure.
  • Figure 12 is a schematic diagram cut along the dotted line in Figure 11 after step S470 is completed in an embodiment of the present disclosure
  • Figure 13 is a schematic diagram cut along the second direction after step S480 is completed in the embodiment of the present disclosure.
  • Figure 14 is a schematic diagram cut along the second direction after step S510 is completed in the embodiment of the present disclosure.
  • Figure 15 is a schematic diagram cut along the dotted line in Figure 14 after step S510 is completed in an embodiment of the present disclosure
  • Figure 16 is a schematic diagram cut along the dotted line in Figure 4 after step S520 is completed in an embodiment of the present disclosure
  • Figure 17 is a schematic diagram cut along the second direction after step S140 is completed in the embodiment of the present disclosure.
  • Figure 18 is a schematic diagram cut along the first direction after backfilling with insulating material in an embodiment of the present disclosure
  • Figure 19 is a schematic diagram cut along the second direction after step S610 is completed in the embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram cut along the second direction after step S150 is completed in the embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • FIG. 1 shows a flow chart of the method for forming a semiconductor structure of the present disclosure.
  • the formation method may include steps S110 to S150, wherein:
  • Step S110 provide a substrate, the substrate includes a substrate and an insulating dielectric layer, the substrate includes a plurality of first trenches spaced apart along the first direction, and the insulating dielectric layer fills each of the first trenches;
  • Step S120 pattern etching the substrate to form a plurality of second trenches spaced apart along a second direction, where the second direction intersects the first direction;
  • Step S130 form word line structures in each of the second trenches
  • Step S140 form an air gap between two adjacent word line structures
  • Step S150 seal the air gap.
  • the method for forming a semiconductor structure of the present disclosure forms a second trench in the substrate and buries the word line structure in the second trench, which helps save structural space and improves device integration; on the other hand, it helps to save structural space and improve device integration;
  • an air gap can be formed between two adjacent word line structures. Since the dielectric constant of the air gap is small, the parasitic capacitance between the word line structures can be effectively reduced and the power consumption of the device is reduced; on the other hand, through Sealing the air gap can seal the air gap between adjacent word line structures, which can prevent the final semiconductor structure from breaking at the opening of the air gap and improve product yield.
  • a substrate is provided.
  • the substrate includes a substrate and an insulating dielectric layer.
  • the substrate includes a plurality of first trenches spaced apart along a first direction.
  • the insulating dielectric layer fills Each of the first trenches.
  • the substrate 1 may include a substrate 11 and an insulating dielectric layer 12 .
  • the substrate 11 may be provided with a plurality of first electrodes spaced apart along the first direction A. grooves (not shown in the figure), and each first groove can extend along the second direction B.
  • the first trench may be a groove-like structure formed by an inward depression on the surface of the substrate 11 , and may penetrate both ends of the substrate 11 .
  • the first direction A may intersect the second direction B.
  • the first direction A and the second direction B may be perpendicular to each other.
  • verticality can be absolutely vertical or approximately vertical, and there will inevitably be deviations during the manufacturing process.
  • angle deviations may occur due to limitations in the manufacturing process, such that the first direction A and the second direction There is a certain deviation in the angle between B. As long as the angle deviation between the first direction A and the second direction B is within a preset range, the first direction A and the second direction B can be considered to be perpendicular.
  • the preset range may be 10°, that is, when the angle between the first direction A and the second direction B is greater than or equal to 80° and less than or equal to 100°, it can be considered that the first direction A and the second direction B are equal to or greater than 80°.
  • the second direction B is vertical.
  • the insulating material can be filled into each first trench respectively to form the insulating dielectric layer 12 .
  • the insulating dielectric layer 12 can fill each first trench, and the upper surface of the insulating dielectric layer 12 can be flush with the upper surface of the substrate 11 .
  • a substrate 1 is provided.
  • the substrate 1 includes a substrate 11 and an insulating dielectric layer 12 .
  • the substrate 11 includes a plurality of first trenches spaced apart along a first direction A.
  • the insulating dielectric layer 12 Filling each first trench may include steps S210 to S230, wherein:
  • Step S210 provide substrate 11.
  • the substrate 11 may have a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be silicon or other semiconductor materials.
  • the shape and material of the substrate 11 are not specifically limited here.
  • Step S220 etching the substrate 11 to form a plurality of first trenches distributed at intervals, the first trenches extending along the second direction B, and the plurality of first trenches extending along the second direction B.
  • the first direction A is distributed at intervals.
  • a photolithography process can be used to form a plurality of first trenches in the substrate 11 .
  • Each first trench can extend along the second direction B, and the plurality of first trenches can be spaced apart along the first direction A.
  • a photoresist layer can be formed on the surface of the substrate 11 by spin coating or other methods.
  • the material of the photoresist layer can be a positive photoresist or a negative photoresist, which is not specifically limited here.
  • the shape of the surface of the photoresist layer away from the substrate 11 may be the same as the shape of the surface of the substrate 11 .
  • the photoresist layer can be exposed using a mask, and the pattern of the mask can match the pattern required for each first trench.
  • the exposed photoresist layer can be developed to form a developed area, which can expose the substrate 11, and the pattern of the developed area can be the same as the pattern required for the first trench, and the size of the developed area can be Same size as desired first trench.
  • the substrate 11 may be anisotropically etched in the development area to form each first trench. It should be noted that in the direction perpendicular to the substrate 11 , the first trench does not penetrate the substrate 11 , that is, the substrate 11 material still remains at the bottom of the first trench.
  • Step S230 Fill each first trench with an insulating material to form an insulating dielectric layer 12.
  • Vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition can be used to fill the first trench with the insulating material.
  • the insulating material can fill all the first trenches.
  • the insulating material may be an oxide, for example, it may be silicon oxide.
  • step S120 the substrate is patterned and etched to form a plurality of second trenches spaced apart along a second direction B.
  • the second direction B and the first direction A are intersect.
  • the substrate 1 can be etched to form a plurality of second trenches 101 spaced apart in the substrate 1 .
  • each second trench 101 may extend along the first direction A, and the plurality of second trenches 101 may be spaced apart along the second direction B.
  • the second trench 101 does not penetrate the substrate 11 in a direction perpendicular to the substrate 11 , that is, the bottom of the second trench 101 still retains material of the substrate 11 .
  • the depth of the second trench 101 may be less than the depth of the first trench, or may be equal to the depth of the first trench, which is not specifically limited here.
  • each second trench 101 and each first trench may be separated into a plurality of groups spaced apart along the first direction A in the substrate 11 Distributed support columns 110 .
  • the support pillars 110 in each group may be equally spaced along the first direction A; multiple groups of support pillars 110 may be equally spaced along the second direction B.
  • each group of support columns 110 may be distributed at equal intervals along the second direction B.
  • etching the substrate 1 to form a plurality of second trenches 101 spaced apart along the second direction B may include steps S310 to S350, wherein:
  • Step S310 forming a mask layer 6 on the surface of the substrate 1.
  • the mask layer 6 can be formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, vacuum evaporation, magnetron sputtering, atomic layer deposition or other methods.
  • the mask layer 6 can be multi-layered.
  • the film structure may also be a single-layer film structure, and its material may be at least one of polymer, SiO2, SiN, polysilicon, and SiCN. Of course, it may also be other materials, which are not listed here.
  • the mask layer 6 may be a multi-layer, which may include a polymer layer, an oxide layer and a hard mask layer 6, wherein the polymer layer may be formed on the surface of the substrate 1 and the oxide layer may be located on the hard mask layer. between membrane layer 6 and polymer layer.
  • a polymer layer can be formed on the surface of the substrate 1 through a chemical vapor deposition process, an oxide layer can be formed on the surface of the polymer layer through a vacuum evaporation process, and a hard mask layer 6 can be formed on the surface of the oxide layer through an atomic layer deposition process.
  • Step S320 Form a photoresist layer on the surface of the mask layer 6.
  • a photoresist layer can be formed on the surface of the mask layer 6 away from the substrate 1 by spin coating or other methods.
  • the material of the photoresist layer can be a positive photoresist or a negative photoresist, and is not specifically limited here.
  • Step S330 Expose and develop the photoresist layer to form a plurality of spaced apart development areas.
  • the photoresist layer can be exposed using a mask, and the pattern of the mask can match the pattern required for the second trench 101 . Subsequently, the exposed photoresist layer can be developed to form a plurality of spaced-apart developing areas. Each developing area can expose the surface of the mask layer 6 respectively, and the pattern of the developing area can be consistent with that of the second trench 101 . The required pattern is the same, and the size of the developed area can be the same as the required size of the second trench 101 .
  • Step S340 Etch the mask layer 6 in the development area to form a plurality of mask patterns spaced apart along the second direction B.
  • the orthographic projection of the mask pattern on the substrate 11 is horizontal. Wear a plurality of said first grooves.
  • the mask layer 6 can be etched in each development area through an anisotropic etching process, and the etching area can expose the substrate 1, thereby forming multiple mask patterns on the mask layer 6.
  • the mask patterns can be in a strip shape, and can be It intersects with the extending direction of the first trench, and the orthographic projection of each mask pattern on the substrate 1 can traverse a plurality of first trenches respectively.
  • the mask pattern may be a strip pattern extending along the first direction A, and the plurality of mask patterns may be spaced apart along the second direction B.
  • each film layer can be etched in layers, that is, one time
  • the etching process can etch one layer, and multiple etching processes can be used to etch through the mask layer 6 to form a mask pattern.
  • the shape and size of the mask pattern can be consistent with the requirements of each second trench 101. The pattern and size are the same.
  • the photoresist layer can be removed by cleaning with a cleaning solution or ashing, so that the etched mask layer 6 is no longer covered by the photoresist layer.
  • Step S350 use the mask layer 6 with the mask pattern as a mask to perform anisotropic etching on the substrate 1 to form a plurality of layers extending along the first direction A and spaced apart along the second direction B. Second trench 101.
  • the mask layer 6 with a mask pattern can be used as a mask, and then the substrate 1 can be anisotropically etched to form a plurality of second trenches 101 extending along the first direction A and spaced apart along the second direction B,
  • the second trench 101 is perpendicular to the first trench, and the substrate 11 can be divided into a plurality of support pillars 110 distributed in an array through the first trench and the second trench 101.
  • Support columns 110 may be arranged in rows and columns.
  • step S130 word line structures are formed in each of the second trenches.
  • each second trench 101 can be filled with a conductive material, and then a word line structure 2 can be formed in each second trench 101 .
  • word line structures 2 may be formed in each second trench 101 in one-to-one correspondence. That is, there may be multiple word line structures 2, and the number of word line structures 2 is equal to the number of second trenches 101.
  • Each word line structure 2 can extend along the first direction A, and multiple word line structures 2 can be spaced apart along the second direction B.
  • an insulating layer 3 that subsequently isolates each word line structure 2 may be formed before forming the word line structure 2.
  • forming the insulating layer 3 may include steps S410 to S480. in:
  • Step S410 Form a protective layer 31 conformably attached to the side wall of the second trench 101.
  • the protective layer 31 of the side wall can protect the surface of the side wall of the second trench 101 through the protective layer 31, preventing the side wall of the second trench 101 from being damaged when exposed to the outside world in the subsequent process.
  • the protective layer 31 The material may be an insulating material, which may be the same as the material of the insulating dielectric layer 12 .
  • the material may be silicon nitride or silicon oxide.
  • the material of the protective layer 31 is not particularly limited here.
  • the forming method of the present disclosure may further include:
  • Step S160 Before forming the word line structure 2, a bit line structure 5 is formed at the bottom of the second trench 101. The bit line structure 5 traverses a plurality of the second trenches 101, and the bit line structure 5 The line structure 5 is insulated from the word line structure 2 .
  • a third trench (not shown in the figure) may be formed through the second trench 101 .
  • the specific formation position of the third trench can be defined by each second trench 101, thereby improving the alignment accuracy of the third trench.
  • the third trench may be located at the bottom of the second trench 101 and communicate with the bottom of the second trench 101 .
  • the third trench may penetrate the bottoms of the plurality of second trenches 101 .
  • the number of the third trenches may be multiple, each third trench may extend along the second direction B, and the plurality of third trenches may be spaced apart along the first direction A.
  • forming the bit line structure 5 at the bottom of the second trench 101 may include step S1601 and step S1602, wherein:
  • Step S1601 Remove part of the material of the substrate 11 below the second trench 101 to form a third trench below the second trench 101.
  • the third trench penetrates each of the Second trench 101.
  • the substrate 11 at the bottom of the second trench 101 may be etched to form a third trench, the third trench may extend along the second direction B, and the third trench may extend along the second direction B.
  • the bottoms of each second groove 101 are connected, that is, the third groove can hollow out the bottom of each support column 110 distributed along the second direction B, and then the third groove can hollow out the bottom of each support column 110 spaced along the second direction B.
  • the bottoms of the distributed second trenches 101 are connected.
  • each support pillar 110 can be supported by the insulating dielectric layer 12 between the support pillars 110 to prevent the support pillars 110 from collapsing, thereby improving product yield.
  • the specific formation position of the third trench can be defined by each second trench 101, thereby improving the alignment accuracy of the third trench.
  • the mask layer 6 forming the second trenches 101 can be used as a mask to etch the bottom of the second trenches 101, thereby forming a hole through each second trench.
  • the third trench of the trench 101 can avoid forming a separate mask layer 6 for accommodating the trench of the bit line structure 5, which can simplify the process and reduce the manufacturing cost.
  • Step S1602 Fill the third trench with a second conductive material to form the bit line structure 5 .
  • the second conductive material can be filled in each third trench by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition or thermal evaporation. Of course, other methods can also be used to fill the third trench.
  • the three trenches are respectively filled with the second conductive material, and then the bit line structure 5 is formed in the third trench.
  • the second conductive material can be deposited on the surface of the mask layer 6 at the same time.
  • Stop deposition the second conductive material located outside the third trench can be removed through an etching process, leaving only the second conductive material located within the third trench, so that the bit line structure 5 is formed only within the third trench.
  • the second conductive material may be a material with strong metallicity, and the contact resistance of the finally formed bit line structure 5 may be reduced through the material with strong metallicity.
  • the material may be titanium nitride or silicon cobalt.
  • bit line structures 5 may be formed in each third trench in one-to-one correspondence. That is, there may be multiple bit line structures 5 , and the number of bit line structures 5 is equal to the number of third trenches. Each bit line structure 5 may extend along the second direction B, and multiple bit line structures 5 may be spaced apart along the first direction A.
  • Step S420 Form a first insulating material layer 3311 on the surface of the structure formed by the substrate 1 and the protective layer 31.
  • a first insulating material layer 3311 can be formed on the surface of the structure formed by the substrate 11 and the protective layer 31 using processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. It should be noted that when the bit line structure 5 is formed on the bottom of the substrate 11, the first insulating material layer 3311 can be formed on the surface of the bit line structure 5 at the same time, and the bit line structure 5 and subsequent structures can be protected through the first insulating material layer 3311.
  • the word line structure 2 formed in the second trench 101 is insulated and isolated, thereby avoiding coupling or short circuit between the bit line structure 5 and the subsequently formed word line structure 2, thereby improving product yield.
  • the thickness of the first insulating material layer 3311 may be 2 nm to 5 nm.
  • the thickness of the first insulating material layer 3311 may be 2 nm, 3 nm, 4 nm or 5 nm.
  • the first insulating material layer 3311 may have a thickness of 2 nm to 5 nm.
  • the thickness of the material layer 3311 can also be other values, which are not listed here.
  • the material of the first insulating material layer 3311 may be different from the material of the protective layer 31 .
  • the material may be silicon nitride.
  • the material of the first insulating material layer 3311 may also be other materials. , no special restrictions are made here.
  • Step S430 Form a first insulating layer 32 in the second trench 101 with the first insulating material layer 3311, and the top of the first insulating layer 32 is lower than the top of the first insulating material layer 3311. .
  • the second trench 101 having the protective layer 31 and the first insulating material layer 3311 can be filled with insulating material, and then the first insulating layer 32 is formed in the second trench 101 .
  • the first insulating layer 32 can be formed in the second trench 101 by chemical vapor deposition, physical vapor deposition or atomic layer deposition.
  • insulating material can be deposited simultaneously in the second trench 101 and on the surface of the first insulating material layer 3311 located at the top of the second trench 101 , and then the deposited insulating material can be etched back so that the top of the first insulating layer 32 is lower than the top of the first insulating material layer 3311.
  • the first layer located on the top of the second trench 101 can be removed simultaneously.
  • the insulating material on the surface of the insulating material layer 3311 only retains the insulating material located in the second trench 101 , thereby forming the first insulating layer 32 in the second trench 101 .
  • the depth of etching back the insulating material may be 15 nm to 25 nm, that is, the height difference between the top of the first insulating layer 32 and the top of the first insulating material layer 3311 may be 15 nm to 25 nm.
  • the height difference between the top of the first insulating layer 32 and the top of the first insulating material layer 3311 can be 15 nm, 18 nm, 21 nm, 24 nm or 25 nm. Of course, it can also be other height differences, which are not listed here. .
  • the material of the first insulating layer 32 is different from the material of the first insulating material layer 3311.
  • the material of the first insulating layer 32 may be silicon oxide
  • the material of the first insulating material layer 3311 may be silicon oxide.
  • the material may be silicon nitride.
  • Step S440 Form a second insulating material layer on top of the first insulating layer 32.
  • a second insulating material layer (not shown in the figure) may be formed on top of the first insulating layer 32.
  • the material of the second insulating material layer may be the same as the material of the first insulating material layer 3311.
  • the second insulating material layer can be in contact with the first insulating material layer 3311, and the first insulating layer 32 can be covered by the second insulating material layer and the first insulating material layer 3311.
  • the second insulating material layer can be formed on the top of the first insulating layer 32 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In this process, for process convenience, the second insulating material layer 3311 can be formed on the surface of the first insulating material layer 3311 at the same time. A second layer of insulating material is deposited.
  • Step S450 Planarize the surface of the second insulating material layer so that the top of the second insulating material layer is flush with the surface of the substrate 11, and the remaining second insulating material layer is flush with the surface of the substrate 11.
  • the first insulating material layers 3311 together constitute the second insulating layer 331 .
  • the surface of the second insulating material layer can be ground or polished through a chemical mechanical polishing process until the first insulating material layer 3311 and the second insulating material layer located on the top of the substrate 11 are completely removed. In this process, the second insulating material layer can be polished. The tops of the two insulating material layers and the top of the first insulating material layer 3311 are both flush with the surface of the substrate 11 . In some embodiments of the present disclosure, as shown in FIG. 8 , the remaining second insulating material layer may together with the first insulating material layer 3311 form the second insulating layer 331 , that is, the second insulating layer 331 may Layer 32 covers one week.
  • Step S460 etching back the protective layer 31 and the insulating dielectric layer 12 to form an insulating gap 302 .
  • the protective layer 31 and the insulating dielectric layer 12 can be etched back to form an insulating gap 302 between the second insulating layer 331 and the sidewall of the second trench 101 .
  • part of the protective layer 31 can be removed, but the protective layer 31 is not completely removed.
  • the protective layer 31 at the end far away from the bit line structure 5 can be removed, while the protective layer 31 away from the bit line structure 5 can be removed. 5 the protective layer 31 at the closer end.
  • the thickness of the insulating dielectric layer 12 can be reduced so that the top of the insulating dielectric layer 12 is lower than the top of each support pillar 110 .
  • the thickness of the insulating dielectric layer 12 can be removed perpendicular to the substrate 11 The thickness of the protective layer 31 removed in the direction is the same.
  • the width of the insulating gap 302 formed between the second insulating layer 331 and the sidewall of the second trench 101 after the protective layer 31 is removed can be much smaller than that of the adjacent support pillars 110 after the insulating dielectric layer 12 is removed. spacing between.
  • Step S470 fill the insulating gap 302 with insulating material, and the insulating material and the second insulating layer 331 together form the passivation layer 33 .
  • the insulating material can be filled in the insulating gap 302 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In order to accurately position the word line structure 2 in the future, the insulating material can fill the insulating gap 302 for process convenience. , during the process of depositing the insulating material, the insulating material can be deposited on the surface of the remaining insulating dielectric layer 12 at the same time.
  • the insulating material may be the same as the material of the second insulating layer 331 , and the insulating material located in the insulating gap 302 may together with the second insulating layer 331 form the passivation layer 33 .
  • Step S480 Remove a predetermined thickness of the protective layer 31 in a direction perpendicular to the substrate 11 to form a word line filling trench 201.
  • the word line filling trench 201 does not expose the second trench. Bottom of slot 101.
  • a wet etching process can be used to remove part of the protective layer 31 located on the sidewall of the second trench 101 , thereby forming a word line filling trench 201 for accommodating the word line structure 2 .
  • the protective layer 31 can be etched through the exposed surface of the insulating dielectric layer 12 .
  • a dilute hydrofluoric acid solution (DHF) can be used to etch the exposed surface of the insulating dielectric layer 12 , and then hollowed out downwardly in the insulating dielectric layer 12 Create a space, which can extend laterally and expose the protective layer 31.
  • the exposed protective layer 31 can continue to be treated with a dilute hydrofluoric acid solution (DHF). Etch, and then remove part of the protective layer 31 located on the sidewalls of the second trench 101, so as to expose the sidewalls of each support pillar 110.
  • DHF dilute hydrofluoric acid solution
  • a mixed solution of HF and deionized water with a concentration of 49% can be used to clean the insulating dielectric layer 12 and the protective layer 31 , where the preparation ratio of HF and deionized water can be 1:500 to 1:2000. , for example, it can be 1:500, 1:1000, 1:1500 or 1:2000. Of course, it can also be other ratios, which will not be listed here.
  • the protective layer 31 at the bottom of the second trench 101 can be retained.
  • the protective layer 31 covering the surface of the bit line structure 5 can be retained, and the bit line structure can be protected by the remaining protective layer 31 5 and the subsequent word line structure 2 formed in the word line filling trench 201 are insulated and isolated to avoid short circuit or coupling between the word line structure 2 and the bit line structure 5 . That is, the protective layer 31 is located between the bit line structure 5 and the word line structure 2 , and the bit line structure 5 and the word line structure 2 are insulated by the protective layer 31 .
  • the passivation layer 33 and the remaining protective layer 31 may together constitute the insulating layer 3 of the present disclosure.
  • the word line structure 2 may be formed in the word line filling trench 201.
  • forming the word line structure 2 may include step S510 and step S520, wherein:
  • Step S510 form an inter-gate dielectric layer 21 at the bottom of the word line filling trench 201 and the sidewall of the word line filling trench 201 away from the insulating layer 3 .
  • the material of the inter-gate dielectric layer 21 may include silicon oxide, silicon nitride, silicon oxynitride, etc., or may be a combination of the aforementioned materials, and its thickness may be 1 nm to 9 nm. For example, it may be 1 nm, 2 nm, 4 nm, 6nm, 8nm or 9nm, of course, it can also be other thicknesses, so I won’t list them one by one here.
  • each word line filling trench 201 and each word line filling trench can be filled by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation or thermal oxidation.
  • the sidewall of the groove 201 away from the insulating layer 3 forms an inter-gate dielectric layer 21 conformably attached.
  • the inter-gate dielectric layer 21 can also be formed by other methods, and is not specifically limited here. It should be noted that the inter-gate dielectric layer 21 can be conformally attached to the exposed sidewalls of each support pillar 110 to facilitate the subsequent formation of a gate-all-around structure.
  • a thermal oxidation process can be used to treat the surface of the inter-gate dielectric layer 21 to improve the density of the film layer of the inter-gate dielectric layer 21, thereby reducing leakage current and improving gate control capability. It can also enhance the blocking effect of the inter-gate dielectric layer 21 on the impurities in the substrate 11, prevent the impurities in the substrate 11 from diffusing into the word line filling trench 201, and improve the structural stability.
  • Step S520 fill the word line filling trench 201 with the inter-gate dielectric layer 21 with the first conductive material 22 to form the word line structure 2 .
  • the first conductive material 22 can fill the word line filling trenches 201 and each word line filling trench 201 , and the first conductive material 22 can interact with the gates on the surface of each support pillar 110
  • the interlayer dielectric layer 21 is in contact.
  • the first conductive material 22 may be tungsten, titanium nitride, etc. Of course, it may also be other materials with strong conductive properties, which are not listed here.
  • each support pillar 110 having the inter-gate dielectric layer 21 and the second trench 101 can be formed by processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation.
  • the first conductive material 22 is deposited on the surface of the formed structure, thereby forming the word line structure 2 .
  • the word line structure 2 can also be formed by other methods, and the method of forming the word line structure 2 is not particularly limited here.
  • an insulating layer 3 can be formed between adjacent word line structures 2 , and the adjacent word line structures 2 can be insulated through the insulating layer 3 Insulation isolation is performed to avoid coupling or short circuit between word line structures 2 .
  • step S140 an air gap is formed between two adjacent word line structures.
  • the air gap 301 may be formed between adjacent word line structures 2 .
  • the air gap 301 may be located in the insulating layer 3 between the adjacent word line structures 2 . Since the air gap 301 The dielectric constant is small, which can effectively reduce the parasitic capacitance between the word line structures 2 and reduce the power consumption of the device.
  • forming the air gap 301 may include step S610 and step S620, wherein:
  • step S610 after forming the word line structure 2 , the passivation layer 33 is etched back until the first insulating layer 32 is exposed.
  • an insulating material can be deposited on the surface of the exposed word line structure 2 to perform inspection on the surface of the exposed word line structure 2 . Insulation protection prevents coupling or short circuit between the word line structure 2 and other structures formed subsequently, which helps to improve product yield.
  • the insulating material may be the same as the material of the passivation layer 33 , for example, the insulating material may be silicon nitride.
  • the insulating material can be deposited on the surface of the exposed word line structure 2 through chemical vapor deposition, physical vapor deposition, atomic layer deposition or thermal evaporation.
  • the insulating material can at least fill the gaps between the support pillars 110 .
  • insulating material can be deposited on the top of each support pillar 110 at the same time, and then the insulating material can be planarized through a polishing or grinding process to remove the insulating material on the top of the support pillar 110 and make it The top of each support column 110 is exposed.
  • the passivation layer 33 can be etched back (as shown in FIG. 19 ) until the top of the first insulating layer 32 is exposed to facilitate subsequent removal of the first insulating layer 32 .
  • Step S620 Remove the first insulating layer 32 to form the air gap 301.
  • the first insulating layer 32 can be removed through an etching process, thereby forming an air gap 301 in the insulating layer 3 .
  • the width of the air gap 301 can be equal to the width of the first insulating layer 32 .
  • the air gap 301 can be formed in the insulating layer 3 .
  • the width of the gap 301 may be 1 nm to 15 nm.
  • it may be 1 nm, 3 nm, 6 nm, 9 nm, 12 nm or 15 nm.
  • it may also be other widths, which are not specifically limited here.
  • an acidic solution may be used to selectively etch the first insulating layer 32 to thereby remove the first insulating layer 32 .
  • the first insulating layer 32 and the passivation layer 33 are made of different materials and have a high selective etching ratio.
  • the selective etching ratio of the first insulation layer 32 to the passivation layer 33 may be 10:1.
  • the acidic solution may be hydrofluoric acid.
  • step S150 the air gap is sealed.
  • the air gap 301 can be sealed to prevent the final semiconductor structure from breaking at the opening of the air gap 301, thereby improving product yield.
  • sealing the air gap 301 may include forming a sealing layer 4 on the surface of the passivation layer 33 having the air gap 301 , and the sealing layer 4 at least covers the air gap. 301 opening.
  • the sealing layer 4 can be located on the surface of the remaining passivation layer 33 and can at least fill the opening of the air gap 301 so as to seal the opening of the air gap 301.
  • chemical vapor deposition, physical vapor deposition, or atomic layer deposition can be used.
  • the sealing layer 4 is formed on the surface of the passivation layer 33 by deposition, vacuum evaporation or magnetron sputtering.
  • the material of the sealing layer 4 may be an insulating material, for example, the material may be silicon nitride.
  • the thickness of the sealing layer 4 can be set according to actual needs, and there is no special limit to the thickness of the sealing layer 4 here.
  • FIG. 20 shows a schematic diagram of the semiconductor structure of the present disclosure.
  • the semiconductor structure may include a substrate 1, a plurality of word line structures 2 and a sealing layer 4, wherein:
  • the substrate 1 includes a substrate 11 and an insulating dielectric layer 12.
  • the substrate 11 includes a plurality of first trenches spaced apart along the first direction A and a plurality of second trenches 101 spaced apart along the second direction B.
  • the insulating dielectric layer 12 fills each first trench, the second trench 101 penetrates each first trench and the insulating dielectric layer 12 inside, and the second direction B intersects the first direction A;
  • a plurality of word line structures 2 are respectively formed in each second trench 101, and an air gap 301 is formed between two adjacent word line structures 2;
  • the sealing layer 4 at least covers the opening of the air gap 301 .
  • the semiconductor structure of the present disclosure helps to save structural space and improve device integration by burying the word line structure 2 in the second trench 101; on the other hand, it can bury the word line structure 2 in the second trench 101. 2, an air gap 301 is formed between them. Since the dielectric constant of the air gap 301 is small, it can effectively reduce the parasitic capacitance between the word line structures 2 and reduce the power consumption of the device; on the other hand, the air gap 301 is processed through the sealing layer 4 Sealing can seal the air gap 301 between adjacent word line structures 2, which can prevent the finally formed semiconductor structure from breaking at the opening of the air gap 301, and can improve product yield.
  • the semiconductor structure of the present disclosure can be formed by the method for forming the semiconductor structure in any of the above embodiments.
  • the method for forming the semiconductor structure can be formed by the method for forming the semiconductor structure in any of the above embodiments.
  • Embodiments of the present disclosure also provide a memory, which may include the semiconductor structure in any of the above embodiments.
  • a memory which may include the semiconductor structure in any of the above embodiments.
  • the specific details, formation processes and beneficial effects have been detailed in the corresponding semiconductor structure and the method for forming the semiconductor structure. Description will not be repeated here.
  • the memory can be dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (static random access memory, SRAM), etc.
  • DRAM Dynamic Random Access Memory
  • SRAM static random access memory
  • other storage devices may also be used, which are not listed here.

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Abstract

一种半导体结构及其形成方法、存储器，形成方法包括：提供基底，基底包括衬底和绝缘介质层，衬底包括多个沿第一方向间隔分布的第一沟槽，绝缘介质层填充各第一沟槽（S110）；对基底进行图案化蚀刻，以形成多个沿第二方向间隔分布的第二沟槽，第二方向与第一方向相交（S120）；在各第二沟槽内分别形成字线结构（S130）；在相邻的两个字线结构之间形成气隙（S140）；对气隙进行封口（S150）。该形成方法可减小寄生电容，降低功耗，提高产品稳定性。

Description

半导体结构及其形成方法、存储器
交叉引用
本公开要求于2022年8月24日提交的申请号为202211024239.3名称为“半导体结构及其形成方法、存储器”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种半导体结构及其形成方法、存储器。
背景技术
随着移动设备的不断发展，手机、平板电脑、可穿戴设备等带有电池供电的移动设备被越来越多地应用于生活中，存储器作为移动设备中必不可少的元件，人们对存储器的小体积、集成化提出了巨大的需求。
目前，动态随机存储器(Dynamic Random Access Memory，DRAM)以其快速的传输速度被广泛应用于移动设备中。但是，随着半导体器件体积的不断缩小，单位面积中的字线结构越来越多，使得字线结构间的间距变小，字线结构间的寄生电容日益增大，半导体结构的功耗也随之增大。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
有鉴于此，本公开提供一种半导体结构及其形成方法、存储器，可减小寄生电容，降低功耗，提高产品稳定性。
根据本公开的一个方面，提供一种半导体结构的形成方法，包括：
提供基底，所述基底包括衬底和绝缘介质层，所述衬底包括多个沿第一方向间隔分布的第一沟槽，所述绝缘介质层填充各所述第一沟槽；
对所述基底进行图案化蚀刻，以形成多个沿第二方向间隔分布的第二沟槽，所述第二方向与所述第一方向相交；
在各所述第二沟槽内分别形成字线结构；
在相邻的两个所述字线结构之间形成气隙；
对所述气隙进行封口。
在本公开的一种示例性实施例中，所述形成方法还包括：
在相邻的所述字线结构之间形成绝缘层，所述气隙位于所述绝缘层内。
在本公开的一种示例性实施例中，形成所述绝缘层包括：
形成随形贴附于所述第二沟槽的侧壁的保护层；
在所述基底与所述保护层共同构成的结构的表面形成第一绝缘材料层；
在具有所述第一绝缘材料层的所述第二沟槽内形成第一绝缘层，所述第一绝缘层的顶部低于所述第一绝缘材料层的顶部；
在所述第一绝缘层的顶部形成第二绝缘材料层；
对所述第二绝缘材料层的表面进行平坦化处理，以使所述第二绝缘材料层的顶部与所述衬底的表面齐平，剩余的所述第二绝缘材料层与所述第一绝缘材料层共同 构成第二绝缘层；
对所述保护层及所述绝缘介质层进行回蚀刻，以形成绝缘空隙；
在所述绝缘空隙内填充绝缘材料，所述绝缘材料与所述第二绝缘层共同构成钝化层；
在垂直于所述衬底的方向上，去除预设厚度的所述保护层，以形成字线填充沟槽，所述字线填充沟槽未露出所述第二沟槽的底部。
在本公开的一种示例性实施例中，形成所述字线结构，包括：
在所述字线填充沟槽的底部及所述字线填充沟槽远离所述绝缘层的侧壁形成栅间介质层；
在具有所述栅间介质层的所述字线填充沟槽内填充第一导电材料，以形成字线结构。
在本公开的一种示例性实施例中，形成所述气隙，包括：
在形成所述字线结构后，对所述钝化层进行回蚀刻，直至露出所述第一绝缘层；
去除所述第一绝缘层，以形成所述气隙。
在本公开的一种示例性实施例中，对所述气隙进行封口，包括：
在具有所述气隙的所述钝化层的表面形成封口层，所述封口层至少覆盖所述气隙的开口。
在本公开的一种示例性实施例中，所述形成方法还包括：
在形成所述字线结构之前，所述第二沟槽的底部形成位线结构，所述位线结构横穿多个所述第二沟槽，且所述位线结构与所述字线结构绝缘设置。
在本公开的一种示例性实施例中，形成所述位线结构包括：
去除位于所述第二沟槽下方的所述衬底的部分材料，以在所述第二沟槽的下方形成第三沟槽，所述第三沟槽贯通各所述第二沟槽；
在所述第三沟槽内填充第二导电材料，以形成所述位线结构。
在本公开的一种示例性实施例中，所述保护层位于所述位线结构与所述字线结构之间，所述位线结构与所述字线结构通过所述保护层绝缘。
根据本公开的一个方面，提供一种半导体结构，包括：
基底，所述基底包括衬底和绝缘介质层，所述衬底包括多个沿第一方向间隔分布的第一沟槽和多个沿第二方向间隔分布的第二沟槽，所述绝缘介质层填充各所述第一沟槽，所述第二沟槽贯通各所述第一沟槽及其内部的所述绝缘介质层，所述第二方向与所述第一方向相交；
多个字线结构，分别形成于各所述第二沟槽内，且相邻的两个所述字线结构之间形成有气隙；
封口层，至少覆盖所述气隙的开口。
在本公开的一种示例性实施例中，所述半导体结构还包括：
绝缘层，形成于相邻的所述字线结构之间，所述气隙位于所述绝缘层内。
在本公开的一种示例性实施例中，所述绝缘层包括：
保护层，位于所述第二沟槽的侧壁，且在垂直于所述衬底的方向上，所述保护层的顶部低于所述第二沟槽的顶表面；
钝化层，填满具有所述保护层的所述第二沟槽，且在垂直于所述衬底的方向上，所述钝化层远离所述保护层的一端形成有字线填充沟槽，所述气隙位于相邻的所述字线填充沟槽之间的所述钝化层内，且所述气隙与所述字线填充沟槽通过所述钝化层绝缘。
在本公开的一种示例性实施例中，所述字线结构包括：
栅间介质层，形成于所述字线填充沟槽的底部及所述字线填充沟槽远离所述绝 缘层的侧壁；
第一导电层，填满于具有所述栅间介质层的所述字线填充沟槽。
在本公开的一种示例性实施例中，所述半导体结构还包括：
位线结构，形成于所述第二沟槽的底部，所述位线结构横穿多个所述第二沟槽，且所述位线结构与所述字线结构绝缘设置。
在本公开的一种示例性实施例中，所述保护层位于所述位线结构与所述字线结构之间，所述位线结构与所述字线结构通过所述保护层绝缘。
根据本公开的一个方面，提供一种存储器，包括上述任意一项所述的半导体结构。
本公开的半导体结构及其形成方法、存储器，一方面，通过在衬底中形成第二沟槽，并将字线结构埋设在第二沟槽内，有助于节省结构空间，可提高器件集成度；另一方面，可在相邻两个字线结构之间形成气隙，由于气隙的介电常数较小，可有效降低字线结构之间的寄生电容，降低器件功耗；再一方面，通过对气隙进行封口，可将气隙封闭在相邻的字线结构之间，可避免最终形成的半导体结构在气隙的开口处断裂，可提高产品良率。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施方式中的半导体结构的形成方法的流程图；
图2为本公开实施方式中的基底的示意图；
图3为本公开实施方式中的基底沿第二方向剖开的示意图；
图4为本公开实施方式中的字线结构沿第二方向剖开的示意图；
图5为本公开实施方式中的保护层的示意图；
图6为本公开实施方式中的第一绝缘材料层的示意图；
图7为本公开实施方式中的第一绝缘层的示意图；
图8为本公开实施方式中的第二绝缘层的示意图；
图9为本公开实施方式中完成步骤S460后沿第二方向剖开的示意图；
图10为本公开实施方式中完成步骤S460后沿图9中虚线剖开的示意图；
图11为本公开实施方式中完成步骤S470后沿第二方向剖开的示意图；
图12为本公开实施方式中完成步骤S470后沿图11中虚线剖开的示意图；
图13为本公开实施方式中完成步骤S480后沿第二方向剖开的示意图；
图14为本公开实施方式中完成步骤S510后沿第二方向剖开的示意图；
图15为本公开实施方式中完成步骤S510后沿图14中虚线剖开的示意图；
图16为本公开实施方式中完成步骤S520后沿图4中虚线剖开的示意图；
图17为本公开实施方式中完成步骤S140后沿第二方向剖开的示意图；
图18为本公开实施方式中回填绝缘材料后沿第一方向剖开的示意图；
图19为本公开实施方式中完成步骤S610后沿第二方向剖开的示意图；
图20为本公开实施方式中完成步骤S150后沿第二方向剖开的示意图。
附图标记说明：
1、基底；11、衬底；12、绝缘介质层；101、第二沟槽；110、支撑柱；2、字 线结构；21、栅间介质层；22、第一导电材料；201、字线填充沟槽；3、绝缘层；31、保护层；32、第一绝缘层；33、钝化层；331、第二绝缘层；3311、第一绝缘材料层；301、气隙；302、绝缘空隙；4、封口层；5、位线结构；6、掩膜层；A、第一方向；B、第二方向。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开实施方式提供了一种半导体结构的形成方法，图1示出了本公开的半导体结构的形成方法的流程图，参见图1所示，该形成方法可包括步骤S110-步骤S150，其中：
步骤S110，提供基底，所述基底包括衬底和绝缘介质层，所述衬底包括多个沿第一方向间隔分布的第一沟槽，所述绝缘介质层填充各所述第一沟槽；
步骤S120，对所述基底进行图案化蚀刻，以形成多个沿第二方向间隔分布的第二沟槽，所述第二方向与所述第一方向相交；
步骤S130，在各所述第二沟槽内分别形成字线结构；
步骤S140，在相邻的两个所述字线结构之间形成气隙；
步骤S150，对所述气隙进行封口。
本公开的半导体结构的形成方法，一方面，通过在衬底中形成第二沟槽，并将字线结构埋设在第二沟槽内，有助于节省结构空间，可提高器件集成度；另一方面，可在相邻两个字线结构之间形成气隙，由于气隙的介电常数较小，可有效降低字线结构之间的寄生电容，降低器件功耗；再一方面，通过对气隙进行封口，可将气隙封闭在相邻的字线结构之间，可避免最终形成的半导体结构在气隙的开口处断裂，可提高产品良率。
下面对本公开实施方式中半导体结构的形成方法的具体细节进行详细说明：
如图1所示，在步骤S110中，提供基底，所述基底包括衬底和绝缘介质层，所述衬底包括多个沿第一方向间隔分布的第一沟槽，所述绝缘介质层填充各所述第一沟槽。
在本公开的一种示例性实施方式中，如图2所示，基底1可包括衬底11和绝缘介质层12，衬底11内可设有多个沿第一方向A间隔分布的第一沟槽(图中未示出)，且各第一沟槽均可沿第二方向B延伸。第一沟槽可以是由衬底11表面向内凹陷所构成的槽状结构，其可与衬底11的两端贯通。
第一方向A可与第二方向B相交，例如，第一方向A与第二方向B可相互垂直。需要说明的是，垂直可以是绝对垂直，也可以是大致垂直，在制造过程中难免会有偏差，在本公开中，可能由于制作工艺限制引起角度的偏差，使得第一方向A和第二方向B的夹角有一定的偏差，只要第一方向A和第二方向B的角度偏差在预设范围内，均可认为第一方向A与第二方向B垂直。举例而言，预设范围可为10°，即：第一方向A和第二方向B的夹角在大于或等于80°，小于或等于100°的范围内时均可认为第一方向A和第二方向B垂直。
可向各第一沟槽内分别填充绝缘材料，进而形成绝缘介质层12。绝缘介质层12可填满各第一沟槽，且绝缘介质层12的上表面可与衬底11的上表面齐平。
在本公开的一种示例性实施方式中，提供基底1，基底1包括衬底11和绝缘介质层12，衬底11包括多个沿第一方向A间隔分布的第一沟槽，绝缘介质层12填充各第一沟槽(即步骤S110)可包括步骤S210-步骤S230，其中：
步骤S210，提供衬底11。
衬底11可呈平板结构，其可为矩形、圆形、椭圆形、多边形或不规则图形，其材料可以是硅或其他半导体材料，在此不对衬底11的形状及材料做特殊限定。
步骤S220，对所述衬底11进行蚀刻，以形成多个间隔分布的第一沟槽，所述第一沟槽沿所述第二方向B延伸，多个所述第一沟槽沿所述第一方向A间隔分布。
可采用光刻工艺在衬底11内形成多个第一沟槽，各第一沟槽均可沿第二方向B延伸，且多个第一沟槽可沿第一方向A间隔分布。举例而言，可通过旋涂或其他方式在衬底11表面形成光刻胶层，光刻胶层的材料可以是正性光刻胶或负性光刻胶，在此不做特殊限定。光刻胶层远离衬底11的表面的形状可与衬底11表面的形状相同。可采用掩膜版对光刻胶层进行曝光，该掩膜版的图案可与各第一沟槽所需的图案匹配。随后，可对曝光后的光刻胶层进行显影，从而形成显影区，该显影区可露出衬底11，且显影区的图案可与第一沟槽所需的图案相同，显影区的尺寸可与所需的第一沟槽的尺寸相同。可在显影区对衬底11进行非等向刻蚀，以形成各第一沟槽。需要说明的是，在垂直于衬底11的方向上，第一沟槽未将衬底11贯通，即第一沟槽的底部仍保留有衬底11材料。
步骤S230，在各所述第一沟槽内分别填充绝缘材料，以形成绝缘介质层12。
可采用真空蒸镀、磁控溅射、化学气相沉积、物理气相沉积或原子层沉积等方式在第一沟槽内填充绝缘材料，绝缘材料可填满所有的第一沟槽。在一实施方式中，绝缘材料可以为氧化物，例如，其可为氧化硅。
如图1所示，在步骤S120中，对所述基底进行图案化蚀刻，以形成多个沿第二方向B间隔分布的第二沟槽，所述第二方向B与所述第一方向A相交。
可对基底1进行蚀刻，进而在基底1内形成多个间隔分布的第二沟槽101。如图3所示，各第二沟槽101均可沿第一方向A延伸，多个第二沟槽101可沿第二方向B间隔分布。在本公开的一些实施方式中，在垂直于衬底11的方向上，第二沟槽101未将衬底11贯通，即第二沟槽101的底部仍保留有衬底11的材料。举例而言，在垂直于衬底11的方向上，第二沟槽101的深度可小于第一沟槽的深度，也可等于第一沟槽的深度，在此不做特殊限定。
在本公开的一种示例性实施方式中，继续参见图2及图3所示，各第二沟槽101和各第一沟槽可在衬底11内分隔出多组沿第一方向A间隔分布的支撑柱110。举例而言，每组中的支撑柱110可沿第一方向A等间距间隔分布；多组支撑柱110可沿第二方向B间隔分布。举例而言，各组支撑柱110可沿第二方向B等间距间隔分布。
在本公开的一种示例性实施方式中，对基底1进行蚀刻，以形成多个沿第二方向B间隔分布的第二沟槽101(即步骤S120)可包括步骤S310-步骤S350，其中：
步骤S310，在所述基底1的表面形成掩膜层6。
本公开实施方式中，可通过化学气相沉积、物理气相沉积、真空蒸镀、磁控溅射、原子层沉积或其它方式在基底1的表面形成掩膜层6，掩膜层6可为多层膜层结构，也可以为单层膜层结构，其材料可以是聚合物、SiO2、SiN、多晶硅和SiCN中至少一种，当然，也可以是其它材料，在此不再一一列举。
在一些实施方式中，掩膜层6可为多层，其可以包括聚合物层、氧化层和硬掩膜层6，其中，聚合物层可形成于基底1的表面，氧化层可位于硬掩膜层6和聚合物层之间。可通过化学气相沉积工艺在基底1的表面形成聚合物层，通过真空蒸镀工艺在聚合物层的表面形成氧化层，通过原子层沉积工艺在氧化层的表面形成硬掩膜层6。
步骤S320，在所述掩膜层6的表面形成光刻胶层。
可通过旋涂或其它方式在掩膜层6背离基底1的表面形成光刻胶层，光刻胶层的材料可以是正性光刻胶或负性光刻胶，在此不做特殊限定。
步骤S330，对所述光刻胶层进行曝光并显影，以形成多个间隔分布的显影区。
可采用掩膜版对光刻胶层进行曝光，该掩膜版的图案可与第二沟槽101所需的图案匹配。随后，可对曝光后的光刻胶层进行显影，从而形成多个间隔分布的显影区，每个显影区可分别露出掩膜层6的表面，显影区的图案可与第二沟槽101所需的图案相同，显影区的尺寸可与第二沟槽101所需的尺寸相同。
步骤S340，在所述显影区对所述掩膜层6进行蚀刻，以形成多个沿第二方向B间隔分布的掩膜图案，所述掩膜图案在所述衬底11上的正投影横穿多个所述第一沟槽。
可通过非等向蚀刻工艺在各显影区对掩膜层6进行蚀刻，蚀刻区域可露出基底1，从而在掩膜层6上形成多个掩膜图案，掩膜图案可呈条形，并可与第一沟槽的延伸方向相交，且各掩膜图案在基底1上的正投影可分别横穿多个第一沟槽。举例而言，掩膜图案可为沿第一方向A延伸的条形图案，多个掩膜图案可沿第二方向B间隔分布。
需要说明的是，当掩膜层6为单层结构时，可采用一次蚀刻工艺形成掩膜图案，当掩膜层6为多层结构时，可对各膜层进行分层蚀刻，即：一次蚀刻工艺可蚀刻一层，可采用多次蚀刻工艺将掩膜层6刻透，以形成掩膜图案，在一实施方式中，掩膜图案的形状和尺寸可与各第二沟槽101所需的图案和尺寸相同。
需要说明的是，在完成上述蚀刻工艺后，可通过清洗液清洗或通过灰化等工艺去除光刻胶层，使经过蚀刻后的掩膜层6不再被光刻胶层覆盖。
步骤S350，以具有所述掩膜图案的掩膜层6为掩膜对所述基底1进行非等向蚀刻，以形成多个沿所述第一方向A延伸且沿第二方向B间隔分布的第二沟槽101。
可采用具有掩膜图案的掩膜层6为掩膜，进而对基底1进行非等向蚀刻，以便形成多个沿第一方向A延伸且沿第二方向B间隔分布的第二沟槽101，在本公开的一些实施方式中，第二沟槽101与第一沟槽垂直，可通过第一沟槽和第二沟槽101将衬底11分隔成多个呈阵列分布的支撑柱110，各支撑柱110可以行和列的形式排布。形成各第二沟槽101后无需去除掩膜层6，以备后续蚀刻形成第三沟槽的过程中使用，可避免单独形成用于容纳位线结构5的沟槽的掩膜层6，可简化工艺，降低制造成本。
如图1所示，在步骤S130中，在各所述第二沟槽内分别形成字线结构。
如图4所示，可在各第二沟槽101内分别填充导电材料，进而在各第二沟槽101内分别形成字线结构2。在本公开的一些实施方式中，可在各第二沟槽101一一对应的形成字线结构2。即：字线结构2可为多个，且字线结构2的数量与第二沟槽 101的数量相等。各字线结构2均可沿第一方向A延伸，且多个字线结构2可沿第二方向B间隔分布。
在本公开的一种示例性实施方式中，在形成字线结构2之前可先形成后续隔绝各字线结构2的绝缘层3，举例而言，形成绝缘层3可包括步骤S410-步骤S480，其中：
步骤S410，形成随形贴附于所述第二沟槽101的侧壁的保护层31。
如图5所示，可采用真空蒸镀、磁控溅射、化学气相沉积、物理气相沉积或原子层沉积等方式在第二沟槽101的侧壁形成随形贴附于第二沟槽101的侧壁的保护层31，可通过保护层31保护第二沟槽101的侧壁的表面，防止在后续工艺中第二沟槽101的侧壁暴露在外界的表面被破坏，保护层31的材料可以是绝缘材料，其材料可与绝缘介质层12的材料相同，例如，其材料可以是氮化硅或氧化硅等，在此不对保护层31的材料做特殊限定。
在本公开的一种示例性实施方式中，本公开的形成方法还可包括：
步骤S160，在形成所述字线结构2之前，所述第二沟槽101的底部形成位线结构5，所述位线结构5横穿多个所述第二沟槽101，且所述位线结构5与所述字线结构2绝缘设置。
在本公开的些一实施方式中，继续参见图5所示，可在形成保护层31后，可通过第二沟槽101形成第三沟槽(图中未示出)，在此过程中，可通过各第二沟槽101限定第三沟槽的具体形成位置，提高第三沟槽的对位精度。第三沟槽可位于第二沟槽101的底部，并与第二沟槽101的底部连通。在本公开的一些实施方式中，第三沟槽可将多个第二沟槽101的底部贯通。第三沟槽的数量可为多个，各第三沟槽均可沿第二方向B延伸，且多个第三沟槽可沿第一方向A间隔分布。
在本公开的一种示例性实施方式中，在第二沟槽101的底部形成位线结构5可包括步骤S1601及步骤S1602，其中：
步骤S1601，去除位于所述第二沟槽101下方的所述衬底11的部分材料，以在所述第二沟槽101的下方形成第三沟槽，所述第三沟槽贯通各所述第二沟槽101。
可对位于第二沟槽101的底部的衬底11进行蚀刻，以形成第三沟槽，第三沟槽可沿第二方向B延伸，且可在第二方向B上第三沟槽可将各第二沟槽101的底部连通，即第三沟槽可将支撑柱110沿第二方向B间隔分布的各支撑柱110的底部掏空，进而通过第三沟槽将沿第二方向B间隔分布的各第二沟槽101的底部连通，此时，可通过各支撑柱110之间的绝缘介质层12对各支撑柱110进行支撑，以避免支撑柱110倒塌，进而提高产品良率。在此过程中，可通过各第二沟槽101限定第三沟槽的具体形成位置，进而提高第三沟槽的对位精度。
需要说明的是，在形成第三沟槽的过程中，可继续以形成第二沟槽101的掩膜层6作为掩膜对第二沟槽101的底部进行蚀刻，进而形成贯通各第二沟槽101的第三沟槽，可避免单独形成用于容纳位线结构5的沟槽的掩膜层6，可简化工艺，降低制造成本。
步骤S1602，在所述第三沟槽内填充第二导电材料，以形成所述位线结构5。
可通过真空蒸镀、磁控溅射、化学气相沉积、物理气相沉积、原子层沉积或热蒸发等方式在各第三沟槽内分别填充第二导电材料，当然，也可采用其他方式在第三沟槽内分别填充第二导电材料，进而在第三沟槽内形成位线结构5。
在本公开的一些实施方式中，在填充第二导电材料的过程中，为了工艺方便，可在掩膜层6的表面同时沉积第二导电材料，当第二导电材料填满第三沟槽后停止沉积；可通过蚀刻工艺去除位于第三沟槽之外的第二导电材料，只保留位于第三沟槽内的第二导电材料，以便于只在第三沟槽内形成位线结构5。
在本公开的一种示例性实施方式中，第二导电材料可为金属性较强的材料，可通过金属性较强的材料降低最终形成的位线结构5的接触电阻。例如，其材料可为氮化钛或钴化硅等。
在本公开的一些实施方式中，可在各第三沟槽一一对应的形成位线结构5。即：位线结构5可为多个，且位线结构5的数量与第三沟槽的数量相等。各位线结构5均可沿第二方向B延伸，且多个位线结构5可沿第一方向A间隔分布。
步骤S420，在所述基底1与所述保护层31共同构成的结构的表面形成第一绝缘材料层3311。
参见图6所示，可采用化学气相沉积、物理气相沉积或原子层沉积等工艺在衬底11与保护层31共同构成的结构的表面形成第一绝缘材料层3311。需要说明的是，当衬底11底部形成有位线结构5时，第一绝缘材料层3311可同时形成于位线结构5的表面，可通过第一绝缘材料层3311对位线结构5和后续在第二沟槽101中形成的字线结构2进行绝缘隔离，进而避免位线结构5与后续形成的字线结构2之间发生耦合或短路，可提高产品良率。
在本公开的一些实施方式中，第一绝缘材料层3311的厚度可为2nm～5nm，举例而言，第一绝缘材料层3311的厚度可为2nm、3nm、4nm或5nm，当然，第一绝缘材料层3311的厚度也可为其他数值，在此不再一一例举。
在本公开的一些实施方式中，第一绝缘材料层3311的材料可与保护层31的材料不同，例如，其材料可为氮化硅，当然，第一绝缘材料层3311的材料还可以是其他，在此不做特殊限定。
步骤S430，在具有所述第一绝缘材料层3311的所述第二沟槽101内形成第一绝缘层32，所述第一绝缘层32的顶部低于所述第一绝缘材料层3311的顶部。
参见图7所示，可在具有保护层31及第一绝缘材料层3311的第二沟槽101内填充绝缘材料，进而在第二沟槽101内形成第一绝缘层32。举例而言，可通过化学气相沉积、物理气相沉积或原子层沉积的方式在第二沟槽101内形成第一绝缘层32。在此过程中，为了工艺方便，在形成第一绝缘层32的过程中，可同时在第二沟槽101内及位于第二沟槽101顶部的第一绝缘材料层3311的表面同时沉积绝缘材料，随后可对沉积的绝缘材料进行回蚀刻，以使第一绝缘层32的顶部低于第一绝缘材料层3311的顶部，在此过程中，可同步去除位于第二沟槽101顶部的第一绝缘材料层3311的表面的绝缘材料，只保留位于第二沟槽101内的绝缘材料，进而在第二沟槽101内形成第一绝缘层32。
在本公开的一些实施方式中，对绝缘材料进行回蚀刻的深度可为15nm～25nm，即，第一绝缘层32的顶部与第一绝缘材料层3311的顶部的高低差可为15nm～25nm，例如，第一绝缘层32的顶部与第一绝缘材料层3311的顶部的高低差可为15nm、18nm、21nm、24nm或25nm，当然，也可以是其他高度差，在此不再一一例举。
在本公开的一些实施方式中，第一绝缘层32的材料与第一绝缘材料层3311的材料不同，举例而言，第一绝缘层32的材料可为氧化硅，第一绝缘材料层3311的材料可为氮化硅。
步骤S440，在所述第一绝缘层32的顶部形成第二绝缘材料层。
在形成第一绝缘层32后，可在第一绝缘层32的顶部形成第二绝缘材料层(图中未示出)，第二绝缘材料层的材料与第一绝缘材料层3311的材料可以相同，第二绝缘材料层可与第一绝缘材料层3311接触连接，可通过第二绝缘材料层和第一绝缘材料层3311，将第一绝缘层32包覆一周。
可通过化学气相沉积、物理气相沉积或原子层沉积的方式在第一绝缘层32的顶部形成第二绝缘材料层，在此过程中，为了工艺方便，可在第一绝缘材料层3311的 表面同时沉积第二绝缘材料层。
步骤S450，对所述第二绝缘材料层的表面进行平坦化处理，以使所述第二绝缘材料层的顶部与所述衬底11的表面齐平，剩余的所述第二绝缘材料层与所述第一绝缘材料层3311共同构成第二绝缘层331。
可通过化学机械研磨工艺对第二绝缘材料层的表面进行研磨或抛光，直至位于衬底11顶部的第一绝缘材料层3311和第二绝缘材料层被完全去除，在此过程中，可使第二绝缘材料层的顶部及第一绝缘材料层3311的顶部均与衬底11的表面齐平。在本公开的一些实施方式中，如图8所示，剩余的第二绝缘材料层可与第一绝缘材料层3311共同构成第二绝缘层331，即，第二绝缘层331可将第一绝缘层32包覆一周。
步骤S460，对所述保护层31及所述绝缘介质层12进行回蚀刻，以形成绝缘空隙302。
如图9及图10所示，可对保护层31及绝缘介质层12进行回蚀刻，进而在第二绝缘层331与第二沟槽101的侧壁之间形成绝缘空隙302，在一些实施方式中，在回蚀刻过程中，可去除部分保护层31，并未将保护层31完全去除，具体而言，可去除距离位线结构5较远的一端的保护层31，而保留距离位线结构5较近的一端的保护层31。同时，可减薄绝缘介质层12的厚度，以使绝缘介质层12的顶部低于各支撑柱110的顶部，在一些实施方式中，绝缘介质层12去除的厚度可与在垂直于衬底11的方向上去除的保护层31的厚度相等。
需要说明的是，去除保护层31后在第二绝缘层331与第二沟槽101的侧壁之间形成的绝缘空隙302的宽度可远小于去除绝缘介质层12后相邻的各支撑柱110之间的间距。
步骤S470，在所述绝缘空隙302内填充绝缘材料，所述绝缘材料与所述第二绝缘层331共同构成钝化层33。
可通过化学气相沉积、物理气相沉积或原子层沉积的方式在绝缘空隙302内填充绝缘材料，为了后续能够精准的定位字线结构2的位置，该绝缘材料可填满绝缘空隙302，为了工艺方便，在沉积绝缘材料的过程中，可在剩余的绝缘介质层12的表面同时沉积绝缘材料，在此过程中，由于绝缘空隙302的宽度远小于去除绝缘介质层12后相邻的各支撑柱110之间的间距，在将绝缘空隙302填满后只会在各支撑柱110暴露出来的侧壁的表面形成一层较薄的绝缘材料，而不会填满相邻的各支撑柱110之间的间隙，进而可将绝缘介质层12的表面暴露出来。完成步骤S470后沿第二方向B剖开的截面图如图11所示，完成步骤S470后沿第一方向A剖开的截面图如图12所示。
绝缘材料可与第二绝缘层331的材料相同，位于绝缘空隙302内的绝缘材料可与第二绝缘层331共同构成钝化层33。
步骤S480，在垂直于所述衬底11的方向上，去除预设厚度的所述保护层31，以形成字线填充沟槽201，所述字线填充沟槽201未露出所述第二沟槽101的底部。
如图13所示，可采用湿法蚀刻工艺去除部分位于第二沟槽101的侧壁的保护层31，进而形成用于容纳字线结构2的字线填充沟槽201，在此过程中，可通过绝缘介质层12暴露的表面对保护层31进行蚀刻，例如，可采用氢氟酸稀释溶液(DHF)对绝缘介质层12暴露的表面进行蚀刻，进而在绝缘介质层12中向下掏空出一个空间，该空间可横向延伸并暴露出保护层31，由于保护层31的材料与绝缘介质层12的材料相同，可继续采用氢氟酸稀释溶液(DHF)对暴露出来的保护层31进行蚀刻，进而去除位于第二沟槽101的侧壁的部分保护层31，以便露出各支撑柱110的侧壁。
举例而言，可采用浓度为49％的HF与去离子水的混合溶液对绝缘介质层12及 保护层31进行清洗，其中，HF与去离子水的配制比例可以为1:500～1:2000，举例而言，其可以是1:500、1:1000、1:1500或1:2000，当然，还可以是其他比例，在此不再一一列举。在湿法蚀刻过程中，可保留位于第二沟槽101底部的保护层31，举例而言，可保留覆盖于位线结构5表面的保护层31，可通过剩余的保护层31对位线结构5及后续在字线填充沟槽201中形成的字线结构2进行绝缘隔离，避免字线结构2与位线结构5之间发生短路或耦合。即：保护层31位于位线结构5与字线结构2之间，位线结构5与字线结构2通过保护层31绝缘。钝化层33和剩余的保护层31可共同构成本公开的绝缘层3。
在形成绝缘层3后可在字线填充沟槽201内形成字线结构2，在本公开的一种示例性实施方式中，形成字线结构2可包括步骤S510及步骤S520，其中：
步骤S510，在所述字线填充沟槽201的底部及所述字线填充沟槽201远离所述绝缘层3的侧壁形成栅间介质层21。
栅间介质层21的材料可以包括氧化硅、氮化硅、氮氧化硅等，也可为前述材料的组合，其厚度可以是1nm～9nm，举例而言，其可以是1nm、2nm、4nm、6nm、8nm或9nm，当然，也可以是其他厚度，在此不再一一列举。
举例而言，如图14及图15所示，可通过化学气相沉积、物理气相沉积、原子层沉积、热蒸发或热氧化等方式在各字线填充沟槽201的底部及各字线填充沟槽201远离绝缘层3的侧壁形成随形贴附的栅间介质层21，当然，也可通过其他方式形成栅间介质层21，在此不做特殊限定。需要说明的是，栅间介质层21可随形贴附于暴露出来的各支撑柱110的侧壁上，以便于后续形成环栅结构。
在本公开的一些实施方式中，可采用热氧化工艺对栅间介质层21的表面进行处理，以提高栅间介质层21的膜层的致密性，进而减小漏电流，提高栅控能力，还可增强栅间介质层21对衬底11中杂质的阻隔效果，避免衬底11中的杂质扩散至字线填充沟槽201内，可提高结构稳定性。
步骤S520，在具有所述栅间介质层21的所述字线填充沟槽201内填充第一导电材料22，以形成字线结构2。
如图4及图16所示，第一导电材料22可填充字线填充沟槽201，并可填满各字线填充沟槽201，且第一导电材料22可与各支撑柱110表面的栅间介质层21接触。第一导电材料22可以是钨或氮化钛等，当然，也可以是其他导电性能较强的材料，在此不再一一列举。
举例而言，可通过化学气相沉积、物理气相沉积、原子层沉积、真空蒸镀、磁控溅射或热蒸发等工艺在具有栅间介质层21的各支撑柱110与第二沟槽101共同构成的结构的表面沉积第一导电材料22，进而形成字线结构2。当然，也可通过其他方式形成字线结构2，在此不对字线结构2的形成方式做特殊限定。
在本公开的一种示例性实施方式中，在形成字线结构2后，相邻的字线结构2之间均可形成有绝缘层3，可通过绝缘层3对相邻的字线结构2进行绝缘隔离，避免各字线结构2之间发生耦合或短路。
如图1所示，在步骤S140中，在相邻的两个所述字线结构之间形成气隙。
如图17所示，气隙301可形成于相邻的字线结构2之间，举例而言，气隙301可位于相邻的字线结构2之间的绝缘层3内，由于气隙301的介电常数较小，可有效降低字线结构2之间的寄生电容，降低器件功耗。
在本公开的一种示例性实施方式中，形成气隙301可包括步骤S610及步骤S620，其中：
步骤S610，在形成所述字线结构2后，对所述钝化层33进行回蚀刻，直至露出所述第一绝缘层32。
在本公开的一些实施方式中，如图18所示，在形成字线结构2后，可在暴露出来的字线结构2的表面沉积绝缘材料，以便对暴露出来的字线结构2的表面进行绝缘保护，避免字线结构2与后续形成的其他结构之间发生耦合或短路，有助于提高产品良率。该绝缘材料可与钝化层33的材料相同，例如，该绝缘材料可为氮化硅。
举例而言，可通过化学气相沉积、物理气相沉积、原子层沉积或热蒸发等方式在暴露出来的字线结构2的表面沉积绝缘材料，绝缘材料可至少填满各支撑柱110之间的间隙。在此过程中，为了工艺方便，可在各支撑柱110的顶部同时沉积绝缘材料，随后可通过抛光或研磨工艺对绝缘材料进行平坦化处理，进而去除位于支撑柱110顶部的绝缘材料，并使各支撑柱110的顶部暴露出来。随后，可对钝化层33进行回蚀刻(如图19所示)，直至露出第一绝缘层32的顶部，以便于后续除去第一绝缘层32。
步骤S620，去除所述第一绝缘层32，以形成所述气隙301。
继续参见图17所示，可通过蚀刻工艺去除第一绝缘层32，进而在绝缘层3中形成气隙301，气隙301的宽度可与第一绝缘层32的宽度相等，举例而言，气隙301的宽度可为1nm～15nm，例如，其可为1nm、3nm、6nm、9nm、12nm或15nm，当然，也可以是其他宽度，在此不做特殊限定。
在本公开的一种示例性实施例中，可采用酸性溶液对第一绝缘层32进行选择性蚀刻，进而去除第一绝缘层32。在此过程中，第一绝缘层32与钝化层33的材料不同，且具有高的选择蚀刻比。例如，第一绝缘层32与钝化层33的选择蚀刻比可为10:1。在本公开的一些实施例中，酸性溶液可为氢氟酸。
如图1所示，在步骤S150中，对所述气隙进行封口。
可对气隙301进行封口，进而避免最终形成的半导体结构在气隙301的开口处断裂，可提高产品良率。
在本公开的一种示例性实施方式中，如图20所示，对气隙301进行封口可包括在具有气隙301的钝化层33的表面形成封口层4，封口层4至少覆盖气隙301的开口。
封口层4可位于剩余的钝化层33的表面，并可至少填满气隙301的开口，以便于密封气隙301的开口，举例而言，可采用化学气相沉积、物理气相沉积、原子层沉积、真空蒸镀或磁控溅射等方式在钝化层33的表面形成封口层4。封口层4的材料可为绝缘材料，例如，其材料可为氮化硅。封口层4的厚度可根据实际需要设定，在此不对封口层4的厚度做特殊限定。
需要说明的是，尽管在附图中以特定顺序描述了本公开中半导体结构的形成方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开还提供了一种半导体结构，图20示出了本公开的半导体结构的示意图，参见图20所示，该半导体结构可包括基底1、多个字线结构2及封口层4，其中：
基底1包括衬底11和绝缘介质层12，衬底11包括多个沿第一方向A间隔分布的第一沟槽和多个沿第二方向B间隔分布的第二沟槽101，绝缘介质层12填充各第一沟槽，第二沟槽101贯通各第一沟槽及其内部的绝缘介质层12，第二方向B与第一方向A相交；
多个字线结构2分别形成于各第二沟槽101内，且相邻的两个字线结构2之间形成有气隙301；
封口层4至少覆盖气隙301的开口。
本公开的半导体结构，一方面，通过将字线结构2埋设在第二沟槽101内，有助于节省结构空间，可提高器件集成度；另一方面，可在相邻两个字线结构2之间形成气隙301，由于气隙301的介电常数较小，可有效降低字线结构2之间的寄生电容，降低器件功耗；再一方面，通过封口层4对气隙301进行封口，可将气隙301封闭在相邻的字线结构2之间，可避免最终形成的半导体结构在气隙301的开口处断裂，可提高产品良率。
本公开的半导体结构可由上述任一实施方式中的半导体结构的形成方法形成，其具体细节及有益效果可参考上述半导体结构的形成方法的实施例，此处不再赘述。
本公开实施例还提供一种存储器，该存储器可包括由上述任一实施例中的半导体结构，其具体细节、形成工艺以及有益效果已经在对应的半导体结构及半导体结构的形成方法中进行了详细说明，此处不再赘述。
举例而言，该存储器可以是动态随机存取存储器(Dynamic Random Access Memory，DRAM)、静态随机存取存储器(static random access memory，SRAM)等。当然，还可以是其它存储装置，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (16)

  1. 一种半导体结构的形成方法，包括：
    提供基底，所述基底包括衬底和绝缘介质层，所述衬底包括多个沿第一方向间隔分布的第一沟槽，所述绝缘介质层填充各所述第一沟槽；
    对所述基底进行图案化蚀刻，以形成多个沿第二方向间隔分布的第二沟槽，所述第二方向与所述第一方向相交；
    在各所述第二沟槽内分别形成字线结构；
    在相邻的两个所述字线结构之间形成气隙；
    对所述气隙进行封口。
  2. 根据权利要求1所述的形成方法，其中，所述形成方法还包括：
    在相邻的所述字线结构之间形成绝缘层，所述气隙位于所述绝缘层内。
  3. 根据权利要求2所述的形成方法，其中，形成所述绝缘层包括：
    形成随形贴附于所述第二沟槽的侧壁的保护层；
    在所述基底与所述保护层共同构成的结构的表面形成第一绝缘材料层；
    在具有所述第一绝缘材料层的所述第二沟槽内形成第一绝缘层，所述第一绝缘层的顶部低于所述第一绝缘材料层的顶部；
    在所述第一绝缘层的顶部形成第二绝缘材料层；
    对所述第二绝缘材料层的表面进行平坦化处理，以使所述第二绝缘材料层的顶部与所述衬底的表面齐平，剩余的所述第二绝缘材料层与所述第一绝缘材料层共同构成第二绝缘层；
    对所述保护层及所述绝缘介质层进行回蚀刻，以形成绝缘空隙；
    在所述绝缘空隙内填充绝缘材料，所述绝缘材料与所述第二绝缘层共同构成钝化层；
    在垂直于所述衬底的方向上，去除预设厚度的所述保护层，以形成字线填充沟槽，所述字线填充沟槽未露出所述第二沟槽的底部。
  4. 根据权利要求3所述的形成方法，其中，形成所述字线结构，包括：
    在所述字线填充沟槽的底部及所述字线填充沟槽远离所述绝缘层的侧壁形成栅间介质层；
    在具有所述栅间介质层的所述字线填充沟槽内填充第一导电材料，以形成字线结构。
  5. 根据权利要求3所述的形成方法，其中，形成所述气隙，包括：
    在形成所述字线结构后，对所述钝化层进行回蚀刻，直至露出所述第一绝缘层；
    去除所述第一绝缘层，以形成所述气隙。
  6. 根据权利要求5所述的形成方法，其中，对所述气隙进行封口，包括：
    在具有所述气隙的所述钝化层的表面形成封口层，所述封口层至少覆盖所述气隙的开口。
  7. 根据权利要求3所述的形成方法，其中，所述形成方法还包括：
    在形成所述字线结构之前，所述第二沟槽的底部形成位线结构，所述位线结构横穿多个所述第二沟槽，且所述位线结构与所述字线结构绝缘设置。
  8. 根据权利要求7所述的形成方法，其中，形成所述位线结构包括：
    去除位于所述第二沟槽下方的所述衬底的部分材料，以在所述第二沟槽的下方形成第三沟槽，所述第三沟槽贯通各所述第二沟槽；
    在所述第三沟槽内填充第二导电材料，以形成所述位线结构。
  9. 根据权利要求7所述的形成方法，其中，所述保护层位于所述位线结构与所述字线结构之间，所述位线结构与所述字线结构通过所述保护层绝缘。
  10. 一种半导体结构，包括：
    基底，所述基底包括衬底和绝缘介质层，所述衬底包括多个沿第一方向间隔分布的第一沟槽和多个沿第二方向间隔分布的第二沟槽，所述绝缘介质层填充各所述第一沟槽，所述第二沟槽贯通各所述第一沟槽及其内部的所述绝缘介质层，所述第二方向与所述第一方向相交；
    多个字线结构，分别形成于各所述第二沟槽内，且相邻的两个所述字线结构之间形成有气隙；
    封口层，至少覆盖所述气隙的开口。
  11. 根据权利要求10所述的半导体结构，其中，所述半导体结构还包括：
    绝缘层，形成于相邻的所述字线结构之间，所述气隙位于所述绝缘层内。
  12. 根据权利要求11所述的半导体结构，其中，所述绝缘层包括：
    保护层，位于所述第二沟槽的侧壁，且在垂直于所述衬底的方向上，所述保护层的顶部低于所述第二沟槽的顶表面；
    钝化层，填满具有所述保护层的所述第二沟槽，且在垂直于所述衬底的方向上，所述钝化层远离所述保护层的一端形成有字线填充沟槽，所述气隙位于相邻的所述字线填充沟槽之间的所述钝化层内，且所述气隙与所述字线填充沟槽通过所述钝化层绝缘。
  13. 根据权利要求12所述的半导体结构，其中，所述字线结构包括：
    栅间介质层，形成于所述字线填充沟槽的底部及所述字线填充沟槽远离所述绝缘层的侧壁；
    第一导电层，填满于具有所述栅间介质层的所述字线填充沟槽。
  14. 根据权利要求12所述的半导体结构，其中，所述半导体结构还包括：
    位线结构，形成于所述第二沟槽的底部，所述位线结构横穿多个所述第二沟槽，且所述位线结构与所述字线结构绝缘设置。
  15. 根据权利要求14所述的半导体结构，其中，所述保护层位于所述位线结构与所述字线结构之间，所述位线结构与所述字线结构通过所述保护层绝缘。
  16. 一种存储器，包括权利要求10-15任一项所述的半导体结构。
PCT/CN2022/124071 2022-08-24 2022-10-09 半导体结构及其形成方法、存储器 WO2024040697A1 (zh)

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CN102479811A (zh) * 2010-11-29 2012-05-30 三星电子株式会社 非易失性存储器件及其制造方法
CN104269381A (zh) * 2014-10-10 2015-01-07 上海新储集成电路有限公司 Nand型闪存单元结构的制备方法
CN106952919A (zh) * 2016-01-05 2017-07-14 中芯国际集成电路制造(上海)有限公司 快闪存储器及其制作方法
CN211555887U (zh) * 2020-04-14 2020-09-22 福建省晋华集成电路有限公司 存储器
WO2021169786A1 (zh) * 2020-02-27 2021-09-02 长鑫存储技术有限公司 半导体结构的形成方法及半导体结构

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CN104269381A (zh) * 2014-10-10 2015-01-07 上海新储集成电路有限公司 Nand型闪存单元结构的制备方法
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