WO2022077982A1 - 半导体器件、半导体结构及其形成方法 - Google Patents

半导体器件、半导体结构及其形成方法 Download PDF

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Publication number
WO2022077982A1
WO2022077982A1 PCT/CN2021/106693 CN2021106693W WO2022077982A1 WO 2022077982 A1 WO2022077982 A1 WO 2022077982A1 CN 2021106693 W CN2021106693 W CN 2021106693W WO 2022077982 A1 WO2022077982 A1 WO 2022077982A1
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Prior art keywords
layer
sacrificial
forming
substrate
trench
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PCT/CN2021/106693
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English (en)
French (fr)
Inventor
吴秉桓
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长鑫存储技术有限公司
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Priority to EP21879030.1A priority Critical patent/EP4207287A4/en
Priority to US17/452,614 priority patent/US20220122987A1/en
Publication of WO2022077982A1 publication Critical patent/WO2022077982A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device, a semiconductor structure and a method for forming the same.
  • DRAM Dynamic Random Access Memory
  • the existing dynamic random access memory includes bit lines and capacitor contact windows alternately arranged with the bit lines.
  • bit lines and capacitor contact windows are formed, due to the influence of the manufacturing process, structural abnormalities are prone to occur, and the device yield is low.
  • the present disclosure provides a semiconductor device, a semiconductor structure and a method for forming the same, which can avoid structural abnormalities and improve device yield.
  • a method for forming a semiconductor structure comprising:
  • the passivation layer in the through hole is removed to form a capacitive contact structure in the through hole.
  • a method for forming a semiconductor structure comprising:
  • the passivation layer in the through hole is removed to form a capacitive contact structure.
  • a semiconductor structure formed by the method for forming a semiconductor structure described in any one of the above.
  • a semiconductor device including the semiconductor structure described in any one of the above, and a capacitor in contact connection with the capacitive contact structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in the related art.
  • FIG. 2 is a flowchart of a method for forming a semiconductor structure according to a first embodiment of the disclosure.
  • FIG. 3 is a flowchart of a method for forming a semiconductor structure according to a second embodiment of the disclosure.
  • FIG. 4 is a top view of the substrate in the first embodiment of the disclosure.
  • FIG. 5 is a schematic structural diagram corresponding to the step S120 in FIG. 2 .
  • FIG. 6 is a plan view corresponding to the structure in FIG. 5 .
  • FIG. 7 is a schematic diagram corresponding to the structure of FIG. 2 after step S130 is completed.
  • FIG. 8 is a plan view corresponding to the structure in FIG. 7 .
  • FIG. 9 is a schematic diagram of the semiconductor structure according to the first embodiment of the disclosure.
  • FIG. 10 is a flowchart corresponding to step S140 in FIG. 2 .
  • FIG. 11 is a schematic diagram corresponding to the structure of FIG. 10 after step S1401 is completed.
  • FIG. 12 is a schematic structural diagram corresponding to the step S1402 in FIG. 10 .
  • FIG. 13 is a schematic structural diagram corresponding to the step S1403 in FIG. 10 .
  • FIG. 14 is a top view corresponding to the structure after step S1403 in FIG. 10 is completed.
  • FIG. 15 is a schematic diagram corresponding to the structure of FIG. 2 after step S160 is completed.
  • FIG. 16 is a schematic diagram corresponding to the structure in FIG. 15 cut in a direction parallel to .
  • 17 is a top view of the substrate in the second embodiment of the disclosure.
  • FIG. 18 is a schematic diagram corresponding to the structure of FIG. 3 after step S220 is completed.
  • FIG. 19 is a plan view corresponding to the structure in FIG. 18 .
  • FIG. 20 is a schematic structural diagram corresponding to step S230 in FIG. 2 .
  • FIG. 21 is a plan view corresponding to the structure in FIG. 20 .
  • FIG. 22 is a schematic diagram of a filling layer in the second embodiment of the disclosure.
  • FIG. 23 is a plan view corresponding to the structure in FIG. 22 .
  • FIG. 24 is a schematic structural diagram corresponding to step S240 in FIG. 3 .
  • FIG. 25 is a schematic diagram of a semiconductor structure according to a second embodiment of the disclosure.
  • FIG. 26 is a flowchart corresponding to step S250 in FIG. 3 .
  • FIG. 27 is a schematic diagram corresponding to the structure of FIG. 26 after step S2501 is completed.
  • FIG. 28 is a schematic diagram corresponding to the structure of FIG. 26 after step S2502 is completed.
  • FIG. 29 is a schematic diagram corresponding to the structure of FIG. 26 after step S2503 is completed.
  • FIG. 30 is a top view corresponding to the structure after step S2503 in FIG. 26 is completed.
  • FIG. 31 is a schematic structural diagram corresponding to step S270 in FIG. 3 .
  • FIG. 32 is a plan view corresponding to the structure in FIG. 31 .
  • FIG. 33 is a schematic diagram corresponding to the structure of FIG. 3 after step S280 is completed.
  • FIG. 34 is a schematic view of the structure in FIG. 33 cut along a direction parallel to .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • a semiconductor device mainly includes a plurality of alternately distributed bit line structures 2 formed on a substrate 1 and capacitive contact windows 3 due to the formation of capacitive contact structures.
  • the bit line structures 2 In the manufacturing process, it is necessary to form the bit line structures 2 on the substrate 1 first, and then respectively form the capacitive contact structures between two adjacent bit line structures 2 .
  • an air gap structure 4 is usually formed on the sidewall of the bit line structure 2 .
  • the air gap structure 4 is designed, the protection strength between the bit line structure 2 and the capacitor contact structure is weakened; moreover, since the bit line structure 2 and the capacitor contact structure are performed in different periods, exposure bias is likely to occur between layers.
  • the capacitor contact window 3 is formed, the air gap structure 4 is easily damaged, resulting in structural abnormality and low device yield.
  • the first embodiment of the present disclosure provides a method for forming a semiconductor structure. As shown in FIG. 2 , the forming method may include:
  • Step S110 providing a substrate, and forming a sacrificial layer on the substrate;
  • Step S120 patterning the sacrificial layer to form side-by-side trenches and through holes in the sacrificial layer
  • Step S130 forming an insulating layer covering the trench sidewalls and the through-hole sidewalls;
  • Step S140 forming a conductive layer and a passivation layer in sequence in the trench and the through hole, so as to form a bit line structure in the trench;
  • Step S150 removing the passivation layer in the through hole to form a capacitor contact structure in the through hole.
  • the second embodiment of the present disclosure also provides a method for forming a semiconductor structure, as shown in FIG. 3 , the forming method may include:
  • Step S210 providing a substrate, and forming a sacrificial layer on the substrate;
  • Step S220 patterning the sacrificial layer to form a first sacrificial structure and a second sacrificial structure distributed side by side;
  • Step S230 forming an insulating layer covering the sidewalls of the first sacrificial structure and the sidewalls of the second sacrificial structure;
  • Step S240 removing the first sacrificial structure to form a trench, and removing the second sacrificial structure to form a through hole;
  • Step S250 forming a conductive layer and a passivation layer in sequence in the trench and the through hole to form a bit line structure in the trench;
  • Step S260 removing the passivation layer in the through hole to form a capacitive contact structure.
  • the semiconductor device, the semiconductor structure and the method for forming the same in the embodiments of the present disclosure can insulate and protect both sides of the bit line structure and the capacitor contact structure through an insulating layer, so as to prevent the bit line structure and the capacitor contact structure from contacting with other structures, and reduce the cost of the device. Risk of short circuit.
  • the capacitor contact structure and the bit line structure can be formed at the same time through the same preparation process, so as to avoid the problem of misalignment of the capacitor contact structure caused by the stepwise preparation of the capacitor contact structure and the bit line structure.
  • the structure is formed in the trench, and the capacitor contact structure is formed in the through hole, and the positions of the two are pre-defined. Therefore, the formed capacitor contact structure will not shift, avoid structural abnormalities, and improve device yield.
  • step S110 a substrate is provided, and a sacrificial layer is formed on the substrate.
  • the substrate 100 may have a flat plate structure, and a bit line forming area 101 and a capacitor contact structure 420 forming area 102 may be pre-defined on the substrate 100 , and the substrate 100 may be rectangular, circular,
  • the material of the ellipse, polygon or irregular shape may be silicon or other semiconductor materials, and the shape and material of the substrate 100 are not particularly limited herein.
  • the sacrificial layer 200 can be formed on the surface of the substrate 100.
  • the sacrificial layer 200 can be a thin film formed on the substrate 100 or a coating layer formed on the substrate 100.
  • it can be a photoresist or a hard coating.
  • the material of the mask can be silicon dioxide or the like, which is not particularly limited here.
  • the thickness of the sacrificial layer 200 can be the same as the required thickness of the bit line structure. In one embodiment, the thickness of the sacrificial layer 200 can range from 50 nm to 200 nm. For example, it can be 50 nm, 100 nm, 150 nm or 200 nm. Other thicknesses are not listed here.
  • the sacrificial layer 200 can be formed on the substrate 100 by atomic layer deposition, vacuum evaporation, magnetron sputtering, chemical vapor deposition or physical vapor deposition, etc.
  • the sacrificial layer 200 can also be formed on the substrate 100 by other processes , the forming process of the sacrificial layer 200 is not particularly limited here.
  • step S120 patterning is performed on the sacrificial layer, so as to form parallel trenches and through holes in the sacrificial layer.
  • the sacrificial layer 200 can be patterned by photolithography according to the pre-defined bit line formation region 101 and the capacitor contact structure 420 formation region 102 to form side-by-side distribution in the sacrificial layer 200 trenches 201 and through holes 202.
  • the grooves 201 may pass through at both ends, and may be strip-shaped in the direction parallel to the substrate 100 , and may extend in the direction parallel to the substrate 100 .
  • the through hole 202 can be a circular hole, a rectangular hole or an irregular hole-like structure, which is not limited herein.
  • the through holes 202 may be multiple, the multiple through holes 202 may be arranged in a row, and may be spaced along the extending direction of the trenches 201 .
  • each trench 201 can form a group with each row of through holes 202 , and multiple groups of trenches 201 and through holes 202 can be formed side by side, and in adjacent two groups of trenches 201 and through holes
  • the columns formed by 202 are alternately distributed, that is, the through holes 202 are distributed on both sides of the trench 201 and can be arranged at intervals along the extending direction of the trench.
  • a mask material layer may be formed on the side of the sacrificial layer 200 away from the substrate 100 by chemical vapor deposition, vacuum evaporation, atomic layer deposition or other methods.
  • the mask material layer may have multiple layers or a single layer.
  • the material of the layer structure can be at least one of polymer, SiO2, SiN, poly, and SiCN, and of course, can also be other materials, which will not be listed here.
  • a photoresist layer may be formed on the surface of the mask material layer away from the sacrificial layer 200 by spin coating or other methods, and the photoresist layer material may be positive photoresist or negative photoresist, which is not limited herein.
  • the photoresist layer can be exposed using a mask, the pattern of which can be matched to the desired pattern of the sacrificial layer 200 . Then, the exposed photoresist layer can be developed to form a plurality of developing areas, each developing area can expose the mask material layer, and the pattern of the developing area can be the same as that required by the sacrificial layer 200, and each developing area
  • the dimensions of the regions can be matched to the desired dimensions of trenches 201 and vias 202 .
  • the mask material layer may be etched in the developing region by a plasma etching process, and the sacrificial layer 200 may be exposed in the etching region, thereby forming a desired mask pattern on the mask material layer.
  • the photoresist layer can be removed by cleaning with a cleaning solution or by ashing and other processes, so that the mask material layer is no longer covered by the photoresist layer, and the formed mask layer is exposed to obtain a hard mask.
  • Membrane structure
  • the sacrificial layer 200 can be anisotropically etched according to the mask pattern.
  • the sacrificial layer 200 can be etched in the developing area of the mask pattern by a dry etching process, and the substrate 100 is used as an etch stop layer.
  • trenches 201 and through holes 202 are formed side by side.
  • FIG. 5 shows the structure after step S120 in the embodiment of the first forming method of the present disclosure is completed.
  • step S130 an insulating layer covering the sidewalls of the trench and the sidewalls of the through hole is formed.
  • an insulating layer 300 that conforms to the shape can be formed on the sidewall of the through hole 202 and the sidewall of the trench 201 , and the insulating layer 300 on both sidewalls of the trench 201 can be covered with the trench
  • the two sidewalls of the trench 201 when the trench 201 is strip-shaped, the insulating layers 300 located on the two sidewalls of the trench 201 can be disposed opposite to each other; the insulating layer 300 located on the sidewalls of the through hole 202 can be covered with the holes of the through hole 202 wall, that is: when the through hole 202 is a circular hole, the cross section of the insulating layer 300 located on the side wall of the through hole 202 in the direction parallel to the substrate 100 may be circular; when the through hole 202 is a rectangular hole, The cross section of the insulating layer 300 located on the sidewall of the through hole 202 in the direction parallel to the substrate 100 may be rectangular.
  • the thickness of the insulating layer 300 may range
  • the insulating layer 300 located on the sidewall of the trench 201 may be separated from the insulating layer 300 located on the sidewall of the through hole 202 by the sacrificial layer 200 .
  • the side of the insulating layer 300 close to the substrate 100 may be in contact with the substrate 100 , and the side away from the substrate 100 may be flush with the surface of the sacrificial layer 200 away from the substrate 100 .
  • the insulating layer 300 may be a thin film formed on the sidewall of the through hole 202 and the sidewall of the trench 201, or may be a film formed on the sidewall of the through hole 202 and the sidewall of the trench 201, which is not specially described here. limited.
  • the insulating layer 300 may be formed on the sidewalls of the through holes 202 and the sidewalls of the trenches 201 by using a chemical vapor deposition process. Of course, the insulating layer 300 may also be formed by other processes, which are not limited herein.
  • the material of the sacrificial layer 200 and the material of the insulating layer 300 may have a high etching ratio, for example, the etching ratio of the material of the sacrificial layer 200 to the material of the insulating layer 300 may be greater than 100:1.
  • the material of the insulating layer 300 may be Si3N4 or SiCN, of course, may also be other insulating materials, which will not be listed one by one here.
  • step S140 a conductive layer and a passivation layer are sequentially formed in the trench and the through hole, so as to form a bit line structure in the trench.
  • the bit line structure 410 can be formed in the trench 201 , and the capacitor contact structure 420 can be formed in the through hole 202 , and then the source or drain in the substrate 100 can pass through the bit line structure 410 .
  • the pole contacts are connected to the capacitor through the capacitive contact structure 420 , so as to store the electric charge collected by the capacitor through the capacitive contact structure 420 .
  • the capacitive contact structures 420 may be formed in each of the through holes 202 , and each capacitive contact structure 420 may have a corresponding capacitor, and a plurality of capacitive contact structures 420 may be used At the same time, charges are stored to improve the storage capacity of the DRAM; when there are multiple trenches 201 , a bit line structure 410 can be formed in each trench 201 .
  • the conductive layer can be a single-layer structure or a multi-layer structure, and its material can be a conductor or semiconductor material, for example, it can be polysilicon, silicon germanium (SiGe), tungsten, titanium, cobalt, etc., or a combination thereof , of course, other conductive materials can also be used, for example, it can also be a combination of metal silicides and different metal silicides, and the number of layers and materials of the conductive layer are not particularly limited here.
  • Atomic layer deposition, vacuum evaporation, magnetron sputtering, chemical vapor deposition or physical vapor deposition can be used to form a conductive layer and a passivation layer 403 in the trench 201 and the through hole 202 in turn.
  • Other methods can also be used.
  • the conductive layer and the passivation layer 403 are formed, which will not be listed one by one here.
  • sequentially forming a conductive layer and a passivation layer 403 in the trench 201 and the through hole 202 may include steps S1401 to S1403, wherein:
  • Step S1401 forming a first conductive layer on the surface of the substrate exposed by the trenches and the through holes.
  • the first conductive layer 401 may be a thin film formed on the surface of the substrate 100 , and the material may be polysilicon, and the surface of the substrate 100 exposed by the trenches 201 and the through holes 202 may be exposed by atomic layer deposition.
  • a first conductive layer 401 is formed, the first conductive layer 401 can be in contact with the substrate 100 , and the surface of the first conductive layer 401 facing away from the substrate 100 can be lower than the end of the insulating layer 300 facing away from the substrate 100 .
  • Step S1402 forming a second conductive layer on the surface of the first conductive layer away from the substrate, where the top surface of the second conductive layer is lower than the top surface of the sacrificial layer.
  • the second conductive layer 402 may be a thin film formed on the side of the first conductive layer 401 away from the substrate 100 , and the material may be tungsten.
  • a second conductive layer 402 is formed on the side of the conductive layer 401 facing away from the substrate 100 .
  • the second conductive layer 402 can be in contact with the first conductive layer 401 , and the surface of the conductive layer 401 facing away from the first conductive layer 401 can be lower than the insulating layer 300 The end facing away from the substrate 100 .
  • Step S1403 forming a passivation layer on the surface of the second conductive layer away from the substrate, and the top surface of the passivation layer is flush with the top surface of the sacrificial layer 200 .
  • the passivation layer 403 can be a thin film formed on the side of the second conductive layer 402 away from the first conductive layer 401, which can be used to protect the surface of the conductive layer, and its material can be silicon nitride,
  • the passivation layer 403 may be simultaneously formed on the side of the second conductive layer 402 away from the first conductive layer 401 by chemical vapor deposition or physical vapor deposition, thereby forming the bit line structure 410 in the trench 201 .
  • the surface of the passivation layer 403 facing away from the second conductive layer 402 may be flush with the top surface of the sacrificial layer 200 .
  • step S150 the passivation layer located in the through hole is removed to form a capacitive contact structure in the through hole.
  • the passivation layer 403 in the via hole 202 may be removed to form the capacitive contact structure 420 in the via hole 202 , that is, the capacitive contact structure 420 may include a conductive layer formed on the substrate 100 .
  • the passivation layer 403 in each of the through holes 202 may be removed by an anisotropic etching process, so as to form the capacitor contact structure 420 in each of the through holes 202 .
  • the forming method of the present disclosure may further include steps S160 and S170, as shown in FIG. 2, wherein:
  • Step S160 after the passivation layer is formed, the sacrificial layer is removed to form an isolation gap.
  • the sacrificial layer 200 may be removed by a wet etching process to form an isolation gap, and the isolation gap may include a gap between two adjacent capacitor contact structures 420 in the same column.
  • wet etching may be performed using an acidic solution, which may be hydrofluoric acid, such as buffered hydrofluoric acid (BHF), 49% hydrofluoric acid, or dilute hydrofluoric acid (DHF), in use, the preparation ratio of the acid solution and deionized water can be set according to the specific material of the sacrificial layer 200, and the proportion and concentration of the etching solution are not specially limited here.
  • an acidic solution which may be hydrofluoric acid, such as buffered hydrofluoric acid (BHF), 49% hydrofluoric acid, or dilute hydrofluoric acid (DHF)
  • BHF buffered hydrofluoric acid
  • DHF dilute hydrofluoric acid
  • Step S170 forming a dielectric layer covering the isolation gap.
  • a dielectric layer can be filled in the isolation gap, and the dielectric layer can be made of a material with a lower dielectric constant, which can effectively reduce the parasitic capacitance between the bit line structures 410 and reduce the power consumption of the device.
  • the dielectric layer can be a silicon oxide material.
  • the dielectric layer may fill each isolation gap; in another embodiment, during the deposition of the dielectric layer, the second gap 212 may be quickly sealed to form an air gap, due to the dielectric properties of the air.
  • the constant is smaller than the dielectric constant of silicon oxide, and the formation of air gaps can reduce the parasitic capacitance of the device.
  • the dielectric layer 500 covering the isolation gap can be deposited by controlling the deposition rate of the dielectric layer 500 to quickly seal the second gap 212 and form an air gap, and in order to prevent bit lines in subsequent packaging and practical applications Cracks are generated between the structures 410 to ensure device stability, and the top surface of the air gap does not exceed the top surface of the bit line structure 410 .
  • an air gap can also be formed in the dielectric layer between two adjacent capacitive contact structures 420, so as to further reduce the parasitic capacitance.
  • the second embodiment of the present disclosure also provides a method for forming a semiconductor structure, as shown in FIG. 3 , the forming method may include:
  • step S210 a substrate is provided, and a sacrificial layer is formed on the substrate.
  • the substrate 600 may have a flat plate structure, and a bit line forming area 601 and a capacitor contact structure 920 forming area 602 may be pre-defined on the substrate 600 .
  • the substrate 600 may be rectangular, circular, oval,
  • the material of the polygonal or irregular shape may be silicon or other semiconductor materials, and the shape and material of the substrate 600 are not particularly limited herein.
  • a sacrificial layer 700 can be formed on the surface of the substrate 600 .
  • the sacrificial layer 700 can be a thin film formed on the substrate 600 or a coating formed on the substrate 600 , and the material of the sacrificial layer 700 can be dioxide Silicon is not particularly limited here.
  • the sacrificial layer 700 can be formed on the substrate 600 by atomic layer deposition, vacuum evaporation, magnetron sputtering, chemical vapor deposition or physical vapor deposition, etc. Of course, the sacrificial layer 700 can also be formed on the substrate 600 by other processes , the forming process of the sacrificial layer 700 is not particularly limited here.
  • Step S220 patterning the sacrificial layer to form a first sacrificial structure and a second sacrificial structure distributed side by side.
  • the sacrificial layer 700 can be patterned by a photolithography process according to the pre-defined bit line formation region 601 and the capacitor contact structure 920 formation region 602 to form side-by-side distribution in the sacrificial layer 700 of the first sacrificial structure 710 and the second sacrificial structure 720 .
  • the first sacrificial structures 710 may be strip-shaped in a direction parallel to the substrate 600 and may extend in a direction parallel to the substrate 600 .
  • the second sacrificial structure 720 can be a circular column, a rectangular column or an irregular-shaped column structure, which is not limited herein.
  • the plurality of second sacrificial structures 720 may be arranged in a row, and may be arranged at intervals along the extending direction of the first sacrificial structures 710 .
  • each row of the first sacrificial structures 710 can form a group with each row of the second sacrificial structures 720 , and a plurality of sets of the first sacrificial structures 710 and the second sacrificial structures 720 can be formed side by side, and the adjacent two The rows formed by the first sacrificial structures 710 and the second sacrificial structures 720 in the group are alternately distributed, that is, the second sacrificial structures 720 are distributed on both sides of the first sacrificial structures 710 and can be spaced along the extending direction of the first sacrificial structures 710 set up.
  • a mask material layer may be formed on the side of the sacrificial layer 700 away from the substrate 600 by chemical vapor deposition, vacuum evaporation, atomic layer deposition or other methods.
  • the mask material layer may have multiple layers or a single layer.
  • the material of the layer structure can be at least one of polymer, SiO2, SiN, poly, and SiCN, and of course, can also be other materials, which will not be listed here.
  • a photoresist layer may be formed on the surface of the mask material layer away from the sacrificial layer 700 by spin coating or other methods, and the photoresist layer material may be positive photoresist or negative photoresist, which is not limited herein.
  • the photoresist layer can be exposed using a mask, the pattern of which can be matched to the desired pattern of the sacrificial layer 700 . Subsequently, the exposed photoresist layer can be developed to form a plurality of developing areas, each developing area can expose the mask material layer, and the pattern of the developing area can be the same as that required by the sacrificial layer 700, and each developing area can be The dimensions of the regions can be matched to the desired dimensions of the regions other than the first sacrificial structure 710 and the second sacrificial structure 720 .
  • the mask material layer may be etched in the developing region by a plasma etching process, and the sacrificial layer 700 may be exposed in the etching region, thereby forming a desired mask pattern on the mask material layer.
  • the photoresist layer can be removed by cleaning with a cleaning solution or by ashing and other processes, so that the mask material layer is no longer covered by the photoresist layer, and the formed mask layer is exposed to obtain a hard mask.
  • Membrane structure
  • the sacrificial layer 700 can be anisotropically etched according to the mask pattern.
  • the sacrificial layer 700 can be etched in the developing area of the mask pattern by a dry etching process, and the substrate 600 is used as an etch stop layer.
  • a first sacrificial structure 710 and a second sacrificial structure 720 are formed side by side in the sacrificial layer 700 .
  • FIG. 18 shows the structure after step S220 in the embodiment of the second forming method of the present disclosure is completed.
  • Step S230 forming an insulating layer covering the sidewalls of the first sacrificial structure and the sidewalls of the second sacrificial structure.
  • an insulating layer 800 conforming to the shape can be formed on the sidewall of the first sacrificial structure 710 and the sidewall of the second sacrificial structure 720 , and the insulating layers on both sidewalls of the first sacrificial structure 710
  • the two sidewalls of the first sacrificial structure 710 can be covered with 800.
  • the insulating layers 800 located on the two sidewalls of the first sacrificial structure 710 can be disposed opposite to each other; on the side of the second sacrificial structure 720
  • the insulating layer 800 of the wall can cover the outer wall of the second sacrificial structure 720 , that is, when the second sacrificial structure 720 is a circular column, the insulating layer 800 located on the sidewall of the second sacrificial structure 720 is in a direction parallel to the substrate 600 .
  • the cross section of the upper part may be circular; when the second sacrificial structure 720 is a rectangular column, the cross section of the insulating layer 800 on the sidewall of the second sacrificial structure 720 in the direction parallel to the substrate 600 may be rectangular.
  • the insulating layer 800 located on the sidewall of the first sacrificial structure 710 can be in contact with the insulating layer 800 located on the sidewall of the second sacrificial structure 720 , and the side of the insulating layer 800 close to the substrate 600 can be connected to the substrate 600
  • the side of the sacrificial layer 700 facing away from the substrate 600 may be flush with the surface of the sacrificial layer 700 facing away from the substrate 600 .
  • the insulating layer 800 may be a thin film formed on the sidewall of the second sacrificial structure 720 and the sidewall of the first sacrificial structure 710 , or may be a thin film formed on the sidewall of the second sacrificial structure 720 and the sidewall of the first sacrificial structure 710 .
  • the film layer is not particularly limited here.
  • the insulating layer 800 can be formed on the sidewall of the second sacrificial structure 720 and the sidewall of the first sacrificial structure 710 by chemical vapor deposition process. Of course, the insulating layer 800 can also be formed by other processes, which is not limited herein.
  • the material of the sacrificial layer 700 and the material of the insulating layer 800 may have a high etching ratio, for example, the etching ratio of the material of the sacrificial layer 700 and the material of the insulating layer 800 may be greater than 100:1.
  • the material of the insulating layer 800 may be Si3N4 or SiCN, and of course, may also be other insulating materials, which will not be listed here.
  • the isolation gap may include the first gap 731 between two adjacent capacitive contact structures 920 in the same column , and a second gap (not shown in the figure) between the adjacent bit line structure 910 and the capacitor contact structure 920 , in one embodiment, the sidewalls of the first sacrificial structure 710 and the side of the second sacrificial structure 720 are formed to cover the sidewalls of the first sacrificial structure 710
  • the second gap may be a gap between the insulating layer 800 on the sidewall of the bit line structure 910 and the insulating layer 800 on the sidewall of the capacitor contact structure 920 .
  • the forming method of the present disclosure may further include depositing a filling layer 740 in the isolation gap, as shown in FIG. 22 and FIG. 23 , the filling layer 740 may be removed after the formation of the bit line structure 910 and the capacitor contact structure 920 to avoid the formation of the bit line
  • the isolation gap is filled with conductive material during structure 910 and capacitive contact structure 920 .
  • the filling layer 740 may be a material with a lower density to facilitate subsequent removal.
  • the filling layer 740 may be formed in the isolation gap by chemical vapor deposition or physical vapor deposition. Of course, the filling layer 740 may also be formed by other methods, and the formation method of the filling layer 740 is not particularly limited herein.
  • Step S240 removing the first sacrificial structure to form a trench, and removing the second sacrificial structure to form a through hole.
  • the first sacrificial structure 710 may be removed by a wet etching process to form the trench 701 , and the second sacrificial structure 720 may be removed to form the through hole 702 at the same time.
  • wet etching may be performed using an acidic solution, which may be hydrofluoric acid, such as buffered hydrofluoric acid (BHF), 49% hydrofluoric acid, or dilute hydrofluoric acid (DHF), during use, the ratio of acid solution to deionized water can be set according to the specific materials of the first sacrificial structure 710 and the second sacrificial structure 720, and the ratio and concentration of the etching solution are not limited here. .
  • BHF buffered hydrofluoric acid
  • DHF dilute hydrofluoric acid
  • step S250 a conductive layer and a passivation layer are sequentially formed in the trench and the through hole, so as to form a bit line structure in the trench.
  • a bit line structure 910 can be formed in the trench 701 , while a capacitor contact structure 920 can be formed in the through hole 702 , and then the bit line structure 910 can be connected to the source or drain contact in the substrate 600 . , and is connected to the capacitor through the capacitive contact structure 920 , so as to store the charges collected by the capacitor through the capacitive contact structure 920 .
  • a capacitive contact structure 920 may be formed in each of the through holes 702 , and each capacitive contact structure 920 may have a corresponding capacitor. , charges can be stored simultaneously through a plurality of capacitive contact structures 920 to improve the storage capacity of the DRAM; when there are multiple first contact structures, there are also multiple trenches 701, and a bit line structure can be formed in each trench 701 910 in order to electrically lead the device out.
  • the conductive layer can be a single-layer structure or a multi-layer structure, and its material can be a conductor or semiconductor material, for example, it can be polysilicon, silicon germanium (SiGe), tungsten, titanium, cobalt, etc., or a combination thereof , of course, other conductive materials can also be used, for example, it can also be a combination of metal silicides and different metal silicides, and the number of layers and materials of the conductive layer are not particularly limited here.
  • Atomic layer deposition, vacuum evaporation, magnetron sputtering, chemical vapor deposition or physical vapor deposition can be used to form a conductive layer and a passivation layer 903 in the trench 701 and the through hole 702 in turn.
  • Other methods can also be used.
  • the conductive layer and the passivation layer 903 are formed, which will not be listed one by one here.
  • sequentially forming a conductive layer and a passivation layer 903 in the trench 701 and the through hole 702 may include steps S2501 to S2503, wherein:
  • Step S2501 forming a first conductive layer on the surface of the substrate exposed by the trenches and the through holes.
  • the first conductive layer 901 may be a thin film formed on the surface of the substrate 600 , and the material may be polysilicon, and the surface of the substrate 600 exposed by the trenches 701 and the through holes 702 may be exposed by atomic layer deposition.
  • a first conductive layer 901 is formed, the first conductive layer 901 can be in contact with the substrate 600 , and the surface of the first conductive layer 901 facing away from the substrate 600 can be lower than the end of the insulating layer 800 facing away from the substrate 600 .
  • Step S2502 forming a second conductive layer on the surface of the first conductive layer away from the substrate, where the top surface of the second conductive layer is lower than the top surface of the sacrificial layer.
  • the second conductive layer 902 can be a thin film formed on the side of the first conductive layer 901 away from the substrate 600 , and its material can be tungsten, which can be deposited on the first conductive layer 901 by vacuum evaporation or magnetron sputtering.
  • a second conductive layer 902 is formed on the side of the conductive layer 901 facing away from the substrate 600 .
  • the second conductive layer 902 can be in contact with the first conductive layer 901 , and the surface of the conductive layer 901 facing away from the first conductive layer 901 can be lower than the insulating layer 800 The end facing away from the substrate 600 .
  • Step S2503 forming a passivation layer on the surface of the second conductive layer away from the substrate, and the top surface of the passivation layer is flush with the top surface of the sacrificial layer.
  • the passivation layer 903 can be a thin film formed on the side of the second conductive layer 902 away from the first conductive layer 901, which can be used to protect the surface of the conductive layer, and its material can be silicon nitride,
  • a passivation layer 903 may be simultaneously formed on the side of the second conductive layer 902 away from the first conductive layer 901 by chemical vapor deposition or physical vapor deposition, thereby forming a bit line structure 910 in the trench 701 .
  • the surface of the passivation layer 903 facing away from the second conductive layer 902 may be flush with the top surface of the sacrificial layer 700 .
  • Step S260 removing the passivation layer in the through hole to form a capacitor contact structure.
  • the passivation layer 903 in the through hole 702 may be removed to form a capacitive contact structure 920 in the through hole 702 , that is, the capacitive contact structure 920 may include a conductive layer formed on the substrate 600 .
  • an anisotropic etching process may be used to remove the passivation layer 903 in each of the through holes 702 to form the capacitor contact structure 920 in each of the through holes 702 .
  • the forming method of the present disclosure may further include the steps of:
  • Step S270 removing the filling layer to expose the isolation gap.
  • the filling layer 740 filling the isolation gap can be removed by a wet etching process.
  • the filling layer 740 can be removed by etching the filling layer 740 with an acid solution.
  • the acidic solution can selectively etch the filling layer 740 without causing damage or destruction to other film layers.
  • Step S280 controlling the deposition rate to form a dielectric layer covering the isolation gap, so as to quickly seal the second gap and form an air gap, the top surface of the air gap does not exceed the top surface of the bit line structure.
  • a dielectric layer can be filled in the isolation gap, and the dielectric layer can be made of a material with a lower dielectric constant, which can effectively reduce the parasitic capacitance between the bit line structures 910 and reduce the power consumption of the device.
  • the dielectric layer can be a silicon oxide material.
  • the dielectric layer may fill each isolation gap; in another embodiment, the second gap may be quickly sealed during deposition of the dielectric layer, forming an air gap, due to the dielectric constant of air. Smaller than the dielectric constant of silicon oxide, the formation of air gaps can reduce the parasitic capacitance of the device.
  • the dielectric layer 750 covering the isolation gap can be deposited by controlling the deposition rate of the dielectric layer 750 to quickly seal the second gap and form an air gap, and in order to prevent the bit line structure in subsequent packaging and practical applications Cracks are generated between 910 to ensure device stability, and the top surface of the air gap does not exceed the top surface of the bit line structure 910 .
  • an air gap can also be formed in the dielectric layer between two adjacent capacitive contact structures 920, so as to further reduce the parasitic capacitance.
  • Embodiments of the present disclosure also provide a semiconductor structure that can be formed by the method of forming a semiconductor structure in any of the above-described embodiments.
  • a semiconductor structure that can be formed by the method of forming a semiconductor structure in any of the above-described embodiments.
  • Embodiments of the present disclosure further provide a semiconductor device, which may include the semiconductor structure in any of the above-mentioned embodiments and a capacitor in contact with the capacitive contact structure 920 in the semiconductor structure.
  • the collected charge is stored.
  • DRAM Dynamic Random Access Memory

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Abstract

本公开提供一种半导体器件、半导体结构及其形成方法，涉及半导体技术领域。该形成方法包括：提供衬底，并在衬底上形成牺牲层；对牺牲层进行图案化处理，以在牺牲层中形成并排分布的沟槽及通孔；形成覆盖沟槽侧壁及通孔侧壁的绝缘层；在沟槽及通孔内依次形成导电层和钝化层，以在沟槽内形成位线结构；去除位于通孔内的钝化层，以在通孔内形成电容接触结构。

Description

半导体器件、半导体结构及其形成方法
交叉引用
本公开基于申请号为202011103875.6、申请日为2020年10月15日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种半导体器件、半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)因具有体积小、集成化程度高及传输速度快等优点，被广泛应用于手机、平板电脑等移动设备中。
现有动态随机存储器包括位元线及与位元线交替设置的电容接触窗口，但是在形成位元线及电容接触窗口时，受制备工艺影响，易出现结构异常，器件良率较低。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开提供一种半导体器件、半导体结构及其形成方法，可避免结构异常，提高器件良率。
根据本公开的一个方面，提供一种半导体结构的形成方法，包括：
提供衬底，并在所述衬底上形成牺牲层；
对所述牺牲层进行图案化处理，以在所述牺牲层中形成并排分布的沟槽及通孔；
形成覆盖所述沟槽侧壁及所述通孔侧壁的绝缘层；
在所述沟槽及所述通孔内依次形成导电层和钝化层，以在所述沟槽内形成位线结构；
去除位于所述通孔内的所述钝化层，以在所述通孔内形成电容接触结构。
根据本公开的一个方面，提供一种半导体结构的形成方法，包括：
提供衬底，并在所述衬底上形成牺牲层；
对所述牺牲层进行图案化处理，以形成并排分布的第一牺牲结构及第二牺牲结构；
形成覆盖所述第一牺牲结构侧壁及所述第二牺牲结构侧壁的绝缘层；
去除所述第一牺牲结构以形成沟槽，去除所述第二牺牲结构以形成通孔；
在所述沟槽和所述通孔内依次形成导电层和钝化层，以在所述沟槽内形成位线结构；
去除位于所述通孔内的所述钝化层，以形成电容接触结构。
根据本公开的一个方面，提供一种半导体结构，所述半导体结构由上述任意一项所述的半导体结构的形成方法形成。
根据本公开的一个方面，提供一种半导体器件，所述半导体器件包括上述任意一项所述的半导体结构，以及与所述电容接触结构接触连接的电容器。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中半导体结构的结构示意图。
图2为本公开第一种实施方式半导体结构的形成方法的流程图。
图3为本公开第二种实施方式半导体结构的形成方法的流程图。
图4为本公开第一种实施方式中衬底的俯视图。
图5为对应于图2中完成步骤S120后的结构示意图。
图6为对应于图5中的结构的俯视图。
图7为对应于图2中完成步骤S130后的结构示意图。
图8为对应于图7中的结构的俯视图。
图9为本公开第一种实施方式半导体结构的示意图。
图10为对应于图2中步骤S140的流程图。
图11为对应于图10中完成步骤S1401后的结构示意图。
图12为对应于图10中完成步骤S1402后的结构示意图。
图13为对应于图10中完成步骤S1403后的结构示意图。
图14为对应于图10中完成步骤S1403后的结构的俯视图。
图15为对应于图2中完成步骤S160后的结构示意图。
图16为对应于图15中的结构沿平行于成的方向剖开的示意图。
图17为本公开第二种实施方式中衬底的俯视图。
图18为对应于图3中完成步骤S220后的结构示意图。
图19为对应于图18中的结构的俯视图。
图20为对应于图2中完成步骤S230后的结构示意图。
图21为对应于图20中的结构的俯视图。
图22为本公开第二种实施方式中填充层的示意图。
图23为对应于图22中的结构的俯视图。
图24为对应于图3中完成步骤S240后的结构示意图。
图25为本公开第二种实施方式半导体结构的示意图。
图26为对应于图3中步骤S250的流程图。
图27为对应于图26中完成步骤S2501后的结构示意图。
图28为对应于图26中完成步骤S2502后的结构示意图。
图29为对应于图26中完成步骤S2503后的结构示意图。
图30为对应于图26中完成步骤S2503后的结构的俯视图。
图31为对应于图3中完成步骤S270后的结构示意图。
图32为对应于图31中的结构的俯视图。
图33为对应于图3中完成步骤S280后的结构示意图。
图34为应于图33中的结构沿平行于成的方向剖开的示意图。
图中：1、衬底；2、位线结构；3、电容接触窗口；4、气隙结构；
100、衬底；101、位线形成区域；102、电容接触结构形成区域；200、牺牲层；201、沟槽；202、通孔；211、第一间隙；212、第二间隙；300、绝缘层；410、位线结构；401、第一导电层；402、第二导电层；403、钝化层；420、电容接触结构；500、介质层；600、衬底；601、位线形成区域；602、电容接触结构形成区域；700、牺牲层；701、沟槽；702、通孔；710、第一牺牲结构；720、第二牺牲结构；731、第一间隙；740、填充层；750、介质层；800、绝缘层；910、位线结构；901、第一导电层；902、第二导电层；903、钝化层；920、电容接触结构。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”和“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”、“第二”和“第三”仅作为标记使用，不是对其对象的数量限制。
在相关技术中，如图1所示，半导体器件主要包括形成于衬底1上的交替分布的多个位线结构2和由于形成电容接触结构的电容接触窗口3。在制造过程中，需要先在衬底1上形成各位线结构2，再在相邻两个位线结构2之间分别形成电容接触结构。此外，为了降低器件的寄生电容，通常在各位线结构2侧壁形成气隙结构4。但是，气隙结构4的设计时位线结构2与电容接触结构之间的防护强度减弱；而且，由于位线结构2与电容接触结构在不同时期进行，所以层与层之间容易发生曝光偏移，使得电容接触结构易出现对不准的问题，在形成电容接触窗口3时易对气隙结构4造成破坏，引起结构异常，器件良率较低。
本公开第一种实施方式提供了一种半导体结构的形成方法，如图2所示，该形成方法可以包括：
步骤S110，提供衬底，并在所述衬底上形成牺牲层；
步骤S120，对所述牺牲层进行图案化处理，以在所述牺牲层中形成并排分布的沟槽及通孔；
步骤S130，形成覆盖所述沟槽侧壁及所述通孔侧壁的绝缘层；
步骤S140，在所述沟槽及所述通孔内依次形成导电层和钝化层，以在所述沟槽内形成位线结构；
步骤S150，去除位于所述通孔内的所述钝化层，以在所述通孔内形成电容接触结构。
本公开第二种实施方式也提供了一种半导体结构的形成方法，如图3所示，该形成方法可以包括：
步骤S210，提供衬底，并在所述衬底上形成牺牲层；
步骤S220，对所述牺牲层进行图案化处理，以形成并排分布的第一牺牲结构及第二牺牲结构；
步骤S230，形成覆盖所述第一牺牲结构侧壁及所述第二牺牲结构侧壁的绝缘层；
步骤S240，去除所述第一牺牲结构以形成沟槽，去除所述第二牺牲结构以形成通孔；
步骤S250，在所述沟槽和所述通孔内依次形成导电层和钝化层，以在所述沟槽内形成位线结构；
步骤S260，去除位于所述通孔内的所述钝化层，以形成电容接 触结构。
本公开实施例的半导体器件、半导体结构及其形成方法，可通过绝缘层对位线结构及电容接触结构的两侧进行绝缘保护，防止位线结构和电容接触结构与其他结构接触，降低器件的短路风险。此外，电容接触结构与位线结构可通过相同的制备工艺同时形成，避免对电容接触结构和位线结构分次制备所造成的电容接触结构对不准的问题，且在制备过程中，位线结构形成于沟槽内，电容接触结构形成于通孔内，两者的位置已预先定义好，因而，形成的电容接触结构不会发生偏移，避免结构异常，提高器件良率。
下面对本公开第一种实施方式半导体结构的形成方法的各步骤进行详细说明：
如图2所示，在步骤S110中，提供衬底，并在所述衬底上形成牺牲层。
如图4和图5所示，衬底100可呈平板结构，可在衬底100上预先定义出位线形成区域101和电容接触结构420形成区域102，衬底100可为矩形、圆形、椭圆形、多边形或不规则图形，其材料可以是硅或其他半导体材料，在此不对衬底100的形状及材料做特殊限定。
可在衬底100的表面形成牺牲层200，牺牲层200可以是形成于衬底100上的薄膜，也可以是形成于衬底100上涂层，举例而言，其可以是光刻胶或硬掩模，其材料可以是二氧化硅等，在此不做特殊限定。牺牲层200的厚度可与所需的位线结构的厚度相同，在一实施方式中，其厚度范围可为50nm～200nm，例如，其可以是50nm、100nm、 150nm或200nm，当然，也可以是其他厚度，在此不再一一列举。可通过原子层沉积、真空蒸镀、磁控溅射、化学气相沉积或物理气相沉积等方式在衬底100上形成牺牲层200，当然，还可通过其他工艺在衬底100上形成牺牲层200，在此不对牺牲层200的成型工艺做特殊限定。
如图2所示，在步骤S120中，对所述牺牲层进行图案化处理，以在所述牺牲层中形成并排分布的沟槽及通孔。
如图5及图6所示，可根据预先定义好的位线形成区域101和电容接触结构420形成区域102采用光刻工艺对牺牲层200进行图案化处理，以在牺牲层200中形成并排分布的沟槽201及通孔202。在垂直于衬底100的方向上，沟槽201可两端贯通，且其在平行于衬底100的方向上可呈条状，并可沿平行于衬底100的方向延伸。通孔202可为圆形孔、矩形孔或不规则形状的孔状结构，在此不做特殊限定。
通孔202可为多个，多个通孔202可排成一列，并可沿沟槽201的延伸方向间隔设置。在一实施方式中，每条沟槽201可与每列通孔202构成一组，可形成多组并排分布的沟槽201和通孔202，且在相邻两组中沟槽201与通孔202所构成的列交替分布，即：各通孔202分布于沟槽201两侧，并可延槽的延伸方向间隔设置。
举例而言，可通过化学气相沉积、真空蒸镀、原子层沉积或其它方式在牺牲层200背离衬底100的一侧形成掩膜材料层，掩膜材料层可以有多层，也可以为单层结构，其材料可以是聚合物、SiO2、SiN、poly和SiCN中至少一种，当然，也可以是其它材料，在此不再一一 列举。
可通过旋涂或其它方式在掩膜材料层背离牺牲层200的表面形成光刻胶层，光刻胶层材料可以是正性光刻胶或负性光刻胶，在此不做特殊限定。
可采用掩膜版对光刻胶层进行曝光，该掩膜版的图案可与牺牲层200所需的图案匹配。随后，可对曝光后的光刻胶层进行显影，从而形成多个显影区，每个显影区可露出掩膜材料层，且显影区的图案可与牺牲层200所需的图案相同，各显影区的尺寸可与所需的沟槽201及通孔202的尺寸相匹配。
可通过等离子蚀刻工艺在显影区对掩膜材料层进行蚀刻，蚀刻区域可露出牺牲层200，从而在掩膜材料层上形成所需的掩膜图案。在完成上述蚀刻工艺后，可通过清洗液清洗或通过灰化等工艺去除光刻胶层，使掩膜材料层不再被光刻胶层覆盖，将形成的掩膜层暴露出来，得到硬掩膜结构。
可根据掩膜图案对牺牲层200进行非等向蚀刻，举例而言，可通过干法蚀刻工艺在掩膜图案的显影区对牺牲层200进行蚀刻，并以衬底100作为蚀刻停止层，在牺牲层200内形成并排分布的沟槽201及通孔202。图5示出了完成本公开第一种形成方法的实施方式中步骤S120后的结构。
如图2所示，在步骤S130中，形成覆盖所述沟槽侧壁及所述通孔侧壁的绝缘层。
如图7及图8所示，可在通孔202的侧壁及沟槽201的侧壁形成 随形贴合的绝缘层300，且位于沟槽201两侧壁的绝缘层300可铺满沟槽201的两个侧壁，当沟槽201为条状时，位于沟槽201两侧壁的绝缘层300可相对设置；位于通孔202侧壁的绝缘层300可铺满通孔202的孔壁，即：当通孔202为圆形孔时，位于通孔202侧壁的绝缘层300在平行于衬底100的方向上的横截面可呈圆形；当通孔202为矩形孔时，位于通孔202侧壁的绝缘层300在平行于衬底100的方向上的横截面可呈矩形。绝缘层300的厚度范围可为1nm～5nm，当然，也可以是其他厚度范围，在此不做特殊限定。
需要说明的是，位于沟槽201侧壁的绝缘层300可与位于通孔202侧壁的绝缘层300通过牺牲层200隔开。绝缘层300靠近衬底100的一侧可与衬底100接触连接，其背离衬底100的一侧可与牺牲层200背离衬底100的表面齐平。
绝缘层300可以是形成于通孔202的侧壁及沟槽201的侧壁的薄膜，也可以是形成于通孔202的侧壁及沟槽201的侧壁的膜层，在此不做特殊限定。可采用化学气相沉积工艺在通孔202的侧壁及沟槽201的侧壁形成绝缘层300，当然，还可通过其他工艺形成绝缘层300，在此不做特殊限定。
需要说明的是，牺牲层200的材料与绝缘层300的材料可与具有高的蚀刻比，举例而言，牺牲层200的材料与绝缘层300的材料的蚀刻比可大于100:1。举例而言，绝缘层300的材料可以是Si3N4或SiCN，当然，还可以是其他绝缘材料，在此不再一一列举。
如图2所示，在步骤S140中，在所述沟槽及所述通孔内依次形 成导电层和钝化层，以在所述沟槽内形成位线结构。
如图8和图9所示，可在沟槽201内形成位线结构410，同时在通孔202内形成电容接触结构420，进而可通过位线结构410与衬底100中的源极或漏极接触连接，通过电容接触结构420与电容器接触连接，以通过电容接触结构420对电容器收集的电荷进行存储。
需要说明的是，当通孔202为多个时，可在各通孔202中均形成电容接触结构420，各电容接触结构420均可具有与之对应的电容器，可通过多个电容接触结构420同时存储电荷，以提高DRAM的存储能力；当沟槽201为多个时，可在各沟槽201中均形成位线结构410。
导电层可为单层结构，也可为多层结构，其材料可以是导体或半导体材料，举例而言，其可以是多晶硅、硅锗(SiGe)、钨、钛、钴等材料或其组合物，当然，还可以是其他导电材料，例如，其还可以是金属硅化物及不同金属硅化物的组合物，在此不对导电层的膜层数量及材料做特殊限定。
可采用原子层沉积、真空蒸镀、磁控溅射、化学气相沉积或物理气相沉积等方式在沟槽201及通孔202内依次形成导电层和钝化层403，当然，还可通过其他方式形成导电层和钝化层403，在此不再一一列举。
在一实施方式中，如图10所示，在所述沟槽201及所述通孔202内依次形成导电层和钝化层403可以包括步骤S1401-步骤S1403，其中：
步骤S1401，在所述沟槽和所述通孔露出的所述衬底的表面形成 第一导电层。
如图11所示，第一导电层401可以是形成于衬底100表面的薄膜，其材料可为多晶硅，可通过原子层沉积的方式在沟槽201和通孔202露出的衬底100的表面同时形成第一导电层401，第一导电层401可与衬底100接触连接，且其背离衬底100的表面可低于绝缘层300背离衬底100的一端。
步骤S1402，在所述第一导电层背离所述衬底的表面形成第二导电层，所述第二导电层的顶表面低于所述牺牲层的顶表面。
如图12所示，第二导电层402可以是形成于第一导电层401背离衬底100的一侧的薄膜，其材料可为钨，可通过真空蒸镀或磁控溅射的方式在第一导电层401背离衬底100的一侧同时形成第二导电层402，第二导电层402可与第一导电层401接触连接，且其背离第一导电层401的表面可低于绝缘层300背离衬底100的一端。
步骤S1403，在所述第二导电层背离所述衬底的表面形成钝化层，所述钝化层的顶表面与所述牺牲层200的顶表面齐平。
如图13-图14所示，钝化层403可以是形成于第二导电层402背离第一导电层401的一侧的薄膜，可用于保护导电层的表面，其材料可为氮化硅，为了工艺方便，可通过化学气相沉积或物理气相沉积的方式在第二导电层402背离第一导电层401的一侧同时形成钝化层403，进而在沟槽201内形成位线结构410。需要说明的是，钝化层403背离第二导电层402的表面可与牺牲层200的顶表面齐平。
如图2所示，在步骤S150中，去除位于所述通孔内的所述钝化 层，以在所述通孔内形成电容接触结构。
如图9所示，可去除位于通孔202内的钝化层403，以在通孔202中形成电容接触结构420，即：电容接触结构420可包括形成于衬底100上的导电层。举例而言，可采用非等向蚀刻工艺去除位于各通孔202内的钝化层403，以在各通孔202内均形成电容接触结构420。
在本公开的一种实施方式中，本公开的形成方法还可包括步骤S160及步骤S170，如图2所示，其中：
步骤S160，在形成所述钝化层后，去除所述牺牲层，以形成隔离间隙。
如图15所示，在形成钝化层403后，可通过湿法刻蚀工艺去除牺牲层200，以形成隔离间隙，该隔离间隙可包括同一列中相邻两个电容接触结构420之间的第一间隙211，以及位于位线结构410及与之相邻的电容接触结构420之间的第二间隙212。
举例而言，可采用酸性溶液进行湿法刻蚀，酸性溶液可以是氢氟酸，举例而言，其可以是缓冲氢氟酸(BHF)、浓度为49％的氢氟酸或稀氢氟酸(DHF)，在使用时，可根据牺牲层200的具体材料设定酸性溶液与去离子水的配制比例，在此不对刻蚀溶液的配比及浓度做特殊限定。以本公开的第一种实施方式为例，完成步骤S160后的结构如图15及图16所示。
步骤S170，形成覆盖所述隔离间隙的介质层。
如图9及图15所示，可在隔离间隙中填充介电层，介电层可由具有较低介电常数的材料构成，可有效降低位线结构410间的寄生电 容，降低器件功耗。举例而言，其可以是氧化硅材料。在一实施方式中，介电层可填满各隔离间隙；在另一实施方式中，在沉积介电层的过程中可在第二间隙212处快速封口，形成气隙，由于空气的介电常数小于氧化硅的介电常数，气隙的形成可降低器件的寄生电容。举例而言，可通过控制介质层500的沉积速率沉积覆盖隔离间隙的介质层500，以对所述第二间隙212进行快速封口并形成气隙，且为了防止在后续封装及实际应用中位线结构410之间产生裂纹，保证器件稳定性，气隙的顶表面不超过位线结构410的顶表面。
需要说明的是，在对第二间隙212进行快速封口的同时在相邻两个电容接触结构420之间的介电层中也可形成气隙，以便进一步减小寄生电容。
本公开第二种实施方式也提供了一种半导体结构的形成方法，如图3所示，该形成方法可以包括：
步骤S210，提供衬底，并在所述衬底上形成牺牲层。
如图17所示，衬底600可呈平板结构，可在衬底600上预先定义出位线形成区域601和电容接触结构920形成区域602，衬底600可为矩形、圆形、椭圆形、多边形或不规则图形，其材料可以是硅或其他半导体材料，在此不对衬底600的形状及材料做特殊限定。
如图18所示，可在衬底600的表面形成牺牲层700，牺牲层700可以是形成于衬底600上的薄膜，也可以是形成于衬底600上涂层，其材料可以是二氧化硅，在此不做特殊限定。可通过原子层沉积、真空蒸镀、磁控溅射、化学气相沉积或物理气相沉积等方式在衬底600 上形成牺牲层700，当然，还可通过其他工艺在衬底600上形成牺牲层700，在此不对牺牲层700的成型工艺做特殊限定。
步骤S220，对所述牺牲层进行图案化处理，以形成并排分布的第一牺牲结构及第二牺牲结构。
如图18-图19所示，可根据预先定义好的位线形成区域601和电容接触结构920形成区域602采用光刻工艺对牺牲层700进行图案化处理，以在牺牲层700中形成并排分布的第一牺牲结构710及第二牺牲结构720。第一牺牲结构710在平行于衬底600的方向上可呈条状，并可沿平行于衬底600的方向延伸。第二牺牲结构720可为圆形柱、矩形柱或不规则形状的柱状结构，在此不做特殊限定。
如图19所示，第二牺牲结构720可为多个，多个第二牺牲结构720可排成一列，并可沿第一牺牲结构710的延伸方向间隔设置。在一实施方式中，每条第一牺牲结构710可与每列第二牺牲结构720构成一组，可形成多组并排分布的第一牺牲结构710和第二牺牲结构720，且在相邻两组中第一牺牲结构710与第二牺牲结构720所构成的列交替分布，即：各第二牺牲结构720分布于第一牺牲结构710两侧，并可延第一牺牲结构710的延伸方向间隔设置。
举例而言，可通过化学气相沉积、真空蒸镀、原子层沉积或其它方式在牺牲层700背离衬底600的一侧形成掩膜材料层，掩膜材料层可以有多层，也可以为单层结构，其材料可以是聚合物、SiO2、SiN、poly和SiCN中至少一种，当然，也可以是其它材料，在此不再一一列举。
可通过旋涂或其它方式在掩膜材料层背离牺牲层700的表面形成光刻胶层，光刻胶层材料可以是正性光刻胶或负性光刻胶，在此不做特殊限定。
可采用掩膜版对光刻胶层进行曝光，该掩膜版的图案可与牺牲层700所需的图案匹配。随后，可对曝光后的光刻胶层进行显影，从而形成多个显影区，每个显影区可露出掩膜材料层，且显影区的图案可与牺牲层700所需的图案相同，各显影区的尺寸可与所需的第一牺牲结构710及第二牺牲结构720以外的区域的尺寸相匹配。
可通过等离子蚀刻工艺在显影区对掩膜材料层进行蚀刻，蚀刻区域可露出牺牲层700，从而在掩膜材料层上形成所需的掩膜图案。在完成上述蚀刻工艺后，可通过清洗液清洗或通过灰化等工艺去除光刻胶层，使掩膜材料层不再被光刻胶层覆盖，将形成的掩膜层暴露出来，得到硬掩膜结构。
可根据掩膜图案对牺牲层700进行非等向蚀刻，举例而言，可通过干法蚀刻工艺在掩膜图案的显影区对牺牲层700进行蚀刻，并以衬底600作为蚀刻停止层，在牺牲层700内形成并排分布的第一牺牲结构710及第二牺牲结构720。图18示出了完成本公开第二种形成方法的实施方式中步骤S220后的结构。
步骤S230，形成覆盖所述第一牺牲结构侧壁及所述第二牺牲结构侧壁的绝缘层。
如图20及图21所示，可在第一牺牲结构710侧壁及第二牺牲结构720的侧壁形成随形贴合的绝缘层800，且位于第一牺牲结构710 两侧壁的绝缘层800可铺满第一牺牲结构710的两个侧壁，当第一牺牲结构710为条状时，位于第一牺牲结构710两侧壁的绝缘层800可相对设置；位于第二牺牲结构720侧壁的绝缘层800可铺满第二牺牲结构720的外壁，即：当第二牺牲结构720为圆形柱时，位于第二牺牲结构720侧壁的绝缘层800在平行于衬底600的方向上的横截面可呈圆形；当第二牺牲结构720为矩形柱时，位于第二牺牲结构720侧壁的绝缘层800在平行于衬底600的方向上的横截面可呈矩形。
需要说明的是，位于第一牺牲结构710侧壁的绝缘层800可与位于第二牺牲结构720侧壁的绝缘层800接触连接，且绝缘层800靠近衬底600的一侧可与衬底600接触连接，其背离衬底600的一侧可与牺牲层700背离衬底600的表面齐平。
绝缘层800可以是形成于第二牺牲结构720的侧壁及第一牺牲结构710的侧壁的薄膜，也可以是形成于第二牺牲结构720的侧壁及第一牺牲结构710的侧壁的膜层，在此不做特殊限定。可采用化学气相沉积工艺在第二牺牲结构720的侧壁及第一牺牲结构710的侧壁形成绝缘层800，当然，还可通过其他工艺形成绝缘层800，在此不做特殊限定。
需要说明的是，牺牲层700的材料与绝缘层800的材料可与具有高的蚀刻比，举例而言，牺牲层700的材料与绝缘层800的材料的蚀刻比可大于100:1。举例而言，绝缘层800的材料可以是Si3N4或SiCN，当然，还可以是其他绝缘材料，在此不再一一列举。
在本公开的一种实施方式中，第一牺牲结构710及第二牺牲结构 720之间可具有隔离间隙，隔离间隙可包括同一列中相邻两个电容接触结构920之间的第一间隙731，以及相邻位线结构910和电容接触结构920之间的第二间隙(图中未示出)，在一实施方式中，在形成覆盖第一牺牲结构710侧壁及第二牺牲结构720侧壁的绝缘层800之后，第二间隙可为位于位线结构910侧壁的绝缘层800与位于电容接触结构920侧壁的绝缘层800之间的空隙。
本公开的形成方法还可包括在隔离间隙沉积填充层740，如图22和图23所示，在形成位线结构910及电容接触结构920后可去除该填充层740，以避免在形成位线结构910及电容接触结构920的过程中隔离间隙被导电材料所填充。填充层740可为密度较小的材料，以便于后续去除。可采用化学气相沉积或物理气相沉积的方式在隔离间隙中形成填充层740，当然，也可以通过其他方式形成填充层740，在此不对填充层740的形成方式做特殊限定。
步骤S240，去除所述第一牺牲结构以形成沟槽，去除所述第二牺牲结构以形成通孔。
如图24所示，在形成绝缘层800后，可通过湿法刻蚀工艺去除第一牺牲结构710以形成沟槽701，同时去除第二牺牲结构720以形成通孔702。举例而言，可采用酸性溶液进行湿法刻蚀，酸性溶液可以是氢氟酸，举例而言，其可以是缓冲氢氟酸(BHF)、浓度为49％的氢氟酸或稀氢氟酸(DHF)，在使用时，可根据第一牺牲结构710及第二牺牲结构720的具体材料设定酸性溶液与去离子水的配制比例，在此不对刻蚀溶液的配比及浓度做特殊限定。完成步骤S240后的结构 如图24所示。
步骤S250，在所述沟槽和所述通孔内依次形成导电层和钝化层，以在所述沟槽内形成位线结构。
如图25所示，可在沟槽701内形成位线结构910，同时在通孔702内形成电容接触结构920，进而可通过位线结构910与衬底600中的源极或漏极接触连接，通过电容接触结构920与电容器接触连接，以通过电容接触结构920对电容器收集的电荷进行存储。
需要说明的是，当第二接触结构为多个时，通孔702也为多个，可在各通孔702中均形成电容接触结构920，各电容接触结构920均可具有与之对应的电容器，可通过多个电容接触结构920同时存储电荷，以提高DRAM的存储能力；当第一接触结构为多个时，沟槽701也为多个，可在各沟槽701中均形成位线结构910，以便将器件电学引出。
导电层可为单层结构，也可为多层结构，其材料可以是导体或半导体材料，举例而言，其可以是多晶硅、硅锗(SiGe)、钨、钛、钴等材料或其组合物，当然，还可以是其他导电材料，例如，其还可以是金属硅化物及不同金属硅化物的组合物，在此不对导电层的膜层数量及材料做特殊限定。
可采用原子层沉积、真空蒸镀、磁控溅射、化学气相沉积或物理气相沉积等方式在沟槽701及通孔702内依次形成导电层和钝化层903，当然，还可通过其他方式形成导电层和钝化层903，在此不再一一列举。
在一实施方式中，如图26所示，在所述沟槽701及所述通孔702内依次形成导电层和钝化层903可以包括步骤S2501-步骤S2503，其中：
步骤S2501，在所述沟槽和所述通孔露出的所述衬底的表面形成第一导电层。
如图27所示，第一导电层901可以是形成于衬底600表面的薄膜，其材料可为多晶硅，可通过原子层沉积的方式在沟槽701和通孔702露出的衬底600的表面同时形成第一导电层901，第一导电层901可与衬底600接触连接，且其背离衬底600的表面可低于绝缘层800背离衬底600的一端。
步骤S2502，在所述第一导电层背离所述衬底的表面形成第二导电层，所述第二导电层的顶表面低于所述牺牲层的顶表面。
如图28所示，第二导电层902可以是形成于第一导电层901背离衬底600的一侧的薄膜，其材料可为钨，可通过真空蒸镀或磁控溅射的方式在第一导电层901背离衬底600的一侧同时形成第二导电层902，第二导电层902可与第一导电层901接触连接，且其背离第一导电层901的表面可低于绝缘层800背离衬底600的一端。
步骤S2503，在所述第二导电层背离所述衬底的表面形成钝化层，所述钝化层的顶表面与所述牺牲层的顶表面齐平。
如图29-图30所示，钝化层903可以是形成于第二导电层902背离第一导电层901的一侧的薄膜，可用于保护导电层的表面，其材料可为氮化硅，为了工艺方便，可通过化学气相沉积或物理气相沉积 的方式在第二导电层902背离第一导电层901的一侧同时形成钝化层903，进而在沟槽701内形成位线结构910。需要说明的是，钝化层903背离第二导电层902的表面可与牺牲层700的顶表面齐平。
步骤S260，去除位于所述通孔内的所述钝化层，以形成电容接触结构。
如图25所示，可去除位于通孔702内的钝化层903，以在通孔702中形成电容接触结构920，即：电容接触结构920可包括形成于衬底600上的导电层。举例而言，可采用非等向蚀刻工艺去除位于各通孔702内的钝化层903，以在各通孔702内均形成电容接触结构920。
在本公开的一种实施方式中，在沟槽701和通孔702内形成导电层和钝化层903之后，本公开的形成方法还可包括步骤：
步骤S270，去除所述填充层以暴露所述隔离间隙。
如图31-图32所示，可采用湿法蚀刻工艺去除填充隔离间隙的填充层740，举例而言，可通过酸性溶液酸蚀填充层740以去除填充层740。该酸性溶液可对填充层740进行选择性蚀刻，不会对其他膜层结构造成损伤或破坏。
步骤S280，控制沉积速率形成覆盖所述隔离间隙的介质层，以对所述第二间隙进行快速封口并形成气隙，所述气隙的顶表面不超过所述位线结构的顶表面。
图33-图34所示，可在隔离间隙中填充介电层，介电层可由具有较低介电常数的材料构成，可有效降低位线结构910间的寄生电 容，降低器件功耗。举例而言，其可以是氧化硅材料。在一实施方式中，介电层可填满各隔离间隙；在另一实施方式中，在沉积介电层的过程中可在第二间隙处快速封口，形成气隙，由于空气的介电常数小于氧化硅的介电常数，气隙的形成可降低器件的寄生电容。举例而言，可通过控制介质层750的沉积速率沉积覆盖隔离间隙的介质层750，以对所述第二间隙进行快速封口并形成气隙，且为了防止在后续封装及实际应用中位线结构910之间产生裂纹，保证器件稳定性，气隙的顶表面不超过位线结构910的顶表面。
需要说明的是，在对第二间隙进行快速封口的同时在相邻两个电容接触结构920之间的介电层中也可形成气隙，以便进一步减小寄生电容。
本公开实施方式还提供一种半导体结构，该半导体结构可由上述任一实施方式中的半导体结构的形成方法形成。半导体结构以及有益效果可参考上述任一实施方式中的半导体结构的形成方法，在此不再详述。
本公开实施方式还提供一种半导体器件，该半导体器件可包括上述任一实施方式中的半导体结构以及与该半导体结构中的电容接触结构920接触连接的电容器，可通过电容接触结构920对电容器中收集的电荷进行存储。半导体器件以及有益效果可参考上述实施方式中的半导体结构的形成方法，在此不再详述。例如，其可以是动态随机存取存储器(Dynamic Random Access Memory，DRAM)。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易 想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (14)

  1. 一种半导体结构的形成方法，包括：
    提供衬底，并在所述衬底上形成牺牲层；
    对所述牺牲层进行图案化处理，以在所述牺牲层中形成并排分布的沟槽及通孔；
    形成覆盖所述沟槽侧壁及所述通孔侧壁的绝缘层；
    在所述沟槽及所述通孔内依次形成导电层和钝化层，以在所述沟槽内形成位线结构；
    去除位于所述通孔内的所述钝化层，以在所述通孔内形成电容接触结构。
  2. 根据权利要求1所述的形成方法，其中，所述沟槽侧壁的绝缘层与所述通孔侧壁的绝缘层通过所述牺牲层隔开。
  3. 根据权利要求1所述的形成方法，其中，在所述沟槽及所述通孔内依次形成导电层和钝化层，包括：
    在所述沟槽和所述通孔露出的所述衬底的表面形成第一导电层；
    在所述第一导电层背离所述衬底的表面形成第二导电层，所述第二导电层的顶表面低于所述牺牲层的顶表面；
    在所述第二导电层背离所述衬底的表面形成钝化层，所述钝化层的顶表面与所述牺牲层的顶表面齐平。
  4. 根据权利要求1-3任一项所述的形成方法，其中，所述形成方法还包括：
    在形成所述钝化层后，去除所述牺牲层，以形成隔离间隙；
    形成覆盖所述隔离间隙的介质层。
  5. 根据权利要求4所述的形成方法，其中，所述通孔为多个，各所述通孔分布于所述沟槽两侧，并沿所述沟槽的延伸方向间隔设置；各所述通孔中均形成有所述电容接触结构，各所述沟槽中均形成有所述位线结构。
  6. 根据权利要求5所述的形成方法，其中，所述隔离间隙包括相邻两个所述电容接触结构之间的第一间隙，以及位于所述位线结构及与之相邻的电容接触结构之间的第二间隙；所述形成覆盖所述隔离间隙的介质层，包括：
    控制所述介质层的沉积速率沉积覆盖所述隔离间隙的介质层，以对所述第二间隙进行快速封口并形成气隙，所述气隙的顶表面不超过所述位线结构的顶表面。
  7. 一种半导体结构的形成方法，包括：
    提供衬底，并在所述衬底上形成牺牲层；
    对所述牺牲层进行图案化处理，以形成并排分布的第一牺牲结构及第二牺牲结构；
    形成覆盖所述第一牺牲结构侧壁及所述第二牺牲结构侧壁的绝缘层；
    去除所述第一牺牲结构以形成沟槽，去除所述第二牺牲结构以形成通孔；
    在所述沟槽和所述通孔内依次形成导电层和钝化层，以在所述沟槽内形成位线结构；
    去除位于所述通孔内的所述钝化层，以形成电容接触结构。
  8. 根据权利要求7所述的形成方法，其中，所述第一牺牲结构的侧壁的绝缘层与所述第二牺牲结构的侧壁的绝缘层接触连接。
  9. 根据权利要求7所述的形成方法，其中，在所述沟槽及所述通孔内依次形成导电层和钝化层，包括：
    在所述沟槽和所述通孔露出的所述衬底的表面形成第一导电层；
    在所述第一导电层背离所述衬底的表面形成第二导电层，所述第二导电层的顶表面低于所述牺牲层的顶表面；
    在所述第二导电层背离所述衬底的表面形成钝化层，所述钝化层的顶表面与所述牺牲层的顶表面齐平。
  10. 根据权利要求7-9任一项所述的形成方法，其中，所述第一牺牲结构及第二牺牲结构之间具有隔离间隙，在形成覆盖所述第一牺牲结构侧壁及所述第二牺牲结构侧壁的绝缘层之后，所述形成方法还包括：
    在所述隔离间隙沉积填充层。
  11. 根据权利要求10所述的形成方法，其中，所述第二牺牲结构为多个，各所述第二牺牲结构分布于所述第一牺牲结构两侧，并沿所述第一牺牲结构的延伸方向间隔设置。
  12. 根据权利要求11所述的形成方法，其中，所述隔离间隙包括相邻两个所述电容接触结构之间的第一间隙，以及相邻位线结构和电容接触结构之间的第二间隙；在所述沟槽和所述通孔内形成导电层和钝化层之后，还包括：
    去除所述填充层以暴露所述隔离间隙；
    控制沉积速率形成覆盖所述隔离间隙的介质层，以对所述第二间隙进行快速封口并形成气隙，所述气隙的顶表面不超过所述位线结构的顶表面。
  13. 一种半导体结构，其中，所述半导体结构由权利要求1-12任一项所述的半导体结构的形成方法形成。
  14. 一种半导体器件，其中，所述半导体器件包括权利要求13所述的半导体结构，以及与所述电容接触结构接触连接的电容器。
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