CN102005474A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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Abstract
本发明涉及半导体装置及其制造方法。在n型Si衬底(10)上形成有多个IGBT单元(24)。各个IGBT单元(24)具有栅极电极(46)和第一发射极电极(54)。下层栅极布线(14)在n型Si衬底(10)上形成,连接于栅极电极(46)。层间绝缘膜(66)覆盖第一发射极电极(54)及下层栅极布线(14)。第二发射极电极(20)在层间绝缘膜(66)上形成,经由层间绝缘膜(66)的开口连接于第一发射极电极(54)。第二发射极电极(20)隔着层间绝缘膜(66)在下层栅极布线(14)的上方延伸。
Description
技术领域
本发明涉及能够增大发射极电极的半导体装置及其制造方法。
背景技术
在逆变器等的电力变换装置中使用IGBT(Insulated Gate BipolarTransistor,绝缘栅双极晶体管)(例如,参照专利文献1)。为了提高该IGBT的工作性能,进行了IGBT单元的结构的重新研究、晶片厚度的合理化。可是,根据这些手段的性能提高正在不断接近极限。因此,研究增大相对于芯片面积的发射极电极的面积,降低电流密度的方案。
专利文献1:日本特开2008-135536号公报
为了不增大芯片而增大发射极电极,只要减小栅极焊盘、栅极布线以及终端区域(terminating region)即可。可是,栅极焊盘的大小被与外部的连接面积、例如Al引线的线径所制约。此外,当减少栅极布线的根数时,导致并联连接的IGBT单元间的不平衡工作。而且,根据IGBT的额定电流,在ON和OFF的切换时的数μsec中有时流过数A的栅极电流,因此栅极布线的宽度受到电迁移的制约。此外,使终端区域为纵方向的N-层的厚度以下在原理上是不可能的。进而,当使终端区域过小时,担心有品质上的问题。因此,不能够增大发射极电极。
此外,近年来,有许多应用了传递模塑(transfer molding)技术的制品。可是,由于模塑树脂和半导体衬底的热膨胀系数的差,模塑树脂的应力导致半导体衬底上的电极随时间经过而剥落(slide,滑动)。为了防止该情况,对电极进行薄膜化,减小阶梯差。可是,由于担心上述栅极布线的宽度的限制、在引线键合时向单元部的损伤,所以电极的薄膜化有极限。此外,也考虑利用聚酰亚胺涂覆来保护布线,但这成为成本上升的要因。
发明内容
本发明正是为了解决上述那样的课题而完成的,其第一目的在于获得一种能够增大发射极电极的半导体装置及其制造方法。本发明的第二目的在于获得一种能够防止模塑树脂的应力导致的电极的滑动的半导体装置及其制造方法。
本发明的半导体装置的特征在于,具备:半导体衬底;多个IGBT单元,在上述半导体衬底上形成,分别具有栅极电极和第一发射极电极;第一栅极布线,在上述半导体衬底上形成,连接于上述栅极电极;层间绝缘膜,覆盖上述第一发射极电极和上述第一栅极布线;以及第二发射极电极,在上述层间绝缘膜上形成,经由上述层间绝缘膜的开口连接于上述第一发射极电极,上述第二发射极电极隔着上述层间绝缘膜在上述第一栅极布线的上方延伸。
通过本发明,能够增大发射极电极。
附图说明
图1是表示本发明的实施方式1的半导体装置的上视图。
图2是表示图1的区域A中的n型Si衬底的表面的扩大上视图。
图3是沿着图1和图2的B-B′的剖视图。
图4是沿着图1和图2的C-C′的剖视图。
图5是沿着图1的D-D′的剖视图。
图6是表示图1的区域E中的n型Si衬底的表面的扩大上视图。
图7是沿着图1和图6的F-F′的剖视图。
图8是沿着图1和图6的G-G′的剖视图。
图9是表示本发明的实施方式1的半导体装置的制造工序的剖视图。
图10是表示本发明的实施方式1的半导体装置的制造工序的剖视图。
图11是表示本发明的实施方式1的半导体装置的制造工序的剖视图。
图12是表示第一比较例的半导体装置的上视图。
图13是沿着图12的H-H′的剖视图。
图14是沿着图12的I-I′的剖视图。
图15是表示本发明的实施方式2的半导体装置的上视图。
图16是表示本发明的实施方式3的半导体装置的剖视图。
图17是表示本发明的实施方式4的半导体装置的剖视图。
图18是表示本发明的实施方式4的半导体装置的制造工序的剖视图。
图19是表示本发明的实施方式4的半导体装置的制造工序的剖视图。
图20是表示本发明的实施方式4的半导体装置的制造工序的剖视图。
图21是表示第二比较例的半导体装置的剖视图。
附图标记说明
10 n型Si衬底(半导体衬底)
12、14、16 下层栅极布线(第一栅极布线)
18、88 上层栅极布线(第三栅极布线)
20 第二发射极电极
24 IGBT单元
46 栅极电极
54 第一发射极电极
56 下层栅极布线(第二栅极布线)
58、60、62、64、110、112、114 第一场板电极
66 层间绝缘膜
68、116、118、120、122 第二场板电极
70 保护膜
90 第三发射极电极
92 Ti膜
94 Ni膜
96 Au膜
具体实施方式
以下,针对实施本发明的方式,参照附图详细地进行说明。对同样的构成要素赋予相同的附图标记,省略说明。
实施方式1
图1是表示本发明的实施方式1的半导体装置的上视图。该半导体装置是沟槽型的IGBT。
在n型Si衬底10(半导体衬底)上形成有由Al构成的、下层栅极布线12、14、16、上层栅极布线18、第二发射极电极20以及栅极焊盘22。栅极布线12、14、16、18连接于栅极焊盘22。环状的上层栅极布线18在n型Si衬底10上配置在第二发射极电极20的外侧。直线状的下层栅极布线12、14、16(第一栅极布线)配置在第二发射极电极20的下方。
第二发射极电极20例如被引线键合并从外部被输入发射极电流(主电流)。在第二发射极电极20下形成有多个IGBT单元(后述)。栅极焊盘22例如被引线键合并从外部被输入栅极电压。栅极布线12、14、16、18对并联连接的IGBT单元的栅极电极施加栅极电压。
图2是表示图1的区域A中的n型Si衬底的表面的扩大上视图。图3是沿着图1和图2的B-B′的剖视图。图4是沿着图1和图2的C-C′的剖视图。图5是沿着图1的D-D′的剖视图。
第二发射极电极20的下方区域是在n型Si衬底10上形成了多个IGBT单元24的单元区域。从该单元区域朝向外侧,在n型Si衬底10的上表面形成有环状的p阱26、28、30、32以及沟道截止环(channelstopper)34。其中,p阱28、30、32及沟道截止环34在n型Si衬底10的终端区域形成。
在单元区域中,在n型Si衬底10的上表面有选择地形成有p型基极区域36。在该p型基极区域36内有选择地形成有n+型发射极区域38和p+型区域40。
以贯通p型基极区域36的方式形成有沟槽42。在沟槽42内形成有栅极绝缘膜44。在栅极绝缘膜44上形成有栅极电极46。沿着沟槽42在p型基极区域36中形成沟道。
在n型Si衬底10上形成有氧化膜48(绝缘膜)。在p阱26上隔着氧化膜48形成有栅极电极50。该栅极电极50经由氧化膜48的开口连接于多个IGBT单元24的栅极电极46。栅极电极50被层间绝缘膜52覆盖。在层间绝缘膜52上形成有由Al构成的、第一发射极电极54、下层栅极布线56(第二栅极布线)以及第一场板电极58、60、62、64。其中,第一场板电极58、60、62、64形成在n型Si衬底10的终端区域。
第一发射极电极54经由氧化膜48和层间绝缘膜52的开口连接于n+型发射极区域38和p+型区域40。下层栅极布线56经由层间绝缘膜52的开口连接于栅极电极50。第一场板电极58、60、62、64经由氧化膜48和层间绝缘膜52的开口分别连接于p阱28、30、32以及沟道截止环34。
第一发射极电极54、下层栅极布线56以及第一场板电极58、60、62、64被层间绝缘膜66覆盖。在层间绝缘膜52上形成有由Al构成的、第二发射极电极20、上层栅极布线18(第三栅极布线)以及第二场板电极68。第二发射极电极20、上层栅极布线18以及第二场板电极68经由层间绝缘膜66的开口分别连接于第一发射极电极54、下层栅极布线56以及第一场板电极58。上层栅极布线18及第二场板电极68被氮化硅那样的半绝缘性的保护膜70覆盖。再有,上层栅极布线18的宽度比下层栅极布线56的宽度宽,第二场板电极68比第一场板电极58、60、62、64厚。
在n型Si衬底10的下表面形成有p型集电极区域72。在p型集电极区域72连接有集电极电极74。集电极电极74从衬底侧起依次层叠了Al层76、Ti层78、Ni层80以及Au层82。
图6是表示图1的区域E中的n型Si衬底的表面的扩大上视图。图7是沿着图1和图6的F-F′的剖视图。图8是沿着图1和图6的G-G′的剖视图。
在n型Si衬底10上形成有直线状的p阱84。在该p阱84的两侧形成有多个IGBT单元24。在p阱84上隔着氧化膜48形成有直线状的栅极电极86。该栅极电极86经由氧化膜48的开口连接于多个IGBT单元24的栅极电极46。栅极电极86被层间绝缘膜52覆盖。在层间绝缘膜52上形成有第一发射极电极54及直线状的下层栅极布线14。下层栅极布线14经由层间绝缘膜52的开口连接于栅极电极86。在下层栅极布线14的两侧,第一发射极电极54经由氧化膜48和层间绝缘膜52的开口连接于n+型发射极区域38和p+型区域40。第二发射极电极20隔着层间绝缘膜66在下层栅极布线14的上方延伸。因此,下层栅极布线14被第二发射极电极20覆盖,没有露出。
以下,针对本实施方式的半导体装置的制造方法进行说明。图9-11是表示本发明的实施方式1的半导体装置的制造工序的剖视图。
首先,如图9所示,在n型Si衬底10的上表面形成扩散区域。然后,在n型Si衬底10上形成氧化膜48。在p阱26(84)上隔着氧化膜48形成栅极电极50(86)。
接着,如图10所示,通过沉积等形成层间绝缘膜52,在氧化膜48及层间绝缘膜52有选择地形成开口。然后,通过溅射、蒸镀对铝等的导电性材料进行成膜,有选择地进行蚀刻而在同一工序中形成第一发射极电极54、下层栅极布线56(12、14、16)以及第一场板电极58、60、62、64。
接着,如图11所示,通过沉积等形成层间绝缘膜66,在层间绝缘膜66有选择地形成开口。然后,通过溅射、蒸镀对铝等的导电性材料进行成膜,有选择地进行蚀刻而在同一工序中形成第二发射极电极20、上层栅极布线18以及第二场板电极68。之后,经过通常的IGBT的制造工序,制造本实施方式的半导体装置。
针对本实施方式的效果,一边与第一比较例进行比较一边进行说明。图12是表示第一比较例的半导体装置的上视图。图13是沿着图12的H-H′的剖视图。图14是沿着图12的I-I′的剖视图。
在第一比较例中,栅极布线、发射极电极以及场板电极仅是1层。因此,在芯片中央露出栅极布线12、14、16,所以第一发射极电极54变小。
在这里,IGBT单元的栅极电极46一般由多晶硅构成,与由Al构成的下层栅极布线12、14、16相比电阻高。因此,在接近于下层栅极布线12、14、16的单元和从栅极布线远离的单元中,在工作定时中产生不一致。为了减少该不一致,需要缩窄下层栅极布线12、14、16的间隔。因此,不能为了增大第一发射极电极54而减少下层栅极布线12、14、16的根数。
另一方面,在本实施方式中,第二发射极电极20隔着层间绝缘膜66在栅极电极50的上方延伸。因此,不减少下层栅极布线12、14、16的根数,就能够与第一比较例的第一发射极电极54相比,增大第二发射极电极20。因此,第二发射极电极20的发射极电位在芯片内变得均等,因此能够抑制不平衡工作、振荡。
此外,在第一比较例中,由于下层栅极布线12、14、16露出,所以需要以不与下层栅极布线12、14、16接触的方式进行引线键合。因此,能够引线键合到第一发射极电极54的区域狭窄。另一方面,在本实施方式中,由于下层栅极布线12、14、16没有露出,所以能够引线键合到第二发射极电极20的区域宽阔。
此外,在本实施方式中,使上层栅极布线18的宽度比下层栅极布线56的宽度宽。由此,能够降低芯片内的寄生栅极电阻,抑制不平衡工作。再有,下层栅极布线12、14、16、56的宽度设定为为了传递栅极电位所需要的宽度。
此外,通过采用在终端区域配置了环状的p阱28、30、32及第一场板电极58、60、62、64的保护环结构,从而能够在栅极电极施加时使耗尽层延伸,在OFF时保持在集电极/发射极之间施加的电压。最外周的沟道截止环34为了截止耗尽层而设置。因此,在终端区域能够保持耐压。
此外,在第一比较例的情况下,在同一工序中形成第一场板电极58、60、62、64和第二发射极电极54。由于为了提高引线键合性需要将第一发射极电极54增厚,所以场板电极58、60、62、64也变厚。因此,在对第一比较例的半导体装置进行传递模塑的情况下,由于模塑树脂与Si和Al的热膨胀率的不同,所以第一场板电极58、60、62、64由于模塑树脂的应力而滑动。
另一方面,在本实施方式中,由于第一场板电极58、60、62、64和第二发射极电极20在不同工序中形成,所以能够使第一场板电极58、60、62、64比第二场板电极68较薄地形成。由此,能够防止模塑树脂的应力导致的电极的滑动。
此外,通过以保护膜70覆盖第一场板电极58、60、62、64和第二场板电极68,能够从水分/应力/杂质等对其进行保护。
此外,在本实施方式中,在同一工序中形成第一发射极电极54和下层栅极布线12、14、16、56和第一场板电极58、60、62、64。而且,在同一工序中形成第二发射极电极20和上层栅极布线18和第二场板电极68。由此,能够削减工序,降低成本。
实施方式2
图15是表示本发明的实施方式2的半导体装置的上视图。图15与实施方式1的图1对应。在第二发射极电极20的中央(芯片中央)配置的下层栅极布线14上形成有上层栅极布线88。其它结构与实施方式1的结构相同。
如果能够确保向第二发射极电极20的引线键合的自由度的话,在第二发射极电极20的中央也能够形成上层栅极布线88。由此能够进一步降低栅极电阻。
实施方式3
图16是表示本发明的实施方式3的半导体装置的剖视图。图16与实施方式1的图7对应。在第二发射极电极20上形成有第三发射极电极90。其它结构与实施方式1的结构相同。
第三发射极电极90具有从第二发射极电极20侧起依次形成的Ti膜92、Ni膜94和Au膜96。这些膜以溅射、蒸镀等方法进行成膜,有选择地被蚀刻。像这样,第三发射极电极90具有作为焊接接合材料的Ni,因此能够进行焊接接合。
当如第一比较例那样,下层栅极布线12、14、16露出时,也阻碍焊接接合的自由度。另一方面,在本实施方式中,第二和第三发射极电极20、90隔着层间绝缘膜66在栅极电极14的上方延伸。因此,焊接接合的自由度上升。
此外,通过使用焊接接合,从而与使用引线键合的情况相比,能够降低通电时的导通电阻。而且,能够延长与芯片的接合面到剥离为止的寿命。
实施方式4
图17是表示本发明的实施方式4的半导体装置的剖视图。图17与实施方式1的图3对应。仅针对与实施方式1不同的终端区域的结构进行说明。其它结构与实施方式1相同。
在终端区域中在层间绝缘膜52上,形成有相互离开的由Al构成的第一场板电极98、100、102。第一场板电极98、102经由氧化膜48和层间绝缘膜52的开口分别连接于p阱28以及沟道截止环34。第一场板电极98、100、102被层间绝缘膜66覆盖。
在层间绝缘膜66上,形成有相互离开的由Al构成的第二场板电极104、106、108。第二场板电极104经由层间绝缘膜52的开口连接于第一场板电极98。第二场板电极106、108配置在邻接的第一场板电极98、100、102之间的区域上。
像这样,采用使第一场板电极98、100、102和第二场板电极104、106、108电容耦合的场板结构。在该情况下,也与实施方式1同样地,能够在栅极电极施加时使耗尽层延伸,在OFF时保持施加到集电极/发射极之间的电压。最外周的沟道截止环34为了截止耗尽层而设置。因此,在终端区域能够保持耐压。
接着,针对本发明的实施方式4的半导体装置的制造方法进行说明。图18-20是表示本发明的实施方式4的半导体装置的制造工序的剖视图。
首先,如图18所示,在n型Si衬底10的上表面形成扩散区域。然后,在n型Si衬底10上形成氧化膜48。在p阱26(84)上隔着氧化膜48形成栅极电极50(86)。
接着,如图19所示,通过沉积等形成层间绝缘膜52,在氧化膜48及层间绝缘膜52有选择地形成开口。然后,通过溅射、蒸镀对铝等的导电性材料进行成膜,有选择地进行蚀刻而在同一工序中形成第一发射极电极54、下层栅极布线56(12、14、16)以及第一场板电极98、100、102。
接着,如图20所示,通过沉积等形成层间绝缘膜66,在层间绝缘膜66有选择地形成开口。然后,通过溅射、蒸镀对铝等的导电性材料进行成膜,有选择地进行蚀刻而在同一工序中形成第二发射极电极20、上层栅极布线18以及第二场板电极104、106、108。之后,经过通常的IGBT的制造工序,制造本实施方式的半导体装置。
针对本实施方式的效果,一边与第二比较例进行比较一边进行说明。图21是表示第二比较例的半导体装置的剖视图。在第二比较例中,栅极布线及发射极电极仅是1层。因此,第一场板电极110、112、114与栅极电极50在同一工序中形成,第二场板电极116、118、120、122与第一发射极电极54以及下层栅极布线56在同一工序中形成。由此,因为第一场板电极110、112、114由多晶硅构成,所以受到制造上的制约。
另一方面,在本实施方式中,第一场板电极98、100、102与第一发射极电极54和下层栅极布线56在同一工序中形成,第二场板电极104、106、108与第二发射极电极20以及上层栅极布线18在同一工序中形成。由此,因为第一场板电极由Al构成,所以不受制造上的制约。
Claims (12)
1.一种半导体装置,其特征在于,具备:
半导体衬底;
多个IGBT单元,在所述半导体衬底上形成,分别具有栅极电极和第一发射极电极;
第一栅极布线,在所述半导体衬底上形成,连接于所述栅极电极;
层间绝缘膜,覆盖所述第一发射极电极和所述第一栅极布线;以及
第二发射极电极,在所述层间绝缘膜上形成,经由所述层间绝缘膜的开口连接于所述第一发射极电极,其中,
所述第二发射极电极隔着所述层间绝缘膜在所述第一栅极布线的上方延伸。
2.根据权利要求1所述的半导体装置,其特征在于,还具备:
第二栅极布线,在所述半导体衬底上形成,连接于所述栅极电极,被所述层间绝缘膜覆盖;以及
第三栅极布线,在所述层间绝缘膜上形成,经由所述层间绝缘膜的开口连接于所述第二栅极布线,其中,
所述第三栅极布线的宽度比所述第二栅极布线的宽度宽。
3.根据权利要求2所述的半导体装置,其特征在于,所述第二栅极布线和所述第三栅极布线在所述半导体衬底上配置在所述第二发射极电极的外侧。
4.根据权利要求2所述的半导体装置,其特征在于,所述第二栅极布线和所述第三栅极布线在所述半导体衬底上配置在所述第二发射极电极的中央。
5.根据权利要求1~4的任一项所述的半导体装置,其特征在于,还具备:第三发射极电极,其在所述第二发射极电极上形成,并具有Ni。
6.根据权利要求5所述的半导体装置,其特征在于,所述第三发射极电极具有:从所述第二发射极电极侧起依次形成的Ti膜、Ni膜和Au膜。
7.根据权利要求1~4的任一项所述的半导体装置,其特征在于,还具备:
第一场板电极,在所述半导体衬底上的终端区域中形成,被所述层间绝缘膜覆盖;以及
第二场板电极,在所述层间绝缘膜上形成,经由所述层间绝缘膜的开口连接于所述第一场板电极。
8.根据权利要求1~4的任一项所述的半导体装置,其特征在于,还具备:
多个第一场板电极,在所述半导体衬底上的终端区域中相互离开而形成,被所述层间绝缘膜覆盖;以及
多个第二场板电极,在所述层间绝缘膜上形成,配置在邻接的所述第一场板电极之间的区域上。
9.根据权利要求7所述的半导体装置,其特征在于,所述第一场板电极比所述第二场板电极薄。
10.根据权利要求7的任一项所述的半导体装置,其特征在于,还具备:保护膜,覆盖所述第二场板电极。
11.一种半导体装置的制造方法,制造权利要求2~4的任一项所述的半导体装置,其特征在于,
在同一工序中形成所述第一发射极电极、所述第一栅极布线及所述第二栅极布线,
在同一工序中形成所述第二发射极电极及所述第三栅极布线。
12.一种半导体装置的制造方法,制造权利要求7所述的半导体装置,其特征在于,
在同一工序中形成所述第一发射极电极、所述第一栅极布线及所述第一场板电极,
在同一工序中形成所述第二发射极电极及所述第二场板电极。
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CN104979179A (zh) * | 2014-04-10 | 2015-10-14 | 三菱电机株式会社 | 半导体装置以及半导体装置的制造方法 |
CN110192284A (zh) * | 2017-01-19 | 2019-08-30 | 株式会社日立功率半导体 | 半导体装置和电力变换装置 |
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CN104979179A (zh) * | 2014-04-10 | 2015-10-14 | 三菱电机株式会社 | 半导体装置以及半导体装置的制造方法 |
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Also Published As
Publication number | Publication date |
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DE102010038641B4 (de) | 2014-03-13 |
US8294244B2 (en) | 2012-10-23 |
DE102010038641A1 (de) | 2011-03-03 |
JP2011049393A (ja) | 2011-03-10 |
CN102005474B (zh) | 2013-06-26 |
US20110049562A1 (en) | 2011-03-03 |
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